Package carrier, method for manufacturing package carrier, and display device

Abstract

The invention provides a package carrier, a manufacturing method of the package carrier and a display device, the package carrier comprises a substrate main body, the substrate main body further comprises a first through hole and a first circuit groove, the first through hole penetrates a part of the substrate main body, and the first circuit groove is located in a first surface; the first wiring structure is located on the first surface, the second wiring structure is located on the second surface, the first through hole is filled with the connecting structure, and the first wiring structure and the second wiring structure are electrically connected with each other through the connecting structure; wherein at least part of the first wiring structure is located in the first circuit groove. Therefore, the bonding force between the wiring structure and the substrate main body can be effectively improved, the deviation risk of the wiring structure is reduced, and the circuit precision is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to a packaging substrate, a method for manufacturing the packaging substrate, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and flat panel displays based on light-emitting diodes (LEDs) are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body and wide range of applications, becoming the mainstream of display devices.

[0003] However, the performance of current OLED display products needs to be improved. Summary of the Invention

[0004] To overcome the aforementioned shortcomings in the prior art, the present application aims to provide a packaging carrier board, the packaging carrier board comprising: The substrate body includes a first surface and a second surface disposed opposite to each other, and also includes a first through hole penetrating a portion of the substrate body and a first line groove located on the first surface, wherein at least one of the first through holes communicates with at least one of the first line grooves, and the orthographic projection of the first through hole on the first surface is located within the orthographic projection of at least a portion of the first line groove on the first surface. A first trace structure located on the first surface, a second trace structure located on the second surface, and a connection structure filling the first through hole, wherein at least a portion of the first trace structure and at least a portion of the second trace structure are electrically connected to each other through the connection structure; At least a portion of the first wiring structure is located within the first wiring groove.

[0005] In some possible implementations, the second surface includes a second wiring groove, and the orthographic projection of the first through-hole on the second surface lies within at least a portion of the orthographic projection of the second wiring groove on the second surface. At least a portion of the second wiring structure is located within the second wiring groove, and at least another portion of the second wiring structure protrudes relative to the second surface; Preferably, the first through hole connects the first wiring slot and the second wiring slot.

[0006] In some possible implementations, at least another portion of the first trace structure protrudes relative to the first surface; Preferably, the ratio between the first height of the first wiring structure located within the first wiring groove and the second height of the first wiring structure protruding from the first surface is in the range of 0.8 to 1.25. Preferably, the ratio of the first height to the second height is 1; Preferably, the first height ranges from 8 micrometers to 12 micrometers, and the second height ranges from 8 micrometers to 12 micrometers; Preferably, both the first height and the second height are 10 micrometers.

[0007] In some possible implementations, the packaging carrier board further includes: The seed layer includes a first portion located between the inner wall of the first through hole and the connection structure, a second portion located between the inner wall of the first wiring groove and the first wiring structure, and a third portion located between the inner wall of the second wiring groove and the second wiring structure.

[0008] In some possible implementations, the packaging substrate further includes a first insulating layer located on the side of the first trace structure away from the substrate body, with the portion of the first trace structure protruding from the first surface embedded in the first insulating layer; Preferably, the packaging substrate further includes at least one first rewiring trace embedded in the first insulating layer; at least a portion of the first rewiring trace is connected to the first trace structure; Preferably, the packaging carrier further includes a second insulating layer located on the side of the second wiring structure away from the substrate body; Preferably, the packaging substrate further includes at least one second rewiring trace embedded in the second insulating layer; at least a portion of the second rewiring trace is connected to the second trace structure.

[0009] Another object of this application is to provide a method for manufacturing a packaging carrier board, the method comprising: A substrate body is provided, the substrate body including a first surface and a second surface disposed opposite to each other; A first through hole is formed, extending from the first surface to the second surface; A recessed first wiring groove is formed on the first surface such that the orthographic projection of the first through hole on the first surface is located within the orthographic projection of the first wiring groove on the first surface. A connection structure is formed in the first through hole, a first trace structure is formed on the first surface that is at least partially located in the first trace groove, and a second trace structure is formed on the second surface; the connection structure is used to connect the first trace structure and the second trace structure.

[0010] In some possible implementations, the step of forming a first trace structure at least partially located within the first trace groove on the first surface includes: A first trace structure is formed on the first surface, which is at least partially located within the first trace groove and at least partially protrudes relative to the first surface; The manufacturing method further includes: A second wiring groove is formed on the second surface such that the orthographic projection of the first through hole on the second surface is at least partially located within the orthographic projection of the second wiring groove on the second surface; The step of forming the second trace structure on the second surface includes: A second trace structure is formed on the second surface, which is at least partially located within the second trace groove and at least partially protrudes relative to the second surface.

[0011] In some possible implementations, the steps of forming a connection structure within the first through-hole, forming a first trace structure on the first surface that is at least partially located within the first trace groove and additionally at least partially protruding relative to the first surface, and forming a second trace structure on the second surface include: A seed layer is formed covering the inner wall of the first through hole, the inner wall of the first line groove, the first surface, the second surface, and the inner wall of the second line groove. A barrier layer is formed covering the side of the seed layer away from the substrate body; An electroplating opening is formed on the barrier layer, the electroplating opening exposing the seed layer within the first through hole, the first line groove, and the second line groove; The connection structure, the first routing structure, and the second routing structure are formed based on the seed layer; Remove the blocking layer and the seed layer located on the first surface and the second surface.

[0012] In some possible implementations, the manufacturing method further includes: A first insulating layer is formed on the side of the first surface away from the substrate body, and a second insulating layer is formed on the side of the second surface away from the substrate body; Preferably, the method further includes: providing at least one first rewiring trace within the first insulating layer; and connecting at least a portion of the first rewiring trace to the first trace structure. The method further includes: providing at least one second rewiring trace within the second insulating layer; and at least a portion of the second rewiring trace being connected to the second trace structure.

[0013] Another object of this application is to provide a display device, the display device including the encapsulation carrier provided in this application, or including an encapsulation carrier made by the manufacturing method of the encapsulation carrier provided in this application.

[0014] Compared with the prior art, this application has the following beneficial effects: This application provides a packaging substrate, a method for manufacturing the packaging substrate, and a display device. By providing circuit grooves on the substrate body and forming at least a portion of the wiring structure within the circuit grooves, the bonding force between the wiring structure and the substrate body can be effectively improved, the risk of wiring structure misalignment can be reduced, and the circuit accuracy can be improved. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is one of the cross-sectional views of the packaging carrier provided in this embodiment; Figure 2 This is a cross-sectional schematic diagram of the substrate body provided in this embodiment; Figure 3 This is the second cross-sectional view of the packaging carrier provided in this embodiment; Figure 4 This is the third cross-sectional view of the packaging carrier provided in this embodiment; Figure 5 The fourth cross-sectional view of the packaging carrier provided in this embodiment; Figure 6 Fifth cross-sectional view of the packaging carrier provided in this embodiment; Figure 7 This is a schematic flowchart illustrating the steps of the manufacturing method for the packaging carrier provided in this embodiment; Figure 8 This is one of the schematic diagrams illustrating the manufacturing process of the packaging carrier provided in this embodiment; Figure 9 This is the second schematic diagram illustrating the manufacturing process of the packaging carrier provided in this embodiment; Figure 10 This is the third schematic diagram illustrating the manufacturing process of the packaging carrier provided in this embodiment.

[0017] Icons: 110 - Substrate body; 1101 - First surface; 1102 - Second surface; 211 - First through hole; 221 - First wiring groove; 222 - Second wiring groove; 120 - Seed layer; 130 - Barrier layer; 141 - First routing structure; 142 - Second routing structure; 143 - Connection structure; 151 - First insulating layer; 161 - First redistribution trace; 152 - Second insulating layer; 162 - Second redistribution trace; 170 - Solder mask layer; 180 - Surface finishing part; 190 - Solder ball bump; H1 - First height; H2 - Second height. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0019] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0020] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0021] In the description of this application, it should be noted that the terms "center," "upper," "lower," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of the invention is in use. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. In addition, the terms "first," "second," and "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0022] It should be noted that, where there is no conflict, different features in the embodiments of this application can be combined with each other.

[0023] In some chip packaging structures, in order to enable the chips and circuits on both sides of the packaging substrate to be interconnected, through-glass vias (TGVs) are formed through the substrate body by laser or etching, and wiring structures are formed on the surface of the substrate body at both ends of the through-glass via. The wiring structures on both sides are connected by filling the through-glass via.

[0024] The inventors discovered that in the above solution, the bonding force between the metal trace structure and the glass substrate is insufficient. When the trace structure is dense and the line width is small, the trace structure is prone to shift during the dielectric lamination process, which affects the reliability of the electrical connection.

[0025] In view of this, this embodiment provides a solution that can increase the bonding force between the wiring structure and the substrate body. The solution provided in this embodiment will be described in detail below.

[0026] Please see Figure 1 , Figure 1 The packaging carrier provided in this embodiment may include a substrate body 110, a first wiring structure 141, a second wiring structure 142, and a connection structure 143.

[0027] Please see Figure 2 The substrate body 110 includes a first surface 1101 and a second surface 1102 disposed opposite to each other, and the substrate body 110 also includes a first through hole 211 and a first line groove 221.

[0028] The first line groove 221 is located on the first surface 1101, and the first through hole 211 penetrates a portion of the substrate body 110, that is, at least one first through hole 211 communicates with at least one first line groove 221. The orthographic projection of the first through hole 211 on the first surface 1101 lies within the orthographic projection of at least a portion of the first line groove 221 on the first surface 1101. The first line groove 221 can be formed by laser-induced etching.

[0029] In this embodiment, the material of the substrate body 110 may include glass. The first through hole 211 may be formed by laser-induced wet etching; or the first through hole 211 may also be formed by laser melting, focused discharge, plasma etching, electrochemical discharge processing, etc., and no specific limitation is made in this embodiment.

[0030] Specifically, along the thickness direction of the substrate body 110, the first through hole 211 penetrates the substrate body 110, while the first line groove 221 does not penetrate the substrate body 110.

[0031] Optionally, the second surface 1102 includes a second wiring groove 222, and the orthographic projection of the first through hole 211 on the second surface 1102 is at least partially located within the orthographic projection of the second wiring groove 222 on the second surface 1102. The second wiring groove 222 can be formed by laser-induced etching.

[0032] Specifically, along the thickness direction of the substrate body 110, the first through hole 211 penetrates the substrate body 110, while the second line groove 222 does not penetrate the substrate body 110.

[0033] Furthermore, along the thickness direction of the substrate body 110, the sum of the depths of the first line groove 221 and the second line groove 222 is less than the thickness of the substrate body 110.

[0034] That is, the first through hole 211 can connect the first wiring groove 221 on the first surface 1101 and the second wiring groove 222 on the second surface 1102. For example, at least one first through hole 211 can connect the bottom of at least one first wiring groove 221 and the bottom of at least one second wiring groove 222.

[0035] The first trace structure 141 is located on the first surface 1101, the second trace structure 142 is located on the second surface 1102, and the connecting structure 143 is located in the first through hole 211 and fills the first through hole 211. At least a portion of the first trace structure 141 and at least a portion of the second trace structure 142 are electrically connected to each other through the connecting structure 143.

[0036] In this embodiment, at least a portion of the first trace structure 141 is located within the first trace groove 221. Optionally, at least another portion of the first trace structure 141 protrudes relative to the first surface 1101. That is, at least a portion of the first trace structure 141 is embedded in the substrate body 110, and at least another portion protrudes from the substrate body 110.

[0037] Optionally, at least a portion of the second trace structure 142 is located within the second trace groove 222, and at least another portion of the second trace structure 142 protrudes relative to the second surface 1102. That is, at least a portion of the second trace structure 142 is embedded in the substrate body 110, and at least another portion protrudes from the substrate body 110.

[0038] Based on the above design, in this embodiment, by providing a circuit groove on the substrate body 110, at least a portion of the wiring structure is formed within the circuit groove. Thus, by constraining the formation position of the wiring structure through the circuit groove, the bonding force between the wiring structure and the substrate body 110 can be effectively improved, the risk of wiring structure misalignment can be reduced, and circuit accuracy can be improved.

[0039] See also: [Information on possible implementations] Figure 3The packaging substrate provided in this embodiment may further include a seed layer 120. The seed layer 120 includes a first portion located between the inner wall of the first through hole 211 and the connection structure 143, a second portion located between the inner wall of the first line groove 221 and the first wiring structure 141, and a third portion located between the inner wall of the second line groove 222 and the second wiring structure 142. In this embodiment, a relatively thin seed layer 120 can be first formed based on the substrate body 110 provided with line grooves and the first through hole 211. Then, the seed layer 120 is used as an electroplating electrode to gradually electroplate and form the connection structure 143 filling the first through hole 211, the first wiring structure 141 at least partially located in the first line groove 221, and the second wiring structure 142 at least partially located in the second line groove 222.

[0040] In some possible implementations, the ratio between the first height H1 of the first wiring structure 141 within the first wiring groove 221 and the second height H2 of the first wiring structure 141 protruding from the first surface 1101 ranges from 0.8 to 1.25. For example, the ratio of the first height H1 to the second height H2 can be 0.9, 1, or 1.1.

[0041] In some possible implementations, the first height H1 ranges from 8 micrometers to 12 micrometers, and the second height H2 ranges from 8 micrometers to 12 micrometers. For example, the first height H1 and the second height H2 can be equal and both be 9 micrometers, 10 micrometers, or 11 micrometers.

[0042] In some possible implementations, the seed layer 120 may be made of copper. The first trace structure 141, the second trace structure 142, and the connection structure 143 are made of the same material, and the materials of the first trace structure 141, the second trace structure 142, and the connection structure 143 may include at least one of copper, aluminum, nickel, and silver.

[0043] In some possible implementations, the packaging substrate provided in this embodiment also includes a first insulating layer 151 located on the side of the first wiring structure 141 away from the substrate body 110, with the portion of the first wiring structure 141 protruding from the first surface 1101 embedded in the first insulating layer 151.

[0044] Optionally, the packaging substrate provided in this embodiment further includes at least one first rewiring trace 161 embedded in the first insulating layer 151, and at least a portion of the first rewiring trace 161 is in contact with the first trace structure 141.

[0045] In this case, the first insulating layer 151 covers and wraps the portion of the first wiring structure 141 that protrudes from the first wiring groove 221, increasing the bonding force between the first wiring structure 141 and the first insulating layer 151.

[0046] Optionally, the packaging substrate provided in this embodiment further includes a second insulating layer 152 located on the side of the second wiring structure 142 away from the substrate body 110, and the portion of the second wiring structure 142 protruding from the second surface 1102 is embedded in the second insulating layer 152.

[0047] In this case, the second insulating layer 152 covers and wraps the portion of the second wiring structure 142 that protrudes from the second wiring groove 222, increasing the bonding force between the second wiring structure 142 and the second insulating layer 152. Optionally, the packaging substrate provided in this embodiment further includes at least one second rewiring trace 162 embedded in the second insulating layer 152, and at least a portion of the second rewiring trace 162 is in contact with the second trace structure 142.

[0048] In some possible implementations, the side of the first insulating layer 151 away from the substrate body 110 and the side of the second insulating layer 152 away from the substrate body 110 may be provided with solder resist layers 170, respectively. The solder resist layers 170 include solder joint openings that expose at least a portion of the first rewiring trace 161 and / or the second rewiring trace 162. Solder ball bumps 190 or copper pillars may also be provided in at least a portion of the solder joint openings.

[0049] In this embodiment, the first insulating layer 151 and the first rewiring trace 161 form the first rewiring structure layer, and the second insulating layer 152 and the second rewiring trace 162 form the second rewiring structure layer. The first and second rewiring structure layers can be used to connect with other circuit boards and chips, respectively, so as to realize the rewiring or connection of the corresponding chip pins.

[0050] It should be noted that, please refer to Figure 6 In this embodiment, at least a portion of the first line groove 221 can be connected to at least a portion of the second line groove 222 through the first through hole 211. However, it is also possible that at least a portion of the first line groove 221 is not connected to the second line groove 222 through the first through hole 211, and at least a portion of the second line groove 222 is not connected to the first line groove 221 through the first through hole 211.

[0051] In this case, at least a portion of the first routing structure 141 is connected to the second routing structure 142 through the connection structure 143. Alternatively, at least a portion of the first routing structure 141 may not be connected to the second routing structure 142, and at least a portion of the second routing structure 142 may not be connected to the first routing structure 141.

[0052] For example, when the packaging substrate provided in this embodiment needs to connect some pins of two chips disposed on the same side of the packaging substrate (such as the first surface 1101 side), at least part of the first wiring structure 141 can be used only to form connecting wiring to connect the pins of the two chips, without needing to be connected to the second wiring structure 142 of the second surface 1102.

[0053] Please see Figure 7 This embodiment also provides a method for manufacturing a packaging substrate, which can be used to manufacture the packaging substrate provided in this embodiment. The steps of the method are described in detail below.

[0054] Step S110: Provide a substrate body 110, which includes a first surface 1101 and a second surface 1102 disposed opposite to each other.

[0055] In this embodiment, the material of the substrate body 110 may include glass.

[0056] Step S120: A first through hole 211 is formed, extending from the first surface 1101 to the second surface 1102.

[0057] Alternatively, in one possible implementation, the first via 211 can be formed by laser-induced etching.

[0058] Specifically, in step S120, the substrate body 110 is first patterned by laser irradiation, causing localized modification of the glass material in the substrate body 110 in areas irradiated by the laser relative to areas not irradiated by the laser. Then, the modified areas are etched using hydrofluoric acid (HF) or potassium hydroxide (KOH) solution. Due to the difference in chemical activity between the modified and unmodified areas, anisotropic etching can be achieved during the etching process to remove the modified areas and form the first through hole 211.

[0059] In other possible implementations, the first through hole 211 can also be formed by laser melting, focused discharge, plasma etching or electrochemical discharge machining.

[0060] In step S130, a recessed first line groove 221 is formed on the first surface 1101 so that the orthographic projection of the first through hole 211 on the first surface 1101 is located within the orthographic projection of the first line groove 221 on the first surface 1101.

[0061] Please see Figure 8 Optionally, in this embodiment, a recessed first line groove 221 can be formed on the first surface 1101 by laser-induced etching.

[0062] Optionally, in step S130, a second wiring groove 222 is also formed on the second surface 1102, and the orthographic projection of the first through hole 211 on the second surface 1102 is located within the orthographic projection of the second wiring groove 222 on the second surface 1102. At least a portion of the first wiring groove 221 and at least a portion of the second wiring groove 222 are interconnected through the first through hole 211 penetrating the substrate body 110.

[0063] In step S140, a connecting structure 143 is formed in the first through hole 211, a first wiring structure 141 at least partially located in the first wiring groove 221 is formed on the first surface 1101, and a second wiring structure 142 is formed on the second surface 1102; the connecting structure 143 is used to connect the first wiring structure 141 and the second wiring structure 142 to each other electrically.

[0064] Optionally, if the second surface 1102 also has a second wiring groove 222, in step S140 a second wiring structure 142 may be formed on the second surface 1102 that is at least partially located within the second wiring groove 222 and at least partially protruding from the second surface 1102.

[0065] In some possible implementations, step S140 may include the following sub-steps.

[0066] Step S141: A seed layer 120 is formed covering the inner wall of the first through hole 211, the first surface 1101, the first line groove 221, the second surface 1102, and the second line groove 222.

[0067] Please see Figure 9 In this embodiment, the seed layer 120 can be formed by physical vapor deposition. The seed layer 120 can cover the inner wall of the first through hole 211, the first wiring groove 221, the second wiring groove 222, and other areas of the first surface 1101 and the second surface 1102. Alternatively, the seed layer 120 can also be formed by chemical copper plating.

[0068] Step S142: A barrier layer 130 is formed covering the side of the seed layer 120 away from the substrate body 110. In step S143, an electroplating opening is formed on the barrier layer 130, which exposes the seed layer 120 located in the first through hole 211, the first line groove 221 and the second line groove 222, and covers the seed layer 120 in other areas.

[0069] Optionally, in step S142, a barrier layer 130 with electroplating openings exposing the first through-hole 211, the first line groove 221, and the second line groove 222 can be formed by attaching a dry film to the first surface 1101 and the second surface 1102 and then patterning it. Alternatively, the barrier layer 130 with electroplating openings can be formed by coating photoresist and then exposing and developing it.

[0070] Step S144: Based on the seed layer 120, a connection structure 143, a first routing structure 141, and a second routing structure 142 are formed.

[0071] In this embodiment, the seed layer 120 can be used as an electroplating electrode, and the exposed seed layer 120 surface can be gradually electroplated to form a connection structure 143 filling the first through hole 211, a first wiring structure 141 at least partially located in the first wiring groove 221, and a second wiring structure 142 at least partially located in the second wiring groove 222.

[0072] Since the seed layer 120 outside the first line groove 221 and the second line groove 222 is covered by the barrier layer 130, no wiring structure will be formed at these locations during the electroplating process in step S143.

[0073] Furthermore, since the barrier layer 130 restricts the range of the electroplated trace structure, at least a portion of the formed first trace structure 141 can be higher than the first line groove 221, but its orthogonal projection on the first surface 1101 is still within the range of the electroplating opening of the barrier layer 130; correspondingly, at least a portion of the formed second trace structure 142 can be higher than the second line groove 222, but its orthogonal projection on the second surface 1102 is still within the range of the electroplating opening of the barrier layer 130.

[0074] Step S145: Remove the barrier layer 130 and the seed layer 120 located on the first surface 1101 and the second surface 1102.

[0075] In this embodiment, please refer to Figure 10 After forming the first trace structure 141 and the second trace structure 142, the barrier layer 130 can be removed first, and then the seed layer 120 originally covered by the barrier layer 130 can be removed by etching to form a trace structure 142. Figure 3 The structure shown.

[0076] In some possible implementations, after step S140, the method provided in this embodiment may further include step S150.

[0077] In step S150, a first insulating layer 151 is formed on the side of the first surface 1101 away from the substrate body 110, and a second insulating layer 152 is formed on the side of the second surface 1102 away from the substrate body 110.

[0078] In some possible implementations, the method provided in this embodiment further includes providing at least one first rewiring trace 161 within the first insulating layer 151; at least a portion of the first rewiring trace 161 is connected to the first trace structure 141.

[0079] In some possible implementations, the method provided in this embodiment further includes providing at least one second rewiring trace 162 within the second insulating layer 152; at least a portion of the second rewiring trace 162 is connected to the second wiring structure 142.

[0080] Specifically, at least one first rewiring trace 161 embedded in the first insulating layer 151 may be provided.

[0081] The first insulating layer 151 may include a plurality of first insulator layers. In step S150, the first insulator layer may be first disposed on the side of the first wiring structure 141 away from the substrate body 110. Then, a second through hole is formed through the first insulating layer 151 and exposes at least part of the first wiring structure 141. Then, the first wiring structure 141 is formed on the side of the first insulator layer away from the substrate body 110. At least part of the first rewiring trace 161 extends into the second through hole and contacts the first wiring structure 141.

[0082] Similarly, the first insulator layer and the first rewiring line 161 can be set layer by layer to form a multi-layer rewiring structure.

[0083] At least one second rewiring trace 162 embedded in the second insulating layer 152 may be provided therein.

[0084] The second insulating layer 152 may include a plurality of second insulator layers. In step S150, the second insulator layer may be first disposed on the side of the second wiring structure 142 away from the substrate body 110. Then, a third through hole is formed through the second insulator layer and exposes at least part of the second wiring structure 142. Then, a second rewiring trace 162 is formed on the side of the second insulator layer away from the substrate body 110. At least part of the second rewiring trace 162 extends into the third through hole and contacts the second wiring structure 142.

[0085] Similarly, a second insulator layer and a second wiring route 162 can be set layer by layer to form a multi-layer rewiring structure.

[0086] Optionally, the first insulating layer 151 and the second insulating layer 152 can be formed by methods such as pressing or coating.

[0087] The first layer of wiring trace 161 and the second layer of wiring trace 162 can be formed by processes such as PVD sputtering, coating, photolithography, development, electroplating, resist removal, and etching. The materials of the first layer of wiring trace 161 and the second layer of wiring trace 162 may include at least one of copper, aluminum, nickel, and silver.

[0088] In some possible implementations, after step S150, solder mask layers 170 may be formed on the side of the first rewiring trace 161 and the first insulating layer 151 away from the substrate body 110, and on the side of the second rewiring trace 162 and the second insulating layer 152 away from the substrate body 110, respectively. The solder mask layers 170 are then etched to form solder openings that expose at least a portion of the first rewiring trace 161 or the second rewiring trace 162.

[0089] Next, the first and second wiring traces 161 and 162 exposed by the solder opening are surface treated to form a surface trimming section 180. The material of the surface trimming section 180 may include organic solderable corrosion inhibitor (OSP), electroless nickel immersion gold (ENIG), electroless nickel immersion palladium immersion gold (ENIPIG), electroless nickel immersion palladium immersion gold (ENEPIG), chemical tin (chemical and electroplating), etc.

[0090] Finally, solder ball bumps 190 can be formed within the soldering opening. For the side of the package substrate that needs to connect to other printed circuit boards, the material of the solder ball bumps 190 can include tin, tin-silver alloy, a mixture of copper and tin-silver alloy, a mixture of copper, nickel, and tin-silver alloy, etc. For the side of the package substrate that needs to connect to the chip, the fabrication process for forming the solder ball bumps 190 can use the C4 (Controlled Collapse Chip Connection) process, or copper pillars can be formed instead of solder ball bumps.

[0091] Another object of this application is to provide a display device, which includes the encapsulation substrate provided in this application, or includes an encapsulation substrate made by the manufacturing method of the encapsulation substrate provided in this application.

[0092] The display device may also include at least one chip, which is electrically connected to other chips or other circuit structures via the packaging substrate provided in this embodiment.

[0093] In summary, this application provides a packaging substrate, a method for manufacturing the packaging substrate, and a display device. By providing circuit grooves on the substrate body and allowing at least a portion of the wiring structure to be formed within the circuit grooves, the formation position of the wiring structure is constrained by the circuit grooves, which can effectively improve the bonding force between the wiring structure and the substrate body, reduce the risk of wiring structure misalignment, and improve circuit accuracy.

[0094] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0095] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A packaging carrier board, characterized in that, The packaging carrier includes: The substrate body includes a first surface and a second surface disposed opposite to each other, and also includes a first through hole penetrating a portion of the substrate body and a first line groove located on the first surface, wherein at least one of the first through holes communicates with at least one of the first line grooves, and the orthographic projection of the first through hole on the first surface is located within the orthographic projection of at least a portion of the first line groove on the first surface. A first trace structure located on the first surface, a second trace structure located on the second surface, and a connection structure filling the first through hole, wherein at least a portion of the first trace structure and at least a portion of the second trace structure are electrically connected to each other through the connection structure; At least a portion of the first wiring structure is located within the first wiring groove.

2. The packaging carrier board according to claim 1, characterized in that, The second surface includes a second wiring groove, and the orthographic projection of the first through hole on the second surface lies within at least a portion of the orthographic projection of the second wiring groove on the second surface; Preferably, at least a portion of the second wiring structure is located within the second wiring groove, and at least another portion of the second wiring structure protrudes relative to the second surface; Preferably, the first through hole connects the first wiring slot and the second wiring slot.

3. The packaging carrier board according to claim 1, characterized in that, At least another portion of the first trace structure protrudes relative to the first surface. Preferably, the ratio between the first height of the first wiring structure located within the first wiring groove and the second height of the first wiring structure protruding from the first surface is in the range of 0.8 to 1.

25. Preferably, the ratio of the first height to the second height is 1; Preferably, the first height ranges from 8 micrometers to 12 micrometers, and the second height ranges from 8 micrometers to 12 micrometers; Preferably, both the first height and the second height are 10 micrometers.

4. The packaging carrier board according to claim 2, characterized in that, The packaging carrier also includes: The seed layer includes a first portion located between the inner wall of the first through hole and the connection structure, a second portion located between the inner wall of the first wiring groove and the first wiring structure, and a third portion located between the inner wall of the second wiring groove and the second wiring structure.

5. The packaging carrier board according to claim 3, characterized in that, The packaging substrate further includes a first insulating layer located on the side of the first trace structure away from the substrate body, and the portion of the first trace structure protruding from the first surface is embedded in the first insulating layer. Preferably, the packaging substrate further includes at least one first rewiring trace embedded in the first insulating layer; at least a portion of the first rewiring trace is connected to the first trace structure; Preferably, the packaging carrier further includes a second insulating layer located on the side of the second wiring structure away from the substrate body; Preferably, the packaging substrate further includes at least one second rewiring trace embedded in the second insulating layer; at least a portion of the second rewiring trace is connected to the second trace structure.

6. A method for manufacturing a packaging carrier board, characterized in that, The method includes: A substrate body is provided, the substrate body including a first surface and a second surface disposed opposite to each other; A first through hole is formed, extending from the first surface to the second surface; A recessed first wiring groove is formed on the first surface such that the orthographic projection of the first through hole on the first surface is located within the orthographic projection of the first wiring groove on the first surface. A connection structure is formed in the first through hole, a first trace structure is formed on the first surface that is at least partially located in the first trace groove, and a second trace structure is formed on the second surface; the connection structure is used to connect the first trace structure and the second trace structure.

7. The manufacturing method according to claim 6, characterized in that, The step of forming a first trace structure at least partially located within the first trace groove on the first surface includes: A first trace structure is formed on the first surface, which is at least partially located within the first trace groove and at least partially protrudes relative to the first surface; The manufacturing method further includes: A second wiring groove is formed on the second surface such that the orthographic projection of the first through hole on the second surface is at least partially located within the orthographic projection of the second wiring groove on the second surface; The step of forming the second trace structure on the second surface includes: A second trace structure is formed on the second surface, which is at least partially located within the second trace groove and at least partially protrudes relative to the second surface.

8. The manufacturing method according to claim 7, characterized in that, The steps of forming a connection structure within the first through-hole, forming a first trace structure on the first surface that is at least partially located within the first trace groove and at least partially protruding relative to the first surface, and forming a second trace structure on the second surface include: A seed layer is formed covering the inner wall of the first through hole, the inner wall of the first line groove, the first surface, the second surface, and the inner wall of the second line groove. A barrier layer is formed covering the first surface and the second surface; An electroplating opening is formed on the barrier layer, the electroplating opening exposing the seed layer within the first through hole, the first line groove, and the second line groove; The connection structure, the first routing structure, and the second routing structure are formed based on the seed layer; Remove the blocking layer and the seed layer located on the first surface and the second surface.

9. The manufacturing method according to claim 7, characterized in that, The manufacturing method further includes: A first insulating layer is formed on the side of the first surface away from the substrate body, and a second insulating layer is formed on the side of the second surface away from the substrate body; Preferably, the method further includes: providing at least one first rewiring trace within the first insulating layer; and connecting at least a portion of the first rewiring trace to the first trace structure. The method further includes: providing at least one second rewiring trace within the second insulating layer; and at least a portion of the second rewiring trace being connected to the second trace structure.

10. A display device, characterized in that, The display device includes the encapsulation substrate as described in any one of claims 1-5, or includes an encapsulation substrate made by the manufacturing method of the encapsulation substrate as described in any one of claims 6-9.

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