2.5 D packaging method for improving chip warping and heat dissipation

Abstract

The invention provides a 2.5 D packaging method for improving chip warpage and heat dissipation, which can optimize and improve the warpage of a chip and improve the heat dissipation performance, and meanwhile, adopts a batch flip-chip backflow process, so that the yield is improved, the production efficiency is improved, and the cost is reduced. Firstly, temporary wafer bonding is carried out on an Interposer wafer, an upper-layer chip is inversely arranged on the other side of the Interposer wafer in a reflow soldering mode, bottom filling is carried out, TIM glue is scraped on the back face of the upper-layer chip, a cooling fin is pasted and solidified, then wafer plastic packaging and temporary wafer de-bonding are carried out, an RDL layer and an FC-Bump are prepared on the de-bonding side of the wafer, and the wafer is cut into single chips; the method comprises the following steps of: mounting a plurality of substrates on a substrate, mounting capacitance and resistance elements on the substrates in a surface-mount manner, carrying out flip reflow soldering on a single chip on the substrates, carrying out bottom filling, putting a plurality of substrates in a jig for plastic packaging, grinding to expose radiating fins, carrying out ball mounting on the other sides of the substrates, and finally cutting into single circuits.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor chip packaging, in particular to a 2.5D packaging method for improving chip warping and heat dissipation. BACKGROUND

[0002] With the continuous approach to the physical limit of semiconductor technology, the development of Moore's Law is slowing down, and the way to simply rely on size miniaturization to improve chip performance is facing the challenges of "power wall" and economy. At the same time, in the field of modern high-performance computing, artificial intelligence, etc., the demand for data interaction between computing cores and memories is increasing, and the long-distance interconnection between chips through the substrate in traditional packaging leads to serious signal delay, bandwidth limitation and huge power consumption, forming a "memory wall" bottleneck. In addition, the demand of terminal application for system miniaturization and functional diversification, as well as the urgency of integrating different process and functional chips, requires breaking through the limitations of integration density and interconnection capability of traditional two-dimensional packaging. To cope with the above challenges, 2.5D advanced packaging technology emerges as the times require. 2.5D packaging realizes ultra-short distance and ultra-high bandwidth interconnection between chips by introducing high-density interconnection substrates such as silicon interposers, effectively overcoming the "memory wall". At present, 2.5D packaging is mainly based on flip chip interconnection technology. Before flip chip interconnection with the substrate, the upper layer chip is usually a multi-layer, multi-material combination structure that has undergone multiple processes, and the chip warping is large. It is difficult to use flip reflow soldering process, which is easy to cause virtual soldering of solder joints and affect yield. The use of thermal compression bonding process is high in cost and low in production efficiency. At the same time, the chip interconnection density is high, and the heat dissipation is difficult, so a 2.5D packaging process method for improving chip warping and heat dissipation is needed. SUMMARY

[0003] In view of the above problems, the present application provides a 2.5D packaging method for improving chip warping and heat dissipation, which can optimize and improve the warping of the chip, improve the heat dissipation performance, and at the same time use batch flip reflow process to improve yield while improving production efficiency and reducing cost.

[0004] A 2.5D packaging method for improving chip warping and heat dissipation, characterized by: First, the Interposer wafer is temporarily wafer bonded, the upper layer chip is flip reflow soldered on the other side of the Interposer wafer, the bottom is filled, the TIM glue is drawn on the back of the upper layer chip, the heat dissipation sheet is attached and solidified, then the wafer is molded and the temporary wafer is unbonded, the RDL layer and FC-Bump are prepared on one side of the wafer unbonding, and the single chip is cut; then the capacitor resistor element is attached to the upper surface of the substrate, and the single chip is flip reflow soldered on the substrate, the bottom is filled, and the multiple substrates are placed in the jig for molding, the heat dissipation sheet is polished to expose the heat dissipation sheet, the ball is planted on the other side of the substrate, and finally the single circuit is cut.

[0005] It is further characterized in that it comprises the following steps: S1, temporarily bonding the Interposer wafer bottom layer and the temporary wafer, the upper layer chip is flip-chip reflow soldered on the upper surface of the Interposer wafer, and the bottom is filled; S2, the back of the upper layer chip is attached with a heat sink, and the upper layer chip and the Interposer wafer are molded to obtain a molding layer; S3, the Interposer wafer after molding and the temporary wafer are unbonded, and an RDL layer and an FC-Bump are prepared on one side of the Interposer wafer after unbonding; S4, cutting into single package chips; S5, attaching a capacitor resistor element on the upper surface of the substrate, then flip-chip reflow soldering the single package chip on the substrate, filling the corresponding multiple package chips on the substrate surface, and then placing the substrate in a jig for overall molding to obtain a peripheral molding layer; S6, polishing the molding layer until the heat sink is exposed; S7, BGA ball planting on the bottom of the substrate; S8, finally cutting into single package structures.

[0006] It is further characterized in that: In step S2, TIM glue is drawn on the exposed back of the upper layer chip, and then the heat sink is attached to the back of the chip and solidified; The height of the peripheral molding layer in step S5 is not higher than the molding layer, and then the molding layer on the upper layer of the package chip is polished until the heat sink is exposed through step S6; The height of the peripheral molding layer in step S5 is higher than the molding layer, and then the peripheral molding layer and the molding layer corresponding to the heat sink of the package chip are polished until the heat sink is exposed through step S6.

[0007] After adopting the above technical scheme, the Interposer wafer is used as a silicon adapter, which makes the bonding of the upper layer chip unnecessary for multiple materials, the warping of the upper layer chip after bonding is small, and the heat sink is attached to the back of the upper layer chip. Finally, the heat sink is exposed by polishing as a heat sink, the heat sink is rigid and not easy to bend, which provides mechanical support in the overall structure to improve the warping degree of the chip after molding, and the exposure of the heat sink improves the heat dissipation performance. In summary, it can optimize and improve the warping of the chip, improve the heat dissipation performance, and at the same time adopt the batch flip-chip reflow process, which can improve the yield and production efficiency while reducing the cost. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 The schematic diagram of step S1 of the method of the present application; Figure 2schematic diagram of step S2 of the method of the present application; Figure 3 schematic diagram of step S3 of the method of the present application; Figure 4 schematic diagram of step S4 of the method of the present application; Figure 5 schematic diagram of step S5 of the method of the present application; Figure 6 schematic diagram of step S6 of the method of the present application; Figure 7 schematic diagram of step S7 of the method of the present application; Figure 8 schematic diagram of step S8 of the method of the present application; The names corresponding to the serial numbers in the figure are as follows: Interposer wafer 1, temporary wafer 2, upper chip 3, first bottom filling layer 4, heat sink 5, plastic encapsulation layer 6, FC-bump 7, capacitor resistor element 8, substrate 9, second bottom filling layer 10, peripheral plastic encapsulation layer 11, ball planting 12. DETAILED DESCRIPTION

[0009] A 2.5D packaging method for improving chip warping and heat dissipation is shown in Figures 1-8 : First, the Interposer wafer 1 and the temporary wafer 2 are chain bonded, the upper chip 3 is flip-chip reflow soldered on the other side of the Interposer wafer 1, the bottom filling is performed to obtain the first bottom filling layer 4, the TIM glue is drawn on the exposed back surface of the upper chip 3, the heat sink 5 is attached and solidified, then the wafer plastic encapsulation and the temporary wafer 2 are disbonded, the RDL layer and the FC-bump 7 are prepared on the disbonded side of the Interposer wafer 1, and the single chip is cut; then the capacitor resistor element 8 is attached on the upper surface of the substrate 9, the single chip is flip-chip reflow soldered on the substrate 9, the bottom filling is performed, the multiple chips are placed in the jig for plastic encapsulation, the heat sink 5 is exposed by grinding on the surface of the plastic encapsulation material, the ball planting 12 is performed on the other side of the substrate 9, and finally the single circuit is cut.

[0010] It comprises the following steps: S1, the bottom layer of the Interposer wafer 1 and the temporary wafer 2 are temporarily bonded, the upper chip 3 is flip-chip reflow soldered on the upper surface of the Interposer wafer 1, and the bottom filling is performed to obtain the first bottom filling layer 4; S2, the heat sink 5 is attached on the exposed back surface of the upper chip 3, and the upper chip 4 and the Interposer wafer 1 are plastic encapsulated to obtain the plastic encapsulation layer 6; During the attachment of the heat sink 5, specifically, the TIM glue is drawn on the exposed back surface of the upper chip 3, and then the heat sink 5 is attached on the back surface of the upper chip 3 and solidified; S3, unbonding the plastic encapsulated Interposer wafer 1 and the temporary wafer 2, and preparing an RDL layer and FC-Bump 7 on the unbonded side of the Interposer wafer 1; S4, cutting into single package chips; S5, pasting a capacitor resistor element 8 on the upper surface of a substrate 9, and then flip-chip reflow soldering the single package chips on the substrate 9, filling the corresponding multiple package chips on the surface of the substrate 9 to obtain a second underfill layer 10, and then placing the substrate 9 in a jig for overall plastic encapsulation to obtain a peripheral plastic encapsulation layer 11; S6, grinding the plastic encapsulation layer 6 until the heat dissipation fins 5 are exposed; S7, BGA ball planting 12 on the bottom of the substrate 9; S8, finally cutting into single package structures.

[0011] In a specific implementation, when the height of the peripheral plastic encapsulation layer 11 in step S5 is not higher than the plastic encapsulation layer 6, the plastic encapsulation layer 6 on the upper layer of the package chip is then ground until the heat dissipation fins 5 are exposed in step S6; Or when the height of the peripheral plastic encapsulation layer 11 in step S5 is higher than the plastic encapsulation layer 6, the peripheral plastic encapsulation layer 11 and the plastic encapsulation layer 6 at the corresponding position of the heat dissipation fins 5 of the package chip are then ground until the heat dissipation fins are exposed.

[0012] The working principle is as follows: the Interposer wafer is used as a silicon adapter, which makes the bonding of the upper layer chip unnecessary to use multiple materials, the warping of the upper layer chip after bonding is small, and the heat dissipation fins are attached to the back of the upper layer chip. Finally, the heat dissipation fins are exposed by grinding to serve as heat dissipation. The heat dissipation fins are rigid and not easy to bend, and provide mechanical support in the overall structure to improve the warping degree of the chip after plastic encapsulation. In addition, the exposure of the heat dissipation fins improves the heat dissipation performance. In summary, the warping of the chip can be optimized and improved, the heat dissipation performance can be improved, and at the same time, the batch flip-chip reflow process is adopted to improve the yield and production efficiency while reducing the cost.

[0013] It is apparent for those skilled in the art that the present application is not limited to the details of the foregoing exemplary embodiments, and that the present application can be implemented in other particular forms without departing from the spirit or essential characteristics of the present application. Therefore, the foregoing embodiments should be considered in all respects as illustrative and not restrictive, and the scope of the present application should be defined by the appended claims rather than the foregoing description, and all changes coming within the meaning and equivalency range of the claims are intended to be embraced therein. Any reference signs in the claims should not be construed as limiting the claims to the figures in which the reference signs are used.

[0014] Furthermore, it should be understood that although the specification is described in terms of embodiments, not every embodiment includes every feature or implementation described herein. The specification can include implicit combinations of explicitly mentioned features and / or implicit combinations of implicitly mentioned features. Such combinations are also expressly included within the scope of the specification and an embodiment.

Claims

1. A 2.5D packaging method for improving chip warpage and heat dissipation, characterized in that: First, the interposer wafer is temporarily bonded. The upper-layer chip is flip-chip reflow soldered to the other side of the interposer wafer, and underfill is performed. TIM adhesive is applied to the back of the upper-layer chip, and a heat sink is attached and cured. Then, wafer molding and temporary wafer debonding are performed. An RDL layer and FC-Bump are prepared on the debonded side of the wafer and diced into individual chips. Next, capacitors and resistors are surface-mounted on the substrate, and the individual chips are flip-chip reflow soldered onto the substrate. Underfill is performed, and multiple substrates are placed in a fixture for molding. The heat sink is ground to expose the heat sink. Balls are placed on the other side of the substrate, and finally, the circuit is diced into individual circuits.

2. The 2.5D packaging method for improving chip warpage and heat dissipation according to claim 1, characterized in that, It includes the following steps: S1, Temporarily bond the bottom layer of the Interposer wafer and the temporary wafer, and then flip-chip is reflow soldered onto the top surface of the Interposer wafer and underfilled. S2, a heat sink is attached to the back of the exposed upper chip, and the upper chip and the Interposer wafer are encapsulated to obtain an encapsulation layer; S3, debond the molded Interposer wafer and the temporary wafer, and prepare the RDL layer and FC-Bump on the debonded side of the Interposer wafer; S4 is cut into single-packaged chips; S5, attach capacitor and resistor elements to the upper surface of the substrate, then flip-chip reflow solder a single packaged chip onto the substrate, fill the substrate area with multiple packaged chips corresponding to it, place the substrate in a fixture for overall molding, and obtain an outer molding layer. S6, grind the molding compound until the heat sink is exposed; S7, BGA balling is performed at the bottom of the substrate; The S8 was finally cut into a single-chip package structure.

3. The 2.5D packaging method for improving chip warpage and heat dissipation according to claim 2, characterized in that: In step S2, TIM adhesive is applied to the exposed back of the upper chip, and then the heat sink is attached to the back of the chip and cured.

4. The 2.5D packaging method for improving chip warpage and heat dissipation according to claim 2, characterized in that: In step S5, the height of the outer molding layer is not higher than the molding layer. Then, in step S6, the molding layer on the upper layer of the packaged chip is ground until the heat sink is exposed.

5. The 2.5D packaging method for improving chip warpage and heat dissipation according to claim 2, characterized in that: In step S5, the height of the outer plastic encapsulation layer is higher than that of the plastic encapsulation layer. Then, in step S6, the outer plastic encapsulation layer and the plastic encapsulation layer at the corresponding position of the heat sink of the packaged chip are ground until the heat sink is exposed.

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