Wafer stacking reconstruction process method and device

Abstract

The invention discloses a wafer stacking reconstruction process method and a wafer stacking reconstruction device. The wafer stacking reconstruction process method comprises the following steps: cutting a rectangular wafer in the center of a circular first wafer with a first size; the four vertexes of the rectangular wafer are all located on the circumference of the first wafer; etching at least two alignment marks on a second wafer with a second size, wherein the second size is greater than the first size; and carrying out positioning and bonding on the rectangular wafer and one alignment mark by using bonding equipment. According to the technical scheme provided by the embodiment of the invention, the wafer stacking efficiency and yield are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a wafer stacking reconstruction process method and device. BACKGROUND

[0002] When small-size wafers are stacked into large-size wafers, a large-size wafer needs to be provided with a large number of small-size wafers. In this process, because the wafers are small in size and large in number, the small-size wafers cannot be positioned to the correct position, and therefore, the existing wafer stacking method has low efficiency and yield. SUMMARY

[0003] The present application provides a wafer stacking reconstruction process method and device to solve the problem of low efficiency and yield of wafer stacking.

[0004] According to an aspect of the present application, a wafer stacking reconstruction process method is provided, comprising:

[0005] cutting a rectangular wafer at the central position of a first wafer of a first size in a circular shape; the four vertices of the rectangular wafer are located on the circumference of the first wafer;

[0006] etching at least two alignment marks on a second wafer of a second size, the second size being larger than the first size;

[0007] positioning and bonding the rectangular wafer with one of the alignment marks by using a bonding device.

[0008] Optionally, the cutting of the rectangular wafer at the central position of the first wafer of the first size in the circular shape comprises:

[0009] cutting a rectangular groove in the first wafer by laser grooving;

[0010] cutting the rectangular groove by plasma cutting and cutting the rectangular wafer.

[0011] Optionally, the first size is greater than or equal to 4 inches, and the second size is greater than or equal to 12 inches.

[0012] Optionally, before etching the at least two alignment marks on the second wafer of the second size, the method further comprises:

[0013] pre-cleaning the second wafer;

[0014] forming a first insulating medium film on the surface of the second wafer of the second size by chemical vapor deposition.

[0015] Optionally, the first wafer comprises silicon-based gallium nitride.

[0016] The step of positioning and bonding the rectangular wafer with an alignment mark using a bonding device includes:

[0017] The rectangular wafer is flipped so that one side of the rectangular wafer containing gallium nitride is positioned opposite the alignment mark;

[0018] The rectangular wafer is bonded to the position of the alignment mark on the second wafer.

[0019] Optionally, after positioning and bonding the rectangular wafer with one of the alignment marks using a bonding device, the process includes:

[0020] The silicon substrate of the rectangular wafer is removed by wet etching.

[0021] Optionally, after removing the silicon substrate of the rectangular wafer by wet etching, the method further includes:

[0022] Annealing is performed on the bonded rectangular wafer and the second wafer;

[0023] A second insulating dielectric film is formed on the surfaces of the rectangular wafer and the second wafer by chemical vapor deposition.

[0024] Optionally, before cutting a rectangular wafer at the center of a first circular wafer of the first size, the method further includes:

[0025] The first wafer is pre-cleaned.

[0026] According to another aspect of the present invention, a wafer stacking reconstruction apparatus is provided, which applies the wafer stacking reconstruction process method described in any embodiment of the present invention.

[0027] The technical solution provided by this invention cuts a rectangular wafer from a first wafer of a first size and stacks this large rectangular wafer onto a second wafer of a second size, making it easier to position and bond with the alignment marks on the second wafer. Furthermore, because there are fewer alignment marks on the second wafer, the stacking quality and efficiency between the rectangular wafer and the second wafer are higher, and there is less contamination during the transfer process. By constructing a rectangular wafer of the entire wafer size, the area limitations of traditional solutions are broken, and the stacking of multiple rectangular wafers with a single second wafer can be completed quickly.

[0028] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a flowchart of a wafer stacking reconstruction process provided by an embodiment of the present invention;

[0031] Figure 2 This is a dicing pattern of a first wafer provided according to an embodiment of the present invention;

[0032] Figure 3 This is a flowchart of another wafer stacking reconstruction process provided by an embodiment of the present invention;

[0033] Figure 4 This is a flowchart of another wafer stacking reconstruction process provided by an embodiment of the present invention;

[0034] Figure 5 This is a flowchart of another wafer stacking reconstruction process provided by an embodiment of the present invention;

[0035] Figure 6 This is a flowchart of another wafer stacking reconstruction process provided by an embodiment of the present invention. Detailed Implementation

[0036] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0037] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0038] This invention provides a process method for wafer stacking reconstruction. Figure 1 This is a flowchart illustrating a wafer stacking reconstruction process according to an embodiment of the present invention. (Reference) Figure 1 The process methods for wafer stacking reconstruction include:

[0039] S110. A rectangular wafer is cut out at the center of a first circular wafer of the first size; the four vertices of the rectangular wafer are all located on the circumference of the first wafer.

[0040] In the process of bonding and reconstructing multiple small wafers to another large wafer, if the area of ​​the small wafers is too small and the number is large, there will be a certain error between the alignment marks of the multiple small wafers and the large wafer during the positioning and bonding process, which will lead to a decrease in the bonding yield.

[0041] Therefore, this application cuts a rectangular wafer from the middle of a circular first wafer of a first size, and uses the larger rectangular wafer to bond with another wafer instead of the smaller wafer of the prior art.

[0042] Figure 2 This is a dicing pattern of a first wafer provided in an embodiment of the present invention. (Reference) Figure 2 The four vertices of the rectangular wafer 2 are all located on the circumference of the first wafer 1. The specific length and width of the rectangular wafer 2 can be set according to actual needs.

[0043] S120. Etch at least two alignment marks on a second wafer of a second size, the second size being larger than the first size.

[0044] The second wafer is larger than the first wafer, and therefore, the second wafer is also larger than the rectangular wafer. At least two alignment marks are etched on the second wafer to serve as positioning areas for the rectangular wafer. Therefore, at least two rectangular wafers can be stacked on the second wafer.

[0045] S130. Using bonding equipment, a rectangular wafer is positioned and bonded to an alignment mark.

[0046] Since a first wafer is cut into only one rectangular wafer, the rectangular wafer is relatively large, and the number of rectangular wafers corresponding to a second wafer is relatively small, the positioning speed and the positioning effect are faster when the alignment marks on the rectangular wafer and the second wafer are used for positioning.

[0047] For example, this application can employ vacuum bonding, a technique that tightly bonds a rectangular wafer and a second wafer together in a high-vacuum environment by precisely controlling temperature and pressure. Under vacuum conditions, interference from gas molecules is significantly reduced, contributing to improved bonding purity and strength, and enabling various bonding methods such as silicon-silicon, silicon-glass, and metal-metal bonding. Therefore, this application effectively reduces the impact of impurities on bonding, is adaptable to different types of chips, and exhibits high bonding quality.

[0048] The technical solution provided by this invention cuts a rectangular wafer from a first wafer of a first size and stacks this large rectangular wafer onto a second wafer of a second size, making it easier to position and bond with the alignment marks on the second wafer. Furthermore, because there are fewer alignment marks on the second wafer, the stacking quality and efficiency between the rectangular wafer and the second wafer are higher, and there is less contamination during the transfer process. By constructing a rectangular wafer of the entire wafer size, the area limitations of traditional solutions are broken, and the stacking of multiple rectangular wafers with a single second wafer can be completed quickly.

[0049] Figure 3 A flowchart illustrating another wafer stacking reconstruction process provided in an embodiment of the present invention. (See also...) Figure 3 Based on the above embodiments, optionally, S110, cutting a rectangular wafer at the center position of a first circular wafer of the first size includes:

[0050] S111. A rectangular groove is cut into the first wafer by laser grooving.

[0051] Laser grooving can form a rectangular groove structure on the material surface of the first wafer using laser energy. The rectangular groove is the cutting track. After cutting the cutting track, a rectangular wafer can be obtained.

[0052] S112. A rectangular groove is cut using plasma cutting to cut out a rectangular wafer.

[0053] Plasma dicing involves passing a mixture of gases through a high-frequency electric arc, causing some gases to decompose or ionize into basic atomic particles, thus generating plasma. The gas can be air or a mixture of hydrogen, argon, and nitrogen. The electric arc then jumps to a rectangular groove, where high-pressure gas blows the plasma out. The high temperature generated when the various gases in the plasma return to their normal state rapidly melts the rectangular groove.

[0054] The embodiments of the present invention, through the combination of laser grooving and plasma cutting, greatly reduce or eliminate chips, delamination, and other cutting quality problems, thereby improving the cutting effect.

[0055] Based on the above embodiments, optionally, the first size is greater than or equal to 4 inches, and the second size is greater than or equal to 12 inches.

[0056] For example, when the second wafer is 12 inches, the first wafer can be 4-8 inches. 4-6 alignment marks are set on a second wafer, and 4-6 rectangular wafers cut from the first wafer are stacked on it.

[0057] The technical solution provided by the embodiments of the present invention stacks multiple large-sized rectangular wafers on the second wafer. Because the number of rectangular wafers is small, the rectangular wafers have a more accurate positioning and alignment effect when they are positioned and bonded with the alignment marks on the second wafer, which greatly improves the yield and bonding effect of the rectangular wafers to the second wafer.

[0058] Figure 4 This is a flowchart illustrating another wafer stacking reconstruction process provided in an embodiment of the present invention. (See reference...) Figure 4 Based on the above embodiments, optionally, before etching at least two alignment marks on a second wafer of a second size, S120 further includes:

[0059] S140. Pre-clean the second wafer.

[0060] Pre-cleaning before bonding is a key process step in semiconductor packaging, electronic device manufacturing and other fields. Its purpose is to remove contaminants, oxide layers and other substances from the bonding surface to ensure a clean bonding interface, thereby improving bonding strength, reliability and device performance.

[0061] S150, a first insulating dielectric film is formed on the surface of a second wafer of a second size by chemical vapor deposition.

[0062] In this process, after pre-cleaning, a first insulating dielectric film is formed by chemical vapor deposition (CVD) through a chemical reaction between gaseous substances and the solid surface. For example, the first insulating dielectric film can be a silicon dioxide thin film.

[0063] By covering the surface of the second wafer with a first insulating dielectric film, the hydrophilicity and cleanliness of the second wafer surface can be improved, thereby enhancing the bonding effect between the rectangular wafer and the second wafer.

[0064] Figure 5 This is a flowchart illustrating another wafer stacking reconstruction process provided in an embodiment of the present invention. (See reference...) Figure 5 Based on the above embodiments, optionally, the first wafer includes: gallium nitride on silicon. S130, positioning and bonding the rectangular wafer to an alignment mark using a bonding device includes:

[0065] S131. Flip the rectangular wafer so that one side of the rectangular wafer containing gallium nitride is aligned with the alignment mark.

[0066] S132, Bond the rectangular wafer to the alignment mark position on the second wafer.

[0067] In this process, when bonding the rectangular wafer to the second wafer, only the side of the rectangular wafer containing gallium nitride (GaN) needs to be bonded to the second wafer. Therefore, before bonding, the rectangular wafer needs to be flipped so that the side containing GaN is face-to-face with the second wafer, and the rectangular wafer needs to be aligned with the alignment marks. This arrangement avoids bonding failures caused by material differences.

[0068] Figure 6 This is a flowchart illustrating another wafer stacking reconstruction process provided in an embodiment of the present invention. (See reference...) Figure 6 Based on the above embodiments, optionally, after S130, where the rectangular wafer is positioned and bonded to an alignment mark using a bonding device, the process includes:

[0069] S160, Remove the silicon substrate from the rectangular wafer by wet etching.

[0070] In this process, after the rectangular wafer is bonded to the second wafer, the silicon substrate on the rectangular wafer has no function in subsequent use and needs to be removed.

[0071] Wet etching removes silicon by reacting with chemical reagents to oxidize, dissolve, or complex with the silicon surface, without affecting gallium nitride.

[0072] Continue to refer to Figure 6Based on the above embodiments, optionally, after S160, where the silicon substrate of the rectangular wafer is removed by wet etching, the method further includes:

[0073] S170. Anneal the bonded rectangular wafer and the second wafer.

[0074] S180. A second insulating dielectric film is formed on the surface of a rectangular wafer and a second wafer by chemical vapor deposition.

[0075] Annealing refers to the process of heating the bonding interface after the bonding process is completed. Its purpose is to promote atomic diffusion, eliminate interfacial stress, and improve the bonding strength and reliability between the rectangular wafer and the second wafer through thermal activation.

[0076] After annealing, a second insulating dielectric film can be formed by chemical vapor deposition, which can isolate the rectangular wafer and the second wafer from the external environment and prevent air from corroding the bonded rectangular wafer and the second wafer.

[0077] Based on the above embodiments, optionally, before cutting a rectangular wafer at the center position of the first circular wafer of the first size in S110, the method further includes: pre-cleaning the first wafer.

[0078] By pre-cleaning the first wafer, the cleanliness of the first wafer before bonding can be ensured, thereby improving bonding strength, reliability and device performance.

[0079] This invention also provides a wafer stacking reconstruction apparatus. The wafer stacking reconstruction process provided in any embodiment of this invention has similar beneficial effects to the wafer stacking reconstruction process, and will not be described in detail here.

[0080] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0081] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A process for reconstructing wafer stacking, characterized in that, include: A rectangular wafer is cut out from the center of a first circular wafer of the first size; The four vertices of the rectangular wafer are all located on the circumference of the first wafer; At least two alignment marks are etched on a second wafer of a second size, which is larger than the first size; The rectangular wafer is positioned and bonded to an alignment mark using a bonding device.

2. The wafer stacking reconstruction process according to claim 1, characterized in that, The process of cutting a rectangular wafer at the center of a first circular wafer of a first size includes: A rectangular groove is cut into the first wafer using laser grooving. The rectangular groove is cut using plasma cutting, and the rectangular wafer is cut out.

3. The wafer stacking reconstruction process according to claim 1, characterized in that, The first size is greater than or equal to 4 inches, and the second size is greater than or equal to 12 inches.

4. The wafer stacking reconstruction process according to claim 1, characterized in that, Prior to etching at least two alignment marks on a second wafer of a second size, the process also includes: The second wafer is pre-cleaned; On the surface of the second wafer of the second size, a first insulating dielectric film is formed by chemical vapor deposition.

5. The wafer stacking reconstruction process according to claim 1, characterized in that, The first wafer comprises: gallium nitride on silicon; The step of positioning and bonding the rectangular wafer with an alignment mark using a bonding device includes: The rectangular wafer is flipped so that one side of the rectangular wafer containing gallium nitride is positioned opposite the alignment mark; The rectangular wafer is bonded to the position of the alignment mark on the second wafer.

6. The wafer stacking reconstruction process according to claim 5, characterized in that, After positioning and bonding the rectangular wafer with one of the alignment marks using a bonding device, the process includes: The silicon substrate of the rectangular wafer is removed by wet etching.

7. The wafer stacking reconstruction process according to claim 6, characterized in that, After removing the silicon substrate of the rectangular wafer by wet etching, the process further includes: Annealing is performed on the bonded rectangular wafer and the second wafer; A second insulating dielectric film is formed on the surfaces of the rectangular wafer and the second wafer by chemical vapor deposition.

8. The wafer stacking reconstruction process according to claim 1, characterized in that, Before cutting a rectangular wafer at the center of a first circular wafer of the first size, the process also includes: The first wafer is pre-cleaned.

9. A wafer stacking reconstruction apparatus, characterized in that, The wafer stacking reconstruction process method according to any one of claims 1-8.

Images