Wafer stacking structure forming method and wafer stacking structure

Abstract

The invention relates to the technical field of wafer processing, in particular to a wafer stacking structure forming method and a wafer stacking structure. The forming method comprises the following steps: sequentially stacking N wafers to form a wafer stacking structure; the stacking of any ith wafer from the bottom to the top and the (i-1) th wafer comprises the following steps: trimming the partial thickness of the ith wafer inwards from the edge, so that the trimmed ith wafer forms a boss structure, the boss structure comprises a base body part and a boss part, and the horizontal size of the base body part is larger than that of the boss part; enabling the boss part to face the surface of the (i-1) th wafer, and forming a stacked intermediate with a tower-shaped structure with the (i-1) th wafer; the stacked intermediate is thinned, and the whole thickness of the base body part is removed; and repeating the steps until the (i = N) th wafer is stacked. According to the forming method, the tower-shaped structure instead of a columnar structure is finally formed, so that a large effective area of the wafer is saved, and the loss of the effective area of the wafer is reduced.

Description

Technical Field

[0001] This invention relates to the field of wafer fabrication technology, and more specifically to a method for forming a wafer stacking structure and a wafer stacking structure. Background Technology

[0002] In multi-wafer stacking processes, multiple wafers are stacked sequentially to form a wafer stack structure. During each stacking process, the top wafer often has "suspended" edges on both sides. These suspended edges are prone to "edge chipping" (i.e., edge breakage) during subsequent thinning processes. Therefore, "trimming" is required after each new wafer is added to the stack structure, removing the wafer area extending beyond the connection point between the top and bottom wafers. This results in a significant loss of effective area in the final wafer stack structure. Summary of the Invention

[0003] In view of this, the present invention provides a method for forming a wafer stacking structure and a wafer stacking structure to solve the problem of large effective area loss in the final wafer stacking structure in the multi-wafer stacking process.

[0004] This invention provides a method for forming a wafer stacking structure, wherein N wafers are stacked sequentially to form a wafer stacking structure; where N is a natural number greater than or equal to 3; for any i-th wafer from bottom to top, 2≤i≤N, i is a natural number, the stacking of the i-th wafer with the (i-1)-th wafer includes the following steps: trimming a portion of the thickness of the i-th wafer from the edge inwards, so that the trimmed i-th wafer forms a boss structure, the boss structure including a base portion and a boss portion on the surface of the base portion, the horizontal dimension of the base portion being greater than the horizontal dimension of the boss portion; aligning the boss portion of the trimmed i-th wafer with the surface of the (i-1)-th wafer to form a tower-like stacking intermediate with the (i-1)-th wafer; thinning the stacking intermediate and removing the entire thickness of the base portion; repeating the above steps until the stacking of the i=N-th wafers is completed, forming a tower-like wafer stacking structure.

[0005] Optionally, the step of forming a stacked intermediate with the i-th wafer, with the trimmed protrusion facing the surface of the (i-1)th wafer, includes: after forming the protrusion, forming an i-th upper bonding layer on the surface of the i-th wafer, the i-th upper bonding layer covering the surface of the protrusion facing away from the substrate; forming an i-th lower bonding layer on the surface of the (i-1)th wafer; and in the step of forming the stacked intermediate with the i-th wafer, the i-th upper bonding layer and the i-th lower bonding layer are mated and bonded.

[0006] Optionally, the i-th upper bonding layer further covers the side portion of the boss portion; the sum of the horizontal dimension of the boss portion of the i-th wafer and the horizontal dimension of the i-th upper bonding layer on its side is less than the horizontal dimension of the (i-1)-th wafer.

[0007] Optionally, in the step of trimming the i-th wafer to form the boss structure, the i-th wafer is cut to form the boss by mechanical processing; or, a portion of the edge of the wafer is removed by etching to form the boss.

[0008] Optionally, in the step of thinning the stacked intermediate and removing the entire thickness of the matrix portion, the entire matrix portion is removed by chemical mechanical polishing.

[0009] Optionally, the i-th upper bonding layer and the i-th lower bonding layer include SiO2 bonding layers.

[0010] Optionally, during the process of trimming the i-th wafer inward to form a boss structure, the horizontal dimension of the removed portion accounts for 1 / 150 to 1 / 30 of the horizontal dimension of the i-th wafer.

[0011] Optionally, the thickness of the boss portion accounts for 10 / 11 to 76 / 77 of the thickness of the i-th wafer.

[0012] The present invention also provides a wafer stacking structure, comprising N wafers stacked sequentially; wherein N is a natural number greater than or equal to 3; for any i-th wafer from bottom to top, 2≤i≤N, i is a natural number, the horizontal dimension of the i-th wafer is smaller than the horizontal dimension of the (i-1)-th wafer and larger than the horizontal dimension of the (i+1)-th wafer, forming a tower-like stacking structure.

[0013] Optionally, the surfaces of the i-th wafer and the (i-1)-th wafer are bonded together by the i-th bonding layer; the i-th bonding layer includes the i-th upper bonding layer on the surface of the i-th wafer and the i-th lower bonding layer on the surface of the (i-1)-th wafer.

[0014] Optionally, the horizontal dimension of the i-th upper bonding layer is the same as the horizontal dimension of the i-th lower bonding layer, and both are smaller than the horizontal dimension of the (i-1)-th wafer.

[0015] Optionally, the i-th upper bonding layer covers the surface of the i-th wafer facing the (i-1)-th wafer and also covers the side portion of the i-th wafer.

[0016] Optionally, in the wafer stacking structure, the bottommost wafer is a carrier wafer; the wafers above the bottommost wafer are functional wafers, including memory structure wafers.

[0017] The beneficial effects of this invention are as follows: The method for forming a wafer stacking structure provided by this invention only performs pre-stack trimming on the i-th wafer to form a base portion and a boss portion. The boss portion is stacked with the (i-1)-th wafer. After stacking, the base portion is removed by the thinning process that would have been required earlier. In this way, the remaining boss portion does not have a "suspended" part, that is, it does not require post-stack trimming, nor does it require removing the side portion of the underlying wafer, i.e., the i-th wafer. Finally, a tower-like structure is formed. Therefore, the portion removed by pre-stack trimming can be much smaller than the portion removed by post-stack trimming, and the area of ​​each layer of wafers can be preserved to a greater extent, thus forming a tower-like structure rather than a columnar structure, preserving more effective wafer area and reducing the loss of effective wafer area.

[0018] The wafer stacking structure provided by this invention forms a tower-like stacking structure, in which the area of ​​each layer of wafers can be preserved to a greater extent. Compared with the columnar structure, it preserves more effective wafer area and reduces the loss of effective wafer area. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings used in the description of the specific embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0020] Figures 1A-1E This is a schematic diagram showing the state of the i-th and (i-1)-th wafers when they are stacked and bonded in a wafer stacking structure according to one embodiment.

[0021] Figures 2-6 This is a schematic diagram of the state of each step in the process of stacking and bonding the i-th wafer with the (i-1)-th wafer in a wafer stacking structure formation method according to an embodiment of the present invention.

[0022] Figure 7 This is a schematic diagram of a wafer stacking structure according to an embodiment of the present invention;

[0023] Figure 8 This is a schematic flowchart of a method for forming a wafer stacked structure according to an embodiment of the present invention. Detailed Implementation

[0024] In a wafer stacking process, for the first wafer 100 and the second wafer 200 from bottom to top, i.e., when i = 2, refer to the following case. Figures 1A-1EBecause the second wafer 200 is connected to the first wafer 100 via a connecting layer 300, and the area of ​​the connecting layer 300 is smaller than that of the first wafer 100 and the second wafer 200, the second wafer 200 has a "dangling" edge. Figure 1A (At the dashed box area), to ensure stability and prevent edge chipping during thinning, the excess portion of the upper and lower wafers needs to be removed, for example... Figure 1B The position of the dashed box. (Refer to the image after removal.) Figure 1C The edges of the top and bottom wafers are consistent and there are no overhanging areas, thus preventing edge chipping during wafer thinning. The same reason applies when stacking a third 400 wafer; see reference [link to relevant documentation]. Figure 1D The upper and lower wafers need to be trimmed again to remove the overhanging parts, forming... Figure 1E The stacked structure. As the number of wafers in the stacked structure increases, it becomes like... Figures 1A-1E As shown, the wafer area is continuously reduced, eventually forming a columnar structure based on the area of ​​the topmost wafer after its edge is clipped. This results in a significant loss of the wafer's effective area.

[0025] To address the above problems, this invention provides a method for forming a wafer stacking structure and a wafer stacking structure.

[0026] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. In the description of the present invention, it should be noted that the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0027] Example 1

[0028] This embodiment provides a method for forming a wafer stacking structure.

[0029] N wafers are stacked sequentially to form a wafer stacking structure; where N is a natural number greater than or equal to 3.

[0030] For any i-th wafer from bottom to top, 2≤i≤N, where i is a natural number, its stacking with the (i-1)-th wafer is shown in the reference. Figure 8 ,as well as Figures 2-7 This includes the following steps:

[0031] For a portion of the thickness of the i-th wafer, trim the edge inwards to form a boss structure on the trimmed i-th wafer. The boss structure includes a base portion and a boss portion on the surface of the base portion. The horizontal dimension of the base portion is greater than the horizontal dimension of the boss portion.

[0032] The protrusion of the trimmed i-th wafer is oriented toward the surface of the (i-1)-th wafer, forming a stacked intermediate with the (i-1)-th wafer in a tower-like structure;

[0033] Thin the stacked intermediate body and remove the entire thickness of the base portion;

[0034] Repeat the above steps until the i=Nth wafer is stacked, forming a tower-like wafer stack structure.

[0035] A tower-like structure refers to a multi-layered structure from bottom to top, in which the horizontal dimension of the upper layer is always smaller than the horizontal dimension of the lower layer in any two adjacent layers.

[0036] Taking i=2 as an example, refer to Figure 2 For a portion of the thickness of the second wafer 200, the edge is trimmed inward from the edge, so that the trimmed second wafer forms a boss structure. The boss structure includes a base portion 210 and a boss portion 220 on the surface of the base portion. The horizontal dimension of the base portion 210 is greater than the horizontal dimension of the boss portion 220.

[0037] refer to Figure 5 The protrusion 220 of the trimmed second wafer 200 is oriented toward the surface of the first wafer 100, forming a stacked intermediate with the first wafer 100 in a tower-like structure.

[0038] refer to Figure 6 The intermediate stack is thinned, and the entire thickness of the base portion 210 is removed until only the boss portion 220 remains connected to the first wafer 100.

[0039] For the third and fourth wafers, the structure of the first wafer 100 is compared to that of the first wafer 100, and the subsequent wafers are compared to that of the second wafer 200. The above steps are repeated, with the bosses of the third wafer 400 and the bosses of the fourth wafer 600 stacked upwards to form a structure as shown above. Figure 7 The tower-like stacking structure is used until the required number of wafers are stacked.

[0040] The wafer stacking structure formation method provided in this embodiment only performs pre-stack trimming on the i-th wafer to form a base portion and a boss portion. The boss portion is then stacked with the (i-1)-th wafer. After stacking, the base portion is removed through the thinning process that would have been required earlier. This leaves no "suspended" portion on the remaining boss portion, eliminating the need for post-stack trimming and side removal of the underlying wafer (i-th wafer). The final stacked structure forms a tower-like structure. Therefore, the portion removed during pre-stack trimming is much smaller than the portion removed after stacking, allowing for greater preservation of the wafer area in each layer. This results in a tower-like structure rather than a columnar structure, preserving more effective wafer area and reducing wafer area loss.

[0041] In some embodiments, the step of forming a stacked intermediate with the (i-1)th wafer, with the trimmed boss portion facing the surface of the (i-1)th wafer, includes:

[0042] After the protrusion is formed, an i-th upper bonding layer is formed on the i-th wafer surface, the i-th upper bonding layer covering the surface of the protrusion facing away from the substrate.

[0043] The i-th lower bonding layer is formed on the surface of the (i-1)-th wafer;

[0044] In the step of forming a stacked intermediate between the i-th wafer and the (i-1)-th wafer, the i-th upper bonding layer is docked and bonded to the i-th lower bonding layer.

[0045] by Figures 2-7 Taking the process as an example, the diagram shows a wafer stack structure formed by 3-4 wafers, which is for illustrative purposes only. In practical applications, other numbers of wafers can be stacked, and it is not limited to a stack of 3-4 wafers.

[0046] The step of forming a stacked intermediate with the first wafer 100, with the protrusion 220 of the trimmed second wafer 200 facing the surface of the first wafer 100, includes:

[0047] refer to Figure 3 After the boss portion 220 is formed, a second upper bonding layer 320 is formed on the second wafer surface. The second upper bonding layer 320 covers the surface of the boss portion 220 facing away from the substrate portion 210 and covers the side portion of the boss portion 220.

[0048] refer to Figure 4 A second lower bonding layer 310 is formed on the surface of the first wafer 100 to be stacked wafers;

[0049] refer to Figure 5In the step of forming a stacked intermediate between the second wafer 200 and the first wafer 100, the second upper bonding layer 320 is docked and bonded to the second lower bonding layer 310 to achieve a fixed connection between the first wafer 100 and the second wafer 200.

[0050] The bonding layer connects the two wafers, and also covers the sides of the boss, widening its size to some extent. This provides support for subsequent substrate removal and protects the boss. Furthermore, by expanding the area of ​​this layer, the size that needs to be trimmed inwards during the next wafer stacking is reduced, further saving effective wafer stacking area.

[0051] In some embodiments, the sum of the horizontal dimension of the boss portion of the i-th wafer and the horizontal dimension of the i-th upper bonding layer on its side is less than the horizontal dimension of the (i-1)-th wafer.

[0052] In some other embodiments, the i-th upper bonding layer may only cover the surface of the i-th wafer facing away from the substrate, without covering the side portion of the boss. This simplifies the processing and helps to save the total process time.

[0053] by Figure 4 For example, the sum of the horizontal dimension of the boss 220 of the second wafer 200 and the horizontal dimension of the second upper bonding layer 320 on its side is less than the horizontal dimension of the first wafer 100. If it is equal to or greater than the horizontal dimension of the first wafer 100, on the one hand, during bonding processing, it will "overflow" downwards, causing it to wrap around the wafer below, making the shape of the wafer below unstable and changing the supporting stress on the wafer above, which will easily cause unnecessary interference in subsequent processing. It will also create a "suspended" structure, which will cause cracking during subsequent thinning processes, resulting in wafer cracks or breakage and unnecessary losses.

[0054] In some embodiments, in the step of trimming the i-th wafer to form a boss structure, the i-th wafer is cut to form the boss by mechanical processing; or, a portion of the edge of the wafer is removed by etching to form the boss.

[0055] The trimming process using machining is convenient and easy to implement; it simply involves using a suitable tool to perform rotary cutting according to the design dimensions. In other embodiments, etching can also be used to remove the desired edge portion, forming a boss.

[0056] In some embodiments, in the step of thinning the stacked intermediate and removing the entire thickness of the matrix portion, the entire matrix portion is removed by chemical mechanical polishing.

[0057] refer to Figure 6 The entire thickness of the substrate 210 is removed by chemical mechanical polishing, and the remaining boss 220 is connected to the first wafer 100 below it by a bonding layer. Since wafer stacking originally requires a thinning process, removing the substrate by thinning also removes the "suspended" edge parts, saving process steps.

[0058] In some embodiments, the i-th upper bonding layer and the i-th lower bonding layer comprise SiO2 bonding layers. SiO2 serves as a bonding layer for wafer stacking; the wafer is typically made of Si, and SiO2 has similar structural properties and is easily bonded through processing. In other embodiments, bonding layers may also be formed from materials of other elements.

[0059] In some implementations, during the process of trimming the i-th wafer inward to form a boss structure, the horizontal dimension of the removed portion accounts for 1 / 150 to 1 / 30 of the horizontal dimension of the i-th wafer. If the removed dimension is too large, the dimension to be removed in each step increases, resulting in a corresponding increase in the final effective wafer area loss. If the removed dimension is too small, it is difficult to cover the bonding layer, and "dangling" edges are likely to appear after bonding, requiring additional removal steps. Therefore, a horizontal dimension of the removed portion within the range of 1 / 150 to 1 / 30 of the horizontal dimension of the i-th wafer can achieve a balance between maintaining as much effective wafer area as possible and avoiding "dangling" edges.

[0060] Specifically, taking a 300nm wafer as an example, the edge trimming on one side is about 1mm-5mm indentation; for a wafer, the ring trimming is equivalent to trimming the edges inward on both sides, so the total horizontal size removal is 2mm-10mm.

[0061] In some embodiments, the thickness of the boss portion accounts for 10 / 11 to 76 / 77 of the thickness of the i-th wafer. For example, the wafer thickness is approximately 770 μm, and the boss portion thickness is approximately 700 μm to 760 μm. If the boss portion is too small, the thickness to be removed during thinning is too large, affecting the internal structure of the wafer; if the boss portion thickness is too small, it is difficult to process. Therefore, a boss portion thickness in the range of 700 μm to 760 μm strikes a balance between avoiding impact on the internal structure of the wafer and ease of processing.

[0062] Example 2

[0063] This embodiment provides a wafer stacking structure, comprising N wafers stacked sequentially; where N is a natural number greater than or equal to 3;

[0064] For any i-th wafer from bottom to top, 2≤i≤N, where i is a natural number, the horizontal dimension of the i-th wafer is smaller than the horizontal dimension of the (i-1)-th wafer and larger than the horizontal dimension of the (i+1)-th wafer, forming a tower-like stacked structure.

[0065] A tower-like structure refers to a multi-layered structure from bottom to top, in which the horizontal dimension of the upper layer is always smaller than the horizontal dimension of the lower layer in any two adjacent layers.

[0066] refer to Figure 7 Taking N=4 as an example, the stacked structure has a total of 4 layers. For example, when i=3, the horizontal dimension of the 3rd wafer 400 is smaller than the horizontal dimension of the 2nd wafer 200 and larger than the horizontal dimension of the 4th wafer 600.

[0067] The wafer stacking structure provided in this embodiment forms a tower-like stacking structure. Compared with a columnar stacking structure, the area of ​​each layer of wafers can be preserved to a greater extent, thus retaining more effective wafer area and reducing the loss of effective wafer area.

[0068] In some embodiments, the surfaces of the i-th wafer and the (i-1)-th wafer are bonded together by the i-th bonding layer; the i-th bonding layer includes the i-th upper bonding layer on the surface of the i-th wafer and the i-th lower bonding layer on the surface of the (i-1)-th wafer.

[0069] In some implementations, the horizontal dimension of the i-th upper bonding layer is the same as the horizontal dimension of the i-th lower bonding layer, and both are smaller than the horizontal dimension of the (i-1)-th wafer. The identical horizontal dimensions of the upper and lower bonding layers prevent the formation of "dangling" edge regions after bonding, thus maintaining stable support from below to above, and eliminating the need for additional "trimming" steps.

[0070] In some embodiments, the i-th upper bonding layer covers the surface of the i-th wafer facing the (i-1)-th wafer and also covers the side portion of the i-th wafer. In other embodiments, the i-th upper bonding layer may only cover the surface of the i-th wafer facing the (i-1)-th wafer, without covering the side portion of the i-th wafer.

[0071] In some embodiments, in the wafer stacking structure, the bottommost wafer 100 is a carrier wafer; the wafers above the bottommost wafer 100 are functional wafers, including memory structure wafers. The carrier wafer provides only a carrying function and does not have any internal devices or design structures such as scribes or grooves. A functional wafer refers to a wafer with pre-embedded devices or scribes of specific structures or circuits to achieve a corresponding function. A memory structure wafer refers to a wafer with specific structures for implementing data storage functions.

[0072] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1.A method for forming a wafer stack structure, comprising: stacking N wafers sequentially to form a wafer stack structure, wherein N is a natural number greater than or equal to 3; for any i th wafer from bottom to top, 2≤i≤N, i is a natural number, the stacking of the i th wafer and the (i-1) th wafer comprises the following steps: trimming the i th wafer inwardly from the edge to a partial thickness, so that the trimmed i th wafer forms a boss structure, the boss structure comprises a base part and a boss part on the surface of the base part, the horizontal size of the base part is greater than the horizontal size of the boss part; aligning the boss part of the trimmed i th wafer towards the surface of the (i-1) th wafer to form a tower structure intermediate stack with the (i-1) th wafer; thinning the tower structure intermediate stack to remove the base part of the whole thickness; repeating the above steps until the stacking of the i=N th wafer is completed to form a wafer stack structure in a tower structure. 2.The method for forming a wafer stack structure according to claim 1, wherein the step of aligning the boss part of the trimmed i th wafer towards the surface of the (i-1) th wafer to form a tower structure intermediate stack with the (i-1) th wafer comprises: forming an i th upper bonding layer on the surface of the i th wafer after forming the boss part, the i th upper bonding layer covers the surface of the boss part away from the base part; forming an i th lower bonding layer on the surface of the (i-1) th wafer; in the step of forming a tower structure intermediate stack with the i th wafer and the (i-1) th wafer, the i th upper bonding layer and the i th lower bonding layer are bonded in abutment. 3.The method for forming a wafer stack structure according to claim 2, wherein the i th upper bonding layer also covers the side part of the boss part; the sum of the horizontal size of the boss part of the i th wafer and the horizontal size of the i th upper bonding layer on the side part of the boss part is less than the horizontal size of the (i-1) th wafer. 4.The method for forming a wafer stack structure according to claim 1, wherein in the step of trimming the i th wafer to form a boss structure, the boss part is formed by cutting the i th wafer through mechanical processing; or, the boss part is formed by removing part of the edge of the wafer through etching. 5.The method for forming a wafer stack structure according to claim 1, wherein in the step of thinning the tower structure intermediate stack to remove the base part of the whole thickness, the base part is removed through chemical mechanical polishing. 6.The method for forming a wafer stack structure according to claim 2, wherein the i th upper bonding layer and the i th lower bonding layer comprise SiO 2 bonding layers. 7.The method for forming a wafer stack structure according to claim 1, wherein in the process of trimming the i th wafer inwardly to form a boss structure, the horizontal size of the removed part accounts for 1 / 150 to 1 / 30 of the horizontal size of the i th wafer. 8.The method for forming a wafer stack structure according to claim 1, wherein ​ ​ ​ ​ ​ ​ The thickness of the boss part accounts for 10 / 11 to 76 / 77 of the thickness of the i-th wafer. 9.A wafer stack structure, comprising: N wafers stacked in sequence, wherein N is a natural number greater than or equal to 3; For any i-th wafer from bottom to top, 2≤i≤N, i is a natural number, the horizontal size of the i-th wafer is smaller than that of the i-1-th wafer and larger than that of the i+1-th wafer, forming a tower-like stack structure. 10.The wafer stack structure of claim 9, wherein: The i-th wafer and the i-1-th wafer are bonded by an i-th bonding layer; The i-th bonding layer comprises an i-th upper bonding layer on the surface of the i-th wafer and an i-th lower bonding layer on the surface of the i-1-th wafer. 11.The wafer stack structure of claim 10, wherein: The horizontal size of the i-th upper bonding layer is the same as that of the i-th lower bonding layer, and both are smaller than the horizontal size of the i-1-th wafer. 12.The wafer stack structure of claim 11, wherein: The i-th upper bonding layer covers the surface of the i-th wafer facing the i-1-th wafer and covers the side of the i-th wafer. 13.The wafer stack structure of claim 9, wherein: In the wafer stack structure, the lowermost wafer is a carrier wafer; The wafers above the lowermost wafer are functional wafers, including a storage structure wafer.

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