Multi-path amplification circuit for operating in different power modes

Abstract

Certain aspects of the present disclosure generally relate to an amplification circuit. The amplification circuit generally includes: a first amplification path (490) including a first amplification transistor (460) and coupled between an input node of the amplification circuit and an output node of the amplification circuit; and a second amplification path (492) comprising a second amplification transistor (486) and coupled between the input node and the output node, where the second amplification path (492) further comprises an attenuator (452, 482, 480) coupled between the input node of the amplification circuit and a control input of the second amplification transistor (486).

Description

Cross Reference to Related Applications

[0001] This application claims priority to U.S. Patent Application No. 18 / 338,729, filed June 21, 2023, which is hereby incorporated by reference herein. TECHNICAL FIELD

[0002] Certain aspects of the present disclosure generally relate to electronic assemblies, and more particularly to circuits for signal amplification. BACKGROUND

[0003] Electronic devices include computing devices such as desktop computers, notebook computers, tablet computers, smartphones, wearable devices such as smartwatches, internet servers, and the like. These various electronic devices provide information, entertainment, social interaction, security, safety, productivity, transportation, manufacturing, and other services to human users. Many of the functions of these various electronic devices rely on wireless communication. Wireless communication systems and devices are widely deployed to provide various types of communication content such as voice, video, packet data, messaging, broadcast, and the like. These systems can be capable of supporting communication for multiple users by sharing the available system resources (e.g., time, frequency, and power). Examples of such systems include Code Division Multiple Access (CDMA) systems, Time Division Multiple Access (TDMA) systems, Frequency Division Multiple Access (FDMA) systems, and Orthogonal Frequency Division Multiple Access (OFDMA) systems, such as a Long Term Evolution (LTE) system, or a New Radio (NR) system. A wireless device can include a transmitter for processing a signal for transmission via an antenna. The transmitter can include a power amplifier (PA) for amplifying a signal for transmission. SUMMARY

[0004] The systems, methods, and devices of the present disclosure each have several aspects, no single one of which is solely responsible for its desirable attributes. Without limiting the scope of this disclosure as expressed by the claims which follow, some features will now be discussed briefly. The instant disclosure will be described with reference to a variety of specific language to describe certain aspects. Those skilled in the art will appreciate that the language chosen is for the purpose of clarity and that the scope of the present disclosure would not be termi nated thereby.

[0005] Certain aspects of the present disclosure relate to an amplification circuit. The amplification circuit generally includes a first amplification path including a first amplification transistor and coupled between an input node of the amplification circuit and an output node of the amplification circuit, and a second amplification path coupled between the input node and the output node of the amplification circuit and including a second amplification transistor and an attenuator coupled between the input node of the amplification circuit and a control input of the second amplification transistor.

[0006] Some aspects of this disclosure relate to a method for signal amplification. The method generally includes: determining a power mode for an amplifier circuit; selecting a first amplification path or a second amplification path based on the determined power mode, wherein the first amplification path includes a first amplifying transistor coupled to an output node of the amplifier circuit, and wherein the second amplification path includes a second amplifying transistor coupled to the output node and an attenuator coupled to a control input portion of the second amplifying transistor; and amplifying an input signal via the first amplification path or the second amplification path based on the selection.

[0007] Some aspects of this disclosure relate to an apparatus for signal amplification. The apparatus generally includes: a first component for amplifying an input signal at an input node, the first component for amplification being coupled between the input node and an output node; a component for attenuating the input signal to produce an attenuated signal, the attenuation component being coupled to the input node; and a second component for amplifying the attenuated signal, the second component for amplification being coupled between the attenuation component and the output node.

[0008] To achieve the foregoing and related objectives, one or more aspects include the features fully described below and specifically pointed out in the claims. The following description and drawings illustrate certain exemplary features of one or more aspects in detail. However, these features indicate only a few of the various ways in which the principles of the various aspects can be employed. Attached Figure Description

[0009] To gain a more detailed understanding of the foregoing features of this disclosure, a more specific description, some of which is illustrated in the accompanying drawings, may be obtained by referring to various aspects. However, it should be noted that the drawings illustrate only certain aspects of this disclosure and should therefore not be considered as limiting its scope, as the description may allow for other equivalent aspects.

[0010] Figure 1 This is a diagram illustrating an example wireless communication network based on certain aspects of this disclosure.

[0011] Figure 2 This is a block diagram of an example access point (AP) and an example user terminal based on certain aspects of this disclosure.

[0012] Figure 3 This is a block diagram of an example transceiver front end based on certain aspects of this disclosure.

[0013] Figure 4 An example amplifier circuit implemented with multiple amplification paths according to certain aspects of this disclosure is illustrated.

[0014] Figure 5An example amplifier circuit with multiple amplification paths for implementing different power modes and a shared current source is illustrated according to certain aspects of this disclosure.

[0015] Figure 6 This is a flowchart depicting an example operation for signal amplification according to certain aspects of this disclosure.

[0016] For ease of understanding, the same reference numerals have been used where possible to denote common elements in the figures. It is conceivable that elements disclosed in one aspect may be usefully applied to other aspects without specific description. Detailed Implementation

[0017] Certain aspects of this disclosure generally relate to techniques and apparatus for signal amplification using different amplification paths that allow operation in different power modes. For example, some aspects provide an amplifier circuit that can operate in both low-power mode (LPM) and high-power mode (HPM). The amplifier circuit may include an amplification path for LPM and an amplification path for HPM. The amplification path for LPM may include an attenuator for generating an attenuated signal for amplification when operating in LPM, while the amplification path for HPM may not include such an attenuator. Having separate amplification paths allows attenuators to be implemented in the amplification for LPM with little effect on the amplification path for HPM. A first bias circuit may be used to bias the first amplification path, and a second bias circuit may be used to bias the second amplification path. In some aspects, a current source may be selectively coupled to the first bias circuit or the second bias circuit based on whether the amplifier circuit operates in LPM or HPM. In some aspects, an on-die HBT transistor may be used to act as an attenuator. For example, the attenuator can be tuned via a transistor (e.g., a heterojunction bipolar transistor (HBT)), and the transistor can be implemented on the same semiconductor die as the drive amplifier (DA) and / or power amplifier (PA) used for signal amplification.

[0018] Example wireless communications Figure 1 An example is illustrated of a wireless communication system 100 having an access point 110 and a user terminal 120 in which various aspects of the present disclosure can be implemented. For simplicity, Figure 1Only one access point 110 is shown. An access point (AP) is typically a fixed station that communicates with a user terminal and may also be referred to as a base station (BS), evolved Node B (eNB), next-generation Node B (gNB), or some other term. A user terminal (UT) can be fixed or mobile and may also be referred to as a mobile station (MS), access terminal, user equipment (UE), station (STA), client, wireless device, or some other term. A user terminal can be a wireless device such as a cellular phone, personal digital assistant (PDA), handheld device, wireless modem, laptop computer, tablet computer, personal computer, etc.

[0019] Access point 110 can communicate with one or more user terminals 120 at any given time, on both the downlink and uplink. The downlink (i.e., the forward link) is the communication link from the access point to the user terminal, while the uplink (i.e., the reverse link) is the communication link from the user terminal to the access point. User terminals can also communicate peer-to-peer with other user terminals. System controller 130 can be coupled to the access point and provides coordination and control for the access point.

[0020] The wireless communication system 100 employs multiple transmitting antennas and multiple receiving antennas to transmit data on the downlink and uplink. The access point 110 may be equipped with multiple (…). N ap (Number) antennas to achieve transmit diversity for downlink transmissions and / or receive diversity for uplink transmissions. A set of ( N u The selected user terminal 120 can receive downlink transmissions and transmit uplink transmissions. Each selected user terminal transmits user-specific data to and / or receives user-specific data from the access point. Typically, each selected user terminal may be equipped with one or more antennas (i.e., N ut 1). N u Each selected user terminal may have the same number of antennas or a different number of antennas.

[0021] The wireless communication system 100 can be a time-division duplex (TDD) system or a frequency-division duplex (FDD) system. In a TDD system, the downlink and uplink share the same frequency band. In an FDD system, the downlink and uplink use different frequency bands. The wireless communication system 100 can also utilize a single carrier or multiple carriers for transmission. Each user terminal 120 can be equipped with a single antenna (e.g., to reduce cost) or multiple antennas (e.g., where additional costs can be supported). In some aspects, the user terminal 120 or access point 110 may include an amplifier implemented with multiple amplification paths for operation in different power modes.

[0022] Figure 2 A block diagram of an access point 110 and two user terminals 120m and 120x in a wireless communication system 100 is shown. Access point 110 is equipped with... N ap Each antenna is 224a to 224ap. The user terminal is equipped with 120m. N ut,m Each antenna is 252 mA to 252 mA, while the user terminal 120x is equipped with N ut,x Each antenna ranges from 252xa to 252xu. Access point 110 is a transmitting entity for the downlink and a receiving entity for the uplink. Each user terminal 120 is a transmitting entity for the uplink and a receiving entity for the downlink. As used herein, a “transmitting entity” is an independently operating apparatus or device capable of transmitting data via a frequency channel, and a “receiving entity” is an independently operating apparatus or device capable of receiving data via a frequency channel. In the following description, the subscript “…” dn " indicates the downlink, subscript " up "Indicates uplink, N up One user terminal was selected to transmit simultaneously on the uplink. N dn One user terminal was selected to transmit simultaneously on the downlink. N up "May or may not equal" N dn ,and N up and N dn It can be a static value, or it can be changed for each scheduling interval. Beam control, beamforming, or some other spatial processing technique can be used at the access point and user terminal.

[0023] On the uplink, at each user terminal 120 selected for uplink transmission, the TX data processor 288 receives service data from the data source 286 and control data from the controller 280. The TX data processor 288 processes the service data for that user terminal based on a decoding and modulation scheme associated with the selected rate for that user terminal. d up} to perform processing (e.g., encoding, interleaving, and modulation), and for N ut,m One of the antennas provides the data symbol stream. s up The transceiver front-end (TX / RX) 254 (also referred to as the radio frequency front-end (RFFE)) receives and processes the corresponding symbol stream (e.g., converts to analog, amplifies, filters, and up-converts) to generate the uplink signal. For example, the transceiver front-end 254 can also route the uplink signal via an RF switch to a source for transmit diversity. N ut,m One of the antennas. Controller 280 can control the routing within transceiver front-end 254. Memory 282 can store data and program code for user terminal 120 and can interface with controller 280.

[0024] Multiple can be scheduled N up (120) user terminals simultaneously transmit on the uplink. Each of these user terminals transmits a set of symbol streams it is processing to the access point on the uplink.

[0025] At access point 110, N ap Each antenna 224a to 224ap from all N up A user terminal receives uplink signals transmitted on the uplink. For receive diversity, transceiver front-end 222 can select signals received from one of antennas 224 for processing. Signals received from multiple antennas 224 can be combined to enhance receive diversity. The access point's transceiver front-end 222 also performs processing complementary to that performed by the user terminal's transceiver front-end 254 and provides a recovered uplink data symbol stream. The recovered uplink data symbol stream is a response to the data symbol stream transmitted by the user terminal. s up The RX data processor 242 processes (e.g., demodulates, deinterleaves, and decodes) the uplink data symbol stream used for recovery based on its rate to obtain decoded data. The decoded data for each user terminal may be provided to the data sink 244 for storage and / or to the controller 230 for further processing.

[0026] On the downlink, at access point 110, TX data processor 210 receives data from data source 208 that is scheduled for downlink transmission. N dn The data includes service data from individual user terminals, control data from controller 230, and other data that may come from scheduler 234. These various data types can be transmitted over different transport channels. TX data processor 210 processes the service data for each user terminal (e.g., encoding, interleaving, and modulation) based on a selected rate for that user terminal. TX data processor 210 can provide... N dn One or more user terminals among the user terminals need to be from N ap A downlink data symbol stream is transmitted by one of the antennas. Transceiver front-end 222 receives and processes this symbol stream (e.g., converts it to analog, amplifies it, filters it, and up-converts it) to generate a downlink signal. For example, transceiver front-end 222 can also route this downlink signal via an RF switch to a source for transmit diversity. N ap One or more antennas from antenna 224. Controller 230 can control routing within transceiver front end 222. Memory 232 can store data and program code for access point 110 and can interface with controller 230.

[0027] At each user terminal, 120, N ut,m Antenna 252 receives downlink signals from access point 110. For receive diversity at user terminal 120, transceiver front-end 254 can selectively process signals received from one or more of the antennas 252. Signals received from multiple antennas 252 can be combined to enhance receive diversity. The transceiver front-end 254 of the user terminal also performs processing complementary to that performed by the transceiver front-end 222 of the access point and provides a recovered downlink data symbol stream. RX data processor 270 processes the recovered downlink data symbol stream (e.g., demodulation, deinterleaving, and decoding) to obtain decoded data for the user terminal. In some aspects, transceiver front-end 254 or 222 may include amplifiers implemented with multiple amplification paths for operation in different power modes.

[0028] Figure 3 This is an example transceiver front end 300 in which various aspects of this disclosure can be practiced (such as...). Figure 2A block diagram of the transceiver front-end 300 (222, 254). The transceiver front-end 300 includes at least one transmit (TX) path 302 (also referred to as a "transmit chain") for transmitting signals via one or more antennas and at least one receive (RX) path 304 (also referred to as a "receive chain") for receiving signals via these antennas. When the TX path 302 and RX path 304 share an antenna 303, these paths can be connected to the antenna via an interface 306, which may include any of a variety of suitable radio frequency (RF) devices, such as switches, duplexers, double-ended converters, multiplexers, etc.

[0029] Receiving in-phase (I) and / or quadrature (Q) baseband analog signals from a digital-to-analog converter (DAC) 308, the TX path 302 may include a baseband filter (BBF) 310, a mixer 312, a driver amplifier (DA) 314, and a power amplifier (PA) 316. The BBF 310, mixer 312, DA 314, and PA 316 may be included in a radio frequency integrated circuit (RFIC). In some cases, PA 316 may be external to the RFIC.

[0030] BBF 310 filters the baseband signal received from DAC 308, and mixer 312 mixes the filtered baseband signal with a transmit local oscillator (LO) signal to convert the baseband signal of interest to a different frequency (e.g., up-convert from baseband to RF). This frequency conversion process produces a sum and difference frequency between the LO frequency and the frequency of the baseband signal of interest. This sum and difference frequency is referred to as the "beat frequency." The beat frequency is typically in the RF range, such that the signal output from mixer 312 is typically an RF signal, which may be amplified by DA 314 and / or PA 316 before being transmitted via antenna 303. In some respects, DA 314 and / or PA 316 may be implemented with multiple amplification paths for operation in different power modes. Although one mixer 312 is exemplified, several mixers may be used to up-convert the filtered baseband signal to one or more intermediate frequencies and subsequently up-convert the intermediate frequency (IF) signal to the frequency used for transmission.

[0031] The RX path 304 includes a low-noise amplifier (LNA) 322, a mixer 324, and a baseband filter (BBF) 326. The LNA 322, mixer 324, and BBF 326 may be included in a radio frequency integrated circuit (RFIC), which may or may not be the same RFIC that includes the TX path components. The RF signal received via antenna 303 can be amplified by the LNA 322, and the mixer 324 mixes the amplified RF signal with a received local oscillator (LO) signal to convert the RF signal of interest to a different baseband frequency (i.e., down-conversion). The baseband signal output from the mixer 324 can be filtered by the BBF 326 before being converted to digital I and / or Q signals by an analog-to-digital converter (ADC) 328 for digital signal processing.

[0032] Some transceivers may employ a frequency synthesizer with a variable frequency oscillator (e.g., a voltage-controlled oscillator (VCO) or a digitally controlled oscillator (DCO)) to generate a stable, tunable LO with a specific tuning range. Therefore, the transmit LO frequency may be generated by the TX frequency synthesizer 318, which may be buffered or amplified by the amplifier 320 before being mixed with the baseband signal in the mixer 312. Similarly, the receive LO frequency may be generated by the RX frequency synthesizer 330, which may be buffered or amplified by the amplifier 332 before being mixed with the RF signal in the mixer 324. In some cases, a single frequency synthesizer may be used for both the TX path 302 and the RX path 304.

[0033] Example multipath amplification circuit Some wireless devices can use multimode multiband (MMMB) power amplifiers (PAs), allowing a single PA to support multiple modes and frequency bands to save cost and area. Typical MMMB PAs exhibit good performance in high-power mode (HPM) when signal transmission occurs at high power because the PA can be specifically tuned for HPM. However, under certain conditions, the PA may not transmit at high power, and low-power transmission may be sufficient for the user equipment (UE) to transmit signals (e.g., to a base station). For a typical PA designed with 30 dB gain in HPM (e.g., achieved by a 2- or 3-stage PA), the PA gain may be high in low-power mode (LPM) (e.g., even if the PA's rail voltage (Vcc) and reference current (Iref) decrease), which can lead to problems meeting high dynamic range transceiver specifications.

[0034] Certain aspects of this disclosure relate to amplifier architectures implemented using HPM and LPM amplification paths. Utilizing two amplification paths allows HPM performance to be maintained while implementing an attenuator for the LPM. For example, the LPM amplification path may include an attenuator providing low-gain tunability (e.g., having little impact on the performance of the HPM amplification path). In other words, if a single amplification path is used for both HPM and LPM and an attenuator is used on that single amplification path, the attenuator is likely to adversely affect HPM performance. Compared to using a single amplification path, utilizing separate amplification paths for HPM and LPM (e.g., including separate drive amplifiers (DA)), the attenuator generates an attenuated signal for the LPM amplification path with significantly less impact on the HPM amplification path. While the example attenuation techniques described herein are described relative to multiple amplification paths for the drive amplifier (e.g., referred to as "DA segmentation"), the aspects described herein may be additionally or alternatively implemented using PA segmentation. For example, in some aspects, multiple amplification paths may be used for power amplification, with separate bias circuitry for each amplification path.

[0035] Figure 4 Examples of using multiple amplification paths (e.g., for implementing DA, such as) according to certain aspects of this disclosure are illustrated. Figure 3 An example amplifier circuit 400 is implemented using the DA path of DA 314. As shown, amplifier circuit 400 may include PA transistor 462 (e.g., for implementing PA, such as...). Figure 3 The transistors 460, 486, and 462 may be implemented as one or more heterojunction bipolar transistors (HBTs). One or more HBTs may be implemented on the same die (e.g., a gallium arsenide (GaAs) die) as DA transistor 460 and / or PA transistor 462. DA transistor 460 may be part of HPM amplification path 490, and DA transistor 486 may be part of LPM amplification path 492. The gain associated with each path may be set at least partially using the size of the associated DA transistors. For example, the LPM gain may be set using the associated amplification path (e.g., via attenuation) and by configuring the size of the DA transistors (e.g., transistor 486), which may allow the LPM gain to be reduced (e.g., compared to the HPM gain).

[0036] Each of the amplification paths 490 and 492 can receive a bias signal. For example, transistor 434 (e.g., also referred to herein as a “bias transistor”) can have an emitter coupled to the base of transistor 460 via resistor element 444. The collector of transistor 434 can be coupled to a voltage rail (e.g., coupled to a power source, such as a battery providing a battery voltage (Vbatt)). Current source 432 can provide a reference current (Iref) across resistor element 430, diodes 438 and 440, and resistor element 442. DA_HPM This generates a voltage at the base of transistor 434. Therefore, transistor 434 can be biased to provide a bias signal (e.g., bias current) for biasing transistor 460.

[0037] Similarly, transistor 428 may have an emitter coupled to the base of transistor 486 via resistor 448. The collector of transistor 428 may be coupled to a voltage rail (e.g., via resistor 418). Current source 414 may provide a reference current (Iref) across resistor 416, diodes 422 and 424, and resistor 420. DA_LPM This generates a voltage at the base of transistor 428. Therefore, transistor 428 can be biased to provide a bias signal (e.g., bias current) for biasing transistor 486.

[0038] As shown, amplification path 490 may include ballast capacitor element 446, and amplification path 492 may include ballast capacitor element 450. The collectors of transistors 460 and 486 may be coupled to DA output node 498. DA output node 498 may be coupled to the input of PA (e.g., the base of transistor 462) via interstage matching circuit 456 for impedance matching. The collector of transistor 462 may be coupled to the output node 497 of PA (e.g., having an output RF signal labeled "Rfout"), thereby providing a signal for transmission (e.g., via output impedance matching circuit 499). A reference current (Iref) may be provided as shown. PA This is used to bias the PA (e.g., transistor 462). For example, transistor 472 may have an emitter coupled to the base of transistor 462 via a resistive element 458. The collector of transistor 472 may be coupled to a voltage rail. Current source 487 may provide a reference current (Iref) across resistive element 468 and diodes 464, 466. PA This generates a voltage at the base of transistor 472. Therefore, transistor 472 can be biased, thereby providing a bias signal for biasing transistor 462.

[0039] In some aspects of this disclosure, an attenuator can be implemented for the LPM amplification path 492. For example, the attenuator may include a resistive element 452 coupled between input node 451 and node 453. In some aspects, the resistive element 482 may be coupled between node 453 and the collector of transistor 480. Transistor 480 may be implemented as an HBT (e.g., a GaAs transistor). The emitter of transistor 480 may be coupled to a reference potential node (e.g., electrically grounded), as shown. Input impedance matching circuitry 454 (e.g., for impedance matching) may be coupled between input node 451 and resistive element 452.

[0040] In some aspects, transistor 480 can be biased to tune an attenuator. For example, transistor 412 may have an emitter coupled to the base of transistor 480 via a resistive element 478. In some aspects, a capacitor element 484 may be coupled between the base and collector of transistor 480. Capacitor element 484 can be used to tune an attenuator for a specific frequency band. The collector of transistor 412 may be coupled to a voltage rail, as shown.

[0041] Current source 402 can provide a reference current (Iref) across resistor 404, diodes 406 and 408, and resistor 410. attn This generates a voltage at the base of transistor 412. Therefore, transistor 412 can be biased, thereby providing a bias signal to bias transistor 480 to set the attenuation level of the attenuator (e.g., by adjusting the impedance between node 453 and a reference potential node (e.g., electrically grounded)). As described, the attenuator is implemented for the LPM amplification path and provides attenuation for operation under LPM conditions with little effect on the HPM amplification path.

[0042] Figure 5An example amplifier circuit 500, according to certain aspects of this disclosure, is illustrated with multiple amplification paths for LPM and HPM and a shared current source 502. The reference current for amplifier circuit 500 can be provided by a residual current device (RCD). By using the same current source 502 for both LPM and HPM, the cost of the RCD can be reduced (e.g., the RCD does not need to provide separate reference currents for LPM and HPM). Amplifier circuit 500 can operate under either LPM or HPM. Therefore, current source 502 can be selectively coupled to resistive elements 416 or 430 (e.g., via switch 504) to bias transistor 428 or transistor 434. In other words, when current source 502 is coupled to resistive element 416, a voltage is generated at the base of transistor 428, thereby generating a bias signal for LPM amplification path 492, and when current source 502 is coupled to resistive element 430, a voltage is generated at the base of transistor 434, thereby generating a bias signal for HPM amplification path 490. By using a common current source 502, the number of current sources used to implement amplifier circuit 500 can be reduced compared to amplifier circuit 400, thereby reducing area and power consumption.

[0043] In some respects, amplifier circuit 500 can be implemented with constant attenuation (e.g., with an attenuator having a non-tunable attenuation level). For example, the attenuator may include resistive element 452 in LPM amplification path 492. An amplifier circuit implemented with multiple amplification paths may allow constant attenuation to be used for LPM (e.g., because amplification path 492 including the attenuator is only specified for LPM operation, and not necessarily must support both LPM and HPM).

[0044] Certain aspects of this disclosure provide a dual amplifier embodiment for an MMMB PA with an integrated HBT attenuator design that maintains HPM performance while providing tunability to reduce LPM gain. The programmable LPM gain can be achieved with minimal impact on the HPM path. In addition to the attenuator, attenuation for the LPM amplification path can also be configured by setting the HBT emitter length and width (e.g., of transistor 428). The dual amplifier embodiment described herein can be used to tune the HPM and LPM paths differently.

[0045] Figure 6 This is a flowchart depicting an example operation 600 for signal amplification according to certain aspects of this disclosure. For example, operation 600 may be performed by an electrical device including amplification circuitry (such as amplification circuitry 400 or amplification circuitry 500).

[0046] Operation 600 begins at block 602, where the electrical device determines the power mode (e.g., LPM or HPM) for the amplification circuit. At block 604, the electrical device selects a first amplification path (e.g., amplification path 490) or a second amplification path (e.g., amplification path 492) based on the power mode. The first amplification path may include a first amplifying transistor (e.g., transistor 460) coupled to an output node (e.g., output node 498) of the amplification circuit. The second amplification path may include a second amplifying transistor (e.g., transistor 486) coupled to the output node and an attenuator (e.g., resistive element 452) coupled to a control input (e.g., gate) of the second amplifying transistor. At block 606, the electrical device amplifies the input signal via the first or second amplification path based on this selection.

[0047] In some aspects, the electrical device attenuates an input signal via an attenuator to generate an attenuated signal, and amplifies the attenuated signal using a second amplifying transistor. The electrical device can determine an attenuation level associated with the attenuator. The electrical device can generate a bias signal for the attenuation transistor (e.g., transistor 480) of the attenuator via a bias circuit based on the attenuation level. For example, the attenuator may include a resistive element (e.g., resistive element 452) coupled in series between the input node of the amplifier circuit (e.g., input node 451) and the control input (e.g., gate) of the second amplifying transistor. The attenuation transistor may be coupled between the resistive element and a reference potential node. The electrical device can bias the attenuation transistor with a bias signal. In some aspects, the bias circuit may include a bias transistor (e.g., transistor 412) coupled between a voltage rail and the control input of the attenuation transistor. Generating the bias signal may include supplying current to the control input (e.g., gate) of the bias transistor via a current source.

[0048] In some aspects, the electrical device biases a first amplifying transistor via a first bias circuit (e.g., transistor 434) based on a power mode of HPM, or a second amplifying transistor via a second bias circuit (e.g., transistor 428) based on a power mode of LPM. The first bias circuit may include a first bias transistor (e.g., transistor 434) coupled between a voltage rail and a control input of the first amplifying transistor, the control input of which is selectively coupled to a current source (e.g., current source 502). The second bias circuit may include a second bias transistor (e.g., transistor 428) coupled between a voltage rail and a control input of the second amplifying transistor, the control input of which is selectively coupled to the current source. In some aspects, the electrical device is configured to selectively couple a current source to either the first or second bias transistor based on a power mode (e.g., via switch 504).

[0049] Example aspects Aspect 1: An amplifier circuit comprising: a first amplification path including a first amplification transistor and coupled between an input node and an output node of the amplifier circuit; and a second amplification path coupled between the input node and the output node of the amplifier circuit and including a second amplification transistor and an attenuator coupled between the input node of the amplifier circuit and a control input portion of the second amplification transistor.

[0050] Aspect 2: The amplifier circuit according to aspect 1, wherein the attenuator includes a first resistive element coupled in series between the input node and the control input portion of the second amplifying transistor.

[0051] Aspect 3: The amplification circuit according to aspect 2, wherein the attenuator further includes an attenuation transistor coupled between the first resistive element and the reference potential node.

[0052] Aspect 4: The amplification circuit according to aspect 3, wherein the attenuator further includes a second resistive element coupled between the first resistive element and the reference potential node.

[0053] Aspect 5: The amplification circuit according to aspect 3 or 4 further includes a bias circuit coupled to the control input of the attenuation transistor.

[0054] Aspect 6: The amplifier circuit according to aspect 5, wherein the bias circuit includes a bias transistor coupled between a voltage rail and the control input of the attenuation transistor, the control input of the bias transistor being coupled to a current source.

[0055] Aspect 7: The amplification circuit according to aspect 5 or 6, wherein the attenuation transistor includes a heterojunction bipolar transistor (HBT).

[0056] Aspect 8: The amplification circuit according to any one of Aspects 3 to 7, wherein the attenuation transistor and the first amplification transistor are on the same semiconductor die, and wherein the attenuation transistor and the first amplification transistor are gallium arsenide (GaAs) transistors.

[0057] Aspect 9: The amplifier circuit according to any one of Aspects 1 to 8, wherein: The first amplification path includes a first driver amplifier (DA) segment, the first driver amplifier (DA) segment including the first amplifying transistor; the second amplification path includes a second DA segment, the second DA segment including the second amplifying transistor; and the amplification circuit further includes a power amplifier (PA), the power amplifier (PA) having an input section coupled to the output section of the first DA segment and the output section of the second DA segment.

[0058] Aspect 10: The amplifier circuit according to any one of Aspects 1 to 9 further includes: a first bias circuit coupled to a control input portion of the first amplifying transistor; and a second bias circuit coupled to the control input portion of the second amplifying transistor.

[0059] Aspect 11: The amplifier circuit according to aspect 10, wherein: the first bias circuit is configured to bias the first amplifying transistor based on the operation of the amplifier circuit in high power mode (HPM); and the second bias circuit is configured to bias the second amplifying transistor based on the operation of the amplifier circuit in low power mode (LPM).

[0060] Aspect 12: The amplifier circuit according to aspect 10 or 11, wherein: the first bias circuit includes a first bias transistor coupled between a voltage rail and a control input of the first amplifying transistor, the control input of the first bias transistor being coupled to a first current source; and the second bias circuit includes a second bias transistor coupled between the voltage rail and a control input of the second amplifying transistor, the control input of the second bias transistor being coupled to a second current source.

[0061] Aspect 13: The amplifier circuit according to aspect 12, wherein the first current source and the second current source include the same current source selectively coupled to the control input of the first bias transistor or the control input of the second bias transistor.

[0062] Aspect 14: The amplifier circuit according to any one of Aspects 1 to 13 further includes: a first capacitor element coupled between the input node and the control input portion of the first amplifying transistor; and a second capacitor element coupled between the input node and the control input portion of the second amplifying transistor.

[0063] Aspect 15: A method for signal amplification, the method comprising: determining a power mode for an amplification circuit; selecting a first amplification path or a second amplification path based on the determined power mode, wherein the first amplification path includes a first amplification transistor coupled to an output node of the amplification circuit, and wherein the second amplification path includes a second amplification transistor coupled to the output node and an attenuator coupled to a control input portion of the second amplification transistor; and amplifying an input signal via the first amplification path or the second amplification path based on the selection.

[0064] Aspect 16: The method according to aspect 15 further includes: attenuating the input signal via the attenuator to generate an attenuated signal; and amplifying the attenuated signal using the second amplifying transistor.

[0065] Aspect 17: The method according to aspect 16, the method further comprising: determining an attenuation level associated with the attenuator; generating a bias signal for an attenuation transistor of the attenuator via a bias circuit based on the attenuation level, wherein the attenuator includes a resistive element coupled in series between an input node of the amplifier circuit and the control input of the second amplifying transistor, the attenuation transistor being coupled between the resistive element and a reference potential node; and biasing the attenuation transistor with the bias signal.

[0066] Aspect 18: The method according to aspect 17, wherein: the bias circuit includes a bias transistor coupled between a voltage rail and a control input of the attenuation transistor; and generating the bias signal includes providing current to the control input of the bias transistor via a current source.

[0067] Aspect 19: The method according to aspect 17 or 18, wherein the attenuation transistor comprises a heterojunction bipolar transistor (HBT).

[0068] Aspect 20: The method according to any one of aspects 15 to 19, the method further comprising: biasing the first amplifying transistor via a first bias circuit based on the determined power mode being a high power mode (HPM); or biasing the second amplifying transistor via a second bias circuit based on the determined power mode being a low power mode (LPM).

[0069] Aspect 21: The method according to aspect 20, wherein: the first bias circuit includes a first bias transistor coupled between a voltage rail and a control input of the first amplifying transistor, the control input of the first bias transistor being coupled to a current source; the second bias circuit includes a second bias transistor coupled between the voltage rail and a control input of the second amplifying transistor, the control input of the second bias transistor being coupled to the current source; and the method further includes selectively coupling the current source to the first bias transistor or the second bias transistor based on the power mode.

[0070] Aspect 22: An apparatus for signal amplification, the apparatus comprising: a first component for amplifying an input signal at an input node, the first component for amplification being coupled between the input node and an output node; a component for attenuating the input signal to generate an attenuated signal, the component for attenuation being coupled to the input node; and a second component for amplifying the attenuated signal, the second component for amplification being coupled between the component for attenuation and the output node.

[0071] Aspect 23: The apparatus according to aspect 22 further includes: a component for determining a power mode for the apparatus; and a component for selecting, based on the determined power mode, either the first component for amplifying the input signal or the second component for amplifying the attenuated signal.

[0072] Within this disclosure, the term "exemplary" is used to mean "serving as an example, instance, or illustration." Any specific implementation or aspect described herein as "exemplary" is not necessarily to be construed as superior to or better than other aspects of this disclosure. Similarly, the term "aspect" does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term "coupling" is used herein to refer to direct or indirect coupling between two objects. For example, if object A physically contacts object B, and object B contacts object C, objects A and C can still be considered coupled to each other, even if objects A and C are not in direct physical contact. For example, a first object can be coupled to a second object, even if the first object never has direct physical contact with the second object. The term "circuit" is used broadly and is intended to include hardware implementations of electronic devices and conductors that, when connected and configured, enable the performance of the functions described in this disclosure, without limitation on the type of electronic circuit.

[0073] The apparatus and methods described in the detailed description are illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively, "elements"). These elements may be implemented, for example, in hardware.

[0074] One or more of the components, steps, features, and / or functions illustrated herein may be rearranged and / or combined into a single component, step, feature, or function, or embodied in several components, steps, or functions. Additional elements, components, steps, and / or functions may also be added without departing from the features disclosed herein. The apparatus, devices, and / or components illustrated herein may be configured to perform one or more of the methods, features, or steps described herein.

[0075] It should be understood that the specific order or hierarchy of steps in the disclosed methods is an example of an exemplary process. It should be understood that the specific order or hierarchy of steps in these methods may be rearranged based on design preferences. The appended method claims present the elements of various steps in an exemplary order, but are not intended to limit them to the specific order or hierarchy presented, unless specifically stated herein.

[0076] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to be limited to the aspects shown herein, but are to be consistent with the full scope of the claims, wherein references to elements in the singular form are not intended to mean “one and only one”, but rather “one or more”, unless specifically stated otherwise. Unless otherwise specifically stated, the term “some” refers to one or more. The phrase “at least one of” referring to the list of items means any combination of those items, including a single member. As an example, “at least one of a, b, or c” is intended to cover at least: a, b, c, ab, ac, bc, and abc, and any combination having multiple identical elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other ordering of a, b, and c). All structural and functional equivalents of elements throughout the various aspects described herein that are known to or will later be known to a person skilled in the art are expressly incorporated herein by reference and are intended to be covered by the claims. Furthermore, nothing disclosed herein is intended to be offered to the public, whether or not such disclosure is expressly stated in the claims. No claim element should be construed in accordance with 35 USC § 112(f) unless it is expressly stated using the phrase “component for…” or, in the case of a method claim, using the phrase “step for…”. For example, a component for determining may be a digital controller, such as digital controller 510. A component for generating one or more currents may include a calibration DAC, such as calibration DAC 802.

[0077] It should be understood that the claims are not limited to the precise configurations and components illustrated above. Various modifications, alterations, and variations may be made to the arrangement, operation, and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. An amplifier circuit, the amplifier circuit comprising: A first amplification path, the first amplification path including a first amplification transistor and coupled between the input node and the output node of the amplification circuit; and The second amplification path is coupled between the input node and the output node of the amplifier circuit, and includes a second amplifying transistor and an attenuator coupled between the input node of the amplifier circuit and the control input of the second amplifying transistor.

2. The amplifier circuit of claim 1, wherein the attenuator includes a first resistive element coupled in series between the input node and the control input portion of the second amplifying transistor.

3. The amplifier circuit of claim 2, wherein the attenuator further comprises an attenuation transistor coupled between the first resistive element and the reference potential node.

4. The amplifier circuit of claim 3, wherein the attenuator further comprises a second resistive element coupled between the first resistive element and the reference potential node.

5. The amplifier circuit according to claim 3, further comprising a bias circuit coupled to the control input section of the attenuation transistor.

6. The amplifier circuit of claim 5, wherein the bias circuit includes a bias transistor coupled between a voltage rail and the control input of the attenuation transistor, the control input of the bias transistor being coupled to a current source.

7. The amplifier circuit according to claim 5, wherein the attenuation transistor comprises a heterojunction bipolar transistor (HBT).

8. The amplifier circuit of claim 3, wherein the attenuation transistor and the first amplification transistor are on the same semiconductor die, and wherein the attenuation transistor and the first amplification transistor are gallium arsenide (GaAs) transistors.

9. The amplifier circuit according to claim 1, wherein: The first amplification path includes a first driver amplifier (DA) segment, and the first driver amplifier (DA) segment includes the first amplification transistor; The second amplification path includes a second DA segment, and the second DA segment includes the second amplification transistor; and The amplifier circuit further includes a power amplifier (PA) having an input section coupled to the output of the first DA segment and the output of the second DA segment.

10. The amplifier circuit according to claim 1, further comprising: A first bias circuit is coupled to the control input section of the first amplifying transistor; and A second bias circuit is coupled to the control input of the second amplifying transistor.

11. The amplifier circuit according to claim 10, wherein: The first bias circuit is configured to bias the first amplifying transistor based on the operation of the amplifying circuit in high power mode (HPM); and The second bias circuit is configured to bias the second amplifying transistor based on the operation of the amplifying circuit in low power mode (LPM).

12. The amplifier circuit according to claim 10, wherein: The first bias circuit includes a first bias transistor coupled between a voltage rail and a control input of the first amplifying transistor, the control input of the first bias transistor being coupled to a first current source; and The second bias circuit includes a second bias transistor coupled between the voltage rail and the control input of the second amplifying transistor, the control input of the second bias transistor being coupled to a second current source.

13. The amplifier circuit of claim 12, wherein the first current source and the second current source comprise the same current source selectively coupled to the control input of the first bias transistor or the control input of the second bias transistor.

14. The amplifier circuit according to claim 1, further comprising: A first capacitor element is coupled between the input node and the control input section of the first amplifying transistor; and A second capacitor element is coupled between the input node and the control input section of the second amplifying transistor.

15. A method for signal amplification, the method comprising: Determine the power mode to be used in the amplifier circuit; The first amplification path or the second amplification path is selected based on the determined power mode, wherein the first amplification path includes a first amplification transistor coupled to the output node of the amplification circuit, and wherein the second amplification path includes a second amplification transistor coupled to the output node and an attenuator coupled to the control input of the second amplification transistor; as well as The input signal is amplified via the first amplification path or the second amplification path based on the selection.

16. The method of claim 15, further comprising: The input signal is attenuated by the attenuator to produce an attenuated signal; as well as The attenuated signal is amplified using the second amplifying transistor.

17. The method according to claim 16, further comprising: Determine the attenuation level associated with the attenuator; Based on the attenuation level, a bias signal for the attenuation transistor of the attenuator is generated via a bias circuit, wherein the attenuator includes a resistive element coupled in series between the input node of the amplifier circuit and the control input of the second amplifier transistor, and the attenuation transistor is coupled between the resistive element and a reference potential node. as well as The attenuation transistor is biased using the bias signal.

18. The method of claim 17, wherein: The bias circuit includes a bias transistor coupled between the voltage rail and the control input of the attenuation transistor; and Generating the bias signal involves supplying current to the control input of the bias transistor via a current source.

19. The method of claim 17, wherein the attenuation transistor comprises a heterojunction bipolar transistor (HBT).

20. The method of claim 15, further comprising: Based on the determined power mode being high power mode (HPM), the first amplifying transistor is biased via a first bias circuit; or Based on the determined power mode being low power mode (LPM), the second amplifying transistor is biased via a second bias circuit.

21. The method of claim 20, wherein: The first bias circuit includes a first bias transistor coupled between a voltage rail and a control input of the first amplifying transistor, the control input of the first bias transistor being coupled to a current source; The second bias circuit includes a second bias transistor coupled between the voltage rail and the control input of the second amplifying transistor, the control input of the second bias transistor being coupled to the current source; and The method further includes selectively coupling the current source to the first bias transistor or the second bias transistor based on the power mode.

22. An apparatus for signal amplification, the apparatus comprising: A first component for amplifying the input signal at the input node, the first component for amplification being coupled between the input node and the output node; A component for attenuating the input signal to produce an attenuated signal, the component for attenuation being coupled to the input node; and A second component for amplifying the attenuated signal is coupled between the component for attenuation and the output node.

23. The apparatus of claim 22, further comprising: Components for determining the power mode for the device; and A component for selecting, based on a determined power mode, either the first component for amplifying the input signal or the second component for amplifying the attenuated signal.

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