Ku-band integrated wide-angle scanning active phased array radar module

Abstract

The invention belongs to the technical field of radars, and discloses a Ku-band integrated wide-angle scanning active phased array radar module which comprises a plurality of dielectric substrates and a plurality of copper-clad printing layers which are stacked at intervals, a TR chip and various circuit elements are arranged on the outermost layer, and the Ku-band integrated wide-angle scanning active phased array radar module integrates the functions of radiation, control, power supply and radio frequency feed. According to the function of the copper-clad printing layer, the antenna is divided into an antenna radiation layer, a digital control layer, a power supply layer, a control power supply multiplexing layer, a feed network layer and a ground layer. The three layers are respectively used for forming a high-gain wide-angle scanning array wave beam, modulating amplitude, modulating phase, controlling transceiving channel switching, supplying power, transmitting and distributing equal-power radio-frequency signals and shielding electromagnetic influence between adjacent copper-clad printing layers; the radar module provided by the invention is realized in a compact array space in which the array unit spacing is less than 0.5 wavelength, the 3dB scanning range of a pitching plane can at least reach + / -63 degrees, the 3dB scanning range of an azimuth plane can at least reach 55 degrees, and each unit has good performance.

Description

Technical Field

[0001] This invention belongs to the field of radar technology, specifically relating to a Ku-band integrated wide-angle scanning active phased array radar module. Background Technology

[0002] With the continuous development of radar detection technology, low-latency phased arrays have gradually replaced traditional mechanically scanned arrays in radar detection. However, traditional phased arrays have a narrow antenna beam and a limited scanning range, which cannot meet the application requirements of wide-angle radar detection. Therefore, large-angle scanning phased array antenna technology has emerged and become a key technology in the radar field. In order to increase the scanning range of the antenna array, most existing methods add parasitic electric walls, multilayer dielectric layers, and metasurface structures, etc., to the narrow beam array, which often directly or indirectly increases the size and mass of the phased array, thus limiting its fabrication and application.

[0003] Besides wide-angle scanning antenna technology, the connection scheme between the antenna array and the wave control circuit is another reason for the large size and weight of phased arrays. Traditional schemes mostly design the array and wave control circuit separately and then connect them with cables. This scheme, especially the brick-like layout, directly increases the size of the phased array, making it difficult to meet the current requirements for integrated and lightweight radar phased arrays. In recent years, schemes for integrating the antenna array and circuit in radar phased arrays have been gradually proposed. Laying out the circuit only within the array space is the optimal compact and miniaturized phased array design effect. This effect is currently mainly concentrated in low-frequency phased arrays, such as X-band radar phased arrays, while research on high-frequency radar phased arrays, such as Ku-band radar phased arrays, is extremely scarce. This is mainly because the physical space of the high-frequency array is smaller, making it difficult to provide sufficient space for circuit integration and layout, leading to a significant increase in design difficulty. Laying out circuit devices and lines within the limited space of the high-frequency array already presents a significant challenge; on top of that, integrating various larger connectors within that space poses an even greater challenge to the design of the integration scheme.

[0004] Patent application CN115296014B discloses a millimeter-wave wide-angle scanning phased array radar antenna array based on PCB technology. Although the scanning range can reach 60°, the antenna array in this patent application uses a thirteen-layer substrate including a prepreg. Although it is a passive phased array, the number of layers is large and the overall structure is complex. In addition, this patent application only realizes one-dimensional scanning. Summary of the Invention

[0005] To overcome the shortcomings of the prior art, the present invention aims to provide a Ku-band integrated wide-angle scanning active phased array radar module. The antenna array and wave control circuit are integrated, which not only reduces the overall space of the phased array, thereby maximizing the performance of the phased array within a limited space, but also avoids the problems of high component consumption and high production costs caused by the use of similar components in multiple circuits in separate solutions. The module of the present invention can be spliced ​​through dielectric screw holes, which solves the problem that traditional integral arrays are more difficult to locate during maintenance, and even require large-scale replacement during maintenance, resulting in greater maintenance costs. Moreover, the modular array is more flexible in the design of large phased arrays.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A Ku-band integrated wide-angle scanning active phased array radar module includes a multilayer dielectric substrate, a multilayer copper-clad printed layer, 4n TR chips 13 and various circuit elements 14, integrating radiation, control, power supply and radio frequency feeding functions, where n is the number of groups of TR chips 13. The copper-clad printed layers are stacked and are divided into antenna radiating layer 1, digital control layer, power supply layer, control power supply multiplexing layer, feed network layer and ground layer according to their functions. The antenna radiating layer 1 is used to form a high-gain wide-angle scanning array beam; The digital control layer is used to control the amplitude modulation, phase modulation, and transmit / receive channel switching of the TR chip 13; The power supply layer is used to provide the positive and negative voltages required for the normal operation of the TR chip 13; The control power supply multiplexing layer 5 provides a negative voltage to the TR chip 13 and a portion of the power supply lines of the TR chip 13. The feed network layer is used to transmit low-power radio frequency signals to the TR chip 13, and finally amplify and transmit the signals to the antenna radiating layer 1. The ground layer is used to shield the electromagnetic influence between itself and the adjacent copper-clad printed layers with other functions, and is used in conjunction with the antenna radiating layer 1 to achieve directional radiation, or in conjunction with the feed network layer to achieve radio frequency signal power distribution. A dielectric substrate is arranged between two adjacent copper-clad printed layers. The outermost copper-clad printed layer is equipped with twelve TR chips 13 and various circuit elements 14. The TR chips 13 and circuit elements 14 are electrically connected to the copper-clad printed layers with corresponding functions.

[0007] The dielectric substrate has eleven layers, and the eleven layers are arranged in the following order: first substrate 1001, second substrate 1002, third substrate 1003, fourth substrate 1004, fifth substrate 1005, sixth substrate 1006, seventh substrate 1007, eighth substrate 1008, ninth substrate 1009, tenth substrate 1010 and eleventh substrate 1011. The first substrate 1001, the third substrate 1003, the fifth substrate 1005, the seventh substrate 1007, the ninth substrate 1009 and the eleventh substrate 1011 are printed circuit boards; the second substrate 1002, the fourth substrate 1004, the sixth substrate 1006, the eighth substrate 1008 and the tenth substrate 1010 are prepregs.

[0008] The antenna radiating layer 1 is printed on the non-adjacent surfaces of the first substrate 1001 and the second substrate 1002; The digital control layer includes a first digital control layer 3 and a second digital control layer 4, which are respectively printed on the adjacent surfaces of the third substrate 1003 and the second substrate 1002 or the fourth substrate 1004. The power supply layer includes a first power supply layer 7 and a second power supply layer 8, which are respectively printed on the adjacent surfaces of the seventh substrate 1007 and the sixth substrate 1006 or the eighth substrate 1008. The control power supply multiplexing layer 5 is printed on the adjacent surfaces of the fifth substrate 1005 and the fourth substrate 1004; The power supply network layer includes an inner network layer 10 and an outer network layer 12. The inner network layer 10 is printed on the adjacent surfaces of the ninth substrate 1009 and the tenth substrate 1010, and the outer network layer 12 is printed on the adjacent surfaces of the eleventh substrate 1011 and the tenth substrate 1010. The ground layer includes a first ground layer 2, a second ground layer 6, a third ground layer 9, and a fourth ground layer 11. The first ground layer 2 is printed on the adjacent surfaces of the first substrate 1001 and the second substrate 1002. The second ground layer 6 is printed on the adjacent surfaces of the fifth substrate 1005 and the sixth substrate 1006. The third ground layer 9 is printed on the adjacent surfaces of the ninth substrate 1009 and the eighth substrate 1008. The fourth ground layer 11 is printed on the adjacent surfaces of the eleventh substrate 1011 and the tenth substrate 1010. The fourth ground layer 11 is shared with the inner network layer 10 and the outer network layer 12 to realize radio frequency signal power distribution. Among them, the radiating patch antenna feed via 1201 in the antenna radiating layer 1 is connected to the antenna transmission line 1202 in the external network layer 12, and the control lines in the first digital control layer 3, the second digital control layer 4, and the control power supply multiplexing layer 5 are connected; the power supply lines in the first power supply layer 7 and the second power supply layer 8 are connected; the control power supply multiplexing layer 5 shares a ground copper area with the digital control layer and the power supply layer, and control lines and power supply lines are printed thereon; the radio frequency transmission lines in the internal network layer 10 and the external network layer 12 are connected; the first ground layer 2, the second ground layer 6, the third ground layer 9 and the fourth ground layer 11, the reference ground of the first digital control layer 3, the reference ground of the second digital control layer 4, the reference ground of the control power supply multiplexing layer 5, the reference ground of the internal network layer 10, and the reference ground of the external network layer 12 share a copper area, and all of the above lines adopt the form of grounded coplanar waveguides.

[0009] The TR chips 13 are all four-channel TR chips, configured on the surface of the external network layer 12. Each TR chip 13 integrates four independent channels, which are connected to the four antenna elements in the antenna array respectively. Each channel integrates power management, temperature sensor and wave control circuit module, and supports switching of transmit and receive modes. The TR chip 13 adopts a daisy-chain control architecture. It realizes amplitude modulation, phase modulation and switching control through chip grouping, pin sharing and wiring multiplexing. The 4n TR chips 13 are divided into n groups of four. The TR chips 13 in each group are cascaded. The n groups of TR chips 13 are connected in parallel. The data input pin of one TR chip 13 in the same group is connected to the data output pin of another TR chip 13 for data communication and data initialization. The clock input pin of one TR chip 13 in the same group is connected to the clock output pin of another TR chip 13 to ensure clock synchronization of the TR chips 13 in the group. The data input and data output of the TR chips 13 at both ends of each group are connected in parallel. The clock input and clock output of the TR chips 13 at both ends of each group are connected in parallel. The TR chips 13 in the entire module are connected in parallel on the same control pin and are globally multiplexed. The wiring of the daisy chain control architecture is printed on the first digital control layer 3, the second digital control layer 4, and the control power supply multiplexing layer 5.

[0010] The antenna radiating layer 1 is a single-layer wide-angle scanning microstrip patch antenna array, comprising n groups of 4×4 matrix-arranged microstrip patch units 101. II-shaped structures 102 are arranged between the microstrip patch units 101 in the polarization direction to extend the beam scanning range of the microstrip patch units 101 in their polarization direction and orthogonal polarization direction. Each II-shaped structure 102 includes a II-shaped patch 103. The opening direction of the II-shaped patch 103 is along the polarization direction of the microstrip patch unit 101. The microstrip patch unit 101 is located within the opening of adjacent II-shaped patches 103. Adjacent II-shaped patches 103 are not connected to each other. Three or five grounding vias 104 are symmetrically arranged in the opening between the II-shaped patch 103 and the adjacent microstrip patch unit 101 along the orthogonal polarization direction. The spacing between the grounding vias 104 and the II-shaped patches 103 along the polarization direction of the microstrip patch unit 101 is less than 1 / 4 of the spacing between adjacent microstrip patch units 101.

[0011] The first ground layer 2 has rectangular annular grooves 201 etched between adjacent microstrip patch units 101 along the polarization direction and the orthogonal polarization direction, and all rectangular annular grooves 201 are not interconnected.

[0012] The inner network layer 10 and the outer network layer 12 together constitute a 4n equal power distribution feeder network, using... The hierarchical network architecture is connected to the signal input port of the TR chip 13. If n is even, each hierarchical network adopts a 1:1 equal power distribution feed network; otherwise, one hierarchical network adopts a 1:2 unequal power distribution feed network, and the remaining hierarchical networks adopt a 1:1 equal power distribution feed network. The 1 / 4n equal power distribution feeder network is broken down into: The network consists of several parts, distributed across the external network layer 12. Each part has fewer than eight equal-power distribution feed networks. The equal-power distribution feed networks of each part are connected via trunk lines printed on the internal network layer 10. The equal-power distribution feed networks of each part on the external network layer 12 are respectively connected via... Each feed network coaxial via is connected to the trunk of the inner network layer 10, and shielding holes are set around the 1-to-4n equal power distribution feed network trace to shield electromagnetic interference. The antenna transmission line 1202 of the outer network layer 12 is connected to the input / output pins of the TR chip 13 for antenna impedance matching and radio frequency signal transmission.

[0013] The circuit element 14 includes no less than 8n capacitors 1403, 4n-1 resistors 1402, 1 radio frequency signal connector 1404, and 1 digital header 1401; The digital header 1401 includes a positive voltage pin, a negative voltage pin, and a communication control pin. The negative voltage pin is connected to the negative voltage power supply pin of the TR chip 13 through the negative voltage power supply trace of the power supply multiplexing layer 5 to provide the negative voltage required by the TR chip 13. The communication control pin is connected to the control pin of the TR chip 13 through the first digital control layer 3 and the second digital control layer 4 to transmit communication and control signals. The positive voltage pin is connected to one end of the capacitor 1403. The positive voltage pin can withstand a current of no more than 2.5A. The other end of the capacitor 1403 is connected to the positive voltage power supply pin of the TR chip 13 through the positive voltage power supply trace of the first power supply layer 7 and the second power supply layer 8. The capacitor's energy storage function ensures the continuous and stable delivery of high-power voltage to the TR chip 13. The capacitor 1403 is in surface mount form. Each TR chip 13 is connected to at least one capacitor. All capacitor values ​​include at least two types, with the maximum value being 1 to 3 times the minimum value. The size also corresponds to the value. They are distributed on the external network layer 12 near the non-wired, device-free area of ​​the TR chip 13. The resistor 1402 is disposed between two adjacent equal power distribution feed networks in the external network layer 12 to improve the isolation between the output ports. The radio frequency signal connector 1404 is connected to a first-order equal power distribution feed network via a feed network coaxial via, and is used to introduce externally input radio frequency signals.

[0014] The power supply layer is connected to multiple positive voltage pins of the digital header 1401, providing high-power power supply through multi-pin confluence, and achieving high-power current return through large-area copper plating of the first power supply layer 7 and the second power supply layer 8, so as to meet the high-power power supply and heat dissipation requirements of 4n TR chips 13.

[0015] Each edge of the module shall have at least one medium screw hole 15.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. This invention employs a coplanar periodic II-shaped structure 102, enabling the narrow-beam antenna array to simultaneously achieve wide-angle scanning in both azimuth and elevation directions on a single-layer dielectric substrate. Compared to traditional wide-beam methods that add additional structures such as electric walls, multiple dielectric layers, and metasurface layers to a single-layer radiating structure, the antenna radiating layer constructed in this invention has a lower profile, lighter weight, and is easier to integrate.

[0017] 2. The rectangular annular groove 201 etched in this invention, compared with electromagnetic band gap, decoupling network and loading decoupling surface, this defective decoupling method does not require loading additional structure and can effectively avoid deterioration of the original performance, enhance the performance of the periodic II-shaped structure in the extended beam scanning range, and is more suitable for ensuring good performance of each unit in a compact array space.

[0018] 3. This invention employs a four-channel TR chip with an integrated beam control circuit module that combines phase shifting, power amplification, filtering, and switching functions. Compared to using a single-channel TR chip phased array, this significantly reduces the number of TR chips, thereby reducing their footprint and acquisition costs. This allows for beam control within a compact array space while reserving more space for other components.

[0019] 4. In this invention, the digital control layer circuit is designed based on the daisy chain communication control method. By grouping and cascading and reusing pins, this method is more conducive to reducing the number of module control pins and components compared with the traditional wiring method, so as to realize the communication control of TR in a compact array space.

[0020] 5. The present invention employs a multi-pin confluence, large-area copper-clad return current, combination of large and small capacitors, and distributed energy storage for power supply. This allows for the use of small components and small pin headers within a compact array space to meet the requirements for high-power signal transmission and continuous stable power supply.

[0021] 6. In this invention, the branch decomposition, layered layout, and distributed placement of the 1-to-4n equal power distribution feeder network, compared to the traditional overall single-layer layout, makes it easier to free up more space for component placement within a compact array plane. Compared to the inner single-layer network, it avoids the high cost associated with the deep burial process of isolation resistors.

[0022] 7. This invention, by utilizing the dielectric screw holes on the edge of the module, enables the splicing of multiple identical modules, making the scale of large arrays controllable, while avoiding the large maintenance costs caused by damage to the overall array radiation structure.

[0023] In summary, the modular design of this invention makes the radar module small in size and light in weight, easy to integrate and maintain, with excellent performance, stable operation, and low cost. Attached Figure Description

[0024] Figure 1 This is a structural diagram of the integrated wide-angle scanning active phased array radar module for the Ku-band of this invention.

[0025] Figure 2 This is a cross-sectional layered layout diagram of the integrated wide-angle scanning active phased array radar module of the Ku-band of this invention.

[0026] Figure 3 This is a surface view of the antenna radiating layer 1 of the integrated wide-angle scanning active phased array radar module of the Ku-band of the present invention.

[0027] Figure 4 This is a surface view of the first ground layer 2 of the Ku-band integrated wide-angle scanning active phased array radar module of the present invention.

[0028] Figure 5 This is a perspective view of the II-shaped structure 102 of the Ku-band integrated wide-angle scanning active phased array radar module of the present invention, and an explanatory diagram of its working mechanism.

[0029] Figure 6 This is a perspective view of the antenna element area of ​​the Ku-band integrated wide-angle scanning active phased array radar module of the present invention.

[0030] Figure 7 This is a bottom view of the antenna feeding structure in the external network layer 12 at the corresponding position of the antenna element of the Ku-band integrated wide-angle scanning active phased array radar module of the present invention.

[0031] Figure 8(a) shows the internal architecture and pin diagram of the four-channel TR chip of the Ku-band integrated wide-angle scanning active phased array radar module of the present invention.

[0032] Figure 8(b) is a pinout diagram of the four-channel TR chip of the Ku-band integrated wide-angle scanning active phased array radar module of the present invention.

[0033] Figure 9(a) shows the daisy-chain architecture of the digital control layer circuit of the Ku-band integrated wide-angle scanning active phased array radar module of the present invention.

[0034] Figure 9(b) shows the TR chip grouping of the digital control layer circuit of the Ku-band integrated wide-angle scanning active phased array radar module of the present invention.

[0035] Figure 10 This is a surface view of the first digital control layer 3 of the integrated wide-angle scanning active phased array radar module in the Ku-band of the present invention.

[0036] Figure 11 This is a surface view of the second digital control layer 4 of the Ku-band integrated wide-angle scanning active phased array radar module of the present invention.

[0037] Figure 12 This is a surface view of the control and power supply multiplexing layer 5 of the integrated wide-angle scanning active phased array radar module of the Ku-band of the present invention.

[0038] Figure 13 This is a surface view of the second ground layer 6 of the Ku-band integrated wide-angle scanning active phased array radar module of the present invention.

[0039] Figure 14 This is a surface view of the first power supply layer 7 of the integrated wide-angle scanning active phased array radar module of the Ku-band of the present invention.

[0040] Figure 15This is a surface view of the second power supply layer 8 of the integrated wide-angle scanning active phased array radar module in the Ku-band of the present invention.

[0041] Figure 16 This is a surface view of the third ground layer 9 of the Ku-band integrated wide-angle scanning active phased array radar module of the present invention.

[0042] Figure 17 This is a diagram of the one-to-twelve equal power distribution network architecture of the integrated wide-angle scanning active phased array radar module of the Ku-band of this invention.

[0043] Figure 18 This is a surface view of the internal network layer 10 of the Ku-band integrated wide-angle scanning active phased array radar module of the present invention.

[0044] Figure 19 This is a surface view of the fourth ground layer 11 of the Ku-band integrated wide-angle scanning active phased array radar module of the present invention.

[0045] Figure 20 This is a surface view of the external network layer 12 of the Ku-band integrated wide-angle scanning active phased array radar module of the present invention.

[0046] Figure 21 This is a layout diagram of the circuit element 14 of the integrated wide-angle scanning active phased array radar module of the Ku-band of the present invention.

[0047] Figure 22 This is a diagram showing the larger array structure of the integrated wide-angle scanning active phased array radar module of the Ku-band of this invention.

[0048] Figure 23(a) is a curve of the port reflection coefficient of some array elements in the Ku-band integrated wide-angle scanning active phased array radar module of the present invention before loading the rectangular ring groove.

[0049] Figure 23(b) is a curve of the port reflection coefficient of some array elements in the Ku-band integrated wide-angle scanning active phased array radar module of the present invention after loading a rectangular ring slot.

[0050] Figure 24(a) is a curve of the coupling coefficient of some array elements in the Ku-band integrated wide-angle scanning active phased array radar module of the present invention before loading the rectangular ring slot.

[0051] Figure 24(b) is a curve showing the coupling coefficient of some array elements in the Ku-band integrated wide-angle scanning active phased array radar module of the present invention after loading a rectangular ring slot.

[0052] Figure 25(a) shows the 16.3 GHz E-plane scanning pattern of the Ku-band integrated wide-angle scanning active phased array radar module of the present invention.

[0053] Figure 25(b) shows the H-plane scanning pattern of the Ku-band integrated wide-angle scanning active phased array radar module of the present invention at 16.3 GHz.

[0054] Figure 26 This is a graph showing the reflection coefficient curves of the input port #1 and output ports #2~#13 of the one-to-twelve equal power feeder network of the Ku-band integrated wide-angle scanning active phased array radar module of the present invention.

[0055] Figure 27 This is a diagram showing the transmission coefficient amplitude of the input port #1 to the output ports #2 to #13 of the one-to-twelve equal power feeder network of the Ku-band integrated wide-angle scanning active phased array radar module of this invention.

[0056] Figure 28 This is a phase diagram of the transmission coefficients from input port #1 to output ports #2 to #13 of the one-to-twelve equal power feeder network of the Ku-band integrated wide-angle scanning active phased array radar module of this invention.

[0057] In the diagram, 1 is the antenna radiating layer, 2 is the first ground plane layer, 3 is the first digital control layer, 4 is the second digital control layer, 5 is the control power supply multiplexing layer, 6 is the second ground plane layer, 7 is the first power supply layer, 8 is the second power supply layer, 9 is the third ground plane layer, 10 is the internal network layer, 11 is the fourth ground plane layer, 12 is the external network layer, 13 is the TR chip, 14 is the circuit element, 15 is the dielectric via, 1001 is the first substrate, 1002 is the second substrate, 1003 is the third substrate, 1004 is the fourth substrate, 1005 is the fifth substrate, 1006 is the sixth substrate, 1007 is the seventh substrate, 1008 is the eighth substrate, and 1009 is the... Nine substrates are defined as follows: 1010 is the tenth substrate, 1011 is the eleventh substrate, 101 is a microstrip patch unit, 102 is a type II structure, 103 is a type II patch, 104 is a grounding via, 201 is a rectangular annular slot, 300 is an inter-group trace, 400 is an intra-group connection line, 500 is a global trace, 301 is the first inter-group connection line, 302 is the second inter-group connection line, 303 is the third inter-group connection line, 1201 is an antenna feed coaxial via, 1202 is an antenna transmission line, 1203 is an antenna feed outer conductor coaxial via, 1101 is the first main trunk connection line, 1102 is the second main trunk connection line, and 1103 is the third main trunk connection line. 1204 is the chip grounding hole, 1205 is the first feeder main trunk, 1206 is the second feeder main trunk, 1207 is the third feeder main trunk, 1401 is the digital header, 1402 is the resistor, 1403 is the capacitor, 1404 is the RF signal connector, P1 is the first feeder type coaxial via, P2 is the second feeder type coaxial via, P3 is the third feeder type coaxial via, P4 is the fourth feeder type coaxial via, P5 is the fifth feeder type coaxial via, P6 is the sixth feeder type coaxial via, #1 is the total port number of the 1-to-12 equal power distribution feeder network, and #2~#13 are the output port numbers of the 1-to-12 equal power distribution feeder network. Detailed Implementation

[0058] Compared to common X-band radars, the Ku-band phased array radar in this invention offers superior penetration and anti-jamming capabilities. Furthermore, the modular array design provides better maintainability and greater flexibility in scale control compared to a monolithic array. However, the small physical size of the array at high frequencies severely limits the design space for circuit integration and layout, significantly increasing design complexity. To achieve circuit integration within a compact array space with a spacing of less than 0.5λ between elements, and to enable wide-angle scanning, this invention provides a Ku-band integrated wide-angle scanning active phased array radar module.

[0059] The present invention will now be described in detail with reference to the accompanying drawings.

[0060] like Figure 1 and Figure 2As shown, a Ku-band integrated wide-angle scanning active phased array radar module includes eleven dielectric substrates, twelve copper-clad printed layers, 12 TR chips 13 and various circuit elements 14, integrating radiation, control, power supply and radio frequency feeding functions. The copper-clad printed layers are stacked and are divided into antenna radiating layer 1, digital control layer, power supply layer, control power supply multiplexing layer, feed network layer and ground layer according to their functions. The antenna radiating layer 1 is used to form a high-gain wide-angle scanning array beam; The digital control layer is used to control the amplitude modulation, phase modulation, and transmit / receive channel switching of the TR chip 13; The power supply layer is used to provide the positive and negative voltages required for the normal operation of the TR chip 13; The control power supply multiplexing layer 5 provides a negative voltage to the TR chip 13 and a portion of the power supply lines of the TR chip 13. The power supply network layer is used to distribute radio frequency signals to the TR chip 13 at equal power, and finally amplify and transmit the signals to the antenna radiation layer 1. The ground layer is used to shield the electromagnetic influence between itself and the adjacent copper-clad printed layers with other functions, and is used in conjunction with the antenna radiating layer 1 to achieve directional radiation, or in conjunction with the feed network layer to achieve radio frequency signal power distribution. A dielectric substrate is arranged between two adjacent copper-clad printed layers. The outermost copper-clad printed layer is equipped with twelve TR chips 13 and various circuit elements 14. Each dielectric substrate has multiple matching metallized vias. The TR chips 13 and circuit elements 14 are electrically connected to the copper-clad printed layers with corresponding functions through the metallized vias. The eleven dielectric substrates are arranged in the following order: first substrate 1001, second substrate 1002, third substrate 1003, fourth substrate 1004, fifth substrate 1005, sixth substrate 1006, seventh substrate 1007, eighth substrate 1008, ninth substrate 1009, tenth substrate 1010 and eleventh substrate 1011. The first substrate 1001, the seventh substrate 1007, the ninth substrate 1009 and the eleventh substrate 1011 are printed on Rogers RO4350B substrate (dielectric constant of 3.66 and loss tangent of 0.004), the third substrate 1003 and the fifth substrate 1005 are printed on FR4 substrate (dielectric constant of 4.4 and loss tangent of 0.02), and the upper and lower surfaces of the printed substrates are printed layers; the second substrate 1002, the fourth substrate 1004, the sixth substrate 1006, the eighth substrate 1008 and the tenth substrate 1010 are made of PP material, mainly used for bonding adjacent substrates.

[0061] The antenna radiating layer 1 is printed on the non-adjacent surfaces of the first substrate 1001 and the second substrate 1002; The digital control layer includes a first digital control layer 3 and a second digital control layer 4, which are respectively printed on the adjacent surfaces of the third substrate 1003 and the second substrate 1002 or the fourth substrate 1004. The power supply layer includes a first power supply layer 7 and a second power supply layer 8, which are respectively printed on the adjacent surfaces of the seventh substrate 1007 and the sixth substrate 1006 or the eighth substrate 1008. The control power supply multiplexing layer 5 is printed on the adjacent surfaces of the fifth substrate 1005 and the fourth substrate 1004; The power supply network layer includes an inner network layer 10 and an outer network layer 12. The inner network layer 10 is printed on the adjacent surfaces of the ninth substrate 1009 and the tenth substrate 1010, and the outer network layer 12 is printed on the adjacent surfaces of the eleventh substrate 1011 and the tenth substrate 1010. The ground layer includes a first ground layer 2, a second ground layer 6, a third ground layer 9, and a fourth ground layer 11. The first ground layer 2 is printed on the adjacent surfaces of the first substrate 1001 and the second substrate 1002. The second ground layer 6 is printed on the adjacent surfaces of the fifth substrate 1005 and the sixth substrate 1006. The third ground layer 9 is printed on the adjacent surfaces of the ninth substrate 1009 and the eighth substrate 1008. The fourth ground layer 11 is printed on the adjacent surfaces of the eleventh substrate 1011 and the tenth substrate 1010. The fourth ground layer 11 is shared with the inner network layer 10 and the outer network layer 12 to realize radio frequency signal power distribution. In this configuration, the radiating patch in antenna radiating layer 1 is connected to the TR chip 13 on the external network layer 12 to transmit amplitude and phase information. The control lines in the first digital control layer 3, the second digital control layer 4, and the control power supply multiplexing layer 5 are connected through metallized vias. The power supply lines in the first power supply layer 7 and the second power supply layer 8 are connected through metallized vias. The control power supply multiplexing layer 5 shares a grounded copper area with the digital control layer and the power supply layer, and is printed with both control lines and power supply lines. Since the control power supply multiplexing layer 5 provides a negative voltage, it is not connected to the first power supply layer 7 and the second power supply layer 8. The radio frequency transmission lines in the internal network layer 10 and the external network layer 12 are connected through metallized vias. The reference ground of the first ground layer 2, the second ground layer 6, the third ground layer 9, the fourth ground layer 11, the reference ground of the first digital control layer 3, the reference ground of the second digital control layer 4, the reference ground of the control power supply multiplexing layer 5, the reference ground of the internal network layer 10, and the reference ground of the external network layer 12 share a copper area through metallized vias. All of the above lines adopt the form of grounded coplanar waveguides. In addition, to expand the application of the module, eight screw holes 15 are set on the edge of the module, one screw hole at each of the four corners and two screw holes on each of the two long sides. Multiple modules can be spliced ​​together by using studs to form a larger array.

[0062] like Figure 3 As shown, the antenna radiating layer 1 is a single-layer wide-angle scanning microstrip patch antenna array, comprising three groups of 4×4 (4×12) matrix microstrip patch elements 101. These microstrip patch elements employ a commonly used U-slot microstrip patch antenna. Along the polarization direction of each microstrip patch element 101, a II-shaped structure 102 is positioned between adjacent microstrip patch elements 101 to extend the beam scanning range of the polarization direction and its orthogonal polarization direction. Here, the polarization direction is called the elevation direction, and the orthogonal polarization direction is called the azimuth direction. To avoid grating lobes during beam scanning and to obtain the highest possible gain, the element spacing in both the azimuth and elevation directions is 0.5λ, where λ is the free-space wavelength of 16.3 GHz. Therefore, the overall module planar dimensions are 110.43 mm × 36.81 mm.

[0063] To extend the phased array scanning range, in addition to improving beam performance, the impact of mutual coupling on the phased array scanning performance was also considered. For example... Figure 4 As shown, in the first ground layer 2, rectangular annular grooves 201 are etched between adjacent microstrip patch units 101 along the pitch and azimuth directions. All rectangular annular grooves 201 are not interconnected. The rectangular annular grooves 201 confine the surface current around them, blocking the flow path of coupled current between adjacent microstrip patch units 101. Furthermore, by utilizing their closed-loop characteristics and the opposite propagation paths of the coupled current between adjacent microstrip patch units 101, the coupling between adjacent microstrip patch units 101 is further weakened, while avoiding the performance degradation problem of the microstrip patch unit 101 caused by conventional decoupling structures. In addition, the rectangular annular grooves 201 etched along the polarization direction and the orthogonal polarization direction can respectively confine and enhance the equivalent current of the long arm of the orthogonal polarization direction of the adjacent II-shaped patch 103, as well as the equivalent magnetic current of the two long arms in the polarization direction of a single II-shaped patch 103, further improving the scanning performance.

[0064] Figure 5The loaded II-shaped structure is shown. Each II-shaped structure 102 includes an II-shaped patch 103. The opening direction of the II-shaped patch 103 is along the polarization direction of the microstrip patch unit 101. The microstrip patch unit 101 is located within the opening of the adjacent II-shaped patch 103. The adjacent II-shaped patches 103 are not connected to each other. Three grounding vias 104 are symmetrically arranged along the orthogonal polarization direction in the opening between the II-shaped patch 103 and the adjacent microstrip patch unit 101. The spacing between the grounding vias 104 and the II-shaped patch 103 along the polarization direction of the microstrip patch unit 101 is less than 1 / 4 of the spacing between the adjacent microstrip patch units 101. That is, less than λ / 4. When the array scans in the azimuth direction, the long arms of the polarization direction of the two adjacent II-shaped patches 103 in the azimuth direction are equivalent to a current source loaded in the middle of the two adjacent microstrip patch units 101 in the azimuth direction, thereby reducing the equivalent spacing between the two adjacent units and widening the scanning range in the azimuth direction. When the array scans in the elevation direction, the two long arms of the orthogonal polarization direction of the II-shaped patches 103 in the elevation direction are equivalent to a magnetic current source loaded between the two units in the elevation direction. At the same time, combined with the grounding via 104 containing the vertical current component and relying only on the II-shaped patches, the scanning range of the elevation beam is widened.

[0065] The overall architecture of a single unit and its connection to the external network layer 12 are as follows: Figure 6 and Figure 7 As shown, the U-shaped slot microstrip patch unit 101 is connected to the antenna transmission line 1202 on the external network layer 12 via the antenna feed quasi-coaxial via 1201, and then to the port pin Port #0 of the TR chip 13 for electromagnetic amplitude and phase information transmission. The antenna feed quasi-coaxial via 1201 and the antenna feed outer conductor quasi-coaxial via 1203 together form a quasi-coaxial structure, reducing signal transmission loss.

[0066] The TR chips 13 are all four-channel TR chips, model ARW9654, and their internal architecture and pin distribution are shown in Figure 8(a). The TR chip 13 contains four channels, distributed from the COM port via a four-way power splitter / combiner network. The four channels are independent and can be connected to the four antenna elements in the antenna array via ANT1, ANT2, ANT3, and ANT4 pins respectively. Each channel supports both electromagnetic signal reception and transmission. During transmission, the signal from each channel flows through a digital phase shifter (PS), an RF switch, a digitally controlled attenuator (DA), a digital signal analyzer (DSA) with integrated filtering and sampling functions, a power amplifier (PA), and the RF switch, before being transmitted to the antenna. During reception, the signal from each channel flows from the antenna through the RF switch, a limiting low-noise amplifier (LAN), the DSA with integrated filtering and sampling functions, an operational amplifier (AMP), the RF switch, and the digital phase shifter (PS), before being transmitted to the TR chip 13. In addition to the above functional circuits, power management, a temperature sensor, and a wave control circuit module are also integrated. To achieve the above functions, the TR chip 13 extends to sixty pins, and the corresponding functions of each pin are shown in Figure 8(b). In antenna arrays of the same size, the use of this multi-channel, multi-functional integrated TR chip can significantly reduce the number of TR chips compared to a single-channel TR chip, thereby reducing the planar space it occupies and lowering its purchase cost.

[0067] The TR chip 13 is controlled using a daisy-chain architecture as shown in Figure 9(a). This architecture divides the 12 TR chips into 3 groups, with each group consisting of 4 TR chips. The grouping is shown in Figure 9(b), where Chip 1 to Chip 4 form one group, Chip 5 to Chip 8 form another group, and Chip 9 to Chip 12 form yet another group. The four TR chips within a group are cascaded via an internal connection line 400. Specifically, the data output pin SDO and clock output pin CLKO of one TR chip are connected to the data input pin SDI and clock input pin CLKI of another TR chip, respectively, and this process is repeated sequentially. For example, in the first group of TR chips, the clock line CLKI_1 in the intra-group connection line 400 is connected to the clock input pin CLKI of TR chip Chip1, the clock output pin CLKO of TR chip Chip1 is connected to the clock input pin CLKI of TR chip Chip2, then the clock output pin CLKO of TR chip Chip2 is connected to the clock input pin CLKI of TR chip Chip3, and then the clock output pin CLKO of TR chip Chip3 is connected to the clock input pin CLKI of TR chip Chip4. Similarly, the data input line SDI_1 in the intra-group connection line 400 is connected to the data input pin SDI of TR chip Chip1, the data output pin SDO of TR chip Chip1 is connected to the data input pin SDI of TR chip Chip2, the data output pin SDO of TR chip Chip2 is connected to the data input pin SDI of TR chip Chip3, and the data output pin SDO of TR chip Chip3 is connected to the data input pin SDI of TR chip Chip4.

[0068] The chip select pin CS, data load pin LD, receive control pin TRR, and transmit control pin TRT of TR chips from different groups are connected in parallel via inter-group trace 300, and these four pins of all TR chips are brought out and multiplexed via global trace 500. For example... Figures 10-12 As shown, inter-group traces 300, intra-group connections 400, and global traces 500 are printed within the first digital control layer 3, digital control layer 4, and control power supply multiplexing layer 5, respectively. Based on the TR chip grouping, the inter-group traces 300 include a first inter-group connection 301, a second inter-group connection 302, and a third inter-group connection 303. This chip grouping, pin sharing, and trace multiplexing method reduces the number of module control pins and components while lowering the complexity of the control program design, enabling orderly control of the TR chip 13 within a compact array space. For heat dissipation, the bottom of the TR chip 13 is connected to a chip grounding hole 1204.

[0069] To ensure the normal operation of TR chip 13, as shown in Figure 8(b), a positive voltage of 3.3V needs to be provided to the VDD_FE1, VDD_FE2, VDD_FE3, VDD_FE1, and VDD_DIG pins of TR chip 13, and a negative voltage of -5V needs to be provided to NV5 of TR chip 13. The power supply voltage is supplied by... Figure 21 The digital header is provided, connected to the printed copper layer via metallized vias, and then powered to TR chip 13 via metallized vias near the corresponding power supply pins. The -5V voltage trace is printed on... Figure 12 Control power supply multiplexing layer 5, multiple 3.3V voltages flow through it. Figures 14-15 The entire copper-clad area of ​​the first power supply layer 7 and the second power supply layer 8 is used to ensure the return of multiple high currents. A connection is set between the first power supply layer 7, the second power supply layer 8 and the control power supply multiplexing layer 5. Figure 13 The second ground layer 6 isolates the influence between positive and negative voltages. The area around the metallized vias that pass through the first power supply layer 7 and the second power supply layer 8 and are unrelated to the 3.3V power supply is cut out to avoid interference with other functional layers and power supplies.

[0070] Because the space for a 4×12 antenna array is very limited, therefore, the following is adopted: Figure 21 The digital header 1401 occupies an area of ​​less than 0.25λ × 0.5λ in the center plane. Because the header diameter is less than 0.5mm, a single header can only provide 2.5A of operating current. Therefore, to meet the 3.3V positive voltage and 9A high current required by 12 TR chips 13, four headers are used to power the entire module's TR chips, while capacitors 1403 store energy to ensure a continuous voltage supply. Due to limited array space, capacitors of different sizes are used for energy storage, and they are distributed across available gaps. The different sizes correspond to different capacitance values; specifically, twelve 470uF capacitors and two 1000uF capacitors are used for energy storage and voltage supply.

[0071] The inner network layer 10 and the outer network layer 12 together constitute a 1 / 2 equal power distribution feed network, which is connected to the COM pin of the TR chip 13 to transmit radio frequency signals. A connection is set between the feed network layer and the power supply layer. Figure 16 The third ground layer 9 shown is isolated from each other. Figure 17 This demonstrates a twelve-equal power distribution feeder network architecture, which adopts... In a hierarchical network, the first-level hierarchical network uses a 1:2 unequal power distribution feeder network, while the remaining hierarchical networks use a 1:1 equal power distribution feeder network. For example... Figure 20As shown, the 1:12 equal power distribution feeder network is divided into three main sections: the first feeder backbone 1205, the second feeder backbone 1206, and the third feeder backbone 1207. These three feeder backbones are distributed in the outer network layer 12, thus freeing up more space for the placement of the bottom-level components 14 of the module within a compact array plane. The three backbones correspond to a 1:8 equal power distribution feeder network consisting of one 1:2 unequal power distribution feeder network, seven 1:1 equal power distribution feeder networks, and a 1:4 equal power distribution feeder network consisting of three 1:1 equal power distribution feeder networks, respectively. All three feeder backbones are printed on... Figure 18 The backbone connections in the internal network layer 10 are connected to their respective coaxial vias. The second backbone connection 1102 connects to the third coaxial via P3 of the first feeder backbone 1205 and the fifth coaxial via P5 of the second feeder backbone 1206. The third backbone connection 1103 connects to the fourth coaxial via P4 of the first feeder backbone 1205 and the sixth coaxial via P6 of the third feeder backbone 1207. Furthermore, the first backbone connection 1101 connects to the first coaxial via P1 of the RF signal connector 1404 and the second coaxial via P2 of the first feeder backbone 1205, transmitting RF signals into the network. Shielding holes are provided around the 1-to-12 equal power distribution feeder network traces to shield against electromagnetic interference. Figure 19 The fourth ground layer 11 is located between the inner network layer 10 and the outer network layer 12, forming a grounded coplanar waveguide transmission line structure with these two layers while shielding them from mutual interference. Furthermore, the outer network layer 12 also houses antenna transmission lines 1202 connecting the U-slot patch to the ANT1, ANT2, ANT3, and ANT4 pins of the TR chip 13, which can transmit radio frequency signals and also be used for antenna impedance matching.

[0072] Figure 21 The distribution of the circuit element 14 on the external network layer is shown, including 14 capacitors 1403, 11 resistors 1402, 1 radio frequency signal connector 1404, and 1 digital header 1401. The digital header 1401 includes a positive voltage pin, a negative voltage pin, and a communication control pin. The negative voltage pin is connected to the negative voltage supply pin of the TR chip 13 through the negative voltage supply trace of the power supply multiplexing layer 5, providing the negative voltage required by the TR chip 13. The communication control pin is connected to the control pin of the TR chip 13 through the first digital control layer 3 and the second digital control layer 4, for transmitting communication and control signals. The positive voltage pin is connected to one end of the capacitor 1403, which has a current tolerance of no more than 2.5A. The other end of the capacitor 1403 is connected to the positive voltage supply pin of the TR chip 13 through the positive voltage supply trace of the first power supply layer 7 and the second power supply layer 8, utilizing the energy storage function of the capacitor to ensure the continuous and stable supply of high-power voltage to the TR chip 13. The capacitor 1403 is surface-mount, and each TR chip 13 is connected to at least one capacitor. The capacitor values ​​used include 470uF and 1000uF, with 14 470uF capacitors and 1000uF capacitors. Two 470uF surface mount capacitors, with a planar size 0.45 times that of a 1000uF surface mount capacitor, are placed on the outer network layer 12 in the non-wired, device-free area near the TR chip 13. The resistor 1402 is disposed between two adjacent equal power distribution feed networks in the external network layer 12 to improve the isolation between the output ports. The entire 4×12 active phased array module operates in the Ku band with a compact array space. Its three-dimensional physical dimensions are 11.04cm×3.68cm×0.31cm, and the physical dimensions of each element are 9.2mm×9.2mm. Without occupying additional area besides the antenna array space and without using expensive components or complex processes, it achieves compact integration of a wide-angle scanning active phased array at a lower cost. This is achieved through a single-layer design of the wide-angle scanning antenna array in the antenna radiation layer; pin, trace, and component multiplexing in the daisy-chain architecture of the digital control layer; multi-pin power supply with small header pins, large and small capacitor combinations, and distributed layout in the power supply layer, with large-area copper-clad plane return current; and separate backbone of the feed network layer, layered connection, and distributed layout. It integrates various connectors and circuit devices, and integrates circuit elements including various connectors and circuit devices.

[0073] like Figure 22 As shown, each corner of the module is provided with one medium screw hole 15, and two additional medium screw holes 15 are placed at equal intervals along each long side. A total of eight medium screw holes 15 are provided around the perimeter. Multiple modules can be spliced ​​together through these screw holes to construct a wide-angle detection radar array with controllable scale.

[0074] Simulation Experiment Simulation experiments were conducted using simulation software on the antenna element, phased array, and 1-to-12 equal power distribution feed network in the above embodiments, and the performance results are shown in Figure 23(a). Figure 28 As shown.

[0075] Figures 23(a) and 23(b) show the port reflection coefficients of some antenna elements in the array before and after etching rectangular ring slots on the ground. After etching the rectangular ring slots, the elements have lower reflection coefficients. With a reflection coefficient <-10dB, all elements can operate at 16~16.5GHz. The coupling coefficients before and after etching the rectangular ring slots are shown in Figures 24(a) and 24(b). The rectangular ring slots effectively reduce the coupling between array elements, with coupling coefficients all less than -17dB. According to the scanning patterns of the module in the E-plane and H-plane shown in Figures 25(a) and 25(b), the module can achieve a 3dB scanning range of ±63° in the E-plane (elevation plane) and ±53° in the H-plane (azimuth plane) at 16.3GHz, exhibiting wide-angle scanning characteristics. Existing single-layer Ku-band active phased arrays typically have a 3dB scanning range of ±45°. Solutions achieving a 3dB scanning range of ±60° generally require at least two substrate layers or a loaded metal cavity, resulting in a significant increase in array profile. This invention achieves a low-profile wide-angle scanning array.

[0076] Figures 26-28 It can be seen that the reflection coefficient of the main port #1 and output ports #2 to #13 of the 1-to-12 power distribution network is less than -15dB in the working frequency band. The transmission coefficient of each output port has good consistency, all around -15dB. The actual insertion loss is about 4.3dB. The maximum amplitude difference of each output port is less than 0.5dB, and the phase difference is less than 1°, showing good consistency.

[0077] The above are merely the preferred embodiments of the present invention and do not constitute any limitation on the present invention. Obviously, under the concept of the present invention, the structure, parameters and frequency of the present invention can be modified to obtain better performance of the present invention and to splice them into a larger-scale radar array, but these are all within the protection scope of the present invention.

Claims

1. A Ku-band integrated wide-angle scanning active phased array radar module, characterized in that, The application relates to a multi-layer medium substrate, a multi-layer copper-clad printed layer, 4n TR chips (13) and various circuit elements (14), and integrates radiation, control, power supply and radio frequency feeding functions, wherein n is the number of groups of the TR chips (13). The copper-clad printed layer is arranged in layers, and is divided into an antenna radiation layer (1), a digital control layer, a power supply layer, a control and power supply multiplexing layer, a feeding network layer and a ground layer according to the functions of the copper-clad printed layer. The antenna radiation layer (1) is used for forming a high-gain wide-angle scanning array beam. The digital control layer is used for realizing the control of amplitude modulation, phase modulation and transceiver channel switching of the TR chips (13). The power supply layer is used for providing positive voltage and negative voltage required by the TR chips (13) for normal operation. The control and power supply multiplexing layer (5) provides negative voltage for the TR chips (13) and part of the power supply circuit of the TR chips (13). The feeding network layer is used for transmitting small-power radio frequency signals to the TR chips (13), and finally amplifying and transmitting the signals to the antenna radiation layer (1). The ground layer is used for shielding the electromagnetic influence between the copper-clad printed layers with other functions adjacent to the ground layer, and is used in cooperation with the antenna radiation layer (1) to realize directional radiation, or is used in cooperation with the feeding network layer to realize radio frequency signal power distribution. A medium substrate is arranged between two adjacent copper-clad printed layers, and twelve TR chips (13) and various circuit elements (14) are arranged on the outermost copper-clad printed layer, and the TR chips (13) and the circuit elements (14) are electrically connected with the copper-clad printed layer with corresponding functions.

2. The radar module of claim 1, wherein, The medium substrate has eleven layers, and the arrangement order of the eleven layers is first substrate (1001), second substrate (1002), third substrate (1003), fourth substrate (1004), fifth substrate (1005), sixth substrate (1006), seventh substrate (1007), eighth substrate (1008), ninth substrate (1009), tenth substrate (1010) and eleventh substrate (1011). The first substrate (1001), the third substrate (1003), the fifth substrate (1005), the seventh substrate (1007), the ninth substrate (1009) and the eleventh substrate (1011) are made of printed plates; and the second substrate (1002), the fourth substrate (1004), the sixth substrate (1006), the eighth substrate (1008) and the tenth substrate (1010) are made of prepregs.

3. The radar module of claim 2, wherein, The antenna radiation layer (1) is printed on the non-adjacent surfaces of the first substrate (1001) and the second substrate (1002). The digital control layer includes a first digital control layer (3) and a second digital control layer (4), which are respectively printed on the adjacent surfaces of the third substrate (1003) and the second substrate (1002) or the fourth substrate (1004). The power supply layer includes a first power supply layer (7) and a second power supply layer (8), which are respectively printed on the adjacent surfaces of the seventh substrate (1007) and the sixth substrate (1006) or the eighth substrate (1008). The control power supply multiplexing layer (5) is printed on the adjacent surfaces of the fifth substrate (1005) and the fourth substrate (1004); The feeding network layer comprises an internal network layer (10) and an external network layer (12), the internal network layer (10) is printed on the adjacent surfaces of the ninth substrate (1009) and the tenth substrate (1010), and the external network layer (12) is printed on the adjacent surfaces of the eleventh substrate (1011) and the tenth substrate (1010); The ground layer comprises a first ground layer (2), a second ground layer (6), a third ground layer (9) and a fourth ground layer (11), the first ground layer (2) is printed on the adjacent surfaces of the first substrate (1001) and the second substrate (1002), the second ground layer (6) is printed on the adjacent surfaces of the fifth substrate (1005) and the sixth substrate (1006), the third ground layer (9) is printed on the adjacent surfaces of the ninth substrate (1009) and the eighth substrate (1008), and the fourth ground layer (11) is printed on the adjacent surfaces of the eleventh substrate (1011) and the tenth substrate (1010); the fourth ground layer (11) is shared by the internal network layer (10) and the external network layer (12) to realize power distribution of radio frequency signals; In the antenna radiation layer (1), the coaxial via (1201) of the radiation patch antenna feeding is connected with the antenna transmission line (1202) in the external network layer (12), the control lines in the first digital control layer (3), the second digital control layer (4) and the control power supply multiplexing layer (5) are connected, the power supply lines in the first power supply layer (7) and the second power supply layer (8) are connected, the control power supply multiplexing layer (5) is shared by the digital control layer and the power supply layer to have a ground copper area, and the control lines and the power supply lines are printed simultaneously; the radio frequency transmission lines in the internal network layer (10) and the external network layer (12) are connected; the first ground layer (2), the second ground layer (6), the third ground layer (9) and the fourth ground layer (11), the reference ground of the first digital control layer (3), the reference ground of the second digital control layer (4), the reference ground of the control power supply multiplexing layer (5), the reference ground of the internal network layer (10) and the reference ground of the external network layer (12) share a copper area, and the above lines all adopt a ground coplanar waveguide form.

4. The radar module of claim 3, wherein, The TR chips (13) are all four-channel TR chips, are arranged on the surface of the external network layer (12), are integrated with four independent channels inside a single TR chip (13), are connected with four antenna units in the antenna array respectively, are integrated with a power management, a temperature sensor and a wave control circuit module inside each channel, and support switching of a transceiving mode; The TR chips (13) are all four-channel TR chips, are arranged on the surface of the external network layer (12), are integrated with four independent channels inside a single TR chip (13), are connected with four antenna units in the antenna array respectively, are integrated with a power management, a temperature sensor and a wave control circuit module inside each channel, and support switching of a transceiving mode; The TR chip (13) adopts a daisy chain control architecture, realizes the control of amplitude modulation, phase modulation and switch switching through chip grouping, pin sharing and wire multiplexing, divides 4n TR chips (13) into n groups, each group has four, the TR chips (13) in the group are cascaded, and the n groups of TR chips (13) are connected in parallel with each other, the data input pin of one TR chip (13) in the same group is connected with the data output pin of another TR chip (13) to realize data initialization setting, the clock input pin of one TR chip (13) in the same group is connected with the clock output pin of another TR chip (13) to ensure the clock synchronization of the TR chips (13) in the group, the data input and data output of the TR chips (13) at both ends in each group are connected in parallel, the clock input and clock output of the TR chips (13) at both ends in each group are connected in parallel, and the TR chips (13) in the whole module are connected in parallel with the same control pin and are globally multiplexed. The wire of the daisy chain control architecture is printed on the first digital control layer (3), the second digital control layer (4) and the control power supply multiplexing layer (5).

5. The radar module of claim 3, wherein, The antenna radiation layer (1) is a single-layer wide-angle scanning microstrip patch antenna array, which comprises n groups of 4×4 matrix arranged microstrip patch units (101), and a II-shaped structure (102) is arranged between the polarization direction microstrip patch units (101) for expanding the polarization direction and the beam scanning range of the orthogonal polarization direction of the microstrip patch unit (101), each II-shaped structure (102) comprises a II-shaped patch (103), the opening direction of the II-shaped patch (103) is along the polarization direction of the microstrip patch unit (101), the microstrip patch unit (101) is located in the opening of the adjacent II-shaped patch (103), the adjacent II-shaped patches (103) are not connected with each other, and three or five grounding vias (104) are symmetrically arranged in the opening between the II-shaped patch (103) and the adjacent microstrip patch unit (101) along the orthogonal polarization direction, and the interval between the grounding via (104) along the polarization direction of the microstrip patch unit (101) and the II-shaped patch (103) is less than 1 / 4 of the distance between the adjacent microstrip patch units (101).

6. The radar module of claim 3, wherein, The first ground layer (2) is etched with a rectangular ring groove (201) in the middle of the adjacent microstrip patch units (101) along the polarization direction and the orthogonal polarization direction, and all the rectangular ring grooves (201) are not communicated with each other.

7. The radar module of claim 3, wherein, The internal network layer (10) and the external network layer (12) jointly constitute a 4n-stage equal power distribution feed network, which adopts The stage cascade network architecture is connected with the signal input port of the TR chip (13), if n is even, each stage cascade network adopts a 1:1 equal power distribution feed network, otherwise, the first stage cascade network adopts a 1:2 unequal power distribution feed network, and the rest of the stage cascade networks all adopt a 1:1 equal power distribution feed network. The 1 / 4n equal power distribution feed network is disassembled into parts and is scattered on the external network layer (12), each part being less than an 8-way equal power distribution feed network, and each part equal power distribution feed network is connected to the trunk printed on the internal network layer (10), and each part equal power distribution feed network on the external network layer (12) is connected to the trunk of the internal network layer (10) through a feed network coaxial via, and the 1 / 4n equal power distribution feed network is peripherally provided with a shielding hole for shielding electromagnetic interference, and the antenna transmission line (1202) of the external network layer (12) is connected to the input / output pin of the TR chip (13) for antenna impedance matching and radio frequency signal transmission.

8. The radar module of claim 3, wherein, The circuit element (14) comprises not less than 8n capacitors (1403), 4n-1 resistors (1402), 1 radio frequency signal connector (1404) and 1 digital pin (1401). The digital pin (1401) includes a positive voltage pin, a negative voltage pin, and a communication control pin. The negative voltage pin is connected to the negative voltage supply pin of the TR chip (13) through the negative voltage supply line of the power supply multiplexing layer (5), and is used to provide the negative voltage required by the TR chip (13). The communication control pin is connected to the control pin of the TR chip (13) through the first digital control layer (3) and the second digital control layer (4), and is used to transmit communication and control signals. The positive voltage pin is connected to one end of the capacitor (1403), and the positive voltage pin can withstand a current of not more than 2.5A. The other end of the capacitor (1403) is connected to the positive voltage supply pin of the TR chip (13) through the positive voltage supply line of the first power supply layer (7) and the second power supply layer (8). The capacitor (1403) is used to store energy to ensure the continuous and stable delivery of high-power voltage of the TR chip (13). The capacitor (1403) is in the form of a patch, and each TR chip (13) is connected to at least one capacitor. All capacitors have at least two capacitance values, and the maximum capacitance value is 1-3 times the minimum capacitance value. The size of the capacitor corresponds to the size of the capacitance value, and the capacitor is distributed and placed on the external network layer (12) near the non-wiring device area of the TR chip (13). The resistor (1402) is arranged between two adjacent power distribution networks on the external network layer (12), and is used to improve the isolation between output ports. The radio frequency signal connector (1404) is connected to the first-order power distribution network through the coaxial via of the feed network, and is used to introduce external input radio frequency signals.

9. The radar module of claim 8, wherein, The power supply layer is connected to the plurality of positive voltage pins of the digital pin (1401), and provides high-power power supply through the multi-pin confluence mode. The first power supply layer (7) and the second power supply layer (8) are used to realize the current backflow of high-power, so as to meet the high-power power supply and heat dissipation requirements of the 4n TR chips (13).

10. The radar module of claim 1, wherein, Each edge of the module is provided with at least one medium screw hole (15).

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