A synchronization method and system for servo communication and motor control of an ethercat bus

Abstract

The application discloses a synchronization method for servo communication and motor control of an EtherCAT bus, which comprises the following steps: a mapping relationship between a control period of an auxiliary timer and a PWM signal generator is established, and a physical synchronization signal Sync0 of the EtherCAT bus is mapped as an external trigger source of an input capture unit; when a valid jump edge of the physical synchronization signal Sync0 is detected, the current instantaneous count value of the auxiliary timer is locked into a capture register by the input capture unit without intervention of a software interrupt, so as to form a reference time stamp; the reference time stamp is read in an interrupt service of a servo control period, a phase offset is calculated based on a target phase relationship between the reference time stamp and the physical synchronization signal Sync0, and the reloading value of the PWM signal generator in the next control period is dynamically modulated according to the phase offset.

Description

Technical Field

[0001] This invention relates to the field of automation control technology, and in particular to a method and system for synchronizing servo communication and motor control via EtherCAT bus. Background Technology

[0002] EtherCAT (Ethernet for Control Automation Technology) is a high-performance, real-time industrial Ethernet bus protocol widely used in CNC machine tools, robots, and automated production lines where multi-axis synchronization requirements are extremely high. To ensure the consistency of action of each slave station (such as servo drives) in the network, the EtherCAT protocol employs Distributed Clocks (DC) technology. Through hardware mechanisms, it precisely compensates for network transmission delays, ensuring that the local clocks of all slave stations are highly synchronized with the master station's reference clock.

[0003] In EtherCAT bus-based servo systems, servo drivers need to control motor operation based on periodic control commands (such as position, speed, or torque commands) sent by the master station. To ensure the synchronization of multi-axis movements, each servo slave station typically uses the synchronization signals (Sync0 / Sync1) provided by the EtherCAT bus as a reference to trigger the execution of its local motor control algorithm.

[0004] However, in practical applications, the local control cycle of the servo drive (usually generated by a PWM timer) and the synchronization cycle of the EtherCAT bus are driven by two independent clock sources (crystal oscillators). Due to limitations in hardware manufacturing processes, there will inevitably be a slight frequency deviation between different crystal oscillators (e.g., 29.999MHz and 30.001MHz). Over time, this slight frequency deviation accumulates into a significant phase shift, causing a discrepancy between the number of commands sent by the host computer and the actual number of times the servo drive's motor control algorithm executes over a period of time. If this asynchrony is not corrected, it can lead to data packet loss or repeated readings, resulting in pulsations in motor torque and speed, abnormal noises, and even equipment vibration.

[0005] The existing technical solutions have the following significant drawbacks:

[0006] The SYNC0 signal is used as an external interrupt. Within the interrupt service routine, the PWM timer counter is cleared or a specific value is written for synchronization. Software interrupt response exhibits jitter: the CPU needs time to respond to an interrupt request and enter the interrupt service routine (including saving the context, pipeline refresh, etc.), and this response time is not fixed. When a high-priority interrupt exists in the system or when it is in a critical code segment, the interrupt entry time will be delayed. This microsecond (µs) level software interrupt response jitter is often larger than the nanosecond (ns) level clock oscillator offset, severely impacting the synchronization performance of high-precision servo systems.

[0007] Lack of flexibility in phase adjustment: Traditional hard synchronization methods typically aim for the Sync0 signal to perfectly coincide with the start of the PWM cycle. However, in practical engineering, to allow sufficient time for EtherCAT data packet transmission and parsing, the execution time of the motor control algorithm often needs to maintain a specific fixed phase lag relative to the Sync0 signal (e.g., lag of 30µs). Simply relying on software interrupts to clear the phase lock makes it difficult to achieve this phase lock accurately and stably.

[0008] Therefore, there is an urgent need for a motor control synchronization method that can eliminate software interruption processing delay, eliminate clock cumulative offset, and achieve high-precision phase locking. Summary of the Invention

[0009] In view of the shortcomings of the prior art, this application proposes a synchronization method and system for servo communication and motor control via EtherCAT bus to solve the above-mentioned technical problems.

[0010] According to a first aspect of the present invention, a method for synchronizing servo communication and motor control via EtherCAT bus is proposed, comprising:

[0011] S1. Establish the mapping relationship between the auxiliary timer and the control cycle of the PWM signal generator, and map the physical synchronization signal Sync0 of the EtherCAT bus as the external trigger source of the input capture unit;

[0012] S2. In response to the detection of a valid rising edge of the physical synchronization signal Sync0, the current instantaneous count value of the auxiliary timer is immediately locked into the capture register by the input capture unit without software interruption, forming a reference timestamp.

[0013] S3. In the interrupt service of the servo control cycle, read the reference timestamp, calculate the phase offset based on the target phase relationship between the reference timestamp and the physical synchronization signal Sync0, and dynamically modulate the reload value of the PWM signal generator in the next control cycle according to the phase offset. The synchronization method of this application eliminates the software jitter caused by the uncertain time delay of CPU response interrupt (entering ISR) in the prior art, and can obtain the accurate local count value of the arrival time of the Sync0 signal, thereby accurately quantifying the phase offset between the bus clock and the local clock, laying the foundation for high-precision synchronization control.

[0014] In a specific embodiment, establishing the mapping relationship in step S1 specifically includes configuring the counting period of the auxiliary timer to maintain the same frequency or an integer multiple of the control period of the PWM signal generator. This setting simplifies the calculation logic of the phase offset and eliminates the quantization error caused by cross-clock domain conversion.

[0015] In a specific embodiment, in step S2, the effective transition edge of the physical synchronization signal Sync0 is configured as either a rising edge or a falling edge.

[0016] In a specific embodiment, in step S3, when the target phase relationship is zero phase deviation, the phase offset is calculated using the following formula: ,in, This is the phase offset. To capture the reference timestamp locked in the register, This is to assist the timer in calculating the theoretical count value corresponding to the arrival of the Sync0 signal under ideal synchronization conditions. In applications where phase offset is not required, the offset can be quickly calculated, reducing the CPU's computational load and improving the real-time performance of control.

[0017] In a specific embodiment, when the target phase relationship includes a preset target phase offset value, the phase offset is calculated using the following formula: ,in, This is the count increment corresponding to the target phase offset value. This setting implements "peak-shifting synchronization" or "specific phase locking," allowing the PWM control cycle to maintain a fixed time lag relative to the Sync0 signal. This ensures that the process data transmitted via the EtherCAT bus has been fully received and parsed before the motor control algorithm begins execution, avoiding data read / write conflicts and guaranteeing the real-time performance and effectiveness of control commands.

[0018] In a specific embodiment, in step S3, dynamic modulation specifically includes: presetting a maximum adjustment step size threshold, comparing the absolute value of the calculated phase offset with the size of the maximum adjustment step size threshold; if the absolute value of the phase offset is less than or equal to the maximum adjustment step size threshold, then the phase offset is directly used as a correction amount; if the absolute value of the phase offset is greater than the maximum adjustment step size threshold, then the maximum adjustment step size threshold is assigned a sign direction to the phase offset and used as a correction amount; the correction amount is superimposed on the automatic reload register of the PWM signal generator to change the duration of the next PWM cycle, and through multiple iterative adjustments of cycles, the phase offset gradually approaches zero.

[0019] According to a second aspect of the present invention, a synchronization system for servo communication and motor control via EtherCAT bus is provided, comprising:

[0020] The mapping unit is configured to establish a mapping relationship between the control cycle of the auxiliary timer and the PWM signal generator, and to map the physical synchronization signal Sync0 of the EtherCAT bus as an external trigger source for the input capture unit;

[0021] The capture unit is configured to, in response to the detection of a valid rising edge of the physical synchronization signal Sync0, immediately lock the current instantaneous count value of the auxiliary timer into the capture register to form a reference timestamp using the input capture unit without software interrupt intervention;

[0022] The synchronization control unit is configured to read the reference timestamp during the interrupt service of the servo control cycle, calculate the phase offset based on the target phase relationship between the reference timestamp and the physical synchronization signal Sync0, and dynamically modulate the reload value of the PWM signal generator in the next control cycle according to the phase offset.

[0023] In a specific embodiment, the auxiliary timer and the PWM signal generator share the same clock signal provided by the local clock source module in hardware. This setting ensures that the offset measured by the auxiliary timer is exactly equal to the difference between the EtherCAT bus clock and the PWM local clock, avoiding additional measurement noise introduced by the asynchrony of the dual crystal oscillators due to temperature drift.

[0024] In a specific embodiment, the target phase relationship includes zero phase deviation and a preset target phase offset value.

[0025] In a specific embodiment, the synchronization control unit uses the calculated phase offset as an error input, presets a maximum adjustment step size threshold, and compares the absolute value of the calculated phase offset with the maximum adjustment step size threshold: if the absolute value of the phase offset is less than or equal to the maximum adjustment step size threshold, the phase offset is directly used as a correction amount; if the absolute value of the phase offset is greater than the maximum adjustment step size threshold, the maximum adjustment step size threshold is assigned a sign direction to the phase offset and used as a correction amount; the correction amount is superimposed on the automatic reload register of the PWM signal generator to change the duration of the next PWM cycle, and through multiple iterative adjustments, the phase offset gradually approaches zero.

[0026] Compared with the prior art, the beneficial effects of this application are as follows:

[0027] This invention utilizes the hardware input capture function of a timer to directly latch the timing of the Sync0 signal, replacing the traditional method of clearing the counter via external interrupt software. This improvement completely eliminates microsecond-level random jitter caused by CPU interrupt responses, making the measurement accuracy of phase offset limited only by the clock crystal frequency (typically reaching the nanosecond level), significantly improving the synchronization performance of multi-axis motion control;

[0028] This invention not only achieves traditional zero-phase alignment, but also enables fixed phase lag locking of the PWM cycle relative to the bus signal by pre-setting a target phase offset value. This mechanism ensures that the EtherCAT data packet has been transmitted and parsed before the motor control algorithm is executed, effectively solving the data race problem and guaranteeing the determinism of instruction execution.

[0029] This invention employs a modulation strategy that combines maximum step size limiting with iterative approximation. This strategy effectively solves the problem of sudden changes in the PWM cycle that may be caused by traditional direct synchronization or PID regulation, ensuring that motor speed calculation and current control remain stable and without jumps during the clock offset elimination process, thus achieving a balance between high dynamic response and high operational stability. Attached Figure Description

[0030] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and, together with the description, serve to explain the principles of the invention. Other embodiments and many anticipated advantages of the embodiments will be readily recognized as they become better understood through reference to the following detailed description. Other features, objects, and advantages of this application will become more apparent from reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0031] Figure 1 This is a schematic diagram illustrating data reception anomalies caused by clock skew in existing technologies;

[0032] Figure 2 This is a flowchart of a synchronization method for servo communication and motor control on an EtherCAT bus according to an embodiment of this application.

[0033] Figure 3 This is a schematic diagram illustrating the effect of a synchronization method for servo communication and motor control via EtherCAT bus according to an embodiment of this application.

[0034] Figure 4 This is a schematic diagram illustrating the phase synchronization of communication command parsing and motor control algorithm according to an embodiment of this application;

[0035] Figure 5 This is a schematic diagram of the framework of a synchronous system for servo communication and motor control of an EtherCAT bus according to an embodiment of this application. Detailed Implementation

[0036] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0037] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0038] Figure 1 This is a diagram illustrating data reception anomalies caused by clock skew in existing technologies, such as... Figure 1As shown, the horizontal axis represents the time axis. The orange vertical line (top) represents the "EtherCAT communication command," indicating the moment when the host computer (master station) sends control commands according to its reference clock. The blue vertical line (bottom) represents the "motor control software execution cycle," indicating the moment when the servo driver (slave station) executes the motor control algorithm according to its local crystal oscillator clock. The diagram shows that the intervals of the orange vertical lines (communication commands) and the blue vertical lines (local control) are not perfectly aligned, indicating a slight frequency deviation between the master station clock and the slave station's local clock (frequency difference caused by different crystal oscillator sources). As time progresses (from left to right), the relative position (phase difference) between the orange and blue lines changes continuously, representing the accumulation of phase shift caused by the frequency deviation. Due to clock asynchrony, when the phase shift accumulates to a certain extent, "beat frequency" or "aliasing" phenomena will occur. As shown on the right side of the diagram, two orange vertical lines are inserted between the two blue vertical lines (i.e., one complete motor control cycle), indicating that two EtherCAT commands have been received. When a servo drive receives two commands within a control cycle, the first command is often overwritten by the second command before it can be executed (packet loss), or the execution of control commands may be uneven (jitter), resulting in torque fluctuations, noise, or vibration during motor operation.

[0039] Figure 2 This is a flowchart illustrating a synchronization method for servo communication and motor control via EtherCAT bus according to an embodiment of this application. Figure 2 As shown, the method includes:

[0040] S1. Establish the mapping relationship between the auxiliary timer and the control cycle of the PWM signal generator, and map the physical synchronization signal Sync0 of the EtherCAT bus as the external trigger source of the input capture unit.

[0041] In a specific embodiment, establishing the mapping relationship includes configuring the counting period of the auxiliary timer to maintain the same frequency or an integer multiple of the control period of the PWM signal generator. This allows the time difference measured by the auxiliary timer to be directly mapped to the counting value of the PWM signal generator, and also supports multi-frequency application scenarios where the current loop control frequency is higher than the communication frequency.

[0042] S2. In response to detecting a valid rising edge of the physical synchronization signal Sync0, the input capture unit immediately locks the current instantaneous count value of the auxiliary timer into the capture register without software interruption, forming a reference timestamp. The valid rising edge includes either a rising edge or a falling edge.

[0043] S3. In the interrupt service of the servo control cycle, read the reference timestamp, calculate the phase offset based on the target phase relationship between the reference timestamp and the physical synchronization signal Sync0, and dynamically modulate the reload value of the PWM signal generator in the next control cycle according to the phase offset.

[0044] In a specific embodiment, the target phase relationship includes zero phase deviation and a preset target phase offset value. When the target phase relationship is zero phase deviation, the phase offset is calculated using the following formula: ,in, This is the phase offset. To capture the reference timestamp locked in the register, This is the theoretical count value of the auxiliary timer corresponding to the arrival time of the Sync0 signal under ideal synchronization conditions. When the target phase relationship includes a preset target phase offset value, the phase offset is calculated using the following formula: ,in, This is the count increment corresponding to the target phase offset value.

[0045] In a specific embodiment, dynamic modulation includes: presetting a maximum adjustment step size threshold; comparing the absolute value of the calculated phase offset with the maximum adjustment step size threshold; if the absolute value of the phase offset is less than or equal to the maximum adjustment step size threshold, the phase offset is directly used as a correction value; if the absolute value of the phase offset is greater than the maximum adjustment step size threshold, the maximum adjustment step size threshold is assigned a sign direction to the phase offset and used as a correction value; the correction value is superimposed on the automatic reload register of the PWM signal generator to change the duration of the next PWM cycle, and the phase offset gradually approaches zero through iterative adjustment over multiple cycles. Since the core control algorithm of the servo drive (such as speed calculation in FOC: Speed ​​= encoder position increment / encoder position reading time interval) highly depends on the PWM cycle as a fixed time base, if the PWM cycle is significantly adjusted (e.g., a single adjustment exceeding 2%) in pursuit of fast synchronization, it will directly lead to parameter distortion in the control algorithm, resulting in false jumps in the calculated speed and position, causing current loop oscillation. In a specific example, the system sets a maximum adjustment step size threshold (e.g., 2µs, i.e., 2% of the cycle). The system determines the current phase offset in each cycle: if the offset is small (e.g., 1.5µs) and does not exceed the threshold, it means that direct compensation will not affect control stability, so it directly adjusts by 1.5µs to achieve synchronization in one step; if the offset is large (e.g., 10µs), to ensure the continuity and stability of the control cycle, it only adjusts by 2µs in this cycle. The remaining 8µs deviation will be gradually eliminated over the next four cycles through continuous adjustments of 2µs each time. This method achieves clock synchronization while maximally smoothing the changes in the control cycle, ensuring the smooth operation of the motor.

[0046] This invention strictly limits the amount of adjustment in a single operation by setting a maximum adjustment step size threshold. For minor phase shifts, direct compensation is used to maintain high-precision synchronization; for large shifts caused by initial power-on or other factors, the shifts are divided into multiple cycles of minor adjustments for iterative compensation. This mechanism ensures eventual clock synchronization while maximizing the "rigidity" and stability of the motor control cycle, effectively avoiding motor torque fluctuations and mechanical noise caused by the synchronization adjustment action itself.

[0047] Figure 3 This is a schematic diagram illustrating the effect of a synchronization method for servo communication and motor control via EtherCAT bus according to an embodiment of this application. Figure 3As shown in the figure, this diagram intuitively illustrates the core timing logic of this invention for achieving high-precision clock synchronization based on hardware input capture. The figure shows, from top to bottom along the same time axis, the auxiliary timer counting waveform used as the measurement reference, the PWM timer counter counting waveform used to generate control signals, and the actual PWM output signal. Its working principle is that when the SYNC0 physical synchronization signal from the EtherCAT bus arrives, it directly triggers the hardware input capture unit, instantly latching the current instantaneous count value of the auxiliary timer (i.e., the "capture timer value" indicated in the figure) without software interruption intervention. This mechanism allows the system to accurately record the local timestamp of the arrival time of the SYNC0 signal. By comparing this captured value with the running state of the PWM timer, the phase offset between the bus clock and the local clock can be accurately calculated, thus providing a jitter-free measurement basis for subsequent dynamic adjustment of the PWM cycle reload value and achieving precise phase locking between the motor control cycle and the bus communication cycle.

[0048] Figure 4 A schematic diagram illustrating the phase synchronization of communication command parsing and motor control algorithm according to an embodiment of this application is shown, such as... Figure 4 As shown, through a phase control mechanism, the execution window of the motor control algorithm (blue box) maintains a defined and fixed phase lag relative to the arrival window of the EtherCAT communication command (green box). This ensures that the start-up time of the motor control algorithm immediately follows the transmission and parsing of the latest communication command, thus establishing a strict one-to-one correspondence between the two on the timeline. This effectively prevents data read / write contention caused by clock offset or phase overlap, guaranteeing that control commands are executed in real time, accurately, and without omission.

[0049] Figure 5 This is a schematic diagram of the framework of a synchronous system for servo communication and motor control using an EtherCAT bus, according to an embodiment of this application. Figure 5As shown, the synchronization system includes a mapping unit 301, a capture unit 302, and a synchronization control unit 303. The mapping unit 301 is configured to establish a mapping relationship between the control cycle of the auxiliary timer and the PWM signal generator, and to map the physical synchronization signal Sync0 of the EtherCAT bus as an external trigger source for the input capture unit. The capture unit 302 is configured to, in response to the detection of a valid transition edge of the physical synchronization signal Sync0, immediately lock the current instantaneous count value of the auxiliary timer into the capture register using the input capture unit without software interrupt intervention, forming a reference timestamp. The synchronization control unit 303 is configured to read the reference timestamp during the interrupt service of the servo control cycle, calculate the phase offset based on the target phase relationship between the reference timestamp and the physical synchronization signal Sync0, and dynamically modulate the reload value of the PWM signal generator in the next control cycle according to the phase offset.

[0050] In a specific embodiment, the auxiliary timer and the PWM signal generator share the same clock signal provided by the local clock source module in hardware. This setting eliminates the relative clock error between the measuring tool and the controlled object. It ensures that the offset measured by the auxiliary timer is completely equivalent to the difference between the EtherCAT bus clock and the PWM local clock, avoiding additional measurement noise introduced by the asynchrony of the dual crystal oscillators' temperature drift.

[0051] In a specific embodiment, the target phase relationship includes zero phase deviation and a preset target phase offset value. This setting enhances the versatility of the system, enabling it to meet both scenarios requiring absolute time alignment and scenarios requiring data processing timing security.

[0052] In a specific embodiment, the synchronization control unit calculates the correction amount for a single PWM cycle by introducing a maximum adjustment step size, and adds the correction amount to the automatic reload register of the PWM signal generator to change the duration of the next PWM cycle. This setting achieves precise adjustment of the PWM cycle at the microsecond or even nanosecond level. By changing the PWM timer count period value, the duration of the current PWM cycle is physically lengthened or shortened, thereby achieving physical compensation for phase shift in the next cycle, forming a complete closed-loop control.

[0053] This application can strictly establish the time anchor point between the execution time of the motor control software and the reception time of the new EtherCAT bus command, ensuring that the latest control command of each frame can be executed immediately according to the preset timing after being received. This effectively avoids data overwriting caused by receiving two commands in a single control cycle due to clock offset, fundamentally guaranteeing the consistency and determinism between the host computer control command and the actual execution of the motor algorithm, eliminating motor torque pulsation and speed fluctuation caused by disordered command execution timing, and significantly improving the dynamic response accuracy and operational stability of the servo system.

[0054] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for synchronizing servo communication and motor control via EtherCAT bus, characterized in that, The synchronization method includes: S1. Establish the mapping relationship between the auxiliary timer and the control cycle of the PWM signal generator, and map the physical synchronization signal Sync0 of the EtherCAT bus as the external trigger source of the input capture unit; S2. In response to the detection of a valid transition edge of the physical synchronization signal Sync0, the input capture unit immediately locks the current instantaneous count value of the auxiliary timer into the capture register without software interruption, forming a reference timestamp, so as to completely eliminate the microsecond-level random jitter caused by the CPU response interrupt, and make the measurement accuracy of the phase offset limited only to the nanosecond-level clock crystal frequency. S3. In the interrupt service of the servo control cycle, read the reference timestamp, calculate the phase offset based on the target phase relationship between the reference timestamp and the physical synchronization signal Sync0, and dynamically modulate the reload value of the PWM signal generator in the next control cycle according to the phase offset. The dynamic modulation specifically includes: presetting a maximum adjustment step size threshold; comparing the absolute value of the calculated phase offset with the maximum adjustment step size threshold; if the absolute value of the phase offset is less than or equal to the maximum adjustment step size threshold, the phase offset is directly used as a correction amount; if the absolute value of the phase offset is greater than the maximum adjustment step size threshold, the maximum adjustment step size threshold is assigned a sign direction to the phase offset and used as a correction amount; the correction amount is superimposed on the automatic reload register of the PWM signal generator to change the duration of the next PWM cycle. By changing the PWM timer count period value, the duration of the current PWM cycle is physically lengthened or shortened, thereby achieving physical compensation for the phase offset in the next cycle. Through iterative adjustment of multiple cycles, the phase offset gradually approaches zero.

2. The synchronization method for servo communication and motor control via EtherCAT bus according to claim 1, characterized in that, In step S1, establishing the mapping relationship specifically includes configuring the counting period of the auxiliary timer to maintain the same frequency or an integer multiple of the control period of the PWM signal generator.

3. The synchronization method for servo communication and motor control via EtherCAT bus according to claim 1, characterized in that, In step S2, the effective transition edge of the physical synchronization signal Sync0 is configured as either a rising edge or a falling edge.

4. The synchronization method for servo communication and motor control via EtherCAT bus according to claim 1, characterized in that, In step S3, when the target phase relationship is zero phase deviation, the phase offset is calculated using the following formula: ,in, This is the phase offset. The reference timestamp locked in the capture register. This is the theoretical count value of the auxiliary timer corresponding to the arrival time of the Sync0 signal under ideal synchronization conditions.

5. The synchronization method for servo communication and motor control of EtherCAT bus according to claim 4, characterized in that, When the target phase relationship includes a preset target phase offset value, the phase offset is calculated using the following formula: ,in, This is the count increment corresponding to the target phase offset value.

6. A synchronous system for servo communication and motor control via EtherCAT bus, characterized in that, include: The mapping unit is configured to establish a mapping relationship between the control cycle of the auxiliary timer and the PWM signal generator, and to map the physical synchronization signal Sync0 of the EtherCAT bus as an external trigger source for the input capture unit; The capture unit is configured to, in response to the detection of a valid transition edge of the physical synchronization signal Sync0, immediately lock the current instantaneous count value of the auxiliary timer into the capture register without software interruption intervention, thereby forming a reference timestamp. This completely eliminates microsecond-level random jitter caused by CPU response interrupts, so that the measurement accuracy of the phase offset is limited only to the nanosecond-level clock crystal frequency. A synchronization control unit is configured to read the reference timestamp during an interrupt service of the servo control cycle, calculate the phase offset based on the target phase relationship between the reference timestamp and the physical synchronization signal Sync0, and dynamically modulate the reload value of the PWM signal generator in the next control cycle according to the phase offset. The synchronization control unit uses the calculated phase offset as an error input, presets a maximum adjustment step size threshold, and compares the absolute value of the calculated phase offset with the maximum adjustment step size threshold: if the absolute value of the phase offset is less than or equal to the maximum adjustment step size threshold, then the phase offset is directly used as a correction amount. If the absolute value of the phase offset is greater than the maximum adjustment step size threshold, the maximum adjustment step size threshold is assigned a sign direction to the phase offset and used as a correction amount. The correction amount is superimposed on the automatic reload register of the PWM signal generator to change the duration of the next PWM cycle. By changing the PWM timer count period value, the duration of the current PWM cycle is physically lengthened or shortened, thereby achieving physical compensation for the phase offset in the next cycle. Through iterative adjustment of multiple cycles, the phase offset gradually approaches zero.

7. The synchronous system for servo communication and motor control of EtherCAT bus according to claim 6, characterized in that, The auxiliary timer and the PWM signal generator share the same clock signal provided by the local clock source module in hardware.

8. The synchronous system for servo communication and motor control of EtherCAT bus according to claim 6, characterized in that, The target phase relationship includes zero phase deviation and a preset target phase offset value.

Images