Fine-grained cache partitioning lock method based on risc-v extension instruction and processor

Abstract

The application is suitable for the field of microprocessor architecture, on-chip multi-core system and embedded real-time computing technology, and provides a fine-grained cache partition lock method based on RISC-V extension instruction and a processor, the method comprising: adding a Zicpl extension instruction family in the RISC-V instruction set architecture, the Zicpl extension instruction family comprising a LOCK.CP instruction, an UNLOCK.CP instruction, a TESTLOCK.CP instruction and a SET.CP instruction; adding a partition lock table on the cache controller side of the processor, the partition lock table comprising a plurality of entries, each entry comprising an owner field, a timeout field and a valid field; adding a lock flag and a partition identification field in the Tag area of the cache memory; the application can significantly improve the real-time performance and system energy efficiency, and has significant industrial and economic value.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of microprocessor architecture, on-chip multi-core system and embedded real-time computing, in particular to a fine-grained cache partition lock method based on RISC-V extended instruction and a processor. BACKGROUND

[0002] In current computer systems, cache as a key component between processor and memory, its performance directly affects the running efficiency of the whole system. However, there are many problems when multi-core processors share cache, and the existing technology has obvious defects in cache partition locking:

[0003] Software spinlock / mutex (such as pthread-mutex, POSIX thread mutex, spinlock) is simple to implement and tightly coupled with the operating system, but it needs to access the cache line multiple times when locking, which is easy to cause bus storm, and it cannot perceive the hardware cache granularity;

[0004] PageColoring (page coloring), WayPartition (cache way partitioning), CAT (Class of Service, service class) and other technologies, through operating system or firmware coloring physical pages in page allocation stage, or using related technologies to set priority for cache ways, but there are problems of static allocation leading to utilization decline, and inability to preempt / release partitions on demand during task execution;

[0005] RISCV-A atomic instruction extension only provides consistency guarantee for memory word / double word granularity, and cannot directly use mutual exclusion for "cache partition" hardware resources;

[0006] Intel®ResourceDirectorTechnology (RDT, Resource Director Technology) only supports the allocation technology of the last level cache (LLC, Last Level Cache), and cannot realize the fine-grained lock control of L1 / L2 cache;

[0007] ARMv8.3 lock extension instruction (STILP, Store-ReleasewithImmediateLoadPair / LDAPR, Load-AcquirePC-Relative) only solves the problem of memory order consistency, and does not involve cache physical partition control.

[0008] The prior art has the pain points of lacking a 'hardware level' reentrant lock for cache partition or line, a pure software solution consuming CPU cycles for spinning or polling, a real-time system failing to meet the worst-case execution time requirement of related functions / security specifications in a high-load or jitter scenario, and a coarse isolation granularity of existing hardware-assisted solutions failing to adapt to dynamic task loads. Therefore, in view of the above status quo, there is an urgent need to provide a fine-grained cache partition lock method and processor based on RISC-V extension instructions to overcome the deficiencies in current practical applications. SUMMARY

[0009] The present application provides a fine-grained cache partition lock method and processor based on RISC-V extension instructions, effectively solving the problems in the background art.

[0010] The present application is implemented as follows: a fine-grained cache partition lock method based on RISC-V extension instructions, the method comprising the following steps:

[0011] A Zicpl extension instruction family is added in the RISC-V instruction set architecture, the Zicpl extension instruction family including a LOCK.CP instruction, an UNLOCK.CP instruction, a TESTLOCK.CP instruction, and a SET.CP instruction;

[0012] A partition lock table (PLT) is added on the cache controller side of the processor, the partition lock table containing a plurality of entries, each entry including an owner field, a timeout field, and a valid field;

[0013] A lock flag (L) and a partition identification field (part_id) are added in the Tag region of the cache memory;

[0014] When the LOCK.CP instruction is executed, the processor accesses the partition lock table, if the valid field of the target partition is 0, the owner field of the partition is set to the current hardware thread ID and the valid field is set to 1, and the lock flag of all existing Tags of the partition is updated to 1; if the valid field of the target partition is 1 and the owner field is consistent with the current hardware thread ID, success is returned; if the valid field of the target partition is 1 and the owner field is inconsistent with the current hardware thread ID, failure is returned.

[0015] As a further scheme of the present application: a timeout mechanism is further included, when the timeout field reaches a predetermined threshold, the lock on the corresponding partition is automatically released, and a CPLOCK_TIMEOUT exception is triggered and submitted to the processor exception controller.

[0016] As a further scheme of the present application: the SET.CP instruction is used to dynamically modify the mapping relationship of cache lines to partitions to support live migration.

[0017] As a further scheme of the present application: further comprising a configuration register (CPCFG) added in the privilege architecture;

[0018] The configuration register is used for setting a partition granularity;

[0019] The partition granularity comprises a cache-line level, a cache-set level and a cache-way level.

[0020] As a further scheme of the present application: further comprising a special register and a control and status register (CSR) added, the special register and the control and status register comprising:

[0021] A cache partition identifier (CPID) register, which is implemented by a 5-bit hardware, is used for saving a current operation target partition number, and supports 32 independent partitions;

[0022] A cache partition lock (CPLK) register, which has a bit width equal to a maximum partition number, each bit corresponding to a lock state of a cache partition identifier;

[0023] A global partition lock state register (CPLK_STATCSR), which is a read-only register, is used for indicating a global partition lock state.

[0024] As a further scheme of the present application: the partition lock table adopts a dual-port block random memory (BRAM), a write end of the dual-port block random memory coming from a CPU, and a read end interacting with a cache state machine.

[0025] As a further scheme of the present application: the owner field is used for identifying a hardware thread ID holding a lock, the timeout field is a counter used for timeout counting, and the valid field is used for indicating whether the entry is valid.

[0026] As a further scheme of the present application: further comprising an exception processing step, when a mstatus.WFI timer expires or a hart_reset event occurs, the partition lock table automatically empties a corresponding row; a suspended lock is manually cleaned up through an mcmisc CSR, for use by a debugger; a timeout automatic release lock is realized through the timeout field, to prevent a deadlock.

[0027] As a further scheme of the present application: the UNLOCK.CP instruction is used for unlocking operation on a specified partition;

[0028] The TESTLOCK.CP instruction is used for querying a lock state of a specified partition.

[0029] A processor comprising an instruction decoder, a partition lock table (PLT) and a cache memory, wherein:

[0030] The instruction decoder is configured to identify and execute the fine-grained cache partition lock method based on the RISC-V extension instruction as described above;

[0031] The partition lock table comprises a plurality of entries, each entry comprising an owner field, a timeout field and a valid field, wherein the owner field is used to identify the hardware thread ID holding the lock, the timeout field is a counter for timeout counting, and the valid field is used to indicate whether the entry is valid;

[0032] The Tag region of the cache memory comprises a lock flag (L) and a partition identification field (part_id).

[0033] Compared with the prior art, the present application has the following advantages:

[0034] 1. Average delay: 2-3 cycles for one lock operation, reduced by 72% compared with Linux spinlock (spin lock) (based on Xilinx Versal ACAP (Adaptive Compute Acceleration Platform) VC1902 prototype board, 100MHz clock test).

[0035] 2. Energy consumption: SPEC-cpu2006 (standard performance evaluation suite) *4 parallel compilation, SoC power consumption decreased by 9.4% (Synopsys PrimePower@TSMC28nm HPC process simulation).

[0036] 3. Real-time performance: the peak jitter of the automotive ECU (Electronic Control Unit) control-loop (control loop) is reduced from 18µs to 6µs (AUTOSAR OS v4.3 task scheduling tracker measured).

[0037] 4. Code invasiveness: no need to modify the existing kernel scheduler, only need to call the relevant instructions in the user layer or hypervisor (virtual machine manager).

[0038] The present application can significantly improve the real-time performance and system energy efficiency, and has good compatibility with software and hardware and good feasibility for large-scale production, and has significant industrial and economic value. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the specific embodiments or prior art of the present application, the drawings required to be used in the description of the specific embodiments or prior art will be briefly introduced. Obviously, the drawings described below are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0040] Figure 1 The overall structure of the processor of the present application is shown in the schematic diagram.

[0041] Figure 2 The timing waveform of the LOCK.CP instruction of the present application is shown in the schematic diagram.

[0042] Figure 3 The mapping of the partition and Cache-way of the present application is shown in the schematic diagram.

[0043] Figure 4 The format of the PLT data structure of the present application is shown in the schematic diagram.

[0044] Figure 5 The state transition diagram of the PLT of the present application is shown in the schematic diagram. DETAILED DESCRIPTION

[0045] The technical solutions of the present application will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0046] The present application will be further explained and described below with reference to specific embodiments.

[0047] Please refer to Figures 1-5 The method for fine-grained cache partition locking based on RISC-V extension instruction provided by the embodiments of the present application, the method comprises the following steps:

[0048] A Zicpl extension instruction family is added in the RISC-V instruction set architecture, and the Zicpl extension instruction family comprises a LOCK.CP instruction, an UNLOCK.CP instruction, a TESTLOCK.CP instruction and a SET.CP instruction;

[0049] The SET.CP instruction is used to dynamically modify the mapping relationship of the cache line to the partition, so as to support hot migration;

[0050] The UNLOCK.CP instruction is used to perform an unlocking operation on the specified partition;

[0051] The TESTLOCK.CP instruction is used to query the lock state of a specified partition;

[0052] A partition lock table (PLT) is added on the cache controller side of the processor, which contains a plurality of entries, each of which includes an owner field, a timeout field and a valid field; the partition lock table uses a dual-port block random memory (BRAM), the write end of which comes from the CPU, and the read end interacts with the cache state machine; the owner field is used to identify the hardware thread ID holding the lock, the timeout field is a counter for timeout counting, and the valid field is used to indicate whether the entry is valid;

[0053] A lock flag (L) and a partition identification field (part_id) are added in the Tag area of the cache memory;

[0054] When the LOCK.CP instruction is executed, the processor accesses the partition lock table, if the valid field of the target partition is 0, the owner field of the partition is set to the current hardware thread ID and the valid field is 1, and the lock flag of all existing Tags of the partition is updated to 1; if the valid field of the target partition is 1 and the owner field is consistent with the current hardware thread ID, the success is returned; if the valid field of the target partition is 1 and the owner field is inconsistent with the current hardware thread ID, the failure is returned;

[0055] A timeout mechanism is also included, when the timeout field counts to a predetermined threshold, the lock of the corresponding partition is automatically released, and a CPLOCK_TIMEOUT exception is triggered and submitted to the processor exception controller;

[0056] A configuration register (CPCFG) is also added in the privileged architecture;

[0057] The configuration register is used to set the partition granularity;

[0058] The partition granularity includes cache-line level, cache-set level and cache-way level;

[0059] A dedicated register and control and status register (CSR) are also added, which includes:

[0060] A cache partition identifier (CPID) register, which is implemented by 5-bit hardware, is used to save the current operation target partition number, supporting 32 independent partitions;

[0061] a cache partition lock (CPLK) register, a bit width of the cache partition lock (CPLK) register is equal to a maximum number of partitions, and each bit corresponds to a lock state of a cache partition identifier;

[0062] a global partition lock state register (CPLK_STATCSR), the global partition lock state register is a read-only register, and is used to indicate a global partition lock state;

[0063] The application further comprises an exception processing step, when the mstatus.WFI timer expires or a hart_reset event occurs, the partition lock table is automatically emptied corresponding rows; manual cleaning of the pending lock is supported through the mcmiscCSR, which is used for a debugger; the timeout automatic release of the lock is realized through the timeout field, so as to prevent a deadlock.

[0064] In the embodiment, the application aims to solve the problems of real-time decline and energy consumption rise caused by cache contention of a multi-core processor, and provides a cache partition lock mechanism of "instruction level, hardware acceleration and granularity configurable", so as to achieve:

[0065] Partition locking or unlocking is completed with an overhead of minimum 1 instruction;

[0066] An application or a virtual machine is provided with a determined cache occupation without invading an operating system kernel;

[0067] The mechanism is compatible with a current RISC-V standard, and reserves the integrity of a vector, a floating point, compression and a privilege architecture;

[0068] Lock invalidation automatic recycling is supported, and a deadlock is avoided;

[0069] The application is realized through the following specific technical solutions:

[0070] 1. A special register and a CSR (Control and Status Register) are added

[0071] a CPID (Cache Partition Identifier) register: 5-bit hardware implementation, saving a current operation target partition number, supporting 32 independent partitions;

[0072] a CPLK (Cache Partition LoCK) register: bit width = maximum number of partitions, each bit corresponding to a CPID lock state;

[0073] a CPLK_STATCSR: read-only, global partition lock state;

[0074] CPCFGCSR: Configure partition granularity (0: cacheline; 1: cacheset; 2: cacheway).

[0075] 2. Define Zicpl instruction extension family

[0076] LOCK.CPrd,rs1: Lock the partition specified by rs1, rd returns 0 (success) / 1 (failure);

[0077] UNLOCK.CPrs1: Unlock;

[0078] TESTLOCK.CPrd,rs1: Query lock status;

[0079] SET.CPrd,rs1,rs2: Dynamically modify cacheline -> partition mapping, support hot migration.

[0080] Developers can explicitly enable it through.option arch,+zicpl.

[0081] Cache controller hardware modifications:

[0082] Add 1-bit L (lock) bit and 4-bit part_id (partition number) field in TagRAM;

[0083] Design PartitionLockTable (PLT), capacity = partition number x (owner_hartid + valid + timeout), where:

[0084] owner: 5 bits (support up to 32 hardware threads)

[0085] timeout: 4 bits (timeout threshold = 2^4 * base clock cycles)

[0086] valid: 1 bit

[0087] PLT uses dual-port BRAM (Block RAM) (synchronous), the write end comes from the CPU; the read end interacts with the cache state machine.

[0088] Micro-architecture flow (take LOCK.CP as an example):

[0089] a) ID (Instruction Decode) stage identifies Zicpl, initiates PLT port access;

[0090] b) If target partition valid == 0, write hartid & valid = 1; set L bit 1 for all existing tags of this partition;

[0091] c) If valid == 1 and owner == hartid, return success directly (reentrant);

[0092] d) If owner!= hartid, return failure, guide software to spin or sleep;

[0093] e) Timeout mechanism: automatically generate lock release signal when the timeout counter in PLT is full, and trigger CPLOCK_TIMEOUT exception.

[0094] Exception handling:

[0095] When the mstatus.WFI timer expires or the hart_reset event occurs, the PLT automatically clears the corresponding row.

[0096] Support mcmisc CSR to manually clean up the pending lock for use by the debugger.

[0097] Deadlock prevention: hardware watchdog realizes automatic release of lock through timeout field;

[0098] Through the above technical solutions, the following technical effects can be achieved:

[0099] 1. Average delay: 2-3 cycles for one locking operation, reduced by 72% compared with Linux spinlock (spin lock) (based on Xilinx Versal ACAP (Adaptive Compute Acceleration Platform) VC1902 prototype board, 100MHz clock test).

[0100] 2. Energy consumption: SPEC-cpu2006 (standard performance evaluation suite) *4 parallel compilation, SoC power consumption is reduced by 9.4% (Synopsys PrimePower@TSMC28nmHPC process simulation).

[0101] 3. Real-time performance: the peak value of automobile ECU (Electronic Control Unit) control-loop (control loop) jitter is reduced from 18µs to 6µs (AUTOSAR OS v4.3 task scheduling tracker measurement).

[0102] 4. Code invasiveness: no need to modify the existing kernel scheduler, only need to call relevant instructions in user layer or hypervisor (virtual machine manager).

[0103] wherein, Figure 1 The CPU-core, L1 / L2 Cache, PLT, Zicpl decoder are shown. The core cluster contains multiple RISC-V hardware threads (Harts) supporting Zicpl extension; the cache hierarchy is private L1 cache + shared L2 cache (integrating PLT module); the Zicpl path indicates the hardware path of the LOCK / UNLOCK instruction directly to the PLT through the red arrow; the PLT structure records the partition lock state (owner + timeout + valid).

[0104] Figure 2 The whole process of request, arbitration, Tag-L bit writing and response is shown. The key signals include that the PLT access is initiated in the ID stage, the Tag update completes the cache line locking in the EX stage, and the timeout mechanism starts the hardware watchdog in the WB stage.

[0105] Figure 3 The 8-way L2 allocates way0-1 to partition 0, way2-3 to partition 1, and the like. Among them, Set0 in the static partition is fixedly allocated to the way group (suitable for real-time tasks), Set1 in the dynamic partition is dynamically adjusted according to the SET.CP instruction (suitable for cloud environment), and the CPCFG register is configured with 00: cache-line granularity, 01: cache-set granularity, and 10: cache-way granularity.

[0106] Figure 4 It is the PLT data structure format, and the fields include owner (5b) + timeout (4b) + valid (1b). The owner is the Hart ID (0-31) holding the lock, the timeout is a 4-bit binary counter (0-15 cycles), and the valid is a lock state flag bit. When the timeout decreases from 15 to 0, the valid bit is automatically cleared, the owner is reset to 0, and the CPLOCK_TIMEOUT exception is submitted.

[0107] Figure 5 The timeout exception path is included, wherein Timeout→Exception indicates that the hardware automatically releases the lock and submits the exception; the safety mechanism indicates that the owner and valid bits are cleared after the exception is triggered.

[0108] Please refer to Figures 1-5 The embodiment of the application provides a processor, which comprises an instruction decoder, a partition lock table (PLT) and a cache memory.

[0109] The instruction decoder is used for identifying and executing the fine-grained cache partition lock method based on the RISC-V extension instruction as described above;

[0110] The partition lock table includes a plurality of entries, each entry including an owner field, a timeout field and a valid field, wherein the owner field is used to identify the hardware thread ID holding the lock, the timeout field is a counter for timeout counting, and the valid field is used to indicate whether the entry is valid;

[0111] The Tag region of the cache memory includes a lock flag (L) and a partition identification field (part_id).

[0112] In this embodiment, the overall architecture is designed as follows:

[0113] Target instruction set: RV64GC (64-bit RISC-V, including floating point, compression and other extensions) + Zicpl (the present application) + Sv39 virtual memory;

[0114] Processor core number: 1-128; all share the last level cache (LLC);

[0115] Cache configuration: L132KiBx2 (I / D); L21MiB, 8-way, can be divided into 16 partitions; L3 is optional.

[0116] The detailed encoding of the instruction set extension is shown in Table 1:

[0117] Table 1 Detailed encoding of instruction set extension

[0118] instruction opcode (6b) funct3 (3b) funct7 (7b) format description LOCK.CP 001011 000 0b0111011 I-type lock UNLOCK.CP 001011 001 0b0111011 I-type unlock TESTLOCK.CP 001011 010 0b0111011 I-type testlock SET.CP 0110011 000 0b0111011 R-type set

[0119] In Table 1, the instruction parser is independent of the standard ALU / CSR path, and the LSU request queue is multiplexed to avoid pipeline leakage.

[0120] The cache controller hardware implementation is as follows:

[0121] PLT implementation timing critical path optimization:

[0122] verilog

[0123] / / Three-stage pipeline design

[0124] always@(posedge clk)begin

[0125] if(zicpl_req_valid)begin

[0126] stage1<=PLT[target_id]; / / First beat: read PLT

[0127] stage2 <= check_owner(stage1); / / Second beat: ownership check

[0128] stage3 <= update_tag(stage2); / / Third beat: Tag update

[0129] end

[0130] end

[0131] Tag extension: original 54-bit Tag + L (1b) + part_id (4b); one-time layout in SRAM hard macro; power consumption increase <1%.

[0132] Arbitration logic: when Load / Store hit and Tag.L=1 and part_id is locked by other hart -> return NACK; LSU enters retry.

[0133] System software support as follows:

[0134] Boot phase: OpenSBI (RISC-V boot firmware) writes CPID according to hardware thread ID in sbi_hart_init().

[0135] Linux Kernel (≥6.6): Add ioctl (input / output control) RISCVCACHEP_{LOCK, UNLOCK, SET}; count Lock Miss (lock failure) events in perf_event_open

[0136] Security mechanism:

[0137] S (Supervisor Mode) mode adds scounteren CSR to control user state access permission;

[0138] Hypervisor assigns virtual partition ID to Guest through hcpcfg CSR.

[0139] Compiler support: GCC / LLVM backend adds -march=rv64gc_zicpl; embedded key code generates LOCK.CP / UNLOCK.CP automatically.

[0140] Function and performance tests as follows:

[0141] Lock-Microbench (lock microbenchmark): 8-core (8-core) mutual 1-partition, average lock time 9.2ns; software mutex (mutex) is 34.1ns.

[0142] mysql-oltp (online transaction processing): TPS (transactions per second) improved by 7%, and P99 (99th percentile) latency decreased by 16%.

[0143] 5G base station application: packet loss rate of latency-sensitive services (URLLC, Ultra Reliable Low Latency Communication) decreased by 82%.

[0144] Further improvements are as follows:

[0145] Change the PLT from centralized to distributed per-Bank (per-memory block) structure to improve scalability above 64 cores;

[0146] In combination with RISC-V PMP (Physical Memory Protection), realize integrated permission control of "security domain + cache lock";

[0147] For AI (artificial intelligence) inference scenarios, cooperate with Tensor (tensor) cache to perform row-level locking on activation graph, reducing DRAM (dynamic random access memory) access.

[0148] Compared with the prior art, the beneficial effects of the present application are:

[0149] 1. Average delay: one locking operation is completed in 2-3 cycles, which is reduced by 72% compared with Linux spinlock (spin lock) (based on Xilinx Versal ACAP (Adaptive Compute Acceleration Platform) VC1902 prototype board, 100MHz clock test) (for specific data, please refer to Table 2).

[0150] Table 2: Task scheduling tracker measured table

[0151] 2. Energy consumption: SPEC-cpu2006 (standard performance evaluation suite) *4 parallel compilation, SoC power consumption decreased by 9.4% (Synopsys PrimePower@TSMC28nmHPC process simulation).

[0152] 3. Real-time performance: the peak value of automobile ECU (Electronic Control Unit) control-loop (control loop) jitter decreased from 18µs to 6µs (AUTOSAR OS v4.3 task scheduling tracker measured).

[0153] 4. Code invasive: no need to modify the existing kernel scheduler, just call the relevant instructions in the user layer or hypervisor (virtual machine manager).

[0154] In summary, the present application aims at the technical gap of the lack of hardware-level fine-grained lock for the shared cache of the existing multi-core processor, and proposes a partition lock method taking RISC-V instruction extension as the core and combining cache controller micro-architecture modification, which can significantly improve the real-time performance and system energy efficiency, and has significant industrial and economic value.

[0155] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A fine-grained cache partitioning lock method based on RISC-V extended instructions, characterized in that, The method includes the following steps: The RISC-V instruction set architecture introduces a new Zicpl extended instruction family, which includes the LOCK.CP, UNLOCK.CP, TESTLOCK.CP, and SET.CP instructions. A partition lock table is added on the processor's cache controller side. The partition lock table contains multiple entries, each of which includes an owner field, a timeout field, and a valid field. Add a lock flag and a partition identifier field to the Tag area of ​​the cache memory; When the LOCK.CP instruction is executed, the processor accesses the partition lock table. If the valid field of the target partition is 0, the owner field of the partition is set to the current hardware thread ID and the valid field is set to 1, and the lock flag of all existing tags of the partition is updated to 1. If the valid field of the target partition is 1 and the owner field is consistent with the current hardware thread ID, success is returned. If the valid field of the target partition is 1 and the owner field is inconsistent with the current hardware thread ID, failure is returned. The SET.CP instruction is used to dynamically modify the mapping relationship between cache lines and partitions to support hot migration; The UNLOCK.CP command is used to unlock a specified partition; The TESTLOCK.CP command is used to query the lock status of a specified partition.

2. The fine-grained cache partitioning lock method based on RISC-V extended instructions according to claim 1, characterized in that, It also includes a timeout mechanism, which automatically releases the lock of the corresponding partition and triggers a CPLOCK_TIMEOUT exception to be submitted to the processor exception controller when the timeout field reaches a predetermined threshold.

3. The fine-grained cache partitioning lock method based on RISC-V extended instructions according to claim 1, characterized in that, This also includes adding configuration registers to the privileged architecture; The configuration register is used to set the partition granularity; The partitioning granularity includes cache-line level, cache-set level, and cache-way level.

4. The fine-grained cache partitioning lock method based on RISC-V extended instructions according to claim 1, characterized in that, It also includes newly added dedicated registers and control and status registers, which include: A cache partition identifier register, implemented in 5-bit hardware, is used to store the target partition number of the current operation and supports 32 independent partitions; A cache partition lock register, wherein the bit width of the cache partition lock register is equal to the maximum number of partitions, and each bit corresponds to the lock state of the cache partition identifier; A global partition lock status register, which is a read-only register, is used to indicate the global partition lock status.

5. The fine-grained cache partitioning lock method based on RISC-V extended instructions according to claim 1, characterized in that, The partition lock table uses a dual-port block random access memory (BRAM). The write end of the dual-port BRAM comes from the CPU, while the read end interacts with the cache state machine.

6. The fine-grained cache partitioning lock method based on RISC-V extended instructions according to claim 1, characterized in that, The owner field is used to identify the hardware thread ID that holds the lock, the timeout field is a counter used for timeout counting, and the valid field is used to indicate whether the entry is valid.

7. The fine-grained cache partitioning lock method based on RISC-V extended instructions according to claim 1, characterized in that, It also includes exception handling steps, such as automatically clearing the corresponding row in the partition lock table when the mstatus.WFI timer expires or the hart_reset event occurs; it supports manual clearing of dangling locks via mcmiscCSR for debugger use; and it implements automatic lock release upon timeout through the timeout field to prevent deadlock.

8. A processor, characterized in that, This includes an instruction decoder, a partition lock table, and a cache memory, among which: The instruction decoder is used to identify and execute the Zipl extended instructions as described in any one of claims 1-7; The partition lock table contains multiple entries, each of which includes an owner field, a timeout field, and a valid field. The owner field is used to identify the hardware thread ID that holds the lock, the timeout field is a counter used for timeout counting, and the valid field is used to indicate whether the entry is valid. The Tag area of ​​the cache memory includes a lock flag and a partition identifier field.

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