Server, method and device for identifying NVMe hard disk and storage medium

Abstract

The invention provides a server, a method and equipment for identifying an NVMe hard disk and a storage medium. According to the embodiment of the invention, based on a slot number sequence locally stored by a second programmable logic chip on a backboard in advance, a first programmable logic chip integrates slot number sequences of all backboards, and a corresponding relation based on an MCIO interface identifier and the slot number sequences is constructed, so that a BIOS chip identifies the slot number of an NVMe hard disk based on the corresponding relation; and unified management of server-level logic slot numbers is realized. And the substrate management controller directly queries the localized storage slot number sequence of each backboard, so that the accuracy of the identification result is ensured while the characteristic of not depending on the mainboard is maintained. Therefore, the BIOS chip and the substrate management controller do not need to pay attention to hardware connection details and only need to inquire the uniform slot number sequence locally stored in the backboard, the adaptation cost is remarkably reduced, and the problem of slot number recognition dislocation caused by cable connection changes is solved.

Description

Technical Field

[0001] This application relates to the field of server hard drive identification, and more particularly to a server, a method, device, and storage medium for identifying NVMe hard drives. Background Technology

[0002] Servers can be configured with various types of backplanes, and multiple hard drives are typically integrated on the backplane. During server operation, the BIOS (Basic Input / Output System) or BMC (Baseboard Management Controller) usually assigns slot numbers based on the specific backplane model and its cable connection to the motherboard using a preset mapping relationship.

[0003] This design results in a high degree of coupling between software and hardware, lacking necessary flexibility. If cable connections are not strictly executed according to the established mapping relationship during actual deployment or maintenance, the slot numbers displayed by the BIOS and BMC will not correspond to the physical slots of the hard drive, causing trouble for technicians in troubleshooting, hard drive location, and other maintenance work. Summary of the Invention

[0004] To overcome the aforementioned problems in the prior art, this disclosure provides a server, a method for identifying NVMe hard drives, a device, and a storage medium. Specifically, this application is implemented through the following technical solution:

[0005] According to a first aspect of the embodiments of this specification, a server is provided, the server including a motherboard, a baseboard management controller and at least one backplane, the motherboard including a first programmable logic chip and a BIOS chip, the backplane including a second programmable logic chip and at least one physical slot, the physical slot being used to install an NVMe hard drive; the first programmable logic chip including at least one MCIO interface, the MCIO interface being used to connect to at least one second programmable logic chip.

[0006] The first programmable logic chip is used to pre-allocate a slot number sequence and send it to the second programmable logic chip; and to identify the second programmable logic chip connected to each of the MCIO interfaces in real time, and to construct the correspondence between the identifier of each MCIO interface and each slot number sequence based on the slot number sequence stored in the second programmable logic chip.

[0007] The BIOS chip is used to assign logical slot numbers to each NVMe hard drive in the NVMe hard drive sequence identified by the chip at startup, based on the slot number sequence corresponding to the MCIO interface constructed by the first programmable logic chip, and run the BIOS program based on the assigned logical slot numbers.

[0008] The baseboard management controller is used to query the slot number sequence pre-stored by the second programmable logic chip at startup, assign logical slot numbers to each NVMe hard drive in the NVMe hard drive sequence identified by the chip based on the slot number sequence, and run the baseboard management program based on the assigned logical slot numbers.

[0009] According to a second aspect of the embodiments of this specification, a method for a BIOS chip to identify an NVMe hard drive is provided, wherein the BIOS chip is located on a server motherboard; the motherboard further includes a first programmable logic chip; the server further includes at least one backplane, the backplane including a second programmable logic chip and at least one physical slot for installing an NVMe hard drive; the first programmable logic chip includes at least one MCIO interface, the MCIO interface being used to connect to at least one of the second programmable logic chips; the method includes:

[0010] During startup, the first programmable logic chip obtains the correspondence between the identifiers of each MCIO interface and the slot number sequence; the first programmable logic chip pre-allocates the slot number sequence and sends it to the second programmable logic chip; and the second programmable logic chip connected to each MCIO interface is identified in real time, and the correspondence between the identifiers of each MCIO interface and the slot number sequence is constructed based on the slot number sequence stored in the second programmable logic chip.

[0011] Based on the correspondence between the identifiers of each MCIO interface and the slot number sequence, logical slot numbers are assigned to each NVMe hard drive in the NVMe hard drive sequence identified by this chip, so as to run the BIOS program based on the assigned logical slot numbers.

[0012] According to a third aspect of the embodiments of this specification, a method for a baseboard management controller to identify an NVMe hard drive is provided. The baseboard management controller is disposed in a server, the server further comprising a motherboard and at least one backplane; the motherboard includes a first programmable logic chip; the backplane includes a second programmable logic chip and at least one physical slot for mounting an NVMe hard drive; the method includes:

[0013] At startup, the slot number sequence pre-stored by the second programmable logic chip is queried; the slot number sequence is pre-allocated by the first programmable logic chip and sent to the second programmable logic chip.

[0014] Based on the slot number sequence, a logical slot number is assigned to each NVMe hard drive in the NVMe hard drive sequence identified by this chip, so as to run the baseboard management program based on the assigned logical slot number.

[0015] According to a fourth aspect of the embodiments of this specification, an electronic device is provided, including a processor and a machine-readable storage medium storing machine-executable instructions executable by the processor, the processor being prompted by the machine-executable instructions to perform the method as described in the second or third aspect.

[0016] According to a fifth aspect of the embodiments of this specification, a computer-readable storage medium is provided, wherein the storage medium stores a computer program that, when executed by a processor, implements the method described in the second or third aspect.

[0017] This embodiment of the specification is based on the slot number sequence pre-stored locally by the second programmable logic chip on the backplane. To enable the BIOS program to run, the first programmable logic chip integrates all the slot number sequences of the backplane and constructs a correspondence between MCIO interface identifiers and slot number sequences. The BIOS chip then uses this correspondence to identify the NVMe hard drive slot number, achieving unified management of server-level logical slot numbers. To enable the baseboard management program to run, the baseboard management controller directly queries the locally stored slot number sequence of each backplane, ensuring accuracy of the identification results while maintaining its independence from the motherboard. Therefore, neither the BIOS chip nor the baseboard management controller needs to concern themselves with hardware connection details; they only need to query the unified locally stored slot number sequence on the backplane, significantly reducing adaptation costs and solving the problem of slot number misidentification caused by changes in cable connections. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a server shown in an embodiment of this specification;

[0019] Figure 2 This is a schematic diagram of the interaction in the server of an application example in this manual;

[0020] Figure 3 This is a flowchart illustrating a method for BIOS to recognize an NVMe hard drive, as shown in an embodiment of this specification.

[0021] Figure 4 This is a schematic flowchart illustrating a method for a baseboard management controller to identify an NVMe hard drive, as shown in an embodiment of this specification.

[0022] Figure 5 This is a schematic diagram of the structure of an electronic device provided by way of example in this specification. Detailed Implementation

[0023] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0024] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0025] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0026] To provide stable data storage and processing capabilities, servers typically integrate multiple hard drives on their backplanes. The server backplane, a PCB board, primarily provides physical mounting positions, power interfaces, and high-speed data connection channels for the hard drives. The hard drive backplane connects to the server motherboard via cables and may integrate a programmable logic chip. This programmable logic chip manages the hard drive slots on the backplane, including detecting hard drive presence signals, identifying hard drive types, and reporting backplane-related information to other modules (such as the programmable logic chip integrated on the motherboard and the BMC baseboard management controller) through auxiliary interfaces. The structural design and number of interfaces of the hard drive backplane determine the number and specifications of hard drives that the server can support.

[0027] A server also includes a motherboard, which is the core circuit board of the server, housing the central processing unit, memory, and various expansion slots and interfaces. As the server's connection hub, it provides data paths and power supply to various additional components. The motherboard can perform low-level signal detection and logic control through its integrated programmable logic chip and communicate with the backplane through a dedicated auxiliary interface.

[0028] These components constitute the basic storage architecture of a server. The motherboard provides control and resource allocation, the backplane serves as an expansion and connection unit, and the hard drives mounted on the backplane are the data storage carriers. They connect and exchange data through standardized interfaces and communication protocols, ensuring the stability and scalability of the server storage system.

[0029] Servers can be configured with various types of backplanes, such as 4LFF (four-bay large form factor), 8SFF (eight-bay small form factor), or 12LFF (twelve-bay large form factor). In traditional technical solutions, the BIOS (Basic Input Output System) or BMC (Baseboard Management Controller) typically assigns slot numbers based on a preset mapping relationship according to the specific backplane model and its cable connection method with the motherboard.

[0030] This highly dependent design results in a tight coupling between software and hardware, lacking necessary flexibility. If cable connections are not strictly executed according to the established mapping during actual deployment or maintenance, the logical slot numbers displayed by the BIOS and BMC will not correspond to the physical slots of the hard drives, causing difficulties for technicians in troubleshooting, locating hard drives, and other maintenance tasks. Furthermore, whenever a new hard drive backplane model is introduced, the software layer must be modified and adapted accordingly to integrate the new backplane identification logic and slot mapping table. This process not only increases the workload of software development but also extends the overall project development cycle.

[0031] To illustrate the above traditional technical solutions, please refer to the following example.

[0032] A server has a motherboard with four MCIO interfaces (designated MCIO0 to MCIO3) for connecting to a backplane. This server is configured with two identical 8SFF backplanes (backplane A and backplane B), each capable of accommodating eight NVMe hard drives.

[0033] After configuring the backplane, the system firmware needs to be pre-updated with a mapping table for each backplane and cable connection method. The engineer responsible for writing the mapping table must clearly specify how each cable should be connected beforehand. For example, the mapping table specifies that backplane A connects to the MCIO0 interface of the motherboard, and backplane B connects to the MCIO1 interface; the eight physical slots (P0 to P7) on backplane A are pre-mapped to slot numbers SLOT0 to SLOT7; and the eight physical slots (P0 to P7) on backplane B are mapped to SLOT8 to SLOT15.

[0034] The BIOS and BMC software code hard-coded the above mapping rules. When the server boots up, the BIOS chip queries the first programmable logic chip and finds a backplane connected to the MCIO0 interface. It automatically identifies this as backplane A and assigns its hard drives to SLOT0 through SLOT7. Similarly, the backplane on the MCIO1 interface is identified as backplane B, and its hard drives are assigned to SLOT8 through SLOT15. The BMC can obtain the same identification result by querying the second programmable logic chip. Therefore, the hard drive order displayed on the BIOS and BMC management interfaces is consistent with the order of the physical slots on the backplane.

[0035] However, this approach has drawbacks in practical deployment. Personnel must strictly adhere to the rules of the mapping table when connecting cables, thus imposing significant constraints on cable layout. Furthermore, incorrect cable connections can lead to incorrect identification results. For example, a maintenance worker in the data center might inadvertently swap the cables connecting backplane A and backplane B during maintenance; backplane A might be plugged into the MCIO1 interface of the motherboard, while backplane B might be plugged into the MCIO0 interface.

[0036] When the server boots up, the BIOS and BMC still strictly adhere to the rules of the hard-coded mapping table for identification. Specifically, the BIOS detects a backplane connected to the MCIO0 interface and immediately identifies it as backplane A, assigning the eight hard drives on backplane B to SLOT0 through SLOT7. Simultaneously, it identifies the backplane connected to the MCIO1 interface as backplane B and assigns the eight hard drives on backplane A to SLOT8 through SLOT15. This misalignment between physical location and logical identification can cause significant confusion and risk for subsequent fault diagnosis, hard drive replacement, and system maintenance.

[0037] Furthermore, the hard-coded nature of this approach makes product iteration more cumbersome. If the server needs to be equipped with a new model of 12LFF backplane, engineers must develop a completely new mapping table for this new backplane. Engineers need to determine which host interface the new backplane should be connected to and redefine a set of slot number offset rules for its physical slots. Therefore, the software development, testing, and verification cycle for each server will be extended, and the adaptation cost for the new backplane will be high.

[0038] The core issue causing these problems is the difficulty in maintaining consistency between the physical topology of the hard drive and the software display logic.

[0039] Therefore, existing technologies lack a universal mechanism that can automatically identify the type and location of hard drive backplanes and dynamically assign slot numbers consistent with the physical layout. This deficiency limits the flexibility and scalability of server storage systems and poses ongoing challenges to large-scale deployment and operation management.

[0040] To solve the aforementioned problems, Figure 1 According to an embodiment of this specification, a server includes a motherboard 100, a baseboard management controller 120, and at least one backplane 110. The motherboard 100 includes a first programmable logic chip 101 and a BIOS chip 102. The backplane 110 includes a second programmable logic chip 111 and at least one physical slot 112 for installing an NVMe hard drive. The first programmable logic chip 101 includes at least one MCIO interface, and the first programmable logic chip 101 is connected to the second programmable logic chip 111 through the MCIO interface.

[0041] The server in this embodiment can be divided into three parts: a motherboard 100, a baseboard management controller 120, and one or more hard disk backplanes 110. The motherboard 100 serves as the computing and control center of the entire server, integrating a first programmable logic chip 101 and a BIOS chip 102. The first programmable logic chip 101 is a semiconductor device responsible for low-level hardware logic control and can be a CPLD, FPGA, or similar chip. The BIOS chip 102 stores the BIOS program and can be a ROM, EEPROM, Flash ROM, or similar chip. The BIOS program is a machine language program embedded in the BIOS chip 102, responsible for the server's hardware initialization and configuration.

[0042] The baseboard management controller 120 is an embedded management system independent of the motherboard 100, used to provide out-of-band management functions for the server. Even when the operating system is not running, the baseboard management controller 120 can still monitor the hardware status and respond to management commands.

[0043] Backplane 110 is a dedicated expansion board for housing and connecting hard disk drives. Each backplane 110 integrates a second programmable logic chip 111 for managing the hardware resources on this backplane 110, and can be a chip such as a CPLD or FPGA. Backplane 110 has one or more physical slots 112, which provide physical mounting locations, power interfaces, and data channels for hard disk drives.

[0044] In order to ensure that the display logic of the BIOS program and the baseboard management program is consistent with the physical topology of the hard disk, the first programmable logic chip 101 in this embodiment of the specification is used to pre-allocate the slot number sequence and send it to the second programmable logic chip 111.

[0045] Before the BIOS program and baseboard management program start, the first programmable logic chip 101 pre-assigns a slot number sequence to each backplane 110. The slot number sequence includes one or more logical slot numbers, and each logical slot number can correspond to a physical slot 112 on the corresponding backplane 110. After the assignment is completed, the first programmable logic chip 101 sends the generated slot number to the second programmable logic chip 111 on each backplane 110 for storage.

[0046] As one or more embodiments of the present invention, the first programmable logic chip 101 is used to pre-allocate a slot number sequence in the following manner:

[0047] The type of the corresponding backplane 110 is obtained by each of the second programmable logic chips 111, the slot number sequence of the backplane 110 is allocated based on the type of the backplane 110, and the allocated slot number sequence is sent to the corresponding second programmable logic chip 111.

[0048] For example, the connection between the first programmable logic chip 101 and each of the second programmable logic chips 111 is achieved through the AUX interface and MCIO interface of the first programmable logic chip 101. The first programmable logic chip 101 includes one or more AUX interfaces and MCIO interfaces, and the number of AUX interfaces and MCIO interfaces is not less than the number of backplane 110. Compared to the MCIO interface used to adapt to the PCIe protocol, the AUX interface is based on a simpler underlying protocol, such as I2C, SMBus, or single-wire signaling. When the server is powered on, the AUX interface can be put into operation immediately, and the first programmable logic chip 101 and the second programmable logic chip 111 can communicate through the AUX interface without relying on the MCIO interface based on the complex PCIe protocol.

[0049] Regarding the slot number allocation process, after the server powers on, the first programmable logic chip 101 sends a request via the AUX interface to each accessible second programmable logic chip 111 to obtain the type of the backplane 110 it manages. Upon receiving the request, the second programmable logic chip 111 reads the pre-programmed or dynamically detected backplane 110 type from its internal storage unit, encapsulates this information into response data, and sends it back to the first programmable logic chip 101 via the same AUX interface. The backplane 110 type is an identifier used to characterize the backplane 110 model and specifications, directly determining the total number and layout of physical slots 112 on the backplane 110, as well as the types of hard drive protocols it supports.

[0050] In some embodiments, each backplane 110 may have a preset unique identifier, backplane 110ID, and the value of the backplane 110ID needs to carry information indicating the type of the backplane 110. The second programmable logic chip 111 can feed back the backplane 110ID as response data to the first programmable logic chip 101. For example, the backplane 110ID carrying "4LFF" represents a four-bay large-format backplane 110, and carrying "8SFF" represents an eight-bay small-format backplane 110.

[0051] After obtaining the type of backplane 110, the first programmable logic chip 101 will assign a corresponding slot number sequence to the backplane 110 based on its type. The principle to be followed during the allocation process is to ensure that each NVMe hard drive that may be plugged into each physical slot 112 of each backplane 110 in the entire server is assigned a globally unique logical slot number.

[0052] In some embodiments, the first programmable logic chip 101 is further configured to assign a slot number sequence of the backplane 110 based on the type of the backplane 110 in the following manner:

[0053] The number of physical slots 112 of the backplane 110 is obtained based on the type of the backplane 110. The type of the backplane 110 is the basis for the allocation logic. The first programmable logic chip 101 can identify the number of physical slots 112 of each backplane 110 according to the type of the backplane 110, and then determine the number of logic slot numbers required for the backplane 110.

[0054] The backplane 110 is assigned a slot number sequence based on the occupied logical slot numbers and the quantity. After determining the number of physical slots 112, the first programmable logic chip 101 first queries the logical slot numbers already allocated to other backplanes 110, then determines the currently available logical slot numbers, and then generates a slot number sequence for the backplane 110 based on the available logical slot numbers and sends it to the second programmable logic chip 111 of the backplane 110. The logical slot number allocation method in this embodiment ensures that all hard drives in the server can obtain globally unique and continuous logical identifiers.

[0055] For example, logical slot numbers can be generated in an integer incrementing manner. The highest allocated slot number is determined by the occupied logical slot numbers. Based on this highest slot number and the latest identified number of physical slots 112 on the backplane 110, the first programmable logic chip 101 can generate a new, continuous sequence of slot numbers to be allocated. The starting number of this sequence is the next number after the highest allocated slot number, and its length is equal to the number of physical slots 112 on the backplane 110.

[0056] For example, in the case where the backplane 110 is of type "8SFF", the first programmable logic chip 101 identifies that this is a backplane 110 that supports 8 small form factor hard drives, that is, the backplane 110 has 8 physical slots 112. Then, it finds that the logical slot numbers already assigned to another backplane 110 are SLOT0 to SLOT7, so the slot number sequence assigned to this backplane 110 is SLOT8 to SLOT15 in sequence.

[0057] Based on the pre-stored slot number sequence in the second programmable logic chip 111, the first programmable logic chip 101 is also used to identify the second programmable logic chip 111 connected to each of the MCIO interfaces in real time, and construct the correspondence between the identifier of each MCIO interface and each slot number sequence based on the slot number sequence stored in the second programmable logic chip 111.

[0058] The first programmable logic chip 101 identifies the second programmable logic chip 111 connected to each MCIO interface in real time, obtains the stored slot number sequence, and then associates the identifier of the MCIO interface with the slot number sequence, thereby providing a basis for determining the logical slot number of each NVMe hard drive.

[0059] In some implementations, the first programmable logic chip 101 initiates a query request to the second programmable logic chip 111 connected to the MCIO interface through each MCIO interface. Then, each of the second programmable logic chips 111 responds to the received query request and returns the pre-stored slot number sequence mentioned in the previous step. After collecting the slot number sequence of the backplane 110, the first programmable logic chip 101 constructs a correspondence accordingly.

[0060] The BIOS chip 102 is used to assign logical slot numbers to each NVMe hard drive in the NVMe hard drive sequence identified by the chip at startup, based on the slot number sequence corresponding to the MCIO interface constructed by the first programmable logic chip 101, and run the BIOS program based on the assigned logical slot numbers.

[0061] The BIOS program is responsible for initializing hardware and identifying device resources during the server's boot phase. Specifically, for identifying device resources, especially storage devices like NVMe hard drives, the BIOS program needs to accurately identify and assign them logical identifiers, or slot numbers, so that the physical installation location of the hard drive (e.g., which backplane 110, which physical slot 112) is translated into a numerical index that the software can easily recognize and manage.

[0062] In some implementations, the process of identifying NVMe hard drives is as follows:

[0063] When the BIOS program is loaded and run by the BIOS chip 102, it performs an enumeration process for PCIe (Peripheral Component Interconnect Express) devices, thereby identifying and configuring all hardware devices connected to the BIOS chip 102 via the PCIe bus. During the enumeration process, the BIOS chip 102 scans the entire PCIe bus topology, accessing each possible device node on the bus level by level. For each device connected to the PCIe bus, the BIOS chip 102 reads the relevant information of that device. For example, devices connected to the PCIe bus may include graphics processing units, network interface controllers, host bus adapters, and various types of hard drives. Hard drives can be further categorized into NVMe hard drives, SATA hard drives, etc. In this embodiment, the types of devices connected to the PCIe bus include at least NVMe hard drives connected via the MCIO interface.

[0064] However, simply knowing the existence of each NVMe drive is insufficient for server management needs, especially when the server is equipped with multiple backplanes 110 and multiple drives. The BIOS program requires a unique logical slot number to identify each NVMe drive. The MCIO interface, as an interface connected to the PCIe bus, can identify one or more devices corresponding to each MCIO interface as NVMe drives during the identification process. These NVMe drives are then recorded as the NVMe drive sequence corresponding to the identifier of that MCIO interface. It should be noted that the NVMe drives in the NVMe drive sequence are identified according to the order of the physical slots 112 on the backplane 110.

[0065] Then, the slot number sequence corresponding to the MCIO interface constructed by the first programmable logic chip 101 is queried through the MCIO interface identifier. After the slot number sequence is found, since both the slot number sequence and the NVMe hard drive sequence follow the order of the physical slots 112 on the backplane 110, logical slot numbers can be assigned to each NVMe hard drive in the NVMe hard drive sequence based on the slot number sequence. Subsequently, all subsequent operations of the BIOS chip 102 in running the BIOS program, including hardware configuration, resource allocation, and submitting hardware topology information to the operating system, will be based on the slot number of the NVMe hard drive.

[0066] It should be noted that the backplane 110 in this embodiment can accommodate various hard drives. Since this embodiment aims to improve the identification method for NVMe hard drives, the connection and identification methods for other types of hard drives, such as SATA hard drives, will not be described here. It is understood that the BIOS chip 102 can identify other types of hard drives on the backplane 110 using any existing method.

[0067] Based on the pre-stored slot number sequence in the second programmable logic chip 111, the hard drive identification process of the baseboard management controller 120 is independent of the first programmable logic device of the aforementioned motherboard 100. The baseboard management controller 120 is used to query the pre-stored slot number sequence in the second programmable logic chip 111 during startup, assign logical slot numbers to each NVMe hard drive in the NVMe hard drive sequence identified by the chip based on the slot number sequence, and run the baseboard management program based on the assigned logical slot numbers.

[0068] In some implementations, the backplane 110 and the baseboard management controller 120 can also establish a communication connection via an AUX-I2C channel. The BIOS chip 102 and the first programmable logic chip 101 can also establish a connection via an I2C channel.

[0069] The baseboard management controller 120 maintains real-time communication with the second programmable logic chips 111 on each backplane 110. The baseboard management controller 120 first initiates a query request to the second programmable logic chip 111 to obtain the slot number sequence pre-stored by the second programmable logic chip 111. During the operation of the baseboard management program, the baseboard management controller 120 actively polls or receives reports from the second programmable logic chip 111, thereby continuously obtaining the NVMe hard drive sequence on each backplane 110. After successfully obtaining the NVMe hard drive sequence, the obtained slot number sequence is used as the NVMe hard drive sequence, serving as its logical identifier in the baseboard management program. Subsequently, all subsequent management operations of the baseboard management controller 120 will be based on this logical slot number. For example, correctly displaying the hard drive's location information on the management interface, recording the hard drive's health status and operating indicators according to the slot number, receiving and processing power-down or positioning commands for hard drives with specific slot numbers, and reporting asset and fault information based on the slot number to the upper-level management system. Accordingly, the hardware view provided by the baseboard management controller 120 is consistent with the physical layout of the hard drive and the logical order recognized by the BIOS.

[0070] Based on the above embodiments, when a new type of hard disk backplane 110 is introduced, since each second programmable logic chip 111 pre-stores the slot number sequence, and the mapping relationship between the MCIO interface identifier and the slot number sequence is only constructed based on the real-time identified MCIO interface identifier when the BIOS chip 102 needs it, instead of being constructed in advance before the server starts as in the traditional solution, plug-and-play hardware compatibility is achieved, and software adaptation costs are reduced.

[0071] This embodiment of the specification is based on the slot number sequence pre-stored locally by the second programmable logic chip 111. To enable the BIOS program to run, the first programmable logic chip 101 integrates the slot number sequences of all backplanes 110, constructing a correspondence between MCIO interface identifiers and slot number sequences. The BIOS chip 102 then identifies the NVMe hard drive slot number based on this correspondence, achieving unified management of server-level logical slot numbers. To enable the baseboard management program to run, the baseboard management controller 120 directly queries the locally stored slot number sequence of each backplane 110, ensuring accuracy of the identification results while maintaining independence from the motherboard 100. Therefore, neither the BIOS chip 102 nor the baseboard management controller 120 needs to concern themselves with hardware connection details; they only need to query the unified locally stored slot number sequence of the backplanes 110, significantly reducing adaptation costs and solving the problem of slot number misidentification caused by changes in cable connections.

[0072] As one or more embodiments of this specification, the first programmable logic chip 101 is further configured to construct the correspondence between the identifiers of each MCIO interface and the sequence of slot numbers in the following manner:

[0073] The second programmable logic chip 111 detects the presence status of the NVMe hard drives in each physical slot 112. During the process of establishing the correspondence, the first programmable logic chip 101 first queries the connected second programmable logic chip 111 through each MCIO interface to check the presence status of the NVMe hard drives in each physical slot 112 in the corresponding backplane 110.

[0074] The logical slot number in the pre-stored slot number sequence of the second programmable logic chip 111 is updated based on the in-situ state. Since the pre-stored slot number sequence is consistent with the number of physical slots 112 on the backplane 110, the in-situ state of each physical slot 112 can sequentially correspond to a logical slot number in the slot number sequence. For physical slots 112 where an NVMe hard drive is in place, its corresponding logical slot number remains unchanged; for physical slots 112 where an NVMe hard drive is not in place, the first programmable logic chip 101 modifies the logical slot number corresponding to that physical slot 112 in the slot number sequence to a default value. This default value is a pre-set identifier, which indicates that the physical slot 112 is currently in an idle state or that other types of hard drives exist, and that no usable NVMe hard drive exists.

[0075] After the update is completed, establish the correspondence between the identifiers of each MCIO interface and the updated slot number sequence.

[0076] This embodiment introduces a hard drive presence status detection and dynamic update mechanism to ensure that the constructed mapping relationship accurately reflects the real-time physical connection status of the server system. This allows the BIOS program to not only obtain the correct slot number allocation when querying the mapping relationship, but also clearly distinguish between available hard drives and free slots, thereby avoiding reporting invalid devices to the operating system and significantly improving the accuracy and reliability of system initialization. Please refer to the following section. Figure 2 Based on the server shown in the above embodiments of this application, Figure 2 This is a schematic diagram of the interaction in the server of an application example of this application.

[0077] In the application example, slot number allocation is first performed. In response to a request from the first programmable logic chip, the second programmable logic chip sends the backplane type (S200). After obtaining the backplane type, the first programmable logic chip allocates a slot number sequence for the backplane based on the backplane type (S201). In S202, the first programmable logic chip sends the allocated slot number sequence to the corresponding second programmable logic chip. In S203, the second programmable logic chip stores the received slot number sequence.

[0078] Subsequently, the process splits into two parallel branches, serving the BIOS chip and the baseboard management controller respectively.

[0079] BIOS chip identification branch:

[0080] S204A, the first programmable logic chip identifies the second programmable logic chip connected to each MCIO interface and requests the slot number sequence from it (S205A). The second programmable logic chip returns the stored slot number sequence (S206A). The first programmable logic chip uses this information to construct a correspondence between the identifiers of each MCIO interface and the slot number sequences (S207A). The BIOS chip performs PCIe enumeration, identifies the NVMe hard drive sequence corresponding to each MCIO interface (S208A), and requests the correspondence from the first programmable logic chip (S209A). The first programmable logic chip returns the correspondence to the BIOS chip (S210A). Based on this correspondence, the BIOS chip assigns the corresponding slot number sequence to the identified NVMe hard drive sequence, and then assigns logical slot numbers to each NVMe hard drive in the NVMe hard drive sequence according to the order of the logical slot numbers in the slot number sequence (S211A). Finally, the BIOS program runs based on the logical slot numbers of the NVMe hard drives (S212A).

[0081] Baseboard management controller identification branch:

[0082] The baseboard management controller queries each of the second programmable logic chips for the NVMe hard drive sequence of the backplane (S204B), and the second programmable logic chips respond by returning the NVMe hard drive sequence of the corresponding backplane (S205B). The baseboard management controller queries the slot number sequence pre-stored by each of the second programmable logic chips (S206B), and the second programmable logic chips respond by returning the slot number sequence (S207B). Accordingly, the baseboard management controller assigns logical slot numbers to each NVMe hard drive in the corresponding NVMe hard drive sequence on the backplane according to the order of the logical slot numbers in the slot number sequence (S208B). Finally, the baseboard management controller runs the baseboard management program based on the slot numbers of the NVMe hard drives (S209B).

[0083] Please see below. Figure 3 , Figure 3 This is a flowchart illustrating a method for a BIOS chip to identify an NVMe hard drive, as shown in an embodiment of this application. The method is applicable to a BIOS chip in a server motherboard; the motherboard further includes a first programmable logic chip; the server further includes at least one backplane, the backplane including a second programmable logic chip and at least one physical slot for installing an NVMe hard drive; the first programmable logic chip includes at least one MCIO interface, the MCIO interface being used to connect to at least one of the second programmable logic chips; the method includes:

[0084] S300: During startup, the first programmable logic chip obtains the correspondence between the identifiers of each MCIO interface and the slot number sequence; the first programmable logic chip pre-allocates the slot number sequence and sends it to the second programmable logic chip; and the second programmable logic chip connected to each MCIO interface is identified in real time, and the correspondence between the identifiers of each MCIO interface and the slot number sequence is constructed based on the slot number sequence stored in the second programmable logic chip.

[0085] S302: Based on the correspondence between the identifiers of each MCIO interface and the slot number sequence, assign logical slot numbers to each NVMe hard drive in the NVMe hard drive sequence identified by this chip, so as to run the BIOS program based on the assigned logical slot numbers.

[0086] As one or more embodiments of the specification, the slot number sequence is pre-allocated by the first programmable logic chip and sent to the second programmable logic chip; the pre-allocated slot number sequence includes:

[0087] The type of the corresponding backplane is obtained through each of the second programmable logic chips, the slot number sequence of the backplane is allocated based on the type of the backplane, and the allocated slot number sequence is sent to the corresponding second programmable logic chip.

[0088] As one or more embodiments of the specification, the correspondence between the identifiers of each MCIO interface and the sequence of slot numbers is constructed in the following manner:

[0089] The presence status of NVMe hard drives in each physical slot is detected by the second programmable logic chip.

[0090] The logic slot number in the pre-stored slot number sequence of the second programmable logic chip is updated based on the in-situ state.

[0091] Construct the correspondence between the identifiers of each MCIO interface and the updated slot number sequence.

[0092] Please see below. Figure 4 , Figure 4 This is a flowchart illustrating a method for a baseboard management controller to identify an NVMe hard drive, as shown in an embodiment of this application. The baseboard management controller is disposed in a server, which further includes a motherboard and at least one backplane; the motherboard includes a first programmable logic chip; the backplane includes a second programmable logic chip and at least one physical slot for installing an NVMe hard drive; the method includes:

[0093] S400: At startup, query the slot number sequence pre-stored by the second programmable logic chip; the slot number sequence is pre-allocated by the first programmable logic chip and sent to the second programmable logic chip;

[0094] S402: Based on the slot number sequence, assign logical slot numbers to each NVMe hard drive in the NVMe hard drive sequence identified by this chip, and run the baseboard management program based on the assigned logical slot numbers.

[0095] This disclosure also provides Figure 5 The diagram illustrates the structure of an exemplary electronic device. The electronic device includes a processor 501 and a machine-readable storage medium 502; the machine-readable storage medium 502 stores machine-executable instructions that can be executed by the processor 501, which in turn cause the processor 501 to perform the method shown in any of the above embodiments.

[0096] Embodiments of the electronic device described in this application can be applied to servers. For example... Figure 5As shown, at the hardware level, the electronic device includes a processor 501, a system bus 503, a network interface, memory, and a machine-readable storage medium 502, and may also include other hardware required for business operations. The processor 501 reads the corresponding computer program from non-volatile memory into memory and then runs it to implement the method shown in any of the above embodiments. Of course, in addition to software implementation, this specification does not exclude other implementation methods, such as logic devices or a combination of hardware and software, etc. That is to say, the execution subject of the following processing flow is not limited to each logic unit, but can also be hardware or logic devices.

[0097] This disclosure also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method shown in any of the above embodiments.

[0098] Computer-readable media, including both permanent and non-permanent, removable and non-removable media, can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, disk storage, quantum memory, graphene-based storage media or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0099] The specific implementation process of the functions and roles of each unit in the above device can be found in the implementation process of the corresponding steps in the above method, and will not be repeated here.

[0100] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to in the description of the method embodiments. The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this application according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0101] The embodiments of the subject matter and functional operation described in this specification can be implemented in the following ways: digital electronic circuits, tangibly embodied computer software or firmware, computer hardware including the structures disclosed in this specification and their structural equivalents, or combinations thereof. Embodiments of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible, non-transitory program carrier for execution by a data processing apparatus or for controlling the operation of a data processing apparatus. Alternatively or additionally, the program instructions may be encoded on artificially generated propagation signals, such as machine-generated electrical, optical, or electromagnetic signals, which are generated to encode information and transmit it to a suitable receiving device for execution by the data processing apparatus. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or combinations thereof.

[0102] The processing and logic described in this specification can be executed by one or more programmable computers that execute one or more computer programs to perform corresponding functions by operating on input data and generating output.

[0103] Suitable computers for executing computer programs include, for example, general-purpose and / or special-purpose microprocessors, or any other type of central processing unit. Typically, the central processing unit receives instructions and data from read-only memory and / or random access memory. The basic components of a computer include a central processing unit for implementing or executing instructions and one or more memory devices for storing instructions and data. Typically, a computer will also include one or more mass storage devices for storing data, such as disks, magneto-optical disks, or optical disks, or the computer will be operatively coupled to such mass storage devices to receive data from or transfer data to them, or both. However, a computer is not required to have such devices. Furthermore, a computer can be embedded in another device, such as a mobile phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS) receiver, or a portable storage device such as a universal serial bus (USB) flash drive, to name a few.

[0104] Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices, such as semiconductor memory devices (e.g., EPROM, EEPROM, and flash memory devices), magnetic disks (e.g., internal hard disks or removable disks), magneto-optical disks, and CD-ROM and DVD-ROM disks. Processors and memory may be supplemented by or incorporated into dedicated logic circuitry.

[0105] While this specification contains numerous specific implementation details, these should not be construed as limiting the scope of any invention or the scope of the claims, but rather are primarily intended to describe features of specific embodiments of a particular invention. Certain features described in the various embodiments herein may also be implemented in combination in a single embodiment. Conversely, various features described in a single embodiment may also be implemented separately in various embodiments or in any suitable sub-combination. Furthermore, while features may function in certain combinations as described above and even initially claimed in this way, one or more features from a claimed combination may be removed from that combination in some cases, and a claimed combination may refer to a sub-combination or a variation thereof.

[0106] Similarly, although the operations are depicted in a specific order in the accompanying drawings, this should not be construed as requiring these operations to be performed in the specific order shown or sequentially, or requiring all illustrated operations to be performed to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0107] Thus, specific embodiments of the subject matter have been described. Other embodiments are within the scope of the appended claims. In some cases, the actions recited in the claims may be performed in a different order and still achieve the desired result. Furthermore, the processes depicted in the drawings are not necessarily shown in a specific order or sequence to achieve the desired result. In some implementations, multitasking and parallel processing may be advantageous.

[0108] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A server, characterized in that, The server includes a motherboard, a baseboard management controller, and at least one backplane. The motherboard includes a first programmable logic chip and a BIOS chip. The backplane includes a second programmable logic chip and at least one physical slot for installing an NVMe hard drive. The first programmable logic chip includes at least one MCIO interface for connecting to at least one second programmable logic chip. The first programmable logic chip is used to pre-allocate a slot number sequence and send it to the second programmable logic chip; In addition, the second programmable logic chip connected to each of the MCIO interfaces is identified in real time, and the correspondence between the identifier of each MCIO interface and the slot number sequence is constructed based on the slot number sequence stored in the second programmable logic chip; The BIOS chip is used to assign logical slot numbers to each NVMe hard drive in the NVMe hard drive sequence identified by the chip at startup, based on the slot number sequence corresponding to the MCIO interface constructed by the first programmable logic chip, and run the BIOS program based on the assigned logical slot numbers. The baseboard management controller is used to query the slot number sequence pre-stored by the second programmable logic chip at startup, assign logical slot numbers to each NVMe hard drive in the NVMe hard drive sequence identified by the chip based on the slot number sequence, and run the baseboard management program based on the assigned logical slot numbers.

2. The server according to claim 1, characterized in that, The first programmable logic chip is also used to pre-allocate the slot number sequence in the following manner: The type of the corresponding backplane is obtained through each of the second programmable logic chips, the slot number sequence of the backplane is allocated based on the type of the backplane, and the allocated slot number sequence is sent to the corresponding second programmable logic chip.

3. The server according to claim 2, characterized in that, The first programmable logic chip is also configured to assign a slot number sequence of the backplane based on the type of the backplane in the following manner: The number of physical slots in the backplate is obtained based on the type of the backplate; The backplane slot number sequence is allocated based on the occupied logical slot number and the quantity.

4. The server according to claim 1, characterized in that, The first programmable logic chip is also used to construct the correspondence between the identifiers of each MCIO interface and the sequence of slot numbers in the following manner: The presence status of NVMe hard drives in each physical slot is detected by the second programmable logic chip. The logic slot number in the pre-stored slot number sequence of the second programmable logic chip is updated based on the in-situ state. Construct the correspondence between the identifiers of each MCIO interface and the updated slot number sequence.

5. A method for a BIOS chip to identify an NVMe hard drive, characterized in that, The BIOS chip is located on the server's motherboard; the motherboard also includes a first programmable logic chip; the server also includes at least one backplane, the backplane including a second programmable logic chip and at least one physical slot for installing an NVMe hard drive; the first programmable logic chip includes at least one MCIO interface for connecting to at least one of the second programmable logic chips; the method includes: During startup, the first programmable logic chip obtains the correspondence between the identifiers of each MCIO interface and the slot number sequence; the first programmable logic chip pre-allocates the slot number sequence and sends it to the second programmable logic chip; and the second programmable logic chip connected to each MCIO interface is identified in real time, and the correspondence between the identifiers of each MCIO interface and the slot number sequence is constructed based on the slot number sequence stored in the second programmable logic chip. Based on the correspondence between the identifiers of each MCIO interface and the slot number sequence, logical slot numbers are assigned to each NVMe hard drive in the NVMe hard drive sequence identified by this chip, so as to run the BIOS program based on the assigned logical slot numbers.

6. The method for identifying an NVMe hard drive using a BIOS chip according to claim 5, characterized in that, The first programmable logic chip pre-allocates the slot number sequence in the following manner: The type of the corresponding backplane is obtained through each of the second programmable logic chips, the slot number sequence of the backplane is allocated based on the type of the backplane, and the allocated slot number sequence is sent to the corresponding second programmable logic chip.

7. The method for BIOS chip identification of NVMe hard drive according to claim 6, characterized in that, The correspondence between the identifiers of each MCIO interface and the sequence of slot numbers is constructed in the following way: The presence status of NVMe hard drives in each physical slot is detected by the second programmable logic chip. The logic slot number in the pre-stored slot number sequence of the second programmable logic chip is updated based on the in-situ state. Construct the correspondence between the identifiers of each MCIO interface and the updated slot number sequence.

8. A method for a baseboard management controller to identify an NVMe hard drive, characterized in that, The baseboard management controller is disposed in a server, the server further comprising a motherboard and at least one backplane; the motherboard includes a first programmable logic chip; the backplane includes a second programmable logic chip and at least one physical slot for mounting an NVMe hard drive; the method includes: At startup, the slot number sequence pre-stored by the second programmable logic chip is queried; the slot number sequence is pre-allocated by the first programmable logic chip and sent to the second programmable logic chip. Based on the slot number sequence, a logical slot number is assigned to each NVMe hard drive in the NVMe hard drive sequence identified by this chip, so as to run the baseboard management program based on the assigned logical slot number.

9. An electronic device, characterized in that, The method includes a processor and a machine-readable storage medium storing machine-executable instructions that can be executed by the processor, the processor being prompted by the machine-executable instructions to perform the method as described in any one of claims 5 to 8.

10. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, implements the method described in any one of claims 5 to 8.

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