Data synchronization system, method, device and equipment and storage medium

Abstract

The invention discloses a data synchronization system, method, device and equipment and a storage medium, and relates to the technical field of data transmission. The system comprises a sender device and a receiver device which are connected through a switch network. The sender equipment is used for sending a data access request and a memory barrier request; the switch network is used for transmitting the memory barrier request on all paths between the sender equipment and the receiver equipment in a multicast manner; after the memory barrier requests transmitted on all the paths are successfully converged into a converged memory barrier request, the converged memory barrier request is sent to a receiver device; and the receiver equipment is used for determining that one or more data access operations sent by the sender equipment before sending the memory barrier request are completed after receiving the aggregation memory barrier request, and the one or more data access operations are associated with the data access request.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of data transmission, and in particular to a data synchronization system, method, device, apparatus and storage medium. BACKGROUND

[0002] A memory barrier in a graphics processing unit (GPU) is a synchronization primitive, whose core role is to ensure the execution order visibility of data access operations and guarantee data consistency, so that all data access operations issued before the memory barrier are completed and globally visible before the operation after the memory barrier starts to execute; and the operation after the memory barrier can correctly read the final modification result of the memory data made by the operation before the memory barrier when it is executed.

[0003] In related technologies, consistency ordered at directory (CORD) reduces directory overhead of message propagation through a logical hierarchy while ensuring causal consistency of message exchange. However, CORD needs to carry an increasing logical identifier in each transaction request, which significantly increases the space ratio in the data packet header, thereby reducing the effective bandwidth utilization and also causing the problem of high complexity of state maintenance at the receiving end. SUMMARY

[0004] Embodiments of the present application provide a data synchronization system, method, device, apparatus and storage medium. The technical solutions provided by the embodiments of the present application are as follows:

[0005] According to an aspect of the embodiments of the present application, a data synchronization system is provided, the system comprising a sender device and a receiver device connected through a switch network;

[0006] The sender device is configured to send a data access request and a memory barrier request;

[0007] The switch network is configured to transmit the memory barrier request in a multicast manner on all paths between the sender device and the receiver device, and after successfully converging all the transmitted memory barrier requests into a converged memory barrier request, send the converged memory barrier request to the receiver device;

[0008] The receiver device is configured to determine that one or more data access operations issued by the sender device before sending the memory barrier request have been completed after receiving the converged memory barrier request, the one or more data access operations being associated with the data access request.

[0009] According to one aspect of the embodiments of this application, a data synchronization method is provided, wherein the method is performed by a multicast switch, the method comprising:

[0010] Receive data access requests and memory barrier requests from the sending device. The memory barrier request is used by the receiving device to determine that one or more data access operations issued before the memory barrier request were sent have been completed. One or more data access operations are associated with the data access request.

[0011] The memory barrier request is transmitted via multicast over all paths between the sending and receiving devices.

[0012] According to one aspect of the embodiments of this application, a data synchronization method is provided, the method comprising being performed by an aggregation switch, the method comprising:

[0013] Receive a memory barrier request sent by a multicast switch. The memory barrier request is used by the receiving device to determine that one or more data access operations issued before the memory barrier request were sent have been completed. The one or more data access operations are associated with the data access request sent by the sending device.

[0014] After successfully aggregating all memory barrier requests transmitted along all paths into a single aggregated memory barrier request, the aggregated memory barrier request is sent to the receiving device.

[0015] According to one aspect of the embodiments of this application, a data synchronization apparatus is provided, the apparatus comprising:

[0016] The receiving module is used to receive data access requests and memory barrier requests sent by the sending device. The memory barrier request is used by the receiving device to determine that one or more data access operations sent before the memory barrier request have been completed. One or more data access operations are associated with the data access request.

[0017] The sending module is used to transmit memory barrier requests via multicast over all paths between the sending and receiving devices.

[0018] According to one aspect of the embodiments of this application, a data synchronization apparatus is provided, the apparatus comprising:

[0019] The receiving module receives memory barrier requests sent by the multicast switch. The memory barrier request is used by the receiving device to determine that one or more data access operations issued before sending the memory barrier request have been completed. The one or more data access operations are associated with the data access request sent by the sending device.

[0020] The sending module is used to send the converged memory barrier request to the receiving device after all memory barrier requests transmitted on all paths have been successfully converged into a single converged memory barrier request.

[0021] According to one aspect of the embodiments of this application, a network device is provided, the network device being deployed with multicast switches and / or aggregation switches, the multicast switches and / or aggregation switches being used to implement the above-described data synchronization method.

[0022] According to one aspect of the embodiments of this application, a computer-readable storage medium is provided, wherein a computer program is stored in the storage medium, the computer program being loaded and executed by a processor to implement the above-described data synchronization method.

[0023] According to one aspect of the embodiments of this application, a computer program product is provided, the computer program product including a computer program, the computer program being loaded and executed by a processor to implement the above-described data synchronization method.

[0024] The technical solutions provided in this application have at least the following beneficial effects:

[0025] The data synchronization system and method based on distributed systems provided in this application can implement memory barrier functionality in switch networks by employing dynamic multicast and reverse aggregation. Based on this, memory barrier requests are dynamically multicasted within the switch network and ultimately aggregated into a single message copy (i.e., an aggregated memory barrier request) to be fed back to the receiving device. This reduces the likelihood of resource consumption during data transmission, optimizes data transmission efficiency, and avoids data redundancy issues.

[0026] Meanwhile, based on dynamic multicast and reverse aggregation, the sending device does not need to add a transaction identifier for each data item, thus eliminating the transmission overhead caused by the identifier and avoiding the possibility of resource occupation during data transmission. It also allows the receiving device to completely bypass the execution flow of memory barriers, without needing to be aware of synchronization logic or maintain a local state cache or identifier queue. Furthermore, based on the technical solution of this application, the end-to-end consistency guarantee logic is fully offloaded to the network layer, allowing the end-side to eliminate the need for dedicated synchronization circuits. The network layer autonomously implements cross-domain barriers, and the receiving end only needs to respond to the final data submitted by the network layer, which also optimizes hardware resources to a certain extent. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of a distributed system provided in one embodiment of this application;

[0028] Figure 2 This is a schematic diagram illustrating message passing and inter-directory collaboration provided in one embodiment of this application;

[0029] Figure 3 This is a structural block diagram of a data synchronization system provided in one embodiment of this application;

[0030] Figure 4 This is a flowchart of a data synchronization system provided in one embodiment of this application;

[0031] Figure 5 This is a flowchart of a data synchronization system provided in one embodiment of this application;

[0032] Figure 6 This is a schematic diagram of a data synchronization system provided in one embodiment of this application;

[0033] Figure 7 This is a schematic diagram of a data synchronization system provided in one embodiment of this application;

[0034] Figure 8 This is a schematic diagram of a data synchronization system provided in one embodiment of this application;

[0035] Figure 9 This is a flowchart of a data synchronization method provided in one embodiment of this application;

[0036] Figure 10 This is a flowchart of a data synchronization method provided in one embodiment of this application;

[0037] Figure 11 This is a flowchart of a data synchronization method provided in one embodiment of this application;

[0038] Figure 12 This is a flowchart of a data synchronization method provided in one embodiment of this application;

[0039] Figure 13 This is a flowchart of a data synchronization method provided in one embodiment of this application;

[0040] Figure 14 This is a structural block diagram of a data synchronization device provided in one embodiment of this application;

[0041] Figure 15 This is a structural block diagram of a data synchronization device provided in one embodiment of this application;

[0042] Figure 16 This is a structural block diagram of a computer device provided in one embodiment of this application. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0044] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0045] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0046] It should be understood that although the terms first, second, etc., may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, a first parameter may also be referred to as a second parameter, and similarly, a second parameter may also be referred to as a first parameter. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0047] It should be noted that this application may display prompt interfaces, pop-ups, or output voice prompts before and during the collection of user data. These prompt interfaces, pop-ups, or voice prompts are used to inform the user that their data is being collected. This ensures that the application only begins the steps for collecting user data after receiving confirmation from the user regarding the prompt interface or pop-up; otherwise (i.e., without user confirmation), the steps for collecting user data end, meaning no user data is collected. In other words, all user data collected in this application is collected with the user's consent and authorization, and the collection, use, and processing of related user data must comply with the relevant laws, regulations, and standards of the relevant countries and regions.

[0048] First, let me introduce the relevant terms used in this application:

[0049] Release Consistency Model:

[0050] For memory access requests between different threads, the Graphics Processing Unit Core (GPU Core) typically follows a release consistency model. This model is a weaker memory consistency model that allows out-of-order read and write operations on different addresses, provided that specific synchronization operations, such as acquire and release, are satisfied, thereby improving the efficiency of parallel execution.

[0051] The Acquire-Release model includes the following key concepts:

[0052] Release semantics: Applicable to memory operations related to storage, memory fences, and atomic operations, ensuring that all memory writes by the same thread preceding the release operation are completed before the release operation. Therefore, memory accesses prior to a release operation cannot be reordered after the release operation.

[0053] Acquire semantics: Applies to memory operations related to load, fence, and atomic operations, ensuring that all memory reads after the acquire operation are executed only after the acquire operation is complete. Therefore, memory accesses after an acquire operation cannot be reordered to occur before the acquire operation.

[0054] Relaxed semantics: It is neither the ordinary semantics of release nor acquire, and is applicable to memory operations related to load, store, and atomic.

[0055] Acquire-Release synchronization: When a thread's acquire semantic memory operation observes a value written by another thread's release semantic memory operation, a synchronization relationship is established between the two memory operations (synchronize-with).

[0056] Synchronize-With provides a memory visibility guarantee: all memory writes made before a Release operation become visible after another thread performs the corresponding acquire operation.

[0057] Coherence Root: The processor has a complex memory subsystem design that caches local or remote data. But no matter how many layers the memory subsystem has or how the coherence protocol is designed, for any address, there must exist a hardware layer where, when a thread's write request to that address reaches this layer, it is visible to other threads within the scope. This layer is called the coherence root of that address.

[0058] This means that without explicit synchronization, the visible order of memory write and read operations by different threads is uncertain. If two threads need to communicate, they need to be synchronized using Acquire-Release.

[0059] Memory barrier:

[0060] A memory barrier in a graphics processing unit (GPU) is a synchronization primitive whose core function is to ensure the following:

[0061] Visibility of execution order: All data access operations (read / write) issued before the memory barrier must be completed and globally visible before the operations after the memory barrier begin execution;

[0062] Data consistency guarantee: This ensures that operations following a memory barrier can correctly read the final modifications made to the memory data by operations preceding the barrier.

[0063] Consistency Ordered at Directory (CORD):

[0064] CORD is a protocol for maintaining causal order in distributed systems. Its core idea is to reduce the directory overhead of message propagation through a logical hierarchical structure while ensuring causal consistency in message exchange. CORD achieves causal ordering guarantees for memory operations through a lightweight distributed counter mechanism and state comparison. Its core process can be summarized as follows:

[0065] The sender assigns an incrementing, unique logical identifier, such as a generation identifier (ID), to each memory transaction to mark the global order of the transactions;

[0066] The directory maintains a receiving queue and dynamically sorts out-of-order transactions according to their identifiers, such as First In, First Out, FIFO order, recording only the identifiers rather than the complete data.

[0067] When the receiving end executes the memory barrier instruction, it compares the highest locally processed identifier with the target identifier specified by the memory barrier. Only when all transactions less than or equal to the target identifier have been completed will the post-memory barrier operation be allowed to execute.

[0068] Please refer to Figure 1 This illustration shows a schematic diagram of a distributed system provided in one embodiment of this application. The distributed system may include: a server device 10, a client device 20, and multiple distributed nodes 30.

[0069] Server device 10 is an electronic device with data computing, processing, and storage functions. In some embodiments, server device 10 may be a terminal device or a server. In some embodiments, a plurality of distributed nodes 30 include server device 10. For example, one or more of the plurality of distributed nodes 30 serve as server device 10. Alternatively, one or more of the plurality of distributed nodes 30 may have the functions of server device 10. Server device 10 is used to receive and respond to data access requests sent by client device 20. The data access request is used to request access to data stored in the plurality of distributed nodes 30.

[0070] Client device 20 is an electronic device with data computing, processing, and storage functions. In some embodiments, client device 20 may be a terminal device or a server. Client device 20 has the need to access data stored in multiple distributed nodes 30.

[0071] Distributed node 30 is an electronic device with data computing, processing, and storage functions. In some embodiments, distributed node 30 can be a terminal device or a server. Each distributed node 30 has independent computing, storage, and communication capabilities, and multiple distributed nodes 30 complete distributed tasks in a collaborative manner.

[0072] In some embodiments, the aforementioned terminal devices may include, but are not limited to, at least one of the following: mobile phones, computers, cloud technology platforms, intelligent robots, intelligent transportation terminal systems, driving control systems, intelligent voice interaction devices, smart home appliances, vehicle terminals, aircraft, game consoles, wearable devices, multimedia playback devices, augmented reality devices, virtual reality devices, and other electronic devices. Other terminal devices may also be included, but this application embodiment does not limit them.

[0073] In some embodiments, the server mentioned above may be an independent physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDN), and big data and artificial intelligence platforms, but is not limited to these.

[0074] The server device 10, client device 20, and multiple distributed nodes 30 can communicate with each other via a network. This network can be a wired network or a wireless network.

[0075] Distributed systems involve message passing and inter-directory collaboration. Figure 2The differences in key metrics such as the number of control messages, latency type, and topology latency under different messaging modes are illustrated, including:

[0076] Source Ordering:

[0077] • Number of control messages: Marked as m+1ctrl msgs, indicating that the total number of control messages in this mode is m+1.

[0078] • Delay type: Includes 2-hop stall and 3-hop delay, reflecting the delay levels caused by the topology during message transmission.

[0079] • Topology: Involves the source node (P0), multiple directory nodes (Dir0...n-2), and the target directory node (Dirn-1), showing the multi-hop transmission path of messages from the source node to the target node.

[0080] Inter-Directory Notification:

[0081] • Number of control messages: Marked as 2n-1ctrl msgs, indicating that the total number of control messages in this mode is 2n-1.

[0082] • Delay types: Includes 0-hop stall and 2-hop delay, reflecting the optimization of delay during message passing (e.g., 0-hop stall means no extra hop delay).

[0083] • Topology: It also contains P0, Dir0...n-2, Dirn-1, but the message passing logic is different from the left side, resulting in changes in the number of control messages and the delay type.

[0084] In existing technologies, CORD technology reduces the directory overhead of message propagation through a logical hierarchy while ensuring causal consistency of message exchange, but it also presents the following challenges:

[0085] The overhead of logical identifier headers: Each transaction request needs to carry an incrementing logical identifier. When the transmitted data payload is small (such as a 16-byte micro-transaction), the space occupied by this identifier in the packet header increases significantly (e.g., a 32-bit ID occupies 25% of the packet header), leading to a decrease in effective bandwidth utilization.

[0086] The complexity of maintaining the receiver's state: The target side needs to maintain a dedicated receive queue for each GPU node in order to dynamically manage out-of-order transactions;

[0087] Blocking latency of memory barriers: If a transaction fails to complete its preceding ID (lower generation) due to out-of-order processing or packet loss, the memory barrier operation will forcibly block subsequent operations until all lower ID transactions are completed (depending on queue reordering and status polling), thereby significantly increasing the local computing resource consumption.

[0088] To address the aforementioned issues, this application proposes a data synchronization system and method based on a distributed system. By employing dynamic multicast and reverse aggregation, a memory barrier function on the GPU is implemented in a switch network, thereby reducing the possibility of resource consumption, optimizing data transmission efficiency, and avoiding data redundancy.

[0089] Indicative, for reference Figure 3 The following is a block diagram of the data synchronization system:

[0090] The data synchronization system 300 includes a sending device 310, a switch network 320, and a receiving device 330, with the sending device 310 and the receiving device 330 connected via the switch network 320. The sending device 310 can be implemented as follows: Figure 1 The server device 10 shown is used to send data access requests and memory barrier requests; the receiver device 330 can be implemented as... Figure 1 The client device 20 shown is used to determine that one or more data access operations initiated by the sending device before sending the memory barrier request have been completed; the switch network 320 can be implemented as Figure 1 At least two distributed nodes 30 are shown.

[0091] In some embodiments, the switch network 320 includes at least a multicast switch 321 and a convergence switch 322. The multicast switch 321 implements dynamic multicast of memory barrier requests, enabling the transmission of the memory barrier request across all paths from the sending device 310 to the receiving device 330. The convergence switch 322 implements reverse aggregation of memory barrier requests, aggregating multiple received memory barrier requests into a single message copy (hereinafter referred to as the aggregated memory barrier request) after data transmission is completed and feeding it back to the receiving device, thereby reducing resource consumption and overhead and optimizing data transmission efficiency. Optionally, based on the different data transmission paths between the sending device 310 and the receiving device 330, the switch network 320 may contain at least one multicast switch 321 and at least one convergence switch 322. The at least one multicast switch 321 implements dynamic multicast of memory barrier requests across multiple path nodes, and the at least one convergence switch 322 implements reverse aggregation of memory barrier requests and feeds back the aggregated message copy to the receiving device.

[0092] At least one aggregation switch 322 can be implemented in several ways. In some embodiments, there are two or more aggregation switches 322 (equivalent to multi-level switches). Each aggregation switch 322 performs a corresponding partial aggregation operation, reverse-aggregating the received memory barrier requests and sending a copy of the aggregated message to the next level. This continues until all message copies are passed to the last aggregation switch 322 (i.e., the last level), where it performs the final reverse aggregation and feeds back the aggregated message copy to the receiving device. In other embodiments, there is only one aggregation switch 322. The switch network includes at least one multicast switch 321 and one aggregation switch 322. The aggregation switch 322 is implemented as the last node or a node near the end of the reachable path between the sending device and the receiving device. This single aggregation switch 322 performs the reverse aggregation of the memory barrier requests and feeds back a copy of the aggregated message to the receiving device. The following embodiments only illustrate the existence of one aggregation switch 322. Embodiments with two or more aggregation switches 322 are similar and will not be described in detail.

[0093] It should be noted that, based on the dynamic changes of the switch network 320, the switches included in this network can optionally implement different functions at different time points. Taking the switch network 320 including switch 1, switch 2, switch 3, and switch 4 as an example, at the first moment, switches 1, 2, and 3 are implemented as multicast switches 321, and switch 4 is implemented as an aggregation switch 322. At this time, memory barrier request 1 is multicast via switches 1, 2, and 3, and is finally sent to switch 4. After receiving all memory barrier requests 1, switch 4 aggregates them into a single aggregated memory barrier request 1 and sends it to the receiving device. At the second moment, due to the change in network link status, the data transmission path between the sending device 310 and the receiving device 330 changes. At this time, switches 1 and 2 are implemented as multicast switches 321, and switch 3 is implemented as an aggregation switch 322. At this time, memory barrier request 1 is multicast via switches 1 and 2, and is finally sent to switch 3. After receiving all memory barrier requests 2, switch 3 aggregates them into a single aggregated memory barrier request 2 and sends it to the receiving device. It is evident that switch 3 can perform different functions at different times. Based on the real-time dynamic changes of the network, it can perform the function of a multicast switch at the first moment and the function of an aggregation switch at the second moment.

[0094] Referring to the above examples, it can be considered that the data synchronization system 300 provided in this application can autonomously implement the memory barrier function between the sending device 310 and the receiving device 330 in the switch network 320. The receiving device 300 does not need to perform related operations of the memory barrier function, which is equivalent to achieving hardware optimization to a certain extent. At the same time, based on the real-time changes of the switch network 320, the transmission path of the memory barrier request associated with the memory barrier function can also be adjusted in real time, which can improve data transmission efficiency to a certain extent, so that the memory barrier function can be completed in the shortest time at the current moment, thereby reducing the risk of network congestion or delay.

[0095] Referring to the foregoing content, Figure 4 The information exchange in a data synchronization system is described, including the following steps:

[0096] Step 401: The sending device sends a data access request and a memory barrier request to the switch network;

[0097] The data access request is used to implement data access operations between the sending device and the receiving device, and is sent to the receiving device via a switch network. For example, the sending device sends a data access request for data writing to the receiving device via the switch network. After receiving the data access request, the receiving device performs the corresponding data access operation, i.e., the data writing operation. Optionally, this application does not limit the number or transmission method of data access requests; there can be one or more data access requests, and the transmission method is sufficient to ensure successful transmission to the receiving device.

[0098] Schematic illustration: A memory barrier request is used to implement the memory barrier function. Similar to a data access request, the memory barrier request is also sent to the receiving device via the switch network. The number of memory barrier requests should be one, and its transmission method will be limited in this application, as described in detail below. After receiving the message related to the memory barrier request (i.e., the aggregated memory barrier request below, which will be omitted here), the receiving device confirms that one or more data access operations associated with the data access request sent by the sending device have been completed, thereby implementing the memory barrier function.

[0099] In some embodiments, data access requests are sent before memory barrier requests; that is, the sending device first sends one or more data access requests, and then sends the memory barrier request, so that the receiving device gradually receives multiple requests. In other embodiments, the memory barrier request may be carried in the last data access request sent. Taking the sending device needing to send n data access requests as an example, the sending device sends the first n-1 data access requests sequentially or simultaneously, and then carries the memory barrier request in the last data access request. It should be noted that both of the above request sending methods are within the scope of protection of this application, and will not be described in detail below.

[0100] Optionally, the memory barrier request carries a Path Tracker Identifier (PTI). In some embodiments, the PTI can be implemented as one of the following: In-band Network Telemetry (INT), used to record the identifiers or addresses of network nodes (such as switches or routers) through which the data packet passes; In-situ Flow Information Telemetry v2 (IFAv2), used to assign a unique identifier to a specified data flow; In-situ Flow Information Telemetry (IFIT), which can use a uniform flow identifier format to ensure cross-device compatibility; or a Customer Specific Integrated Circuit (CSIG), used to support custom path identifier formats, such as private fields or encrypted identifiers. In the embodiments of this application, the PTI can be used to trace the transmission path of the memory barrier request in the switch network; and to identify the source and destination of the memory barrier request, thereby ensuring data integrity. To illustrate, a memory barrier request is uniquely associated with a PTI, and one PTI is used to uniquely identify one memory barrier request. At the same time, when transmitting memory barrier requests, the switch network can use the PTI to determine the number of requests that have arrived, thereby confirming the time node for subsequent processing operations for the memory barrier request (i.e., the reverse aggregation in step 403, which will be omitted here).

[0101] Step 402: The switch network transmits the memory barrier request via multicast over all paths between the sending and receiving devices;

[0102] Upon receiving a memory barrier request from a sending device, the switch network will transmit it in real time across all paths between the sending and receiving devices, based on network conditions. In some embodiments, this step can be implemented by a multicast switch, which may optionally include a dynamic barrier conversion module to identify memory barrier unicast messages from sending devices (such as GPUs) and convert them into multicast messages carrying PTIs (i.e., memory barrier requests). These multicast messages are then transmitted via a multipath network topology to cover all reachable paths between the sending and receiving devices.

[0103] Schematic illustration: The transmission of a memory barrier request across all reachable paths is implemented as a multicast method. Multicast is a computer network group communication technology that enables the concurrent transmission of information (which can be implemented as a memory barrier request in this application) from a single source node to a group of destination nodes. In some embodiments, the multicast of the memory barrier request can be implemented through application-layer multicast or natively supported at the network layer (Layer 3, L3) by network devices (such as routers, switches, base station subsystems, etc.). This embodiment uses a switch network to implement multicast of the memory barrier request as an example; other multicast methods described above can also be alternative implementations of this embodiment, and this application does not limit them. Network-layer multicast allows the source node to perform a single transmission; when the data reaches branch nodes containing group members, these branch nodes are responsible for copying and forwarding it to other local members.

[0104] In some embodiments, the present application implements dynamic multicast based on next-hop routing. Unlike traditional static multicast technology (which relies on fixed multicast group addresses that identify all predefined receiving members), the core of dynamic multicast lies in transmitting data based on real-time routing status.

[0105] Taking dynamic multicast implemented through at least one multicast switch as an example, each multicast switch first identifies the equivalent next hop at the current moment. For example, it dynamically generates a set of equivalent next-hop nodes including at least one equivalent next hop based on the current network topology, and each next-hop node corresponds to a real-time transmission path. Optionally, the source node or each hop node of the multicast switch dynamically determines the set of all next-hop nodes leading to the final destination (usually a specific target device, which can be implemented as a receiving device in this embodiment) based on the current routing table status.

[0106] Subsequently, at least one of the multicast switches sends a memory barrier request to the equivalent next hop at the current moment. It should be noted that the aforementioned determined equivalent next hop set is not a fixed multicast group, but a temporary multicast group dynamically generated based on the network topology. Optionally, this equivalent next hop node set changes in real time based on link status and / or load balancing strategies, such as real-time changes resulting from changes in link status and / or adjustments to load balancing strategies.

[0107] Referring to the foregoing, the real-time multicast approach enables the transmission of memory barrier requests between the sending and receiving devices to cover all reachable paths, thereby ensuring that data packets (i.e., memory barrier requests) are effectively distributed to all potential paths currently leading to the final destination (i.e., the receiving device).

[0108] Step 403: The switch network successfully aggregates all memory barrier requests transmitted on all paths into a single aggregated memory barrier request;

[0109] Step 404: The switch network sends a convergence memory barrier request to the receiving device;

[0110] In this context, the aggregated memory barrier request can be considered a copy of the memory barrier request message. In some embodiments, when the first switch in the switch network receives a memory barrier unicast message, it converts it into a memory barrier multicast message carrying a PTI and performs real-time multicast; the last switch, after receiving the memory barrier multicast messages transmitted on all paths, performs reverse aggregation, converts the memory barrier multicast messages into the original memory barrier unicast messages (i.e., aggregated memory barrier requests), and forwards them.

[0111] It should be noted that the memory barrier request can be a memory barrier unicast message. The conversion from unicast message to multicast message can be implemented by the sending device or by the switch in the switch network. Alternatively, the memory barrier request can be a converted memory barrier multicast message. The conversion from unicast message to multicast message can only be implemented by the sending device. This application does not limit the specific content of the memory barrier request, and both of the above implementation methods are acceptable.

[0112] Based on the aforementioned steps, after the memory barrier request has been transmitted on all reachable paths, the switch network can perform reverse aggregation on all memory barrier requests. Taking steps 403 and 404 as implemented by the aggregation switch as an example, a path counter module and an aggregation decision module can be optionally configured in the aggregation switch. The path counter module is used to count the number of arrivals based on the PTI carried in the memory barrier request, and the aggregation decision module is used to compare the number of arrivals with the total number of paths on all reachable paths and perform reverse aggregation and forwarding of the memory barrier request if preset conditions are met.

[0113] For example, this application employs a multicast-based reverse aggregation method to achieve convergence and data reduction. Specifically, when a data packet (i.e., a memory barrier request) traverses all reachable paths to the final destination (i.e., the receiving device) via dynamic multicast, meaning the memory barrier request has reached the end or near the end of multiple paths, these memory barrier requests distributed across different paths can be identified by the network as objects requiring aggregation. Subsequently, the node performs a reverse aggregation operation, aggregating these memory barrier requests with the same content that have arrived via different paths into a single logical data unit (i.e., a converged memory barrier request), and ultimately transmitting only one valid copy of the message to the final destination device (i.e., the receiving device). Based on this, redundant copies that may arise during distributed multicast transmission can be eliminated, ensuring that the receiving device receives only one and only one converged memory barrier request, even if the memory barrier request has traversed multiple possible paths.

[0114] Furthermore, the nodes at the end or near the end of multiple paths can be considered as the aggregation switch mentioned in the embodiments of this application. That is, in some embodiments, the aggregation switch is deployed in the receiving device (i.e., at the end of multiple paths), and the memory barrier request is reverse aggregated in the receiving device; or the aggregation switch is deployed in the preceding device of the receiving device (i.e., a node near the end of multiple paths), and the aggregation memory barrier request is sent from the preceding device to the receiving device, and the memory barrier request is reverse aggregated in the preceding device.

[0115] Referring to the foregoing, the aggregation adjudication module performs reverse aggregation and forwarding of memory barrier requests under preset conditions, such as the arrival number of memory barrier requests reaching the total number of paths. In this case, the aggregation switch can also perform other operations through the aggregation adjudication module. Optionally, the aggregation switch can also cache memory barrier requests when the arrival number has not reached the total number of paths. If the arrival number is less than the total number of paths, it can be considered that the memory barrier request has not been transmitted on all reachable paths of the sending and receiving devices. At this time, the aggregation switch can block packets (i.e., cache memory barrier requests) and wait for all memory barrier requests on all reachable paths to be transmitted before performing reverse aggregation.

[0116] Step 405: After receiving the converged memory barrier request, the receiving device determines that one or more data access operations issued by the sending device before sending the memory barrier request have been completed, and one or more data access operations are associated with the data access request.

[0117] Based on the aforementioned steps, the receiving device receives only one converged memory barrier request. Subsequently, the receiving device can implement the memory barrier function based on the converged memory barrier request, confirming that one or more data access operations issued by the sending device before sending the memory barrier request have been completed. It can be understood that, based on the aforementioned steps, the receiving device only needs to perform a confirmation operation; no other related operations for the memory barrier function are required, as these can all be implemented at the switch network layer.

[0118] In summary, the data synchronization system and method based on distributed systems provided in this application can implement memory barrier functionality in switch networks by employing dynamic multicast and reverse aggregation. Based on this, memory barrier requests are dynamically multicasted within the switch network and ultimately aggregated into a single message copy (i.e., an aggregated memory barrier request) to be fed back to the receiving device. This reduces the likelihood of resource consumption during data transmission, optimizes data transmission efficiency, and avoids data redundancy issues.

[0119] Meanwhile, based on dynamic multicast and reverse aggregation, the sending device does not need to add a transaction identifier for each data item, thus eliminating the transmission overhead caused by the identifier and avoiding the possibility of resource occupation during data transmission. It also allows the receiving device to completely bypass the execution flow of memory barriers, without needing to be aware of synchronization logic or maintain a local state cache or identifier queue. Furthermore, based on the technical solution of this application, the end-to-end consistency guarantee logic is fully offloaded to the network layer, allowing the end-side to eliminate the need for dedicated synchronization circuits. The network layer autonomously implements cross-domain barriers, and the receiving end only needs to respond to the final data submitted by the network layer, which also optimizes hardware resources to a certain extent.

[0120] In some embodiments, the switch network includes at least two switches for transmitting data access requests and memory barrier requests. (Illustrative reference) Figure 3 The switch network includes at least one multicast switch connected to the sending device and an aggregation switch connected to the receiving device. Figure 5 A flowchart of a data synchronization system provided in an embodiment of this application is shown. Step 402 can be implemented as steps 4021 and 4022, and step 403 can be implemented as steps 4031 and 4032, as detailed below:

[0121] Step 4021: The multicast switch sends the memory barrier request in a multicast manner to the next-hop node of each of the multiple equal-cost paths. Each path is a reachable path between the sending device and the receiving device, and the total number of nodes in the multiple equal-cost paths is the same.

[0122] Step 4022: The multicast switch sends a memory barrier request to the aggregation switch.

[0123] The descriptions of multicast switches, memory barrier requests, and multicast methods can be found in the foregoing content and will not be repeated here; multiple equivalent paths can be considered as all reachable paths between the sending device and the receiving device in the foregoing example.

[0124] Figure 6 and Figure 7 Schematic diagrams of a data synchronization system provided in one embodiment of this application are shown respectively, wherein, Figure 6 The transmission path of the data access request is shown. Figure 7 The transmission path of the memory barrier request is shown below:

[0125] refer to Figure 6 The sending device sends one or more data access requests to switch 1, which are then sent by switch 1 to the receiving device via switches 21, 22, 23, and 3.

[0126] refer to Figure 7 The sending device sends a memory barrier request to switch 1. Switch 1 then performs path traversal via switches 21, 22, and 23 to transmit the memory barrier request to switch 3 via multicast. Switch 3 generates a converged memory barrier request through the aforementioned reverse aggregation method and sends it to the receiving device.

[0127] Among them, switch 1, switch 21, switch 22 and switch 23 can all be considered as the aforementioned multicast switches, used to implement real-time multicast of memory barrier requests, and switch 3 can be considered as the aforementioned aggregation switch, used to receive and reverse aggregate memory barrier requests and send the aggregated memory barrier requests to the receiving device.

[0128] Based on the foregoing, the transmission of memory barrier requests across multiple equivalent paths is implemented using multicast. In this embodiment, the multicast of memory barrier requests via a multicast switch is used as an example. To achieve real-time multicast of memory barrier requests, the multicast switch also needs to determine the next-hop node in real time.

[0129] In some embodiments, the multicast switch is also used to dynamically generate an equivalent next-hop node set based on the current network topology, where the next-hop node is a node in the equivalent next-hop node set. The equivalent next-hop node set changes in real time based on link status and / or load balancing strategies.

[0130] This application embodiment can be understood as implementing dynamic multicast based on next-hop routing, primarily relying on real-time routing status for data transmission. Specifically, the multicast switch first identifies the equivalent next hop at the current moment, that is, dynamically generates an equivalent next-hop node set including at least one equivalent next hop based on the current network topology. For example, the next-hop node set is dynamically determined based on the current routing table status. Subsequently, the multicast switch sends a memory barrier request to the equivalent next hop at the current moment.

[0131] The equivalent next-hop set is not a fixed multicast group, but a temporary multicast group dynamically generated based on the network topology. In some embodiments, real-time changes caused by link state changes and / or load balancing strategy adjustments will cause the current equivalent next-hop set to change in real time.

[0132] According to step 4021, the embodiments of this application may also optionally include the filtering of equivalent paths.

[0133] In some embodiments, the total number of nodes in multiple equivalent paths is the same, which can be understood as the total number of switches transmitting the memory barrier request; in other embodiments, the multiple equivalent paths should also be the path with the smallest total number of nodes among all reachable paths, thereby enabling fast transmission of the memory barrier request and improving data transmission efficiency.

[0134] refer to Figure 8 The given diagram shows that there are multiple ways to implement the reachable path between the sending device and the receiving device, which may include: switch 1, switch 21, switch 4; switch 1, switch 22, switch 4; switch 1, switch 23, switch 4; switch 1, switch 23, switch 31, switch 4; switch 1, switch 23, switch 32, switch 4; switch 1, switch 23, switch 33, switch 4.

[0135] The first three reachable paths each have 3 nodes, while the last three reachable paths each have 4 nodes. Based on the foregoing, in some embodiments, the first three reachable paths can be identified as equivalent paths, while the last three reachable paths can be identified as non-equivalent paths.

[0136] Referring to the foregoing, the multicast of the memory barrier request is implemented through at least one multicast switch. Taking the existence of N multicast switches as an example, the first N-1 multicast switches execute step 4021, and the last multicast switch executes step 4022, thereby realizing real-time multicast. Steps 4021 and 4022 are executed sequentially.

[0137] Step 4031: The aggregation switch counts the number of arriving memory barrier requests based on the received requests;

[0138] Step 4032: When the number of arrivals reaches the total number of paths with multiple equivalent paths, the aggregation switch merges the received memory barrier requests into an aggregation memory barrier request.

[0139] The descriptions of aggregation switches, memory barrier requests, equivalence paths, and aggregation memory barrier requests can be found in the preceding content and will not be repeated here.

[0140] In some embodiments, according to step 4021, the sending device or the first multicast switch converts the memory barrier unicast message into a memory barrier multicast message carrying a PTI (i.e., a memory barrier request), which is then multicast in real time by at least one multicast switch; subsequently, according to step 4032, the aggregation switch converts the memory barrier multicast message into the original memory barrier unicast message (i.e., an aggregation memory barrier request) and forwards it to the receiving device.

[0141] When the memory barrier request carries a PTI, step 4031 can be implemented as follows: receiving the memory barrier request sent by the multicast switch, and counting the arrival count based on the PTI carried in the memory barrier request. The arrival count can be understood as the number of memory barrier requests transmitted on multiple equivalent paths that arrive at the aggregation switch. Illustratively, the aggregation switch can also implement path counting and status detection functions, optionally using a path counter to count the arrival count of memory barrier requests carrying the same PTI.

[0142] In some embodiments, according to step 4032, the aggregation switch may optionally implement a continuous comparison function through an aggregation decision module, continuously comparing the real-time count of arrivals with the total number of paths of multiple equivalent paths; subsequently, when the real-time count reaches the total number of paths, it is equivalent to the aggregation switch detecting that all memory barrier requests in the entire network have arrived, at which point reverse aggregation can be performed, i.e., the aforementioned conversion of multicast packets to unicast packets. Optionally, when the real-time count reaches the total number of paths, a termination barrier packet can also be placed at the end of the queue as an atomic signal indicating the completion of global synchronization, and the receiving device confirms the end of the memory barrier upon receiving the termination barrier packet.

[0143] Referring to step 4032, in some embodiments, the aggregation switch is also used to cache memory barrier requests when the number of arrivals has not reached the total number of paths. This can be understood as follows: if the real-time count of arrivals has not reached the total number of paths for multiple equivalent paths, it is equivalent to at least one memory barrier request still being transmitted (indicating that path coverage across the entire network has not been completed). In this case, the packet needs to be blocked, and reverse aggregation and data forwarding should not be performed.

[0144] Taking the aggregation switch's use of a path counter to count arrivals as an example, the aggregation switch receives multicast packets carrying a PTI (Path Count Indicator) from a multicast switch, and the path count value is used to count the arrivals. This count can be determined based on the sent and received multicast packets. Since the multicast switch knows the number of distributed multicast packets, it can include the path counter in the multicast packets. Subsequently, the aggregation switch performs arrival count determination and reverse aggregation. If the arrival count (i.e., the path counter value) is less than the total number of paths, the multicast packet terminates locally and is no longer forwarded, while the path counter is incremented, awaiting the arrival of subsequent multicast packets. If the arrival count (i.e., the path counter value) equals the total number of paths, the multicast packet is inserted to the end of the queue, and the counter resource carried on the multicast packet is destroyed. Optionally, this may include a step of converting the multicast packet to a unicast packet; see the preceding content for details. Finally, the aggregation switch releases the multicast packets in the queue to the receiving devices in sequence.

[0145] Referring to the foregoing, the aggregation switch is the last node or receiving device in the equivalent path. It can also be understood that the aggregation switch may be located in the logical entity of the receiving device, or it may be located in the logical entity of the preceding device (i.e., the last node in the equivalent path) of the receiving device, and the aggregation memory barrier request is sent from the preceding device to the receiving device. In the first optional implementation, the memory barrier request is reverse-aggregated in the receiving device; in the second optional implementation, the memory barrier request is reverse-aggregated in the preceding device. It should be noted that for a physical switch, in the downlink path from the sending device to the receiving device, the physical switch can act as an aggregation switch; and in the uplink path from the receiving device to the sending device, the physical switch can also act as a multicast switch. That is, a physical switch may simultaneously implement the functions of a multicast switch and an aggregation switch, depending on the transmission direction of the currently processed packets; multicast switches and aggregation switches are implemented as logical entities in some embodiments, not necessarily physical entities. This application does not specifically limit this, as long as they can implement the corresponding real-time multicast and / or reverse aggregation functions.

[0146] In summary, the dynamic multicast and reverse aggregation method provided in this application can also be understood as effectively ensuring the synchronization of data operation order and state at the network layer. Specifically, dynamically generating an equivalent next-hop node set based on the current network topology allows traversal of all currently reachable paths, similar to the "before" operation of a barrier covering all necessary execution units, thus achieving dynamic path coverage. Subsequently, combined with multicast-based reverse aggregation, redundancy is eliminated, similar to the "after" operation of a barrier waiting for all "before" operations to complete and confirm the final state, thus achieving reverse aggregation and state confirmation. Based on this, through the above "distribution-traversal-aggregation-confirmation" process, it can ultimately ensure that the data state received by the receiving device reflects the operation results on all reachable paths, ultimately achieving a strong consistency effect similar to a memory barrier.

[0147] On the other hand, this application also provides a data synchronization method, which is performed by a multicast switch. Figure 9 A flowchart of a data synchronization method provided in one embodiment of this application is shown. The method includes the following steps:

[0148] Step 920: Receive a data access request and a memory barrier request from the sending device. The memory barrier request is used by the receiving device to determine that one or more data access operations issued before sending the memory barrier request have been completed. One or more data access operations are associated with the data access request.

[0149] The descriptions of data access requests and memory barrier requests are as described above and will not be repeated here.

[0150] In some embodiments, the memory barrier request carries a PTI. The relevant description of the PTI is as described above and will not be repeated here.

[0151] Step 940: Transmit the memory barrier request via multicast over all paths between the sending and receiving devices.

[0152] The description of multicast mode can be found in the foregoing content and will not be repeated here.

[0153] refer to Figure 9 , Figure 10 A flowchart of a data synchronization method provided in an embodiment of this application is shown. Step 940 can be implemented as step 941. The method also includes step 930, as follows:

[0154] Step 930: Dynamically generate an equivalent next-hop node set based on the current network topology. The next-hop node is a node in the equivalent next-hop node set.

[0155] The description of the equivalent next-hop set can be found in the foregoing content and will not be repeated here. In some embodiments, the equivalent next-hop node set changes in real time according to link status and / or load balancing strategy.

[0156] Step 941: Send a memory barrier request to the next-hop node of each of the multiple equivalent paths, where each path is a reachable path between the sending device and the receiving device, and the total number of nodes in the multiple equivalent paths is the same.

[0157] The descriptions of equivalent paths and next-hop nodes can be found in the preceding content and will not be repeated here.

[0158] On the other hand, this application also provides a data synchronization method, which is performed by an aggregation switch. Figure 11 A flowchart of a data synchronization method provided in one embodiment of this application is shown. The method includes the following steps:

[0159] Step 1120: Receive a memory barrier request sent by the multicast switch. The memory barrier request is used by the receiving device to determine that one or more data access operations issued before sending the memory barrier request have been completed. The one or more data access operations are associated with the data access request sent by the sending device.

[0160] The descriptions of data access requests and memory barrier requests are as described above and will not be repeated here.

[0161] In some embodiments, the memory barrier request carries a PTI. The relevant description of the PTI is as described above and will not be repeated here.

[0162] Step 1140: After successfully aggregating all memory barrier requests transmitted on all paths into a single aggregated memory barrier request, send the aggregated memory barrier request to the receiving device.

[0163] The descriptions of pooling memory barrier requests and reverse pooling are as described above and will not be repeated here.

[0164] refer to Figure 11 , Figure 12 A flowchart of a data synchronization method according to an embodiment of this application is shown. Step 1140 can be implemented as steps 1141, 1142, and 1143. The method also includes step 1150, as follows:

[0165] Step 1141: Count the number of arriving memory barrier requests based on the received requests;

[0166] Step 1142: When the number of arrivals reaches the total number of paths of multiple equivalent paths, merge the received memory barrier requests into a converged memory barrier request. Each of the multiple paths is a reachable path between the sending device and the receiving device, and the total number of nodes of the multiple equivalent paths is the same.

[0167] Step 1143: Send the convergence memory barrier request to the receiving device;

[0168] Step 1150: If the number of arrivals has not reached the total number of paths, cache the memory barrier request.

[0169] The descriptions of the number of arrivals and the total number of routes are as described above and will not be repeated here.

[0170] It should be noted that steps 1142 and 1150 must be executed separately, and cannot be executed simultaneously.

[0171] In some embodiments, the aggregation switch is deployed in the receiving device, or the aggregation switch is deployed in the preceding device of the receiving device, and the aggregation memory barrier request is sent by the preceding device to the receiving device.

[0172] Indicative, Figure 13 A flowchart of a data synchronization method provided in one embodiment of this application is shown. The method includes the following steps:

[0173] Step 131: The GPU initiates a barrier request;

[0174] Here, the barrier request can be understood as the aforementioned memory barrier unicast message (one implementation of the memory barrier request).

[0175] Step 132: The multicast switch converts PTI multicast packets;

[0176] The converted multicast message can be understood as the aforementioned multicast message carrying a PTI memory barrier (another implementation of a memory barrier request).

[0177] Step 133: Multi-path full network coverage;

[0178] Among them, multi-path full network coverage can be understood as the real-time multicast of the memory barrier request made by the multicast switch.

[0179] Step 134: The aggregation switch performs path calculation;

[0180] The path calculation process can be understood as the aforementioned statistics on the number of arrivals.

[0181] Step 135: The aggregation switch confirms whether the count value is equal to the preset total;

[0182] If the count value has not reached the preset total, proceed to step 136; if the count value has reached the preset total, proceed to step 137.

[0183] Step 136: If the count value has not reached the preset total number, buffer the message to the queue;

[0184] Step 137: When the count value reaches the preset total, generate a termination unicast message;

[0185] The termination of unicast messages can be understood as the aforementioned convergence memory barrier request.

[0186] Step 138: Release the queue and forward;

[0187] Step 139: The target GPU receives the termination signal.

[0188] The termination signal can be understood as the aforementioned convergence memory barrier request.

[0189] In some embodiments, the data synchronization method is implemented by a data synchronization system, which includes a data source entity, a network processing entity, and a target entity. The data source entity can be understood as the aforementioned sending device, implemented in this embodiment as a GPU, i.e., the terminal device initiating the data write and memory barrier request; the network processing entity can be understood as the aforementioned switch network, including multicast switches and aggregation switches; the target entity can be understood as the aforementioned receiving device, implemented in this embodiment as a target GPU (cluster), which only receives the final processing result and does not participate in the data synchronization logic.

[0190] Optionally, the multicast switch is equipped with a dynamic barrier conversion module to identify memory barrier unicast packets sent by the GPU and convert them into multicast packets carrying PTIs; the aggregation switch is deployed at the access layer of the target GPU and integrates a path counter module (to count the number of arriving PTI multicast packets) and an aggregation decision module (to control packet forwarding based on the counter status).

[0191] In some embodiments, the method provided in this application can also be implemented as the following process:

[0192] 1. Unicast to Multicast Conversion (implemented by Multicast Switch): The dynamic barrier conversion module intercepts memory barrier unicast messages sent by the GPU; embeds a globally unique PTI, and converts it into a multicast message, which is then transmitted via a multipath network topology to cover all reachable paths;

[0193] 2. Path counting and status detection (implemented by aggregation switch): The path counter counts the number of multicast packets carrying the same PTI that arrive;

[0194] 3. Aggregation Decision Module Continuous Comparison (implemented by Aggregation Switch): Compares the real-time count value with the preset total number of paths within the PTI; if the preset total number is not reached, the current multicast packet will not be forwarded;

[0195] 4. Termination signal generation and delivery (implemented by aggregation switch): When it is detected that all PTI multicast packets in the entire network have arrived (i.e., the count value = the preset total number), the aggregation adjudication module converts the multicast packet into the original unicast packet and completes the forwarding; the termination barrier packet is placed at the end of the queue as an atomic signal for the completion of global synchronization.

[0196] In other embodiments, the method provided in this application can also be implemented as follows:

[0197] GPU-side operations:

[0198] After the GPU performs a data write, it triggers a data consistency synchronization request with the remote memory domain by appending a write memory barrier instruction. In existing technologies, the GPU issues a memory barrier operation instruction only once, which is transmitted to the receiving end via the network in the form of a unicast message. The receiving end needs to perform logical verification locally to confirm that all previous write operations have been completed before it can execute the post-barrier instruction.

[0199] When the switch receives a memory barrier unicast message from the GPU, it executes the following process:

[0200] • Message type conversion: The dynamic barrier conversion module in the switch converts the input unicast barrier message into a multicast message;

[0201] • Assign a unique path PTI to the multicast message and embed it in the message header;

[0202] • Multicast distribution and path coverage: Based on the current network topology, multicast routing based on equal-cost next hop ensures that packets traverse all reachable paths to the target GPU; when the aggregation switch receives the multicast packet, it records the number of branches of the covered reachable paths through a path counter.

[0203] • Queue management and atomicity guarantee at the aggregation point: The access switch (i.e., the aggregation point) corresponding to the target GPU maintains the receiving queue;

[0204] • Queue blocking mechanism: If the path counter corresponding to the PTI does not reach the expected value (indicating that the entire network path coverage has not been completed), all memory barrier multicast packets with the PTI will be terminated locally and will no longer be sent to the GPU;

[0205] • Queue release condition: When the counter reaches the expected value, the message is temporarily stored in the sending queue for forwarding.

[0206] • GPU memory barrier recognition complete: The target GPU receives the termination barrier message, which confirms that all previous data packets have been globally delivered.

[0207] Optionally, this application may also provide a memory barrier processing system based on a network switching device, comprising:

[0208] The dynamic barrier conversion module is configured to receive memory barrier unicast messages sent by the GPU and convert them into multicast messages carrying PTI.

[0209] The multicast routing engine dynamically generates an equivalent next-hop node set based on the current network topology and distributes multicast packets to all reachable paths to the target GPU.

[0210] The path counter module is used to count the number of multicast packets corresponding to a PTI in each network branch.

[0211] The queue management unit, located on the access switch of the target GPU, performs the following: when the path count value of PTI does not reach the expected threshold, it buffers multicast packets and waits for further aggregation; when the number of received multicast packets reaches the expected threshold, it completes the task of grouping multicast ID packets, and after aggregation, sends an aggregated barrier packet, which enters the switch forwarding queue in sequence to wait for forwarding.

[0212] Optionally, this application may also provide a memory barrier synchronization method performed by an access switch, comprising:

[0213] Receive PTI multicast messages sent by the source switch;

[0214] If the value of the local path counter is less than the expected total number of paths in the PTI, the message is terminated locally and will not be forwarded. The counter is incremented and the message continues to wait for subsequent PTI multicast messages.

[0215] When the counter value is detected to be equal to the expected total number of paths in the PTI, the PTI multicast message is inserted to the end of the queue, and the counter resource for that PTI ID message is destroyed.

[0216] Release all data packets in the queue to the target GPU in sequence.

[0217] Referring to the foregoing, the target GPU does not need to maintain a local transaction queue or barrier state machine; it only needs to parse the finally arriving termination barrier message as a global delivery completion signal.

[0218] In summary, the system and method provided in the embodiments of this application can achieve at least one of the following:

[0219] 1. Eliminate the overhead of transmitting transaction IDs:

[0220] No logical identifier required: The sender does not need to append a Generational ID to each data request, avoiding the consumption of explicit sorting metadata. Simultaneously, it enables significant optimization for small transactions: due to the reduced header load, effective bandwidth can be increased by 25% when the transaction size is ≤16 bytes; and the overall network throughput can be increased by 6–10% when the transaction size is ≤50 bytes.

[0221] 2. On-demand triggering feature of network state management:

[0222] Side effect isolation mechanism: Transaction state tracing for network maintenance (such as path overwrite and commit confirmation) is activated only when the memory barrier is in effect, with zero additional overhead under normal transmission.

[0223] 3. Offload hardware to network: The GPU executes the process completely outside the memory barrier, without needing to be aware of synchronization logic or maintain a local state cache or ID queue.

[0224] 4. Hardware resource and area optimization:

[0225] Cross-domain barriers are implemented autonomously by the network: the end-to-end consistency guarantee logic is fully offloaded to the network layer, eliminating the need for dedicated synchronization circuits on the GPU side. Furthermore, the edge-side logic is extremely simplified; the receiving end only needs to respond to the final data submitted by the network, eliminating the overhead of barrier state polling and out-of-order transaction reorganization.

[0226] The following are embodiments of the apparatus described in this application, which can be used to execute the embodiments of the method described in this application. For details not disclosed in the apparatus embodiments of this application, please refer to the embodiments of the method described in this application.

[0227] Figure 14 A structural block diagram of a data synchronization device according to an embodiment of this application is shown. This device has the functions described above, which can be implemented in hardware or by hardware executing corresponding software. The device includes:

[0228] The receiving module 1420 is used to receive a data access request and a memory barrier request sent by the sending device. The memory barrier request is used by the receiving device to determine that one or more data access operations sent before the memory barrier request have been completed. The one or more data access operations are associated with the data access request.

[0229] The sending module 1440 is used to transmit the memory barrier request in a multicast manner on all paths between the sending device and the receiving device.

[0230] In some embodiments, the sending module 1440 is configured to send a memory barrier request to the next-hop node of each of a plurality of equivalent paths, each path being a reachable path between a sending device and a receiving device, and the total number of nodes in the plurality of equivalent paths being the same.

[0231] In some embodiments, the sending module 1440 is further configured to dynamically generate an equivalent next-hop node set based on the current network topology, wherein the next-hop node is a node in the equivalent next-hop node set.

[0232] In some embodiments, the equivalent next-hop node set changes in real time based on link status and / or load balancing strategy.

[0233] In some embodiments, the memory barrier request carries a PTI.

[0234] Figure 15 A structural block diagram of a data synchronization device according to an embodiment of this application is shown. This device has the functions described above, which can be implemented in hardware or by hardware executing corresponding software. The device includes:

[0235] The receiving module 1520 is used to receive a memory barrier request sent by a multicast switch. The memory barrier request is used by the receiving device to determine that one or more data access operations issued before sending the memory barrier request have been completed. The one or more data access operations are associated with the data access request sent by the sending device.

[0236] The sending module 1540 is used to send the converged memory barrier request to the receiving device after all memory barrier requests transmitted on all paths have been successfully converged into a single converged memory barrier request.

[0237] In some embodiments, the sending module 1540 is used to count the number of arrivals based on the received memory barrier requests; when the number of arrivals reaches the total number of paths of multiple equivalent paths, the received memory barrier requests are merged into a converged memory barrier request, each of the multiple paths being a reachable path between the sending device and the receiving device, and the total number of nodes of the multiple equivalent paths being the same; and the converged memory barrier request is sent to the receiving device.

[0238] In some embodiments, the sending module 1540 is further configured to cache memory barrier requests if the number of arrivals does not reach the total number of paths.

[0239] In some embodiments, the aggregation switch is deployed in the receiving device, or the aggregation switch is deployed in the preceding device of the receiving device, and the aggregation memory barrier request is sent by the preceding device to the receiving device.

[0240] In some embodiments, the memory barrier request carries a PTI.

[0241] It should be noted that the apparatus provided in the above embodiments is only illustrated by the division of the above functional modules when implementing its functions. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the apparatus and method embodiments provided in the above embodiments belong to the same concept, and the specific implementation process can be found in the method embodiments, which will not be repeated here.

[0242] Figure 16 This diagram illustrates a structural block diagram of a computer device 1600 according to an embodiment of the present application, used to implement the data synchronization method provided in the above embodiments. Specifically:

[0243] Typically, computer device 1600 includes a processor 1610 and memory 1620.

[0244] Processor 1610 may include one or more processing cores, such as a quad-core processor or an octa-core processor. Processor 1610 may be implemented using at least one hardware form of Digital Signal Processing (DSP), Field Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). Processor 1610 may also include a main processor and a coprocessor. The main processor, also known as the CPU, is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 1610 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content required to be displayed on the screen.

[0245] The memory 1620 may include one or more computer-readable storage media, which may be non-transitory. The memory 1620 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in the memory 1620 are used to store a computer program configured to be executed by one or more processors to implement the aforementioned data synchronization system and method.

[0246] Those skilled in the art will understand that Figure 16The structure shown does not constitute a limitation on the computer device 1600, and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0247] In an exemplary embodiment, a network device is also provided, which is equipped with a multicast switch and / or an aggregation switch for implementing the method described above.

[0248] In an exemplary embodiment, a computer-readable storage medium is also provided, wherein a computer program is stored in the storage medium, and the computer program, when executed by a processor, implements the aforementioned data synchronization system and method. Optionally, the computer-readable storage medium may include: read-only memory (ROM), random access memory (RAM), solid-state drives (SSDs), or optical discs, etc. The random access memory may include resistive random access memory (ReRAM) and dynamic random access memory (DRAM).

[0249] In an exemplary embodiment, a computer program product is also provided, the computer program product including a computer program stored in a computer-readable storage medium. A processor of a computer device reads the computer program from the computer-readable storage medium, and the processor executes the computer program, causing the computer device to perform the aforementioned data synchronization system and method.

[0250] It should be noted that the collection and processing of relevant data (such as routing information) in this application should strictly comply with the requirements of relevant national laws and regulations, obtain the informed consent or separate consent of the personal information subject, and carry out subsequent data use and processing within the scope of laws and regulations and the authorization of the personal information subject.

[0251] It should be understood that "multiple" as used herein refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. Furthermore, the step numbers described herein are merely illustrative of one possible execution order. In some other embodiments, the steps may not be executed in numerical order, such as two steps with different numbers being executed simultaneously, or two steps with different numbers being executed in the reverse order of the illustration. This application does not limit this.

[0252] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A data synchronization system for implementing memory barriers, characterized in that, The system includes a sending device and a receiving device connected via a switch network; The sending device is used to send data access requests and memory barrier requests; The switch network is configured to transmit the memory barrier request in a multicast manner on all paths between the sending device and the receiving device; and after successfully aggregating the memory barrier requests transmitted on all paths into a single aggregated memory barrier request, send the aggregated memory barrier request to the receiving device. The receiving device is configured to, upon receiving the converged memory barrier request, determine that one or more data access operations issued by the sending device before sending the memory barrier request have been completed, and the one or more data access operations are associated with the data access request.

2. The system according to claim 1, characterized in that, The switch network includes at least one multicast switch connected to the sending device and at least one aggregation switch connected to the receiving device. The multicast switch is used to send the memory barrier request in a multicast manner to the next-hop node of each of a plurality of equal-cost paths, wherein each path is a reachable path between the sending device and the receiving device, and the total number of nodes of the plurality of equal-cost paths is the same. The aggregation switch is configured to count the number of arrivals based on the received memory barrier requests; when the number of arrivals reaches the total number of paths of the plurality of equivalent paths, merge the received memory barrier requests into an aggregation memory barrier request; and send the aggregation memory barrier request to the receiving device.

3. The system according to claim 2, characterized in that, The aggregation switch is also configured to cache the memory barrier request if the number of arrivals does not reach the total number of paths.

4. The system according to claim 2 or 3, characterized in that, The multicast switch is also used to dynamically generate an equivalent next-hop node set based on the current network topology, wherein the next-hop node is a node in the equivalent next-hop node set.

5. The system according to claim 4, characterized in that, The equivalent next-hop node set changes in real time according to the link status and / or load balancing strategy.

6. The system according to any one of claims 2 to 5, characterized in that, The aggregation switch is deployed in the receiving device, or the aggregation switch is deployed in the preceding device of the receiving device, and the aggregation memory barrier request is sent to the receiving device by the preceding device.

7. The system according to any one of claims 1 to 6, characterized in that, The memory barrier request carries a path tracing identifier (PTI).

8. A data synchronization method for implementing memory barriers, characterized in that, The method is executed by a multicast switch, and the method includes: The receiving device receives a data access request and a memory barrier request from the sending device. The memory barrier request is used by the receiving device to determine that one or more data access operations issued before sending the memory barrier request have been completed, and the one or more data access operations are associated with the data access request. The memory barrier request is transmitted via multicast on all paths between the sending device and the receiving device.

9. The method according to claim 8, characterized in that, The step of transmitting the memory barrier request via multicast over all paths between the sending device and the receiving device includes: The memory barrier request is sent to the next-hop node of each of a plurality of equivalent paths, each path being a reachable path between the sending device and the receiving device, and the plurality of equivalent paths having the same total number of nodes.

10. The method according to claim 9, characterized in that, The method further includes: An equivalent next-hop node set is dynamically generated based on the current network topology, and the next-hop node is a node in the equivalent next-hop node set.

11. The method according to claim 10, characterized in that, The equivalent next-hop node set changes in real time according to the link status and / or load balancing strategy.

12. The method according to any one of claims 8 to 11, characterized in that, The memory barrier request carries a path tracing identifier (PTI).

13. A data synchronization method for implementing memory barriers, characterized in that, The method is executed by an aggregation switch, and the method includes: The receiving device receives a memory barrier request sent by a multicast switch. The memory barrier request is used by the receiving device to determine that one or more data access operations issued before sending the memory barrier request have been completed. The one or more data access operations are associated with a data access request sent by the sending device. After successfully aggregating all memory barrier requests transmitted along all paths into a single aggregated memory barrier request, the aggregated memory barrier request is sent to the receiving device.

14. The method according to claim 13, characterized in that, After successfully aggregating all memory barrier requests transmitted along all paths into a single aggregated memory barrier request, sending the aggregated memory barrier request to the receiving device includes: The number of arrivals is counted based on the received memory barrier requests; When the number of arrivals reaches the total number of paths of multiple equivalent paths, the received memory barrier requests are merged into the converged memory barrier request, where each of the multiple paths is a reachable path between the sending device and the receiving device, and the total number of nodes of the multiple equivalent paths is the same. The convergence memory barrier request is sent to the receiving device.

15. The method according to claim 14, characterized in that, The method further includes: If the number of arrivals does not reach the total number of paths, the memory barrier request is cached.

16. The method according to any one of claims 13 to 15, characterized in that, The aggregation switch is deployed in the receiving device, or the aggregation switch is deployed in the preceding device of the receiving device, and the aggregation memory barrier request is sent to the receiving device by the preceding device.

17. The method according to any one of claims 13 to 16, characterized in that, The memory barrier request carries a path tracing identifier (PTI).

18. A data synchronization device, characterized in that, The device includes: A receiving module is used to receive a data access request and a memory barrier request sent by a sending device. The memory barrier request is used by the receiving device to determine that one or more data access operations sent before sending the memory barrier request have been completed, and the one or more data access operations are associated with the data access request. The sending module is used to transmit the memory barrier request in a multicast manner on all paths between the sending device and the receiving device.

19. A data synchronization device, characterized in that, The device includes: The receiving module receives a memory barrier request sent by a multicast switch. The memory barrier request is used by the receiving device to determine that one or more data access operations issued before sending the memory barrier request have been completed. The one or more data access operations are associated with a data access request sent by the sending device. The sending module is configured to send the converged memory barrier request to the receiving device after all the memory barrier requests transmitted on all paths have been successfully converged into a single converged memory barrier request.

20. A network device, characterized in that, The network device is equipped with a multicast switch and / or an aggregation switch, wherein the multicast switch is used to implement the method as described in any one of claims 8 to 12, and the aggregation switch is used to implement the method as described in any one of claims 13 to 17.

21. A computer-readable storage medium, characterized in that, The storage medium stores a computer program that is executed by a processor to implement the method as described in any one of claims 8 to 17.

22. A computer program product, characterized in that, The computer program product includes a computer program that is loaded and executed by a processor to implement the method as described in any one of claims 8 to 17.

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