Self-synchronous receiving method, device, equipment, medium and program product for UART asynchronous serial communication

Abstract

The application provides a self-synchronous receiving method, device, equipment, medium and program product for UART asynchronous serial communication, the method comprising: continuously sampling a serial input signal of a UART receiving pin, and forming a window sequence updated over time according to a preset window length; performing synchronization pattern detection on the window sequence, and generating a synchronization trigger signal when the window sequence meets a preset synchronization pattern; performing synchronization hold control when the synchronization trigger signal is generated, masking a new synchronization trigger during the synchronization hold, and outputting a synchronization enable signal for bit timing based on the synchronization trigger signal; and triggering bit-level resolution of the received serial data and driving receiving state update by using the synchronization enable signal to complete the reception of a frame of data. The application provides a self-synchronous receiving mechanism without fixed baud rate configuration, high synchronization accuracy and strong robustness, and can maintain reliable communication performance in low-power embedded systems and high-noise application environments.

Description

Technical Field

[0001] This application relates to the fields of embedded systems and digital communication technology, and in particular to a self-synchronizing receiving method, apparatus, device, medium and program product for UART asynchronous serial communication. Background Technology

[0002] Asynchronous serial communication (UART) is a type of communication method widely used in embedded systems and digital communication devices. There is no clock signal between the transmitting end and the receiving end. The receiving end usually determines the data reception timing by detecting the start bit level transition and obtains the bit timing by dividing the local clock according to the preset baud rate, thereby completing the sampling decision at the center of the data bit.

[0003] Existing technologies generally employ baud rate generators, frequency multiplication, or oversampling circuits to achieve bit timing and data parsing. However, these solutions are highly dependent on the accuracy of the local clock. When there is a significant clock deviation between the receiver and transmitter, it can easily cause the bit center sampling position to shift, leading to sampling errors. Furthermore, in variable baud rate or adaptive communication scenarios, traditional structures require reconfiguration of the frequency division coefficients, resulting in insufficient flexibility, and the baud rate generator itself also increases hardware resource overhead. Moreover, in terms of frame start detection, the UART receiver relies on a single falling edge for start bit identification, which is susceptible to interference from noise spikes, glitches, or edge jitter, causing false triggering, deviating the sampling timing from the correct data rhythm, and resulting in desynchronization.

[0004] Although existing technologies have enhanced the robustness of start bit detection through oversampling, multi-level sampling, or the introduction of state machines, they still rely on explicit bit time counters or fixed baud rate clocks, making it difficult to restore a stable sampling rhythm solely from the received signal without needing a preset baud rate. Therefore, limitations remain in areas such as multi-baud rate compatibility, adaptive bit timing, and noise immunity, making it difficult to meet the self-synchronization requirements in complex communication environments. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this application provides a self-synchronization receiving method, apparatus, device, medium, and program product for UART asynchronous serial communication, which at least solves the problem that in existing technologies, the UART receiver relies on a preset baud rate and is prone to loss of synchronization under noise interference, making it impossible to stably recover bit timing from the received signal itself.

[0006] To achieve the above objectives and other advantages, some embodiments of this application provide the following aspects:

[0007] In a first aspect, some embodiments of this application provide a self-synchronizing reception method for UART asynchronous serial communication, including:

[0008] The serial input signal of the UART receive pin is continuously sampled, and a window sequence that is updated over time is formed according to a preset window length.

[0009] The window sequence is subjected to synchronization mode detection. When the window sequence meets the preset synchronization mode, a synchronization trigger signal is generated.

[0010] Synchronization hold control is performed when the synchronization trigger signal is generated, new synchronization triggers are blocked during the synchronization hold period, and a synchronization enable signal for bit timing is output based on the synchronization trigger signal.

[0011] The synchronization enable signal is used to trigger bit-level parsing of the received serial data and drive the receive state update in order to receive a complete frame of data.

[0012] Secondly, some embodiments of this application also provide a self-synchronizing receiving device for UART asynchronous serial communication, comprising:

[0013] The sampling module is used to continuously sample the serial input signal of the UART receive pin and form a window sequence that updates over time according to a preset window length.

[0014] The pattern matching module is used to perform synchronization pattern detection on the window sequence, and generate a synchronization trigger signal when the window sequence meets the preset synchronization pattern.

[0015] The synchronization control module is used to perform synchronization holding control when the synchronization trigger signal is generated, to block new synchronization triggers during the synchronization holding period, and to output a synchronization enable signal for bit timing based on the synchronization trigger signal.

[0016] The status update module is used to trigger bit-level parsing of the received serial data and drive the receive status update using the synchronization enable signal, so as to receive a complete frame of data.

[0017] Thirdly, some embodiments of this application also provide an electronic device, the electronic device comprising:

[0018] One or more processors; and a memory storing computer program instructions that, when executed, cause the processors to perform the self-synchronizing reception method for UART asynchronous serial communication as described above.

[0019] Fourthly, some embodiments of this application also provide a computer-readable storage medium having a computer program and / or instructions stored thereon, which, when executed by a processor, implement the self-synchronizing reception method for UART asynchronous serial communication as described above.

[0020] Fifthly, some embodiments of this application also provide a computer program product, including a computer program and / or instructions, which, when executed by a processor, implement the self-synchronizing reception method for UART asynchronous serial communication as described above.

[0021] Compared with existing technologies, the solution provided in this application continuously samples the serial input signal of the UART receiving pin and forms a sampling sequence that updates over time according to a preset window. This allows the receiving side to identify the data frame structure using the actual level change of the input signal as a time reference, without relying on a fixed baud rate clock. By performing synchronization mode detection on the window sequence, the start bit and synchronization timing can be determined based on continuous level characteristics or stable transition patterns. Compared with single-edge triggering, this method has stronger noise immunity and can effectively suppress false triggering caused by jitter, glitches, and transient interference. Furthermore, through a bit timing generation mechanism driven by synchronization hold control and synchronization trigger signal, bit center sampling is driven by the actual received signal sequence, rather than relying on a preset baud rate. This achieves automatic alignment with transmitting clock offset, line jitter, and dynamic baud rate changes, thus adapting to various baud rate conditions. Relying on a receive state update mechanism driven by a synchronization enable signal, operations such as start bit confirmation, data bit parsing, verification processing, and stop bit determination are completed under precise timing rhythms, thereby improving the overall stability and data reconstruction accuracy of asynchronous serial communication. This results in a self-synchronizing receiving mechanism that does not require a fixed baud rate configuration, has high synchronization accuracy, and is robust, enabling it to maintain reliable communication performance in low-power embedded systems and high-noise application environments. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other implementation methods can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a flowchart illustrating the self-synchronization receiving method for UART asynchronous serial communication provided in an embodiment of this application.

[0024] Figure 2 This is a schematic diagram of the input port of the UART self-synchronization receiving circuit in this embodiment;

[0025] Figure 3 This is a schematic diagram of the state machine for the self-synchronization receiving process of UART asynchronous serial communication provided in the embodiments of this application;

[0026] Figure 4This is a schematic diagram of the structure of the self-synchronizing receiving device for UART asynchronous serial communication provided in the embodiments of this application;

[0027] Figure 5 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0029] Some embodiments of this application relate to a self-synchronizing reception method for UART asynchronous serial communication, see reference. Figure 1 As shown, the method may include the following steps:

[0030] Step S1: Continuously sample the serial input signal of the UART receive pin and form a window sequence that updates over time according to the preset window length.

[0031] In one alternative embodiment, such as Figure 2 As shown, the UART self-synchronization receiver circuit includes a reset signal input terminal Uart_RSTx, a clock input terminal Uart_CLKx, and a serial data input terminal Uart_RXDx. Uart_RSTx is used to initialize the internal state machine, counter, and sampling register; Uart_CLKx provides a unified clock reference for internal logic operation and sampling; and Uart_RXDx is the external UART data line input, and the level changes of this signal line constitute the serial data stream that the receiving side needs to parse. Driven by Uart_CLKx, the UART self-synchronization receiver circuit continuously samples the level state on Uart_RXDx and writes the sampled values ​​sequentially into a shift register of a preset window length to form a window sequence that updates over time. This window sequence is used for synchronization mode detection, providing a reliable signal basis for identifying start bit characteristics.

[0032] In an optional embodiment, step S1 specifically includes:

[0033] Step S101: The sampling clock for performing data bit oversampling is obtained by dividing the high-frequency system clock. The effective sampling frequency of the sampling clock and the target baud rate satisfy a preset ratio of five times, so as to form five sampling time slots with basic equal time intervals in each data bit period.

[0034] Step S102: When each sampling time slot arrives, the level signal of the UART receive pin is sampled once to obtain five oversampling results in each data bit period and form a sampling sequence arranged in chronological order;

[0035] Step S103: The latest sampling sequence is moved into a shift register with a preset window length of five in chronological order, and historical sampling sequences that exceed the window length are moved out in a first-in-first-out manner, so that the shift register always maintains the chronological arrangement of the most recent five sampling results, thereby forming a window sequence that slides and updates over time.

[0036] Specifically, in asynchronous serial communication scenarios, since the transmitting and receiving ends do not share a clock, issues such as crystal oscillator errors, temperature drift, and inconsistent baud rate settings may arise, leading to deviations in actual bit timing. To accurately locate the center position of data bits under conditions without a shared clock, the receiving end typically uses oversampling to determine the input signal. In common oversampling designs, lower 3× oversampling (sampling 3 times per bit cycle) can reduce hardware resource consumption, but it is more sensitive to signal jitter and transient glitches; higher 8× or 16× oversampling can provide higher decision accuracy, but requires higher frequency clock support, and the size of the shift register and matching logic increases accordingly, which is not conducive to implementation on resource-constrained embedded platforms.

[0037] Based on a comprehensive balance between hardware resources and synchronization reliability, this embodiment employs a five-fold oversampling method, enabling the receiver to obtain five sampling points with essentially equal time intervals in each UART data bit cycle. This balances bit center determination accuracy with hardware resource overhead. To this end, the receiver utilizes the on-chip high-frequency system clock, which is divided to obtain the sampling clock, ensuring that the effective sampling frequency of the sampling clock satisfies the following relationship:

[0038]

[0039] in, This represents the sampling clock frequency, measured in Hz, used to drive the receiver to perform data bit oversampling. This frequency determines the number of sampling time slots available within each UART data bit cycle; this embodiment uses 5 sampling time slots per bit. BaudRate represents the data transmission rate of the UART communication link, and it determines the length of a single UART data bit cycle. The relationship is as follows: .

[0040] Based on the aforementioned five-fold oversampling relationship, at a typical baud rate (e.g., 9600bps), a sampling clock that meets the five-fold sampling requirement can be obtained by dividing the on-chip high-frequency system clock by an integer multiple, making the effective sampling frequency of this sampling clock approximately five times the UART target baud rate. This results in five essentially equal-time sampling slots within each UART data bit period. The sampling clock triggers a shift register update upon the arrival of each sampling slot, enabling the receiver to continuously obtain five sequentially arranged level samples within a single bit period. Through these five oversampling operations, a stable and continuous local level window can be constructed within one data bit period of the input signal, providing a sufficient data foundation for synchronization mode detection and bit center determination.

[0041] For example, the timing relationship of five-fold oversampling is illustrated using a 9600bps UART communication scenario. At this baud rate, a single bit period is approximately 104.17μs. The update frequency of the effective sampling enable signal (ClockEnax) used by the system to trigger the sampling operation is approximately 48kHz, with a period of approximately 20.83μs. Since one data bit period can contain approximately 104.17μs / 20.83μs ≈ 5 effective samples, the receiver can form five essentially equally spaced sampling points within each bit period.

[0042] In an optional embodiment, a high-frequency system clock of 125MHz can be used as the upper-layer clock source, and a sampling clock of approximately 576kHz can be obtained by first-level frequency division. This sampling clock naturally satisfies the timing relationship of five times oversampling with the commonly used UART baud rate (such as 9600bps).

[0043] After obtaining a sampling clock that satisfies the five-fold oversampling relationship through frequency division, when the valid sampling enable signal of the sampling clock arrives, the receiver performs a sampling operation on the level state of the UART receive pin (Uart_RXDx) once in each sampling time slot. Specifically, within one UART data bit cycle, the sampling clock sequentially generates five equally spaced sampling time slots. The system hardware reads the current level value of the UART receive pin when each sampling time slot arrives and records this level value as the sampling result corresponding to that sampling time slot. In this way, the receiver can continuously acquire five sampling levels arranged in chronological order within one data bit cycle, thereby forming a complete sampling sequence.

[0044] After completing five oversampling operations on the UART receive pin, this embodiment writes the latest sampled result of the current cycle into a shift register of preset length five in chronological order at the end of each sampling time slot. The shift register uses a first-in, first-out (FIFO) update method. When a new sampled result is written to the least significant bit of the register, the existing sampled results in the register are shifted one bit to the higher significant bit in sequence. When the valid data in the register exceeds the window length, the earliest acquired sampled result is automatically shifted out of the register. Through the above shift update mechanism, the shift register always maintains the chronological arrangement of the five most recent sampled results at any given time, thus forming a window sequence that slides in real time with the sampling progress. This window sequence directly reflects the continuous level change characteristics of the UART input signal in a short period of time and serves as the basis for subsequent synchronization mode detection, start bit identification, and edge stability judgment, enabling the reception process to be based on the local statistical characteristics of the real input waveform.

[0045] Through the processing in steps S101-S103 described above, the receiving side can obtain the local timing level variation characteristics of the UART input signal in a stable and continuous manner without relying on a precise baud rate counter. The constructed five-fold oversampling and timing sliding window mechanism enables the data frame structure in UART asynchronous communication scenarios to reliably sense based on the timing characteristics of the input signal itself, laying a stable, interference-resistant foundation for the entire self-synchronizing reception process without relying on precise baud rate settings.

[0046] Step S2: Perform synchronization mode detection on the window sequence. When the window sequence meets the preset synchronization mode, generate a synchronization trigger signal.

[0047] In an optional embodiment, step S2 specifically includes:

[0048] Step S201: By comparing the level consistency of each bit in the window sequence with the corresponding bit in the synchronization mode, it is determined whether the window sequence matches the synchronization mode. The synchronization mode includes a continuous low-level mode for identifying the start bit, a continuous high-level mode for identifying the idle state, and a transition mode for identifying stable edge transitions.

[0049] The level state of each bit in the current window sequence is compared one by one with the corresponding bit in the synchronization mode. If the window sequence is consistent with a certain synchronization mode in all bit positions, then the window sequence is considered to satisfy the corresponding synchronization mode. In this embodiment, the synchronization mode can include the following three categories:

[0050] A continuous low-level pattern (e.g., 5'b00000) is used to identify the UART start bit. When the window sequence presents a continuous low level, it can be considered that an external input signal has entered the start bit stage;

[0051] A continuous high-level mode (e.g., 5'b11111) is used to identify an idle state or as a wake-up signal for certain protocols;

[0052] The transition pattern (e.g., 4'b1100 or 4'b0011) is used to identify stable edge transitions such as falling or rising edges. In the hardware implementation, when the window sequence shows a progressively falling sequence such as "11110→11100→11000" (corresponding to the first four bits of the most recent five samples in the shift register UartRxDat[4:1]==4'b1100), it can be determined that a valid falling edge has occurred in the input signal.

[0053] Synchronization modes are used to characterize the level features in the UART frame structure that have synchronization significance. When the window sequence satisfies any of the above modes, it indicates that a valid synchronization event, such as the falling edge of the start bit, has appeared in the sampling results at the receiving end. By using the above mode matching method, single abnormal sampling caused by short-term glitches or jitter can be effectively filtered out, improving the stability of synchronization decisions.

[0054] Step S202: Generate a synchronization trigger signal when any synchronization mode perfectly matches the window sequence and is not currently in a synchronization lock state.

[0055] Based on a successful synchronization mode match, it is further necessary to determine whether the receiver is currently in a synchronization-locked state. The synchronization-locked state indicates whether the receiver has already completed a valid synchronization trigger in the current data frame. Since a level structure similar to the synchronization mode may still occur during the synchronization hold period, or false transitions may occur due to line noise, triggering new synchronization events while in a locked state will cause the bit center position to be repeatedly reset within the same data frame, disrupting the receiving rhythm and affecting the stability of subsequent data bit decisions. Therefore, the system allows new synchronization triggers when the receiver is in a non-synchronization-locked state, generating a synchronization trigger signal to indicate that the UART receiver has detected a valid frame synchronization event, and accordingly initiates subsequent delay alignment processing and bit center recovery procedures. Conversely, if the window sequence matches the synchronization mode but the receiver is already in a synchronization-locked state, the system will suppress new synchronization triggers to avoid bit timing drift caused by repeated synchronization.

[0056] Through the processing in steps S201-S202, the receiving end can determine the level structure of the input signal based on the window sequence formed by continuous sampling without relying on a fixed baud rate clock, thereby accurately identifying key synchronization events in the UART frame. The window sequence provides level distribution information across multiple sampling points, making synchronization mode detection no longer dependent on a single instantaneous sample, thus reducing the impact of transient interference such as glitches and jitter on synchronization determination. Through the above control logic, it can be ensured that the synchronization trigger signal is generated only when a valid synchronization event is detected for the first time, thereby maintaining the stability of the sampling rhythm of subsequent data bits and improving the reliability of the UART reception process under noise disturbances and transition interference.

[0057] Step S3: When generating the synchronization trigger signal, perform synchronization hold control, block new synchronization triggers during the synchronization hold period, and output a synchronization enable signal for bit timing based on the synchronization trigger signal.

[0058] In an optional embodiment, step S3 specifically includes:

[0059] Step S301: When the synchronization trigger signal is generated, start the synchronization hold timer and build a delay counter based on the synchronization trigger signal so that the delay counter accumulates the bit time offset;

[0060] Step S302: When the accumulated count of the delay counter reaches the target count value for aligning the data bit center, a synchronization enable signal is generated, and the synchronization enable signal is output in the form of a single-cycle pulse as a bit timing reference.

[0061] Step S303: During the effective period of the synchronization hold timer, time masking is performed on the detected synchronization candidate events, so that the synchronization candidate events within the effective period of the timer are judged as pseudo-synchronization events and do not trigger new synchronization behavior.

[0062] Specifically, when the synchronization trigger signal is generated, the receiver first starts a synchronization hold timer to define the effective time window of the current synchronization event and prevent repeated triggering of synchronization behavior within this time window. Simultaneously, the system constructs a delay counter based on the synchronization trigger signal, allowing the delay counter to accumulate counts for subsequent sampling cycles starting from zero.

[0063] The purpose of the delay counter is to establish the time offset between the input signal edge and the center of the data bit. Since UART uses an asynchronous transmission structure, the falling edge of the start bit typically occurs at the boundary of the bit period, while the optimal sampling point for the data bit is located at the center of the bit period. Therefore, a delay counter is needed to accumulate several sampling periods so that the synchronization enable signal is output when the accumulated offset reaches the target. The receiver achieves time alignment from the edge detection moment to the bit center by counting the sampling cycles sequentially.

[0064] After the delay counter starts, the system continuously accumulates the valid count of the sampling clock. When the accumulated value of the delay counter reaches the preset target count value, it indicates that the current sampling cycle has reached the center position of the data bit. At this time, the system generates a synchronization enable signal and outputs the signal in the form of a single-cycle pulse.

[0065] The synchronization enable signal serves as a bit timing reference, triggering data bit decision-making, state machine transitions, and synchronous sampling of subsequent bits. Since the synchronization enable signal is output when the delay counter reaches the alignment condition, its timing corresponds to the center sampling point of the input data bits, thus significantly improving the accuracy of data recovery.

[0066] During the effective period of the synchronization hold timer, the level changes in the window sequence are continuously monitored, and time masking is performed on all detected synchronization candidate events. That is, although bit sequences similar to the synchronization mode structure may appear, or false transitions may occur due to line noise, as long as these candidate events occur within the synchronization hold time window, the system classifies them as false synchronization events and does not allow the generation of new synchronization trigger signals. Time masking avoids repeated synchronization within the same data bit period, preventing the bit center sampling point from being reset multiple times, thus ensuring a stable bit timing rhythm at the receiving end. Furthermore, the time masking mechanism can significantly suppress misjudgments caused by noise interference, ensuring that the synchronization logic only responds to genuine valid start bits or transition events.

[0067] For example, when the receiving end detects a valid synchronization trigger condition (e.g., a falling edge of the start bit or a stable transition mode) in the window sequence, the system first sets the synchronization trigger signal ResumeTag and starts the synchronization hold timer ResumeJmp, loading a preset initial value (e.g., 4). The countdown length of ResumeJmp is used to limit the subsequent valid sampling cycles within the synchronization hold interval. Within this interval, new synchronization trigger events are prohibited to avoid repeated synchronization within the same data bit period, which could cause the bit center position to be reset. ResumeJmp decreases periodically with ClockEnax, and when its value is greater than zero, it indicates that the system is still in the synchronization hold state.

[0068] Simultaneously with the synchronous trigger event, the system starts a delay counter based on the ResumeTag, accumulating subsequent valid sampling time slots from zero. Since the UART bit period under five-fold oversampling conditions contains five sampling points with approximately equal time intervals, and the falling edge of the start bit is usually detected near the first sampling point, a certain number of sampling cycles need to be accumulated by the delay counter to ensure that the generated bit timing pulse falls at the center of the data bit. For example, when the delay counter accumulates to a preset count value (such as the count position corresponding to the 3rd sampling point), the system outputs a synchronization enable signal ResumeSyn. ResumeSyn is generated in the Uart_CLKx field as a single-cycle pulse, indicating that the current sampling time is aligned with the center of the UART data bit, and serves as the bit timing reference for the driving state machine to parse the data bits.

[0069] During the ResumeJmp countdown, the receiver continues to monitor the level changes of the window sequence, but all candidate events similar to those in synchronization mode are forcibly masked and treated as pseudo-synchronization events. For example, even if a falling edge structure similar to the start bit or a brief transition caused by noise reappears within the synchronization hold window, ResumeTag will not be set again or the delay counter will not be rebuilt, thus avoiding repeated resets of bit timing within the same data bit period. Only when ResumeJmp decrements to zero and the receiver exits the synchronization hold state will the system allow the identification of the next valid synchronization trigger event.

[0070] Through the processing in steps S301 to S303 described above, this embodiment, after detecting the start edge or other synchronization events, uses a delay counter to precisely shift the synchronization trigger time to the center position of the data bit, generating a single-cycle synchronization enable signal as the bit timing reference. This ensures that the sampling of each data bit revolves around the bit center, thereby improving the timing accuracy of bit decision. Simultaneously, the synchronization hold timer masks the execution time of subsequent synchronization candidate events within a limited effective timing period, preventing repeated synchronization triggers within the same data bit cycle and preventing the sampling rhythm from being reset multiple times. This ensures the continuity and stability of the bit timing process at the receiving end, reducing the risk of desynchronization caused by jitter, glitches, or pseudo-jumps.

[0071] In an alternative implementation, the method further includes the step of adaptively estimating the data bit period and adjusting the synchronization timing parameters accordingly to improve the robustness of bit timing control under different baud rate conditions and clock skew. The method also includes:

[0072] Based on the effective count of the sampling clock between the generation of two effective synchronous trigger signals, the corresponding data bit time length is determined and recorded as the bit time reference parameter;

[0073] When setting the effective period of the synchronization hold timer or setting the target count value of the delay counter, the bit time base parameter is used to adaptively set the effective period of the timing or the target count value for bit timing control of data bits.

[0074] Specifically, the receiving end continuously records the sampling cycle driven by the sampling clock ClockEnax. When the first synchronization trigger signal ResumeTag is detected, the system clears the current sampling counter SampleCnt and starts the counting process. The sampling counter increments by 1 for each valid ClockEnax sampling period to reflect the actual elapsed physical time.

[0075] During subsequent reception, when the window sequence again satisfies the synchronization mode and generates a second valid synchronization trigger event, the system captures the value of SampleCnt at this time. Since the synchronization trigger event usually corresponds to a critical edge in the UART data frame (such as the falling edge of the start bit, the transition point between data bits, etc.), the number of valid ClockEnax sampling cycles between two valid synchronization triggers can directly reflect a complete data bit cycle.

[0076] The receiving end uses this count value as the data bit time length and records it as the bit time reference parameter BaseBitLen, which characterizes the actual bit period length under the current link environment. This reference parameter can be automatically updated according to environmental changes, its own crystal oscillator deviation, or the baud rate offset of the other end during communication.

[0077] Subsequently, when configuring the effective timing period of the synchronization hold timer ResumeJmp, the hold time window is calculated based on BaseBitLen according to a preset hold ratio or empirical coefficient, ensuring it covers the effective decision interval of the current data bit. This allows the synchronization hold interval to scale proportionally with changes in the actual bit period length. Even if the actual baud rate changes due to temperature drift, crystal oscillator deviation, or line delay, the synchronization shielding logic can still maintain consistency with the actual sampling rhythm, improving the adaptability and stability of the synchronization control.

[0078] Similarly, when setting the target count value of the delay counter for bit center alignment, BaseBitLen can be used for adaptive calculation. For example, if the standard bit period contains 5 oversampling points, the bit center typically corresponds to an offset of BaseBitLen × 0.5. The receiver can calculate a more accurate delay count target based on the actual value of BaseBitLen, ensuring that the ResumeSyn output pulse always falls near the actual data bit center, without relying on a fixed preset delay parameter.

[0079] Through the aforementioned underlying data processing mechanism, the bit center sampling process can be entirely driven by the received data rhythm, enabling adaptive adjustment to different baud rates, jitter environments, and cross-device clock differences. This eliminates the need for a preset baud rate register or external baud rate generator, allowing this method to provide higher robustness, compatibility, and accurate bit decision capabilities in resource-constrained asynchronous communication scenarios.

[0080] Step S4: Use the synchronization enable signal to trigger bit-level parsing of the received serial data and drive the receive status update to receive a complete frame of data.

[0081] In an optional embodiment, step S4 specifically includes:

[0082] Step S401: Each time the synchronization enable signal is output, extract the corresponding data bit sampling result from the current sampling window, and update the internal state of the receiver state machine according to the data bit sampling result. The receiver state machine includes start bit confirmation state, data bit accumulation state, parity bit determination state and stop bit verification state.

[0083] Step S402: In the start bit confirmation state, verify the validity of the start bit level based on the sampling result corresponding to the synchronization enable signal;

[0084] Step S403: In the data bit accumulation state, the decision result corresponding to each synchronization enable signal is shifted into the receiving register according to the predetermined data bit order;

[0085] Step S404: In the check bit determination state, perform error checking on the parsed data bits according to the preset check method;

[0086] Step S405: In the stop bit verification state, the validity of the stop bit is confirmed to generate a complete data frame reception result.

[0087] Specifically, Figure 3 This is a schematic diagram of the state machine for the self-synchronizing reception process of UART asynchronous serial communication provided in this embodiment. This state machine demonstrates the process by which the receiving end, driven by the synchronization enable signal, parses the start bit, data bits, parity bit, and stop bit bit bit by bit. Specifically, the reset signal indicates that the receiving state machine is restored to its initial state when the system powers on or an abnormality occurs; the idle state UART_IDLE indicates that the receiving logic is in the initial state of waiting for the start signal of a new frame; the data receiving state UART_DATA indicates that each data bit is sampled and accumulated sequentially according to the synchronization enable signal; the parity bit determination state UART_FCS1 indicates that when the parity mode is enabled, the corresponding parity calculation is performed on the parsed data bits; and the stop bit verification state UART_ESD1 indicates that the validity of the received stop bit level is confirmed, and the frame reception is determined accordingly.

[0088] Upon the initial triggering of the synchronization enable signal ResumeSyn, if the bit center sampling result is low, it indicates that a valid start bit has been detected, and the state machine transitions from UART_IDLE to the data receiving state UART_DATA.

[0089] In the data reception state UART_DATA, the state machine sequentially samples the data bits in the UART frame under the drive of multiple subsequent synchronization enable signals ResumeSyn, and writes the corresponding bit center sampling result into the receive register. When the accumulated number of data bits reaches the frame format setting value, if the UART frame structure contains a parity bit, the state machine transitions to the parity bit determination state UART_FCS1; if there is no parity bit, it directly enters the stop bit check state UART_ESD1.

[0090] In the parity check state UART_FCS1, the state machine reads the center level of the parity bit based on the trigger of the next synchronization enable signal ResumeSyn, and compares it with the expected parity value calculated based on the received data bits to determine whether the check is correct. After the check is completed, the state machine enters the stop bit check state UART_ESD1.

[0091] In the stop bit verification state UART_ESD1, the state machine, driven by the synchronization enable signal ResumeSyn, samples the stop bit and verifies whether it is at the specified high level. If the stop bit is valid, it indicates that the current frame of UART data has been received and output validly; if the stop bit is invalid, a frame error is recorded and the current parsing result is discarded. After completing the stop bit verification, the state machine returns to the idle state UART_IDLE, ready to receive the next frame of data.

[0092] For example, taking the common UART 8N1 frame format as an example, the data bits are 8 bits; there is no parity bit (Parity=None); and there is 1 stop bit. Under this frame structure, the parsing process of a frame of data by the receiver under the drive of the synchronization enable signal ResumeSyn is shown in the following table:

[0093] UART self-synchronization received frame state transition and action correspondence table

[0094]

[0095] Start bit detection phase (ResumeSyn first trigger): After the synchronous trigger mechanism detects the falling edge of the input signal, ResumeSyn outputs a pulse for the first time. If the bit center sampling result is low at this time, the receiver state machine transitions from the UART_IDLE state to the UART_DATA state, entering the data bit reception process.

[0096] Data bit reception phase (ResumeSyn triggers 2-9): In the next eight ResumeSyn pulses, the state machine sequentially reads data bits D0-D7 from the bit center and writes them into the receive register in order. D0 is the least significant bit (LSB), and D7 is the most significant bit (MSB). As sampling progresses, the receive register gradually constructs an eight-bit complete data field.

[0097] Transition to stop bit check state (10th ResumeSyn trigger): Since the 8N1 frame does not contain a check bit, the state machine directly transitions from the UART_DATA state to the UART_ESD1 state when the 10th ResumeSyn arrives. At this time, the bit center level should be high, indicating that the stop bit is valid.

[0098] Return to idle state and prepare for the next frame (11th ResumeSyn trigger): After the stop bit check is completed, the state machine returns to the UART_IDLE state, receives 8 bits of data in the register as valid data output, and the system waits for the start bit of the next frame of data to appear.

[0099] Through the processing of steps S401 to S405, the receiving end, under the precise drive of the synchronization enable signal, can perform bit-by-bit decision-making and state transitions on the input serial data at a fixed bit-center rhythm, forming a stable and orderly execution link for the parsing process of the entire UART data frame. Specifically, the start bit is validly confirmed under the first synchronization enable pulse, ensuring that the data reception process starts from a clear frame boundary; the data bits are sequentially shifted into the receive register under the action of continuous synchronization enable pulses, enabling 8-bit or other length data fields to be stably recovered without a preset baud rate; the parity bit (if present) is used to determine correctness in the corresponding state, thereby improving data integrity; the stop bit is validly checked at a specified time, used to confirm the end of the frame and trigger the state machine to return to the idle state. Through the above-mentioned state machine-driven phased parsing mechanism, the receiving end can maintain the structured parsing capability of the entire UART frame under asynchronous communication environments, clock deviations, or slight noise interference, ensuring the robustness and overall reliability of the data reception process.

[0100] In summary, the self-synchronizing reception method for UART asynchronous serial communication provided in this application continuously samples the serial input signal of the UART receiving pin and forms a sampling sequence that updates over time according to a preset window. This allows the receiving side to identify the data frame structure using the actual level change of the input signal as a time reference, without relying on a fixed baud rate clock. By performing synchronization mode detection on the window sequence, the start bit and synchronization timing can be determined based on continuous level characteristics or stable transition patterns. Compared with single-edge triggering, this method has stronger noise immunity and can effectively suppress false triggering caused by jitter, glitches, and transient interference. Furthermore, through a bit timing generation mechanism driven by synchronization hold control and synchronization trigger signal, bit center sampling is driven by the actual received signal sequence, rather than relying on a preset baud rate. This achieves automatic alignment with transmitting clock offset, line jitter, and dynamic baud rate changes, thus adapting to various baud rate conditions. Relying on a receive state update mechanism driven by a synchronization enable signal, operations such as start bit confirmation, data bit parsing, verification processing, and stop bit determination are completed under precise timing rhythms, thereby improving the overall stability and data reconstruction accuracy of asynchronous serial communication. This results in a self-synchronizing receiving mechanism that does not require a fixed baud rate configuration, has high synchronization accuracy, and is robust, enabling it to maintain reliable communication performance in low-power embedded systems and high-noise application environments.

[0101] The steps of the various methods described above are only for clarity. In practice, they can be combined into one step or some steps can be split into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this application. Adding insignificant modifications or introducing insignificant designs to the algorithm or process, but without changing the core design of the algorithm and process, are also within the scope of protection of this application.

[0102] Some embodiments of this application also relate to a self-synchronizing receiving device for UART asynchronous serial communication, see reference. Figure 4 As shown, it includes:

[0103] The sampling module is used to continuously sample the serial input signal of the UART receive pin and form a window sequence that updates over time according to a preset window length.

[0104] The pattern matching module is used to detect the synchronization pattern of the window sequence. When the window sequence meets the preset synchronization pattern, a synchronization trigger signal is generated.

[0105] The synchronization control module is used to perform synchronization hold control when a synchronization trigger signal is generated, to block new synchronization triggers during the synchronization hold period, and to output a synchronization enable signal for bit timing based on the synchronization trigger signal.

[0106] The status update module is used to trigger bit-level parsing of the received serial data using the synchronization enable signal and drive the receive status update to complete the reception of a frame of data.

[0107] Specifically, the sampling module is used to continuously sample the serial input signal of the UART receive pin and form a window sequence that slides and updates over time according to a preset window length, thereby preserving the local variation characteristics of the input level and providing a stable data foundation for subsequent synchronous pattern recognition.

[0108] The pattern matching module performs bit-level comparisons on the window sequence output by the sampling module, matching the window sequence bit by bit with the preset start bit mode, stable high level mode, or transition mode. When the window sequence satisfies any synchronization mode and the current system is not in a synchronization lock state, the module outputs a synchronization trigger signal to characterize a valid synchronization event in the UART frame structure.

[0109] Upon receiving a synchronization trigger signal, the synchronization control module initiates a synchronization hold mechanism, limiting the effective time window of the synchronization event and blocking new synchronization candidate events during the hold period to avoid bit decision drift caused by repeated synchronization. Simultaneously, the module drives a delay counter based on the synchronization trigger signal, outputting a single-cycle synchronization enable pulse when the count reaches the target offset corresponding to the center position of the data bit, serving as the bit timing reference.

[0110] The state update module performs bit-level parsing when triggered by the synchronization enable signal. Based on the current state machine stage (including start bit confirmation, data bit accumulation, parity bit determination, and stop bit verification), it extracts and determines the corresponding bit level from the sampling window, and sequentially completes data bit extraction, verification confirmation, and frame end determination to obtain a complete data frame reception result.

[0111] Through the synergistic effect of the aforementioned modules, the device of this application can achieve stable parsing of UART signals with lower logic resources without relying on a fixed baud rate configuration. This is particularly suitable for embedded platforms with low clock precision, limited logic area, or requiring low-power operation. In traditional UART receiver circuits that rely on fixed baud rate division and high-multiplication oversampling, low-power MCUs or SoCs often experience unstable bit center determination due to crystal oscillator deviation, dynamic frequency modulation, or noise interference. The self-synchronizing receiver circuit of this application, constructed through mechanisms such as sliding window sampling, synchronization mode matching, delay alignment, and bit center pulse recovery, can directly recover the bit time reference based on the level sequence of the input signal itself. This reduces the system's dependence on a precise clock source, making it more suitable for integration into resource-constrained low-power embedded platforms.

[0112] The content of the above embodiments of the self-synchronization receiving method for UART asynchronous serial communication is applicable to this device embodiment. The specific functions implemented in this device embodiment are the same as those in the above embodiments of the self-synchronization receiving method for UART asynchronous serial communication, and the beneficial effects achieved are also the same as those achieved in the above embodiments of the self-synchronization receiving method for UART asynchronous serial communication. To reduce repetition, further details are omitted here.

[0113] Furthermore, some embodiments of this application also provide an electronic device. The electronic device can be various forms of digital computer, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, etc. The electronic device can also be various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices.

[0114] The electronic device includes: one or more processors; and a memory storing computer program instructions, which, when executed, cause the processor to perform a self-synchronizing reception method for UART asynchronous serial communication as provided in any one or more of the above embodiments. Figure 5 An exemplary structural diagram of the electronic device is disclosed. The electronic device includes one or more processors 1101, a memory 1102, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components are interconnected via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the electronic device, including instructions stored in or on memory to display graphical information of a GUI on an external input / output device (such as a display device coupled to the interface). In some other embodiments, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple electronic devices can be connected, each providing some of the necessary operations. The components, their connections and relationships, and their functions shown herein are merely examples and are not intended to limit the implementation of the present application described and / or claimed herein.

[0115] The electronic device may further include an input device 1103 and an output device 1104. The processor 1101, memory 1102, input device 1103, and output device 1104 may be connected via a bus or other means. Figure 5 Taking the example of a connection between China and Israel via a bus.

[0116] Input device 1103 can receive input numerical or character information, and generate key signal inputs related to user settings and function control of the electronic device, such as a touch screen, keypad, mouse, trackpad, touchpad, joystick, one or more mouse buttons, trackball, joystick, etc. Output device 1104 may include a display device, auxiliary lighting device (e.g., LED), and haptic feedback device (e.g., vibration motor). The display device may include, but is not limited to, a liquid crystal display, a light-emitting diode display, and a plasma display. In some embodiments, the display device may be a touch screen.

[0117] To provide interaction with the user, the electronic device can be a computer. The computer has: a display device (e.g., a cathode ray tube or LCD monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback); and input from the user can be received in any form (e.g., voice input or tactile input).

[0118] In this embodiment, a computer-readable medium stores a computer program / instructions, which, when executed by a processor, implement a self-synchronizing reception method for UART asynchronous serial communication provided in any one or more of the above embodiments. The computer-readable medium may be included in the electronic device described in the above embodiments; or it may exist independently and not assembled into the device. The computer-readable medium carries one or more computer-readable instructions.

[0119] The memory 1102 can serve as a non-transitory computer-readable storage medium, used to store non-transitory software programs, non-transitory computer-executable programs, and modules. The processor 1101 executes various functional applications and data processing of the server by running the non-transitory software programs, instructions, and modules stored in the memory 1102, thereby implementing the program instructions / modules corresponding to the methods provided in any one or more of the embodiments described above in this application.

[0120] The memory 1102 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the electronic device. Furthermore, the memory 1102 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory 1102 may optionally include memory remotely located relative to the processor 1101, and these remote memories can be connected to the electronic device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0121] It should be noted that the computer-readable medium described in this application can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. Computer-readable media can be, for example, but not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to, electrical connections having one or more wires, portable computer disks, hard disks, random access memory, read-only memory, erasable programmable read-only memory, optical fibers, portable compact disk read-only memory, optical storage devices, magnetic storage devices, or any suitable combination thereof. In this application, a computer-readable medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0122] Computer-readable media include permanent and non-permanent, removable and non-removable media, which can store information by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory, static random access memory, dynamic random access memory, other types of random access memory, read-only memory, electrically erasable programmable read-only memory, flash memory or other memory technologies, read-only optical discs, digital versatile optical discs or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0123] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including local area networks (LANs) or wide area networks (WANs), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0124] In the above embodiments, all or part of the implementation can be achieved through software, hardware, firmware, or any combination thereof. For example, it can be implemented using an application-specific integrated circuit (ASIC), a general-purpose computer, or any other similar hardware device. In some embodiments, the software program of this application can be executed by a processor to implement the above steps or functions. Similarly, the software program of this application (including related data structures) can be stored in a computer-readable recording medium, such as RAM memory, magnetic or optical drives, floppy disks, and similar devices. In addition, some steps or functions of this application can be implemented in hardware, for example, as circuitry that cooperates with a processor to perform the various steps or functions.

[0125] The computer program product provided in this application includes one or more computer programs / instructions. When executed by a processor, these computer programs / instructions generate, in whole or in part, the processes or functions described in this application. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive), etc.

[0126] The flowcharts or block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of devices, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-specific system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0127] The scope of this application is defined by the appended claims rather than the foregoing description, and is therefore intended to encompass all variations falling within the meaning and scope of equivalents of the claims. No reference numerals in the claims should be construed as limiting the scope of the claims. Furthermore, it is clear that the word "comprising" does not exclude other units or steps, and the singular does not exclude the plural. Multiple units or devices recited in a device claim may also be implemented by a single unit or device in software or hardware. Terms such as "first," "second," etc., are used only for distinguishing descriptions and do not indicate any particular order, nor should they be construed as indicating or implying relative importance.

[0128] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily made by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims, and the above embodiments should be regarded as exemplary and non-limiting.

Claims

1. A self-synchronizing receiving method for UART asynchronous serial communication, characterized in that, include: The serial input signal of the UART receive pin is continuously sampled, and a window sequence that is updated over time is formed according to a preset window length. The window sequence is subjected to synchronization mode detection. When the window sequence meets the preset synchronization mode, a synchronization trigger signal is generated. Synchronization hold control is performed when the synchronization trigger signal is generated, new synchronization triggers are blocked during the synchronization hold period, and a synchronization enable signal for bit timing is output based on the synchronization trigger signal, including: When the synchronization trigger signal is generated, a synchronization hold timer is started, and a delay counter is constructed based on the synchronization trigger signal, so that the delay counter accumulates the bit time offset; When the accumulated count of the delay counter reaches the target count value for aligning the data bit center, a synchronization enable signal is generated, and the synchronization enable signal is output in the form of a single-cycle pulse as a bit timing reference. During the effective period of the synchronization hold timer, time masking is performed on the monitored synchronization candidate events, so that the synchronization candidate events located within the effective period of the timer are judged as pseudo-synchronization events and do not trigger new synchronization behavior; The synchronization enable signal is used to trigger bit-level parsing of the received serial data and drive the receive state update in order to receive a complete frame of data.

2. The self-synchronizing reception method for UART asynchronous serial communication according to claim 1, characterized in that, The step of continuously sampling the serial input signal of the UART receive pin and forming a time-updated window sequence according to a preset window length includes: A sampling clock for performing data bit oversampling is obtained by dividing the high-frequency system clock. The effective sampling frequency of the sampling clock and the target baud rate satisfy a preset ratio of five times, so as to form five sampling time slots with basic equal time intervals in each data bit period. When each sampling time slot arrives, the level signal of the UART receive pin is sampled once to obtain five oversampling results in each data bit period, forming a sampling sequence arranged in chronological order; The latest sampling sequence is moved into a shift register with a preset window length of five in chronological order, and historical sampling sequences that exceed the window length are moved out in a first-in-first-out manner, so that the shift register always maintains the chronological arrangement of the five most recent sampling results, thereby forming a window sequence that slides and updates over time.

3. The self-synchronizing reception method for UART asynchronous serial communication according to claim 1, characterized in that, The step of performing synchronization mode detection on the window sequence, and generating a synchronization trigger signal when the window sequence meets a preset synchronization mode, includes: The window sequence is compared with the corresponding bit in the synchronization mode to determine whether the window sequence matches the synchronization mode. The synchronization mode includes a continuous low-level mode for identifying the start bit, a continuous high-level mode for identifying the idle state, and a transition mode for identifying stable edge transitions. The synchronization trigger signal is generated when any synchronization mode perfectly matches the window sequence and is not currently in a synchronization lock state.

4. The self-synchronizing reception method for UART asynchronous serial communication according to claim 1, characterized in that, The self-synchronization receiving method further includes: Based on the effective count of the sampling clock between two valid synchronization trigger signals, the corresponding data bit time length is determined, and the data bit time length is recorded as a bit time reference parameter. When setting the effective period of the synchronization hold timer or setting the target count value of the delay counter, the bit time reference parameter is used to adaptively set the effective period of the timing or the target count value for bit timing control of data bits.

5. The self-synchronizing reception method for UART asynchronous serial communication according to claim 1, characterized in that, The step of triggering bit-level parsing of the received serial data and driving a receive state update using the synchronization enable signal to complete the reception of a frame of data includes: Each time a synchronization enable signal is output, the corresponding data bit sampling result is extracted from the current sampling window, and the internal state of the receiver state machine is updated according to the data bit sampling result. The receiver state machine includes a start bit confirmation state, a data bit accumulation state, a check bit determination state, and a stop bit check state. In the start bit confirmation state, the validity of the start bit level is verified based on the sampling result corresponding to the synchronization enable signal; In the data bit accumulation state, the decision result corresponding to each synchronization enable signal is shifted into the receiving register according to the predetermined data bit order; In the check bit determination state, the parsed data bits are checked for errors according to a preset check method; In the stop bit verification state, the validity of the stop bit is confirmed to generate a complete data frame reception result.

6. A self-synchronizing receiving device for UART asynchronous serial communication, characterized in that, include: The sampling module is used to continuously sample the serial input signal of the UART receive pin and form a window sequence that updates over time according to a preset window length. The pattern matching module is used to perform synchronization pattern detection on the window sequence, and generate a synchronization trigger signal when the window sequence meets the preset synchronization pattern. The synchronization control module is used to perform synchronization hold control when the synchronization trigger signal is generated, to block new synchronization triggers during the synchronization hold period, and to output a synchronization enable signal for bit timing based on the synchronization trigger signal. Specifically, it is used for: When the synchronization trigger signal is generated, a synchronization hold timer is started, and a delay counter is constructed based on the synchronization trigger signal, so that the delay counter accumulates the bit time offset; When the accumulated count of the delay counter reaches the target count value for aligning the data bit center, a synchronization enable signal is generated, and the synchronization enable signal is output in the form of a single-cycle pulse as a bit timing reference. During the effective period of the synchronization hold timer, time masking is performed on the monitored synchronization candidate events, so that the synchronization candidate events located within the effective period of the timer are judged as pseudo-synchronization events and do not trigger new synchronization behavior; The status update module is used to trigger bit-level parsing of the received serial data and drive the receive status update using the synchronization enable signal, so as to receive a complete frame of data.

7. An electronic device, characterized in that, The electronic device includes: One or more processors; and a memory storing computer program instructions that, when executed, cause the processors to perform the self-synchronizing reception method for UART asynchronous serial communication as described in any one of claims 1-5.

8. A computer-readable storage medium having a computer program and / or instructions stored thereon, characterized in that, When the computer program and / or instructions are executed by the processor, they implement the self-synchronizing reception method for UART asynchronous serial communication as described in any one of claims 1-5.

9. A computer program product, comprising a computer program and / or instructions, characterized in that, When the computer program and / or instructions are executed by the processor, they implement the self-synchronizing reception method for UART asynchronous serial communication as described in any one of claims 1-5.

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