Chip routing method and device, electronic equipment and storage medium

Abstract

The invention provides a chip routing method and device, electronic equipment and a storage medium, and relates to the technical field of chip design and manufacture, and the method comprises the steps: carrying out the first-stage interleaving among a plurality of input and output modules based on a memory address of a current data request, and determining a target input and output module; in the target input and output module, performing second-level interleaving among the plurality of links based on the memory address, and determining a target link; and performing third-level interleaving among the plurality of point-to-point channels of the target link, and determining the point-to-point channel of the current data request. According to the method and the device provided by the invention, a three-level progressive interleaving architecture which performs dynamic calculation completely based on the memory address is constructed, the problem that hardware resource consumption is sharply increased due to chip interconnection scale enlargement is solved, the chip cost and power consumption are remarkably saved, and through a step-by-step refined load balancing mechanism, the load balancing efficiency is greatly improved. The routing efficiency in the chip is improved, and the overall communication bandwidth and system performance of chip interconnection are improved.

Description

Technical Field

[0001] This application relates to the field of chip design and manufacturing technology, and in particular to a chip routing method, apparatus, electronic device and storage medium. Background Technology

[0002] In the current field of high-performance computing, interconnecting multiple graphics processing units (GPUs) and other chips into large-scale computing clusters via high-speed links has become the mainstream trend.

[0003] The relevant technologies mainly rely on routing based on register configuration to find the corresponding path. That is, for each possible destination of a data packet, a fixed transmission path is pre-configured in the hardware register. As the cluster size increases, the number of physical links used for interconnection also increases dramatically. The registers used to store routing paths also grow exponentially, leading to a sharp increase in chip design cost, power consumption and area. In addition, the link scalability is poor, and the data load is unevenly distributed on the physical links inside the chip.

[0004] Therefore, how to solve the problem of the surge in hardware resource consumption caused by the expansion of chip interconnect scale has become an urgent technical issue for the industry. Summary of the Invention

[0005] This application provides a chip routing method, apparatus, electronic device, and storage medium to solve the technical problem of a surge in hardware resource consumption caused by the expansion of chip interconnect scale.

[0006] This application provides a chip routing method, including: Based on the memory address of the current data request, the first level of interleaving is performed among multiple input / output modules to determine the target input / output module; In the target input / output module, a second-level interleaving is performed between multiple links based on the memory address to determine the target link; A third-level interleaving is performed among multiple point-to-point channels of the target link to determine the point-to-point channel of the current data request.

[0007] In some embodiments, determining the target input / output module by performing a first-level interleaving among multiple input / output modules based on the memory address of the current data request includes: Based on the preset bits in the memory address, a target input / output module is determined among the plurality of input / output modules; The preset bit is used to indicate the input / output module specified in the current data request.

[0008] In some embodiments, determining the target input / output module among the plurality of input / output modules includes: The interleaving granularity of the memory address is determined based on the first preset data block size.

[0009] In some embodiments, in the target input / output module, a second-level interleaving is performed between multiple links based on the memory address to determine the target link, including: In the case of direct chip connection, the target link connected to the target chip is determined by searching the preset link configuration table based on the chip identifier of the target chip corresponding to the current data request. The preset link configuration table is used to store multiple target chips and the target links connected to each target chip.

[0010] In some embodiments, determining the target link in the target input / output module by performing a second-level interleaving between multiple links based on the memory address includes: In a switching network scenario, the set of currently available links is determined in the target input / output module; The target link is determined based on the memory address and the set of currently available links.

[0011] In some embodiments, determining the target link based on the memory address and the currently available link set includes: The memory address is calculated based on the second preset data block size to obtain the address block index; The target link is determined by performing a modulo operation between the address block index and the number of available links in the current available link set.

[0012] In some embodiments, the step of performing third-level interleaving among multiple point-to-point channels of the target link to determine the point-to-point channel of the current data request includes: Polling is performed among multiple point-to-point channels of the target link to determine the point-to-point channel for the current data request.

[0013] This application provides a chip routing device, including: The first-level interleaving module is used to perform first-level interleaving among multiple input / output modules based on the memory address of the current data request, and to determine the target input / output module; A secondary interleaving module is used in the target input / output module to perform a second-level interleaving between multiple links based on the memory address to determine the target link; The three-level interleaving module is used to perform third-level interleaving among multiple point-to-point channels of the target link to determine the point-to-point channel of the current data request.

[0014] This application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the chip routing method when executing the computer program.

[0015] This application provides a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the chip routing method described above.

[0016] The chip routing method, apparatus, electronic device, and storage medium provided in this application construct a three-level progressive interleaved architecture that is entirely based on dynamic calculations using memory addresses. This architecture sequentially determines the input / output modules, links, and point-to-point channels for processing data requests, replacing the static routing tables that rely on large-scale registers in related technologies. This not only fundamentally solves the problem of drastically increased hardware resource consumption caused by the expansion of chip interconnect scale, significantly saving chip cost and power consumption, but also, through a progressively refined load balancing mechanism, can distribute data requests more evenly across all levels of resources in the interconnect network, such as input / output modules, links, and point-to-point channels, improving the routing efficiency within the chip and thus effectively enhancing the overall communication bandwidth and system performance of the chip interconnect. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0018] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart illustrating the chip routing method provided in this application.

[0020] Figure 2 This is a schematic diagram of the first-level interweaving provided in this application.

[0021] Figure 3 This is a schematic diagram of the chip provided in this application.

[0022] Figure 4 This is a schematic diagram of the chip routing device provided in this application.

[0023] Figure 5 This is a schematic diagram of the structure of the electronic device provided in this application.

[0024] Figure label: 210: First input / output module; 220: Second input / output module; 300: Chip; 310: Computing module; 320: Input / output module; 330: General-purpose chip interconnect fast channel; 311: First switch matrix; 312: Stream processor cluster; 321: Second switch matrix; 322: Dedicated remote communication link; 323: Point-to-point channel; 410: Level 1 interleaving module; 420: Level 2 interleaving module; 430: Level 3 interleaving module; 510: Processor; 520: Communication interface; 530: Memory; 540: Communication bus. Detailed Implementation

[0025] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0026] It should be noted that the terms "first," "second," etc., used in this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that comprises a series of steps, units, or modules is not necessarily limited to those explicitly listed, but may include other steps, units, or modules not explicitly listed or inherent to such processes, methods, products, or devices.

[0027] As chip size continues to increase, the number of chips used for interconnection and the number of links between them are growing rapidly. Routing methods in related technologies rely heavily on lookup tables configured in registers to determine data transmission paths.

[0028] In this mode, the number of routing configuration registers required for the increase of interconnect scale will increase dramatically, resulting in the following disadvantages: (1) High hardware cost: A large number of registers will occupy valuable chip area, increase power consumption and manufacturing cost; (2) Poor scalability: When it is necessary to support a larger chip cluster, the register lookup table will become extremely large and difficult to design and maintain; (3) Insufficient flexibility: The routing path is relatively fixed, which is not conducive to dynamic load balancing.

[0029] In order to address the shortcomings of related technologies, Figure 1 This is a flowchart illustrating the chip routing method provided in this application, as shown below. Figure 1 As shown, the method includes steps 110, 120 and 130.

[0030] Step 110: Based on the memory address of the current data request, perform the first level of interleaving among multiple input / output modules to determine the target input / output module.

[0031] Specifically, the chip routing method provided in this application is executed by a chip routing device or system. This device can be implemented in software, such as a chip routing program running within the chip; or it can be implemented in hardware, such as an artificial intelligence chip, computer, or server that executes the chip routing method.

[0032] The chip in this application embodiment can refer to a processor that performs high-performance computing. The chip can be a graphics processing unit (GPU), a tensor processing unit (TPU), or other types of application-specific integrated circuits (ASICs) specifically designed for artificial intelligence computing tasks.

[0033] When a computing unit inside a chip (such as a cluster of stream processors in a GPU) or an external device initiates a data request, the request must contain a memory address. This memory address is the core input of the routing algorithm in this application embodiment.

[0034] Input / output modules (IO modules) are physical or logical units within a chip specifically designed for handling data input and output. Physically, an IO module can be a self-packaged IO die that integrates the physical interface for external communication. Logically, an IO module can also be a functional area partitioned off from the on-chip system, integrating multiple communication controllers. The chip in this embodiment may include two or more such IO modules to provide high-bandwidth external communication capabilities.

[0035] Interleaving refers to distributing the same memory block across different channels. In this embodiment, first-level interleaving refers to regularly and intermittently allocating received current data requests to one or more input / output modules according to their memory addresses and a preset algorithm. The allocated input / output module is the target input / output module. This allows for preliminary segmentation and load balancing of data requests at the highest communication level of the chip.

[0036] The algorithm used for the first-level interleaving can be varied. In one specific embodiment, one or more bits of a memory address can be examined, and the input / output module can be selected based on the values ​​of these bits. In another specific embodiment, a contiguous memory address space can be divided into several address blocks, and then these address blocks can be mapped to different input / output modules in turn.

[0037] For example, Figure 2 This is a schematic diagram of the first-level interlacing provided in this application, such as... Figure 2 As shown, requests for address blocks 0, 1, and 2 in the address space are sent to the first input / output module 210, while requests for address blocks 3, 4, and 5 are sent to the second input / output module 220.

[0038] Through the first level of interleaving, the data request flow that might have been concentrated on a single input / output module is effectively distributed to one or more input / output modules, thereby identifying one or more target input / output modules.

[0039] Step 120: In the target input / output module, perform a second-level interleaving between multiple links based on memory addresses to determine the target link.

[0040] Specifically, the target input / output module connects multiple links for communication between chips or between a chip and an external device.

[0041] A link refers to a high-speed data transmission channel within a chip. It can be a physical link or a logical link, such as multiple logical channels partitioned from a single wide physical port. In GPU interconnect scenarios, these links can be dedicated remote communication links (RCLinks).

[0042] The second-level interleaving is another process of data request segmentation. It also selects among multiple available links connected to the target I / O module based on the memory address of the current data request. The second-level interleaving further distributes data requests that converge on a single I / O module evenly across all its downstream links, preventing any single link from becoming a communication bottleneck.

[0043] Similar to the first-level interleaving, the specific algorithms for the second-level interleaving can also be diverse. For example, a different algorithm than the first-level interleaving can be used to calculate the memory address and map the result to a link. Alternatively, some arithmetic operation (such as modulo operation) can be performed on the memory address to determine the target link.

[0044] Through the second-level interleaving, the current data request is precisely assigned to one or more specific target links, ready for the next step of transmission.

[0045] Step 130: Perform third-level interleaving between multiple point-to-point channels of the target link to determine the point-to-point channel of the current data request.

[0046] Specifically, a logical link is usually composed of multiple finer-grained peer-to-peer (P2P) channels in parallel to aggregate bandwidth.

[0047] The third level of interleaving involves redistributing the data requests carried by the selected target link to multiple point-to-point channels that make up that link. This is the final step in achieving load balancing.

[0048] Compared to the first two levels of interleaving, the third level of interleaving processes data that has already been highly filtered and diverted. In a specific embodiment, a cyclical allocation strategy can be adopted, in which continuously arriving data packets or data requests are sequentially allocated to the 1st, 2nd, ..., Nth point-to-point channel, and then returned to the 1st, and so on.

[0049] Through the third-level interleaving, the specific physical resources to be used by the data request—one or more specific point-to-point channels—are finally determined, and the data can then be transmitted through these channels.

[0050] The chip routing method provided in this application constructs a three-level progressive interleaving architecture that is entirely based on dynamic calculations of memory addresses. It sequentially determines the input / output modules, links, and point-to-point channels for processing data requests, replacing the static routing tables that rely on large-scale registers in related technologies. This not only fundamentally solves the problem of drastically increased hardware resource consumption caused by the expansion of chip interconnect scale, significantly saving chip cost and power consumption, but also, through a progressively refined load balancing mechanism, can distribute data requests more evenly across all levels of resources in the interconnect network, such as input / output modules, links, and point-to-point channels, improving the routing efficiency within the chip and thus effectively enhancing the overall communication bandwidth and system performance of the chip interconnect.

[0051] It should be noted that each implementation method of this application can be freely combined, rearranged, or executed individually, and does not need to rely on or depend on a fixed execution order.

[0052] In some embodiments, based on the memory address of the current data request, a first-level interleaving is performed among multiple input / output modules to determine the target input / output module, including: The target input / output module is determined among multiple input / output modules based on preset bits in the memory address; The preset bits are used to indicate the input / output module specified in the current data request.

[0053] Specifically, a preset bit refers to one or more predefined bits located in a memory address. These bits are assigned special routing meanings, and their values ​​directly determine which input / output module the data request will be directed to.

[0054] For example, a high-performance chip (such as a GPU) integrates two input / output modules: I / O module 0 (IO Die 0) and I / O module 1 (IO Die 1). To interleave between these two modules, a specific bit in the memory address, such as bit 13, can be set to a preset bit. When the routing device in this chip receives a data request, it performs the following operations: parses the data request and extracts its target memory address; checks the value of bit 13 of that memory address; if the value of bit 13 is "0", the data request is forwarded to I / O module 0; if the value of bit 13 is "1", the data request is forwarded to I / O module 1.

[0055] In this way, all accesses to memory addresses are automatically and one-to-one assigned to one of the two input / output modules based on their address values. Since memory addresses accessed by a program in a typical computing task are usually contiguous or distributed over a large range, this single-bit-based interleaving method can achieve efficient load balancing with extremely low hardware overhead (only one bit needs to be checked).

[0056] It should be noted that the choice of preset bits is flexible. You can choose either relatively high or low bits in the address, depending on the system memory mapping design and the desired interleaving behavior.

[0057] Furthermore, there can be multiple preset bits. For example, if the chip contains four input / output modules (modules 0, 1, 2, and 3), two bits in the memory address (such as bits 13 and 14) can be selected as preset bits. In this case, the routing logic can determine the target input / output module based on the combination of these two bits.

[0058] The chip routing method provided in this application determines the target input / output module based on preset bits and encodes the high-level routing decision information into the memory address itself, eliminating the need for a large number of registers to store the path selection of the input / output module, thus reducing hardware cost and power consumption. At the same time, since its judgment logic is only bit checking and selection, it reduces the routing calculation delay, thereby improving the efficiency of internal chip routing.

[0059] In some embodiments, determining a target input / output module among a plurality of input / output modules includes: The interleaving granularity of memory addresses is determined based on the first preset data block size.

[0060] Specifically, interleaving granularity refers to the size of the contiguous memory address blocks used for interleaving. Interleaving granularity defines that an address block of a given size will be consistently mapped to the same input / output module, and only after this size is exceeded will the next address block of the same size be mapped to a different input / output module. The first preset data block size is a parameter that can be determined during chip design or system configuration. The interleaving granularity can be determined based on the first preset data block size.

[0061] In one specific embodiment, the first preset data block size can be set to 8 kilobytes (8KB). The specific behavior of the first-level interleaving is as follows: all data requests from memory addresses 0 to 8KB-1 will be routed to input / output module 0. All data requests from memory addresses 8KB to 16KB-1 will be routed to input / output module 1. All data requests from memory addresses 16KB to 24KB-1 will be routed back to input / output module 0. This process repeats continuously, in which the chip alternately distributes data requests between the two input / output modules in 8KB units.

[0062] In another specific embodiment, the first preset data block size is not fixed. It can be adjusted according to different application scenarios, memory management strategies, or hardware designs. For example, for applications with small data blocks and intensive random access, a smaller interleaving granularity can be used to improve the immediacy of load balancing; while for applications with large data blocks and primarily sequential access, a larger interleaving granularity can be used to reduce unnecessary input / output module switching overhead and potentially improve data locality.

[0063] The chip routing method provided in this application embodiment can flexibly determine the interleaving granularity of memory addresses by setting a first preset data block size, thereby improving the efficiency of internal chip routing.

[0064] In some embodiments, in the target input / output module, a second-level interleaving is performed between multiple links based on memory addresses to determine the target link, including: In the case of direct chip connection, the target link is determined by searching the preset link configuration table based on the chip identifier of the target chip corresponding to the current data request. The preset link configuration table is used to store multiple target chips and the target links connected to each target chip.

[0065] Specifically, direct chip interconnection refers to the direct interconnection of multiple chips (such as a high-performance computing node containing 2, 4, or 8 GPUs) via a point-to-point high-speed link, without the need for external switching equipment. In this scenario, the connection relationship between any two chips is relatively fixed.

[0066] The target chip's chip identifier is a unique identifier assigned to each chip in a multi-chip system. For example, in a system with 8 GPUs, the chip identifiers of each GPU can be 0, 1, 2, ..., 7. When a source chip (e.g., GPU0) needs to send data to a target chip (e.g., GPU5), the data request will include the target chip's chip identifier "5".

[0067] The preset link configuration table is a key but extremely simplified data structure in this application embodiment. Unlike the large lookup tables in related technologies that store complete routing paths, the preset link configuration table implemented in this application only stores available links between chips. In terms of hardware implementation, this can be a static table composed of a small number of registers, requiring only the storage of multiple port masks, and its size is extremely small, significantly reducing hardware costs. One port corresponds to one link.

[0068] The core of this table is a mapping relationship, where the key is the chip identifier of the target chip, and the value is a set of available links. This set can be efficiently represented using a port mask. A port mask is a binary bit string, where each bit corresponds to a physical link port. If a bit is "1", it means the corresponding link is available to the target chip; if it is "0", it means it is unavailable.

[0069] For example, the source chip is identified as GPU0, which connects to other GPUs through eight link ports (ports 0-7) on its input / output module. The system topology specifies that GPU0 can reach GPU5 via ports 2, 3, and 6. Therefore, in GPU0's preset link configuration table, the entry corresponding to the target chip identifier "5" has a port mask value of binary 01001100. When GPU0's routing logic receives a data request destined for GPU5, it performs a retrieval operation: using "5" as an index, it looks up the preset link configuration table and obtains the port mask 01001100. This mask means that the second-level interleaving can only be selected from the three available links: port 2, port 3, and port 6. These three available links are the target links.

[0070] The chip routing method provided in this application embodiment can directly determine the target link connected to the target chip through a preset link configuration table in the case of direct chip connection, thereby improving the efficiency of internal chip routing.

[0071] In some embodiments, in the target input / output module, a second-level interleaving is performed between multiple links based on memory addresses to determine the target link, including: In a switched network scenario, the set of currently available links is determined in the target input / output module; The target link is determined based on the memory address and the set of currently available links.

[0072] Specifically, a switched network scenario refers to a situation where a large number of chips (such as a cluster of more than 8 GPUs) are not directly interconnected point-to-point, but are connected together through one or more external high-performance switching devices. In this architecture, theoretically, any other chip in the network can be reached from any source chip, and all outbound links are logically considered peers because they are all connected to the unified communication plane of the switched network.

[0073] Unlike direct connection scenarios, routing decisions in switched network scenarios do not need to consider the final target chip identifier, because it is assumed that all outbound links can reach any destination through the switched network. Therefore, it is necessary to determine the set of currently available links based on their usage status among all links in the target input / output module.

[0074] This determination process can be dynamic. For example, the input / output module of a chip typically contains link management logic that continuously monitors the status of each physical link (e.g., whether the link has been successfully initialized, whether a fault has occurred, etc.). When making routing decisions, a state vector or mask can be obtained from the link management unit in real time to determine which links are currently active and available. For example, an input / output module has 8 link ports (ports 0-7). At a certain moment, ports 4 and 5 are inactive due to maintenance or a fault. At this time, the set of currently available links can be determined as {0,1,2,3,6,7}. This set can be represented in the hardware as a dynamically updated vector or list, i.e., the set of currently available links available_port_vec={0,1,2,3,6,7}.

[0075] After determining the set of currently available links, embodiments of this application can evenly distribute data requests across all the determined available links based on their memory addresses. The specific algorithm can be varied; for example, a hash calculation can be performed on the memory addresses, and the result can be mapped to an index in the set of available links.

[0076] The chip routing method provided in this application embodiment calculates each route based on the current real-time available link set in a switching network scenario, which has fault tolerance capability. New data requests are naturally and evenly distributed to available links. The whole process does not require any software intervention, which improves the high availability and communication performance of chip routing.

[0077] In some embodiments, determining the target link based on the memory address and the currently available set of links includes: The memory address is calculated based on the second preset data block size to obtain the address block index; The target link is determined by performing a modulo operation between the address block index and the number of available links in the current set of available links.

[0078] Specifically, the second preset data block size specifies the granularity of memory address calculation during link selection. This parameter can be the same as or different from the first preset data block size mentioned in the first-level interleaving. In a specific embodiment, the second preset data block size can be set to 512 bytes.

[0079] The address block index is an integer value calculated from the original memory address. For example, integer division can be used, with the formula: Address Block Index = Memory Address / Second Preset Data Block Size. In hardware implementation, this is equivalent to a simple right shift operation, with very low overhead. For example, if the memory address is `addr` and the second preset data block size is `block_size`, then the address block index is `addr / block_size`.

[0080] If a data request requests memory address addr=1200 and the second preset data block size is block_size=512, then its address block index is 1200 / 512=2. If another request requests memory address addr=2048, then its address block index is 2048 / 512=4. In this way, contiguous, large-range memory addresses are transformed into contiguous, small-range integer indices.

[0081] Modulo operation is a basic arithmetic operation that calculates the remainder when one number is divided by another. In this embodiment, modulo operation is used to implement a simple and fair round-robin allocation mechanism. Assuming the current available link set is available_port_vec={0,1,2,3,6,7}, then the number of available links available_port_vec_size is 6. The chip routing device will perform the following modulo operation: Link index = Address block index % Number of available links.

[0082] For address addr=1200, its address block index is 2. Link index = 2%6 = 2.

[0083] For address addr=2048, its address block index is 4. Link index = 4%6 = 4.

[0084] For address addr=3072, its address block index is 6. Link index = 6%6 = 0.

[0085] For address addr=3584, its address block index is 7. The link index = 7%6 = 1.

[0086] Finally, using the calculated link index, the target link can be obtained by addressing within the currently available link set (available_port_vec).

[0087] The entire method can be expressed by the following formula: Port_id=available_port_vec[(addr / block_size)%available_port_vec_size].

[0088] Where Port_id is the link index corresponding to the target link.

[0089] The link index is 2, corresponding to available_port_vec[2], and the target link is port 2.

[0090] The link index is 4, corresponding to available_port_vec[4], and the target link is port 6.

[0091] The link index is 0, corresponding to available_port_vec[0], and the target link is port 0.

[0092] The link index is 1, corresponding to available_port_vec[1], and the target link is port 1.

[0093] As can be seen, with the linear growth of memory addresses, data requests are sequentially and cyclically allocated to each available link port in the current set of available links, achieving a uniform distribution across all available links.

[0094] The chip routing method provided in this application embodiment achieves dynamic load balancing in a switching network scenario through address block index calculation and modulo operation; it can be completed using only integer division and modulo operations, resulting in extremely low latency in routing decisions and minimal resource consumption; at the same time, data requests are fairly distributed to each available link, thereby maximizing the utilization of total communication bandwidth.

[0095] In some embodiments, a third-level interleaving is performed among multiple point-to-point channels of the target link to determine the point-to-point channel of the current data request, including: Polling is performed among multiple point-to-point channels on the target link to determine the point-to-point channel for the current data request.

[0096] Specifically, a point-to-point channel refers to a more granular physical or logical sub-channel that constitutes a logical link. The purpose of Level 3 interleaving is to perform final, finest load balancing on the data streams that will be transmitted through the target link within the parallel point-to-point channels.

[0097] For example, after the first two stages of interleaving, a data request is determined to be sent to the target link A. The target link A contains four parallel point-to-point channels, which can be referred to as channel 0, channel 1, channel 2, and channel 3.

[0098] To enable polling interleaving among these four channels, the link's transmitting controller maintains a simple counter or status pointer. This counter ranges from 0 to 3, incrementing by 1 after each successful channel allocation and resetting to zero upon reaching its maximum value.

[0099] The specific allocation process is as follows: The first data request arrives at target link A. At this time, assume the counter value is 0. This request is allocated to channel 0. After allocation, the counter is updated to 1. The second data request arrives. At this time, the counter value is 1. This request is allocated to channel 1. After allocation, the counter is updated to 2. The third data request arrives. At this time, the counter value is 2. This request is allocated to channel 2. After allocation, the counter is updated to 3. The fourth data request arrives. At this time, the counter value is 3. This request is allocated to channel 3. After allocation, the counter is updated to 0 (because 3 is the maximum value, the next value returns to 0 in the loop). This process repeats continuously.

[0100] Through a polling mechanism, continuous data requests are fairly and orderly distributed to all point-to-point channels that constitute the target link.

[0101] The chip routing method provided in this application ensures that each point-to-point channel constituting the link is fully utilized, thereby achieving load balancing of data requests in the link.

[0102] Figure 3 This is a schematic diagram of the chip provided in this application, as shown below. Figure 3 As shown, the chip 300 may include at least one computing module (Compute Die) 310 and at least one input / output module (IO Die) 320.

[0103] The computing module includes a first switch matrix (Crossbar) 311 and multiple stream processor clusters (SPCs) 312.

[0104] The input / output module includes a second switch matrix 321 and multiple dedicated remote communication links 322. Each dedicated remote communication link includes multiple point-to-point channels 323.

[0105] The computing module and the input / output module are connected via the Universal Chiplet Interconnect express (UCIe).

[0106] In this chip, firstly, based on the memory address of the current data request, a first-level interleaving is performed between multiple input / output modules to determine the target input / output module; then, within the target input / output module, a second-level interleaving is performed between multiple links based on the memory address to determine the target link; finally, a third-level interleaving is performed between multiple point-to-point channels of the target link to determine the point-to-point channel of the current data request.

[0107] By employing the aforementioned chip routing method, a three-level progressive interleaving architecture based entirely on dynamic calculations using memory addresses is constructed, eliminating the need for static routing tables in large-scale registers within the chip. This not only fundamentally solves the problem of drastically increased hardware resource consumption caused by the expansion of chip interconnect scale, significantly saving chip cost and power consumption, but also, through a progressively refined load balancing mechanism, enables data requests to be more evenly distributed across various levels of resources in the entire interconnect network, such as input / output modules, links, and point-to-point channels, thereby improving the routing efficiency within the chip.

[0108] The apparatus provided in the embodiments of this application is described below. The apparatus described below can be referred to in correspondence with the method described above.

[0109] Figure 4 This is a schematic diagram of the chip routing device provided in this application, as shown below. Figure 4 As shown, the device includes: The first-level interleaving module 410 is used to perform first-level interleaving among multiple input / output modules based on the memory address of the current data request, and to determine the target input / output module; The second-level interleaving module 420 is used to perform second-level interleaving between multiple links based on memory addresses in the target input / output module to determine the target link; The Level 3 Interleaving Module 430 is used to perform Level 3 interleaving between multiple point-to-point channels of the target link to determine the point-to-point channel of the current data request.

[0110] The chip routing device provided in this application constructs a three-level progressive interleaving architecture that is entirely based on dynamic calculation of memory addresses. It sequentially determines the input / output modules, links, and point-to-point channels for processing data requests, replacing the static routing table that relies on large-scale registers in related technologies. This not only fundamentally solves the problem of a surge in hardware resource consumption caused by the expansion of chip interconnect scale, significantly saving chip cost and power consumption, but also, through a progressively refined load balancing mechanism, can distribute data requests more evenly across all levels of resources in the interconnect network, such as input / output modules, links, and point-to-point channels, improving the routing efficiency within the chip and thus effectively enhancing the overall communication bandwidth and system performance of the chip interconnect.

[0111] Figure 5 This is a schematic diagram of the structure of the electronic device provided in this application, such as... Figure 5 As shown, the electronic device may include: a processor 510, a communications interface 520, a memory 530, and a communications bus 540, wherein the processor 510, the communications interface 520, and the memory 530 communicate with each other via the communications bus 540. The processor 510 can call logical commands stored in the memory 530 to execute the methods described in the above embodiments, for example: Based on the memory address of the current data request, a first-level interleaving is performed between multiple input / output modules to determine the target input / output module; within the target input / output module, a second-level interleaving is performed between multiple links based on the memory address to determine the target link; and a third-level interleaving is performed between multiple point-to-point channels of the target link to determine the point-to-point channel of the current data request.

[0112] Furthermore, the logical commands in the aforementioned memory can be implemented as software functional units and sold or used as independent products, and can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several commands to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0113] The processor in the electronic device provided in this application embodiment can call logical instructions in the memory to implement the above method. Its specific implementation method is the same as the aforementioned method implementation method and can achieve the same beneficial effect, which will not be repeated here.

[0114] This application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to perform the methods provided in the above embodiments.

[0115] The specific implementation method is the same as the aforementioned method implementation method and can achieve the same beneficial effects, so it will not be repeated here.

[0116] This application provides a computer program product, including a computer program that, when executed by a processor, implements the method described above.

[0117] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0118] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0119] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A method of chip routing, characterized by, The method comprises the following steps: determining a target input / output module among a plurality of input / output modules based on a memory address of a current data request through first-level interleaving; determining a target link among a plurality of links in the target input / output module based on the memory address through second-level interleaving; determining a point-to-point channel of the current data request among a plurality of point-to-point channels of the target link through third-level interleaving.

2. The chip routing method of claim 1, wherein, The step of determining the target input / output module among the plurality of input / output modules based on the memory address of the current data request through the first-level interleaving comprises the following steps: determining the target input / output module among the plurality of input / output modules based on a preset bit in the memory address; wherein the preset bit is used to indicate an input / output module specified by the current data request.

3. The chip routing method of claim 2, wherein, The step of determining the target input / output module among the plurality of input / output modules comprises the following steps: determining an interleaving granularity of the memory address based on a first preset data block size.

4. The chip routing method of claim 1, wherein, The step of determining the target link among the plurality of links in the target input / output module based on the memory address through the second-level interleaving comprises the following steps: in a chip direct connection scenario, searching a preset link configuration table based on a chip identifier of a target chip corresponding to the current data request to determine a target link connected to the target chip; wherein the preset link configuration table is used to store a plurality of target chips and target links connected to each target chip.

5. The chip routing method of claim 1, wherein, The step of determining the target link among the plurality of links in the target input / output module based on the memory address through the second-level interleaving comprises the following steps: in a switching network scenario, determining a current available link set in the target input / output module; determining the target link based on the memory address and the current available link set.

6. The chip routing method of claim 5, wherein, The step of determining the target link based on the memory address and the current available link set comprises the following steps: calculating the memory address based on a second preset data block size to obtain an address block index; determining the target link by performing a modulo operation on the address block index and a number of available links in the current available link set.

7. The chip routing method of claim 1, wherein, The step of determining the point-to-point channel of the current data request among the plurality of point-to-point channels of the target link through the third-level interleaving comprises the following steps: determining the point-to-point channel of the current data request among the plurality of point-to-point channels of the target link through polling.

8. A chip routing device, characterized by The method comprises the following steps: a first-level interleaving module is configured to determine a target input / output module among a plurality of input / output modules based on a memory address of a current data request through first-level interleaving; a second-level interleaving module is configured to determine a target link among a plurality of links in the target input / output module based on the memory address through second-level interleaving; a third-level interleaving module is configured to determine a point-to-point channel of the current data request among a plurality of point-to-point channels of the target link through third-level interleaving.

9. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the chip routing method in any one of claims 1 to 7. 10.A non-transitory computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the chip routing method in any one of claims 1 to 7.

Images