Pixel driving circuit, display panel and display device

Abstract

The invention provides a pixel driving circuit, a display panel and a display device. The pixel driving circuit comprises a light-emitting driving branch which comprises a driving transistor, a first electrode of the driving transistor is electrically connected with a first node, a second electrode is electrically connected with a second node, and a grid electrode is electrically connected with a third node; the data voltage write-in branch comprises a first switch transistor, a second switch transistor and a first capacitor; the threshold compensation module is used for compensating the threshold of the driving transistor; a first pole plate of the second capacitor is electrically connected with the first voltage end, and a second pole plate of the second capacitor is electrically connected with the third node; the second capacitor is configured to couple the third node in response to voltage jump at the first voltage end and adjust the gate potential of the driving transistor. According to the pixel driving circuit provided by the invention, at least the driving voltage range can be regulated and controlled.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically, to a pixel driving circuit, a display panel, and a display device. Background Technology

[0002] With the rapid development of display technology towards larger sizes and higher refresh rates, the number of pixels in display panels has increased dramatically, significantly lengthening the power transmission path and leading to increasingly severe voltage drops in the power supply (PVDD and PVEE). This voltage drop causes differences in the actual operating voltage of different display areas. When the gate reset voltage source of the pixel circuit driving transistors uses the power supply voltage (PVDD for N-type driving transistors and PVEE for P-type driving transistors), the uneven power supply voltage across different areas of the display panel results in different reset voltages for the independent pixel circuits in each area. This causes display quality problems such as uneven brightness and color shift, severely affecting the visual effect of large-scale display devices.

[0003] Secondly, the electrical characteristics of TFT transistors in pixel driving circuits are strongly dependent on the manufacturing process. Various characteristics of TFT devices need to maintain a certain level of stability throughout the device's operational lifespan. Therefore, the threshold voltage (V) of a stable TFT device corresponding to a particular semiconductor material is crucial. th The adjustable range of the data voltage is relatively small. To match the electrical characteristics of the device itself and the data output specifications of the display panel driver chip (IC), pixel driving circuits often use the method of adjusting the data voltage range. One approach is to raise or lower the overall potential to adjust the output potential of the data voltage, but this method is strictly limited by the physical specifications of the driver chip (IC) and carries the risk of exceeding the electrical safety range; at the same time, when the data voltage switches near zero volts, the accuracy of positive and negative potential conversion decreases, further affecting grayscale accuracy. Another approach is to utilize the coupling effect of the light emission control signal (EM) to improve the effective range of the data voltage, but when the light emission control signal has multiple pulses, the gate voltage stability of the driver transistor is poor, leading to brightness fluctuations and flickering.

[0004] Therefore, there is an urgent need for a new type of pixel driving circuit to overcome the shortcomings of existing technical solutions. Summary of the Invention

[0005] In view of the above, the purpose of this invention is to solve at least one of the problems existing in the prior art. More specifically, this invention aims to provide a pixel driving circuit, a display panel, and a display device to solve the problem of uneven brightness caused by differences in the gate reset voltage of the driving transistors in different areas of the display panel due to power supply voltage drop. At the same time, it solves the matching problem between the electrical characteristics of the driving transistors and the IC specifications, and improves the display effect of the pixel driving circuit driving the light-emitting device to emit light.

[0006] In a first aspect, the present invention provides a pixel driving circuit, comprising:

[0007] The light-emitting driving branch includes a driving transistor, the first terminal of the driving transistor is electrically connected to a first node, the second terminal of the driving transistor is electrically connected to a second node, and the gate of the driving transistor is electrically connected to a third node, for providing driving current to the light-emitting device.

[0008] The data voltage write branch includes a first switching transistor, a second switching transistor, and a first capacitor, which are used for threshold compensation of the driving transistor.

[0009] In this configuration, the first terminal of the first switching transistor is electrically connected to the data voltage terminal, and the second terminal of the first switching transistor is electrically connected to either the first node or the second node; the first terminal of the second switching transistor is electrically connected to the third node, and the second terminal of the second switching transistor is electrically connected to either the second node or the first node; the gates of both the first and second switching transistors are electrically connected to the first control signal terminal; the first plate of the first capacitor is electrically connected to the third node, and the second plate of the first capacitor is electrically connected to the anode of the light-emitting device through a fourth node; and

[0010] The second capacitor has its first plate electrically connected to the first voltage terminal and its second plate electrically connected to the third node.

[0011] The second capacitor is configured to couple a third node in response to a voltage jump at the first voltage terminal, thereby adjusting the gate potential of the driving transistor.

[0012] In a second aspect, the present invention provides a display panel including the pixel driving circuit as provided in the first aspect.

[0013] Thirdly, the present invention provides a display device including a display panel as provided in the second aspect.

[0014] Compared with the prior art, the pixel driving circuit provided by the present invention achieves at least the following beneficial effects:

[0015] The pixel driving circuit provided by this invention introduces a first voltage terminal into the pixel driving circuit. A first reference voltage signal is input as a reset signal to adjust the voltage of the driving transistor gate. This avoids using a power supply voltage signal with a certain voltage drop characteristic to reset the driving transistor gate, ensuring that all pixel driving circuits in the display panel return to a uniform initial voltage, thus improving the uniformity of display brightness. Furthermore, a second capacitor is introduced as a bias capacitor. The transition of the first reference voltage signal input to the first voltage terminal serves as a bias signal, adjusting the voltage range of the data voltage written to the driving transistor gate. This ensures normal driving of both bright and dark display states, ultimately achieving a more uniform and stable display effect. This design is particularly suitable for pixel driving circuits where the data voltage range is limited to all positive or all negative values, and is compatible with the potential setting specifications of conventional driving chips.

[0016] Furthermore, the display panel and display device provided by the present invention, by using the pixel driving circuit provided in the first aspect, further solve the problems of uneven display effect caused by the use of a power supply voltage with voltage drop characteristics for the reset voltage, and the problem of mismatch between the data voltage (data range) required by the pixel circuit and the IC specifications. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments of the present invention will be described below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of a pixel driving circuit in the prior art;

[0019] Figure 2 This is a timing diagram of a pixel driving circuit in the prior art;

[0020] Figure 3 This is a schematic diagram of the pixel driving circuit provided in one embodiment of the present invention;

[0021] Figure 4 This is a schematic diagram of the pixel driving circuit provided in another embodiment of the present invention;

[0022] Figure 5 This is a circuit timing diagram of a pixel driving circuit provided in one embodiment of the present invention;

[0023] Figure 6 This is a circuit timing diagram of a pixel driving circuit provided in another embodiment of the present invention;

[0024] Figure 7 This is a circuit timing diagram of a pixel driving circuit provided in one embodiment of the present invention;

[0025] Figure 8 This is a schematic diagram of the pixel driving circuit in stage t1 provided by an embodiment of the present invention;

[0026] Figure 9 This is a schematic diagram of the pixel driving circuit in stage t2 provided by an embodiment of the present invention;

[0027] Figure 10 This is a schematic diagram of the pixel driving circuit in stage t3 provided by an embodiment of the present invention;

[0028] Figure 11 This is a schematic diagram of the pixel driving circuit in stage t4 provided by an embodiment of the present invention;

[0029] Figure 12 This is a schematic diagram of the pixel driving circuit in stage t5 provided by an embodiment of the present invention;

[0030] Figure 13 This is a schematic diagram of the pixel driving circuit in stage t6 provided by an embodiment of the present invention;

[0031] Figure 14 This is a schematic diagram of the structure of a display panel provided in one embodiment of the present invention;

[0032] Figure 15 This is a schematic diagram of the structure of a display device provided in one embodiment of the present invention.

[0033] Marked in the image:

[0034] 0: Display device;

[0035] 00: Display panel;

[0036] 10: Pixel driving circuit; 20: Light-emitting device;

[0037] T0: drive transistor, T1: first switching transistor, T2: second switching transistor, T3: third switching transistor, T4: fourth switching transistor, T5: fifth switching transistor, T6: sixth switching transistor;

[0038] G n : First control signal terminal, G n-1 Second control signal terminal, Reset; Third control signal terminal, EM n Fourth control signal terminal, EM n-1 Fifth control signal terminal;

[0039] N1: First node, N2: Second node, N3: Third node, N4: Fourth node;

[0040] C1: First capacitor, C2: Second capacitor;

[0041] Vref1: First voltage terminal, Vref2: Second voltage terminal, PVDD: First power supply voltage terminal, PVEE: Second power supply voltage terminal

[0042] 10': Pixel driving circuit in the prior art; 20': Light-emitting device in the prior art;

[0043] T0': driving transistor in the prior art; T1': first switching transistor in the prior art; T2': second switching transistor in the prior art; T4': fourth switching transistor in the prior art; T5': fifth switching transistor in the prior art; T6': sixth switching transistor in the prior art.

[0044] G1: First control signal terminal in the prior art; G2: Second control signal terminal in the prior art; G3: Third control signal terminal in the prior art; EM1: First light emission control signal terminal in the prior art; EM2: Second light emission control signal terminal in the prior art.

[0045] N1': The first node in the prior art; N2': The second node in the prior art; N3': The third node in the prior art; N4': The fourth node in the prior art.

[0046] C1': The first capacitor in the prior art;

[0047] Vref1': First voltage terminal in the prior art, PVDD': First power supply voltage terminal in the prior art, PVEE': Second power supply voltage terminal in the prior art. Detailed Implementation

[0048] The features of the inventive concept and its implementation methods can be more readily understood by referring to the detailed description and accompanying drawings of the following embodiments. However, the inventive concept can be embodied in many different forms and should not be considered limited to the embodiments presented herein. In the following, exemplary embodiments will be described in more detail with reference to the accompanying drawings, wherein the same reference numerals denote the same elements throughout the drawings. However, the invention can be embodied in various different forms and should not be considered limited to the embodiments shown herein. Rather, these embodiments are provided as examples so that the invention will be sufficient and complete, and will fully convey aspects and features of the invention to those skilled in the art. Therefore, processes, elements, and techniques that are not essential for a complete understanding of the aspects and features of the invention may not be described to those skilled in the art. Unless otherwise stated, the same reference numerals denote the same elements throughout the drawings and written description, and therefore their description will not be repeated.

[0049] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0050] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0051] In embodiments of the present invention, the term "electrical connection" may refer to a direct electrical connection between two components, or it may refer to an electrical connection between two components via one or more other components.

[0052] In this embodiment of the invention, the first node, the second node, the third node, and the fourth node are defined only for the convenience of describing the circuit structure, and the first node, the second node, the third node, and the fourth node are not actual circuit units.

[0053] Various modifications and variations can be made to this invention without departing from its spirit or scope, as will be apparent to those skilled in the art. Therefore, this invention is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this invention can be combined with each other without contradiction.

[0054] The large voltage drop (PVDD or PVEE drop) of the power supply panel in existing medium and large-sized OLED products makes them unsuitable as the gate reset voltage source for driving transistors, often requiring the introduction of a new DC Vref voltage signal. Simultaneously, the process conditions and device stability requirements of TFT transistors limit the adjustable range of the device's electrical characteristic Vth, leading to a mismatch between the data range required by the pixel driving circuit and the IC specifications. Currently, one solution is to raise or lower the overall driving IC potential (including VGH, VGL, PVDD, PVEE, Vref, etc.) so that the IC can still support normal display of the image on the panel. This may require setting extremely high voltages, but existing driving ICs generally do not support extremely high output potentials. Therefore, raising or lowering the overall driving IC potential will exceed the driving IC's set potential specifications. Furthermore, the data voltage range required by the pixel driving circuit is near 0V, resulting in low accuracy of the driving IC's data voltage output value when switching between positive and negative values, thus affecting display accuracy. Another solution is to improve the range of data voltage through the coupling effect of the luminous emission control signal (EM). However, this method requires multiple pulses (pluses) of the luminous emission control signal, which gradually deteriorates the potential stability of the driving transistor gate, still affecting display uniformity. To address this, the present invention provides a pixel driving circuit, a display panel, and a display device. By adding a reference voltage and a capacitor to the pixel driving circuit, voltage jumps and capacitive coupling are used to create a voltage bias at the potential of the driving transistor gate, ensuring that the display panel can still display a normal, stable, and uniform image even when the data voltage is in a fully positive or fully negative range. This solves the problem of uneven display caused by using a power supply voltage with voltage drop characteristics for the reset voltage, while also avoiding the need for the driver chip to switch between positive and negative output data voltages.

[0055] To make the technical problems solved by the present invention, the technical solutions adopted, and the technical effects achieved clearer, the technical solutions of the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0056] Specifically, embodiments of the present invention provide a pixel driving circuit 10, see reference. Figure 3 and Figure 4 , Figure 3 This is a schematic diagram of the pixel driving circuit provided in one embodiment of the present invention; Figure 4 This is a schematic diagram of a pixel driving circuit provided in another embodiment of the present invention. The pixel driving circuit 10 includes a light-emitting driving branch, comprising a driving transistor T0. The first terminal of the driving transistor T0 is electrically connected to a first node N1, the second terminal of the driving transistor T0 is electrically connected to a second node N2, and the gate of the driving transistor T0 is electrically connected to a third node N3, for providing driving current to the light-emitting device 20. A data voltage writing branch includes a first switching transistor T1, a second switching transistor T2, and a first capacitor C1, for threshold compensation of the driving transistor T0. The first terminal of the first switching transistor T1 is electrically connected to the data voltage terminal Vdata, and the second terminal of the first switching transistor T1 is connected to either the first node N1 or the second node N2. Electrical connections are provided; the first terminal of the second switching transistor T2 is electrically connected to the third node N3, and the second terminal of the second switching transistor T2 is electrically connected to the second node N2 or the first node N1; the gates of the first switching transistor T1 and the second switching transistor T2 are both electrically connected to the first control signal terminal Gn; the first plate of the first capacitor C1 is electrically connected to the third node N3, and the second plate of the first capacitor C1 is electrically connected to the anode of the light-emitting device 20 through the fourth node N4; and the second capacitor C2, the first plate of the second capacitor C2 is electrically connected to the first voltage terminal Vref1, and the second plate of the second capacitor C2 is electrically connected to the third node N3; wherein, the second capacitor C2 is configured to adjust the gate potential of the driving transistor T0 in response to the voltage jump of the first voltage terminal Vref1 coupled to the third node N3.

[0057] like Figure 3 and Figure 4 As shown, the pixel driving circuit 10 is electrically connected to the light-emitting device 20. It should be noted that the light-emitting driving branch in the pixel driving circuit 10 refers to the circuit used to provide driving current to the light-emitting device 20 during the light-emitting stage, so as to drive the light-emitting device 20 to emit light. This light-emitting driving branch includes at least one switching transistor that drives the light-emitting device 20 to emit light. (Refer to...) Figure 3 and Figure 4 The system includes a driving transistor T0, which has a first terminal, a second terminal, and a gate. The first terminal can be either a source or a drain, and the second terminal can be either a drain or a source. The first terminal of the driving transistor T0 is connected to a first node N1, the second terminal is connected to a second node N2, and the gate is connected to a third node. The pixel driving circuit 10 is configured to generate a driving current and supply it to the light-emitting device 20 when the driving transistor T0 is turned on during the light-emitting phase, driving the light-emitting device 20 to emit light at a corresponding brightness.

[0058] The data voltage write branch refers to the circuit connected between the data voltage terminal Vdata and the gate of the driving transistor T0. It can be configured to, during the threshold compensation phase, store the data voltage provided by the data voltage terminal Vdata and the threshold voltage of the driving transistor T0 together in the storage capacitor, i.e., the first capacitor C1. This forms an effective data voltage on the gate of the driving transistor T0 after threshold voltage compensation, which is used for data voltage writing and threshold voltage compensation to the driving transistor T0. It should be noted that the data voltage write branch can include various connection methods, such as... Figure 3 and Figure 4 The connection method of the first switching transistor T1 (data writing transistor), the second switching transistor T2 (threshold compensation transistor), the first capacitor C1 and the driving transistor T0.

[0059] Optional, such as Figure 3 As shown, the data write branch is configured to process the first data voltage V input through the first switching transistor T1, the first node N1, the driving transistor T0, the second node N2, the second switching transistor T2, and the third node N3. data1 and the threshold voltage V of the driving transistor T0 th Write to the first capacitor C1 to form and maintain the second data voltage V at the third node N3. data2 The first switching transistor T1 has a first terminal, a second terminal, and a gate. The first terminal is electrically connected to the data voltage terminal Vdata. The second terminal is connected to the first terminal of the driving transistor T0 through the first node N1. The gate is electrically connected to the first control signal terminal Gn. It turns on and off in response to the first control signal (first scan signal). The second switching transistor T2 has a first terminal, a second terminal, and a gate. The first terminal of the second switching transistor T2 is connected to the gate of the driving transistor T0 and the first plate of the first capacitor C1 through the third node N3. The second terminal is connected to the second terminal of the driving transistor T0 through the second node N2. The gate is electrically connected to the first control signal terminal Gn. It turns on and off in response to the first control signal. It can be understood that the first switching transistor T1 and the second switching transistor T2 simultaneously turn on or off in response to the first control signal. When the first switching transistor T1 and the second switching transistor T2 are on, the first data voltage Vdata provided by the data voltage terminal Vdata... data1 The data is transmitted sequentially through the first switching transistor T1 and the first node N1 to the driving transistor T0. Subsequently, the first data voltage V... data1 With the threshold voltage V of the driving transistor T0 th Simultaneously, the data is stored in the first capacitor C1 through the second node N2 and the second switching transistor T2, and the second data voltage V after threshold voltage compensation is formed and maintained on the third node N3. data2.

[0060] Optional, see reference Figure 4 The data write branch is configured to process the first data voltage V input through the first switching transistor T1, the second node N2, the driving transistor T0, the first node N1, and the second switching transistor T2. data1 and the threshold voltage V of the driving transistor T0 th Write to the first capacitor C1, and form and maintain the second data voltage V at the third node N3. data2 In this configuration, the first terminal of the first switching transistor T1 is electrically connected to the data voltage terminal Vdata. The second terminal of the first switching transistor T1 is connected to the second terminal of the driving transistor T0 via the second node N2. Its gate is electrically connected to the first control signal terminal Gn, and it turns on and off in response to the first control signal (first scan signal). The first terminal of the second switching transistor T2 is connected to the first terminal of the driving transistor T0 via the first node N1. The second terminal of the second switching transistor T2 is electrically connected to the first plate of the first capacitor C1 and connected to the gate of the driving transistor T0 via the third node N3. Its gate is electrically connected to the first control signal terminal Gn, and it turns on and off in response to the first control signal. When the first switching transistor T1 and the second switching transistor T2 are both on, the first data voltage Vdata provided by the data voltage terminal Vdata... data1 The data is transmitted sequentially through the first switching transistor T1 and the second node N2 to the driving transistor T0. Subsequently, the first data voltage V... data1 With the threshold voltage V of the driving transistor T0 th Simultaneously, the data is stored in the first capacitor C1 through the first node N1 and the second switching transistor T2, and the second data voltage V after threshold voltage compensation is formed and maintained at the third node N3. data2 The first capacitor C1 serves as the storage capacitor in the pixel driving circuit 10. It is coupled between the gate of the driving transistor T0 and its first terminal, and electrically connected to the anode of the light-emitting device 20. It stores the gate voltage of the driving transistor T0 and maintains a constant gate-source voltage Vgs, thereby ensuring stable driving current. Figure 3 and Figure 4 As shown, the first capacitor C1 has a first plate and a second plate. The first plate is electrically connected to the first electrode of the third node N3 and the second transistor T2, respectively. The second plate of the first capacitor C1 is connected to the fourth node N4. It should be understood that the above embodiments are merely exemplary descriptions of the data voltage writing branch connection method and are not intended to limit the invention. Any other circuit connection method capable of achieving data writing and threshold voltage compensation functions falls within the protection scope of this invention. For ease of description, the following embodiments of this invention will uniformly use the term... Figure 3 The circuit structure shown is used as an example for explanation; its related principles and workflow are also applicable to... Figure 4 The circuit shown and other equivalent variations can be understood by those skilled in the art by referring to the following description. Figure 3 To understand this, please refer to the detailed explanation.

[0061] Furthermore, in this invention, the second capacitor C2 serves as a bias capacitor in the pixel driving circuit 10, configured to be electrically connected between the first voltage terminal Vref1 and the gate of the driving transistor T0, forming a bias branch. This bias branch is configured to generate a bias voltage in response to a voltage jump in the first reference voltage provided by the first voltage terminal Vref1 after the threshold compensation stage, biasing the gate voltage of the driving transistor T0 to a data voltage range from negative to positive. Specifically, referring to... Figure 3 In the bias branch, the first plate of the second capacitor C2 is electrically connected to the first voltage terminal Vref1, and the second plate of the second capacitor C2 is electrically connected to the gate of the driving transistor T0 and the first plate of the first capacitor C1 through the third node N3, or refer to Figure 4 The second plate of the second capacitor C2 is electrically connected to the first plate of the first capacitor C1 and the third node N3, as well as the gate of the driving transistor T0, through nodes respectively. After the data voltage writing stage and the threshold voltage compensation stage, the voltage jump at the first voltage terminal Vref1, i.e., from high potential to low potential or from low potential to high potential, causes the voltage coupling between the two plates of the second capacitor C2 to generate a bias voltage that is written to the third node N3. Since the second plate of the second capacitor C2 is electrically connected to the first plate of the first capacitor C1 and the gate of the driving transistor T0 through the third node N3, the second data voltage V is stored after the data voltage writing stage and the threshold voltage compensation stage. data2 The first capacitor C1 and the second capacitor C2, which responds to voltage jumps, form a third data voltage V at the third node N3 due to the voltage divider effect. data3 This enables the biasing of the gate voltage of the driving transistor T0.

[0062] The pixel driving circuit 10 provided in the above embodiments of the present invention achieves biasing of the voltage range of the input data voltage in the pixel driving circuit 10 by setting voltage jumps and bias capacitors, instead of adjusting the voltage range of the data voltage by raising or lowering the overall driving IC potential, thus avoiding the risk of exceeding the driving IC potential setting specifications; at the same time, adjusting the data voltage range in the pixel driving circuit 10 to a voltage range that crosses zero enables the pixel driving circuit to achieve precise control over the entire brightness range (from pure black to brightest), achieving high-quality, high-uniformity OLED display and effectively improving the display effect of the display panel.

[0063] In one alternative implementation, the data voltage range of the data voltage terminal Vdata is all positive voltages; in response to the potential jump of the first voltage terminal Vref1, the second capacitor C2 couples to the third node N3, and a negative bias value is superimposed on the potential of the third node N3.

[0064] The bias branch is configured such that the first voltage terminal Vref1 provides a first reference voltage, which is a square wave pulse with a first voltage and a second voltage different from the first voltage. After the data voltage writing stage (threshold compensation stage), the first reference voltage jumps from the first voltage to the second voltage, i.e., the bias voltage is the difference between the second voltage and the first voltage. A bias voltage greater than 0 is considered a positive bias value, i.e., ΔV. ref1 A bias voltage greater than 0 indicates a negative bias value, i.e., ΔV. ref1 Less than 0. After the voltage jump, the second capacitor C2 couples to the third node N3. The data voltage at the third node N3 is superimposed with a bias value to form the biased data voltage, V. data1 +V th +k*△V ref1 (coefficient k = C2 / C) N3_all Where C2 is the capacitance value of the second capacitor, C N3_all This is the sum of the capacitance values ​​of all capacitors between the third node N3 and other signal lines or nodes. It is understood that, in the embodiments provided in this application, C... N3_all This is the sum of the capacitance values ​​of the first capacitor C1 and the second capacitor C2. Wherein, when the first data voltage V is input at the data voltage terminal Vdata... data1 When the range is all positive values, the second data voltage V data2 When the value is greater than 0, the driving transistor T0 can only conduct and cannot be completely closed. Therefore, during the light-emitting stage of the driving light-emitting device 20, the display panel can only display a bright image and cannot display a dark (pure black) image. Therefore, refer to [reference needed]. Figure 3 and Figure 5 , Figure 5 This is a timing diagram of a pixel driving circuit provided in one embodiment of the present invention; wherein, when the first reference voltage input to the first voltage terminal Vref1 changes, the bias voltage is biased downward, that is, the first voltage is greater than the second voltage, making the bias value negative, and the positive second data voltage V data2 The superimposed negative bias value forms a third data voltage V that is less than 0. data3 This makes the first data voltage V with all positive values ​​input... data1 The voltage range, presenting the third data voltage V data3The voltage difference between the third node N3 and the first node N1 within the voltage range is suitable for controlling the driving transistor T0 to drive the light-emitting device 20, and can drive the light-emitting device 20 to display a dark (pure black) image during the light-emitting stage.

[0065] The pixel driving circuit 10 provided in the above embodiments of the present invention biases the voltage range of the gate of the driving transistor by superimposing a negative bias value on the full positive data voltage range, so that the gate voltage range has a voltage from negative to positive, which can achieve precise control in the entire brightness range (from pure black to the brightest), and further realize uniform display of images with different brightness.

[0066] In one alternative implementation, the data voltage range of the data voltage terminal Vdata is all positive voltages; in response to the potential jump of the first voltage terminal Vref1, the second capacitor C2 couples to the third node N3, and a negative bias value is superimposed on the potential of the third node N3.

[0067] It is understandable that the first data voltage V provided by the data voltage terminal Vdata... data1 When the range is all negative values, the second data voltage V data2 When the value is less than 0, the driving transistor T0 cannot be fully turned on. Therefore, during the light-emitting stage of the driving light-emitting device 20, the display panel can only display a dark image and cannot display a bright (brightest) image. Therefore, referring to the reference... Figure 3 and reference Figure 6 , Figure 6 This is a timing diagram of a pixel driving circuit provided in one embodiment of the present invention; wherein, when the first reference voltage input to the first voltage terminal Vref1 changes, the bias voltage is biased upward, that is, the first voltage is less than the second voltage, so that the bias value is positive and the second data voltage V is negative. data2 The third data voltage V formed after superimposing this positive bias value data3 Greater than 0, so that for the first data voltage V with all negative values ​​input, data1 The voltage range, presenting the third data voltage V data3 The voltage difference between the third node N3 and the first node N1 can be adapted to control the driving transistor T0 to drive the light-emitting device 20. During the light-emitting phase, the light-emitting device 20 can be driven to display a bright (brightest) image.

[0068] The pixel driving circuit 10 provided in the above embodiments of the present invention biases the voltage range of the gate of the driving transistor by superimposing a positive bias value on the full negative data voltage range, so that the gate voltage range has a voltage range from negative to positive, which can realize precise control in the entire brightness range (from pure black to the brightest), and further realize uniform display of images with different brightness.

[0069] In an optional embodiment, the pixel driving circuit 10 further includes a first reset branch, including a third switching transistor T3; wherein, the first terminal of the third switching transistor T3 is electrically connected to the first voltage terminal Vref1, the second terminal of the third switching transistor T3 is electrically connected to the third node N3, and the gate of the third switching transistor T3 is electrically connected to the second control signal terminal Gn-1.

[0070] refer to Figure 3 The first voltage terminal Vref1 is coupled to the third node N3 through a parallel circuit of the third switching transistor T3 and the second capacitor C2. The first reference voltage input to the first voltage terminal Vref1 is a square wave pulse, having a first voltage and a second voltage different from the first voltage. Before the data voltage writing phase, the first voltage of the first reference voltage is written to the third switching transistor T3 as a reset signal. The third switching transistor T3 is turned on and off in response to the second control signal (first reset signal) provided by the second control terminal Gn-1. When the third switching transistor T3 is turned on, the gate voltage (N3 node voltage) of the driving transistor T0 is reset to the same first voltage. This configuration ensures that the voltage difference between the third node N3 and the first node N1 can turn on the driving transistor (T0) so that the first data voltage can be written during the data writing phase.

[0071] The pixel driving circuit provided in the above embodiments of the present invention resets the gate voltage of the driving transistor by using the first reference voltage input at the first voltage terminal Vref1 as the reset voltage, thereby compensating for the voltage loss during the light emission stage of the display panel, that is, compensating for the voltage drop of the power supply voltage, and realizing uniform display of the image on the display panel.

[0072] In one optional embodiment, the pixel driving circuit further includes a second reset branch, the second reset circuit including a fourth switching transistor T4; wherein, the first terminal of the fourth switching transistor T4 is electrically connected to the second voltage terminal Vref2, the second terminal of the fourth switching transistor T4 is electrically connected to the fourth node N4, and the gate of the fourth switching transistor T4 is electrically connected to the third control signal terminal Reset.

[0073] It should be noted that the second reset branch refers to the circuit that resets the anode of the light-emitting device 20 and the first electrode of the driving transistor T0 respectively during the non-light-emitting stage. (Reference) Figure 3The second reset branch is configured such that the second reference voltage provided by the second voltage terminal Vref2 can be written as a reset signal to the fourth switching transistor T4. The fourth switching transistor T4 is turned on and off in response to the third control signal (second reset signal) provided by the third control signal terminal Reset. When the fourth switching transistor T4 is on, the second reference voltage is coupled to the fourth node N4, ensuring that during the non-light-emitting phase, the anode of the light-emitting device 20 is reset when the fourth switching transistor T4 is on, so that the anode of the light-emitting device 20 is reset to the same second reference voltage; when the fourth switching transistor T4 is off, the first terminal of the driving transistor T0 is reset (node ​​N1 is reset). This ensures that before the light-emitting phase, the fourth node N4 and the first node N1 are restored to the same second reference voltage, and the voltage difference between the third node N3 and the first node N1 can turn on the driving transistor T0 to drive the light-emitting device 20 to emit light for display.

[0074] The pixel driving circuit provided in the above embodiments of the present invention resets the first electrode (source) of the driving transistor T0 and the anode voltage of the light-emitting device 20 by using the second reference voltage provided by the second voltage terminal Vref2 as the reset voltage, thereby compensating for the voltage loss during the light-emitting stage of the display panel, that is, compensating for the voltage drop of the power supply voltage, and realizing the uniform display of the image on the display panel.

[0075] In one optional embodiment, the light-emitting driving branch further includes a fifth switching transistor T5 and a sixth switching transistor T6; the first terminal of the fifth switching transistor T5 is electrically connected to the first power supply voltage terminal PVDD, the second terminal of the fifth switching transistor T5 is electrically connected to the second node N2, and the gate of the fifth switching transistor T5 is connected to the fourth control signal terminal EM. n Electrical connections: The first terminal of the sixth switching transistor T6 is electrically connected to the first node N1, the second terminal of the sixth switching transistor T6 is electrically connected to the anode of the light-emitting device 20, the gate of the sixth switching transistor T6 is electrically connected to the fifth control signal terminal EMn-1, and the cathode of the light-emitting device 20 is electrically connected to the second power supply voltage terminal PVEE.

[0076] Understandably, during the light-emitting stage, the first power supply voltage terminal PVDD provides a positive power signal VDD, which is transmitted to the driving transistor T0 through the conduction of the fifth switching transistor T5 and the second node N2. This causes the driving transistor T0 to generate a corresponding driving current based on the voltage difference between its gate voltage and the positive power signal VDD, and this current is supplied to the anode of the light-emitting device 20 through the sixth transistor T6. The anode of the light-emitting device 20 is electrically connected to the second power supply voltage terminal PVEE, which provides a negative power signal VEE. During the light-emitting stage, a current path is formed through the voltage difference between the first power supply voltage terminal PVDD and the second power supply voltage terminal PVEE. For details, refer to... Figure 3The fifth switching transistor T5, acting as the first light-emitting transistor, is electrically connected to the second electrode of the driving transistor T0 and the first electrode of the second transistor T2 via the second node N2, and is turned on or off in response to the first light-emitting control signal provided by the fourth control signal terminal EMn; the sixth switching transistor T6, acting as the second light-emitting transistor, is electrically connected between the first node N1 of the driving transistor T0 and the anode of the light-emitting device 20, and is turned on or off in response to the second light-emitting control signal transmitted by the fifth control signal terminal EMn-1. In another optional circuit connection method, refer to... Figure 4 The fifth switching transistor T5, acting as the first light-emitting transistor, is electrically connected to the second terminal of the driving transistor T0 and the second terminal of the first switching transistor T1 via the second node N2, and is turned on or off in response to the first light-emitting control signal at the fourth control signal terminal EMn. The sixth switching transistor T6, acting as the second light-emitting transistor, is electrically connected to the first terminal of the second switching transistor T2 and the first terminal of the driving transistor T0 via the first node N1. The light-emitting driving branch is configured such that when the driving transistor T0 is turned on during the light-emitting phase, the voltage provided by the first power supply voltage terminal PVDD can be coupled to the anode of the light-emitting device 20 through the turned-on fifth switching transistor T5, the second node N2, the driving transistor T0, the sixth switching transistor T6, and the fourth node N4. The cathode of the light-emitting device 20 is connected to the second power supply PVEE, and a voltage difference is generated between the two electrodes of the light-emitting device 20, forming a driving current to ensure the light-emitting effect of the driving light-emitting device 20.

[0077] In one optional embodiment, a frame of a display image in which the pixel driving circuit 10 drives the light-emitting device 20 to emit light includes: an emission stage, a first reset stage, a second reset stage, a threshold compensation stage, a bias stage, and a third reset stage; wherein, in the emission stage, the fifth switching transistor T5 and the sixth switching transistor T6 are turned on, and the first switching transistor T1, the second switching transistor T2, the third switching transistor T3, and the fourth switching transistor T4 are turned off; in the first reset stage, the fourth switching transistor T4 and the fifth switching transistor T5 are turned on, and the first switching transistor T1, the second switching transistor T2, the third switching transistor T3, and the sixth switching transistor T6 are turned off; in the second reset stage, the third switching transistor T3 and the fourth switching transistor T4 are turned on, and the first switching transistor T5 is turned off, and the second switching transistor T2, the third switching transistor T3, and the sixth switching transistor T6 are turned off; in the second reset stage, the third switching transistor T3 and the fourth switching transistor T4 are turned on, and the first switching transistor T5 is turned off, and the second switching transistor T6 is turned off, and the third ... third switching transistor T6 is turned off, and the second switching transistor T5 is turned off, and the third switching transistor T6 is turned off, and the third switching transistor T5 is turned off, and the second switching transistor T6 is turned off, and the third switching transistor T5 is turned off, and the third switching transistor T6 is turned off, and the third switching transistor T5 is turned off, and the third switching transistor T6 is turned off, and the third switching transistor T5 is turned off During the threshold compensation phase, transistors T1, T2, T5, and T6 are turned on, while transistors T3, T5, and T6 are turned off. During the bias phase, the voltage at the first voltage terminal Vref1 changes, transistor T4 turns on, and transistors T1, T2, T3, T5, and T6 are turned off. During the third reset phase, transistor T6 turns on, and transistors T1, T2, T3, T5, and T6 are turned off.

[0078] Specifically, refer to the following: Figure 3 , Figure 7 as well as Figure 8 , Figure 7 This is a circuit timing diagram of a pixel driving circuit provided in one embodiment of the present invention; Figure 8 This is a schematic diagram of the pixel driving circuit in stage t1 according to an embodiment of the present invention. In the light emission (t1) stage, the first light emission control signal provided by the fourth control signal terminal EMn and the second light emission control signal provided by the fifth control signal terminal EMn-1 are both set to high level, turning on the fifth switching transistor T5 and the sixth switching transistor T6. At this time, the voltage of the third node N3 is the data input voltage V of the previous frame. data0 Threshold voltage V th The switching voltage (bias value ΔV) at the first voltage terminal Vref1 ref1 The second power supply voltage PVEE, the input voltage VEE, and the voltage V of the light-emitting device 20. OLEDThe sum of these values ​​minus the second reference voltage input at the second voltage terminal Vref2; the voltage at the second node N2 is the positive power supply voltage VDD input to the first power supply voltage PVDD; the voltages at the first node N1 and the fourth node N4 are both the negative power supply voltage VEE input to the second power supply voltage PVEE and the voltage V of the light-emitting device 20. OLED The positive power supply voltage VDD provided by the first power supply voltage terminal PVDD provides driving current to the anode of the light-emitting device 20 through the fifth switching transistor T5, the second node N2, the driving transistor T0, and the sixth switching transistor T6. The cathode of the light-emitting device 20 is electrically connected to the second power supply voltage terminal PVEE, so that a voltage difference is generated between the two electrodes of the light-emitting device 20, driving the light-emitting device to emit light.

[0079] After the light-emitting stage ends, to ensure the light-emitting effect of the light-emitting device 20 in the next light-emitting stage, the anode voltage of the light-emitting device 20 needs to be reset. (Refer to reference...) Figure 7 as well as Figure 9 , Figure 9 This is a schematic diagram of the pixel driving circuit in stage t2 according to an embodiment of the present invention. In the first reset (t2) stage, the second light emission control signal provided by the fifth control signal terminal EMn-1 is set to jump from high level to low level, causing the sixth switching transistor T6 to turn off. The third control signal provided by the third control signal terminal Reset is set to jump from low level to high level, turning on the fourth switching transistor T4. The second reference voltage provided by the second voltage terminal Vref2 is transmitted through the fourth switching transistor T4 to reset the fourth node N4, making the voltage of the fourth node N4 the second reference voltage.

[0080] Further reference Figure 7 as well as Figure 10 , Figure 10 This is a schematic diagram of the pixel driving circuit in stage t3 according to an embodiment of the present invention. The first light emission control signal provided by the fourth control signal terminal EMn is set to jump from high level to low level, causing the fifth switching transistor T5 to turn off. In the second reset (t3) stage, the control signal of the second control signal terminal Gn-1 is set to jump from low level to high level, the third switching transistor T3 is turned on, and the first reference voltage provided by the first voltage terminal Vref1 is transmitted through the third switching transistor T3 to reset the third node N3, making the voltage of the first node N1 the first reference voltage, and the voltages of the third node N3 and the second node N2 remain the same.

[0081] Further reference Figure 7 as well as Figure 11 , Figure 11This is a schematic diagram of the pixel driving circuit in stage t4 according to an embodiment of the present invention. In this circuit, the control signal of the second control signal terminal Gn-1 is set to transition from high to low, and the third switching transistor T3 is turned off. In the threshold compensation (t4) stage, i.e., the data voltage writing stage, the control signal of the first control signal terminal Gn is set to transition from low to high, and the first switching transistor T1 and the second switching transistor T2 are turned on. The first data voltage V provided by the data voltage terminal Vdata... data1 Data is transmitted to the driving transistor T0 via the first switching transistor T1 and the first node N1, where the voltage at the first node N1 is the first data voltage V. data1 To achieve the writing of data voltage, the driving transistor T0, via the second node N2 and the second switching transistor T2, compensates the voltage of the third node N3 to the second data voltage V. data2 That is, the first data voltage V data1 and threshold voltage V th The sum of these values ​​is stored in the first capacitor C1, so that the gate voltage of the driving transistor T0 in the display panel is compensated for the threshold, making the voltages of the driving transistors in the pixel driving circuit of the display panel the same.

[0082] Further reference Figure 7 as well as Figure 12 , Figure 12 This is a schematic diagram of the pixel driving circuit in stage t5 according to an embodiment of the present invention. The first control signal at the first control signal terminal Gn is set to transition from a high level to a low level, the first switching transistor T1 and the second switching transistor T2 are turned off, and during the bias (t5) stage, the first voltage terminal V... ref1 The input first reference voltage transitions from a first level to a second level, where the second level is lower than the first level, and the bias value ΔV ref1 The voltage is negative, the second capacitor C2 is coupled, and it is simultaneously connected to the second data voltage V stored with threshold compensation. data2 The first capacitor C1 generates a voltage divider effect, causing the voltage at the first node N1 to be biased to the third data voltage V. data3 (i.e. V) data1 +V th +k*△V ref1 The coefficient k = C² / C N3_all Where C2 is the capacitance value of the second capacitor, C N3_all (This is the sum of the capacitance values ​​of all capacitors between the third node N3 and other signal lines or nodes.) It is understood that, in the embodiments provided in this application, C... N3_allThis is the sum of the capacitance values ​​of the first capacitor C1 and the second capacitor C2. When the input data voltage range is all positive, the gate voltage range of the driving transistor T0 is adjusted from negative to positive by the first reference voltage jump. Therefore, the driving transistor T0 can drive the light-emitting device 20 to display bright and dark images within this voltage range.

[0083] Further reference Figure 7 as well as Figure 13 , Figure 13 This is a schematic diagram of the pixel driving circuit in stage t6 according to an embodiment of the present invention. In the third reset (t6) stage, i.e., the reset stage of the first terminal (source) of driving transistor T0, the third control signal provided by the third control signal terminal Reset is set to jump from high level to low level, the fourth switching transistor T4 is turned off, and the first light emission control signal transmitted by the fifth control signal terminal EMn-1 is set to jump from low level to high level, turning on the sixth switching transistor T6. The second reference voltage provided by the second voltage terminal Vref2 resets the first terminal (source) of driving transistor T0 through the fourth switching transistor T4, the fourth node N4, and the sixth switching transistor T6, making the voltage of the second node N2 the same as the voltage of the fourth node N4, both being the second reference voltage. At this time, in the pixel driving circuit 10, the voltage of the second node N2 is the second data voltage V. data2 V data1 +V th The voltage at the third node N3 is the third data voltage V. data3 The voltage between the first node N1 and the third node N3 is the second reference voltage, i.e., V. ref2 When the fifth switching transistor T5 and the sixth switching transistor T6 are turned on, the next frame's light-emitting stage begins. Due to the voltage difference between the first node N1, the second node N2, and the third node N3, a path is formed, driving the light-emitting device 20 to emit light and display.

[0084] In one optional embodiment, within one frame of the pixel driving circuit 10 driving the light-emitting device 20 to emit light, the voltage of the first voltage terminal Vref1 changes once. It is understood that, compared to the prior art's multi-pulse method of compensating for voltage drop through EM coupling, this embodiment of the invention pulses the gate voltage of the driving transistor T0 only once during the display of one frame, i.e., the third node N3 is coupled only once. This results in higher stability of the third node N3 and a more stable display effect. In another optional embodiment, the voltage transition edge of the first voltage terminal Vref1 is a falling edge. It is understood that a falling edge for the first voltage terminal Vref1 is suitable for pixel driving circuits where the data voltage range is all positive. In yet another optional embodiment, the voltage transition edge of the first voltage terminal Vref1 is a rising edge. It is understood that a rising edge for the first voltage terminal Vref1 is suitable for pixel driving circuits where the data voltage range is all negative.

[0085] Compared with the prior art, the technical effects of the embodiments of the present invention are more obvious. Specifically, referring to the reference... Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the structure of a pixel driving circuit in the prior art; Figure 2 This is a timing diagram of a pixel driving circuit in the prior art. In this prior art, the pixel driving circuit 10' compensates for the voltage drop generated by PVDD' through EM coupling. Figure 2 It can be seen that EM coupling involves 8 transitions, i.e., multiple pulses, during the display of one frame, which leads to a decrease in the stability of the gate voltage of the driving transistor T0. Further comparison with reference... Figure 3-6 In the embodiments of the present invention, the first voltage terminal Vref1 in the pixel driving circuit 10 only changes once. Therefore, the present invention makes the gate potential stability of the driving transistor better.

[0086] In one alternative implementation, the voltage transition edge of the first voltage terminal Vref1 follows the falling edge of the voltage of the first control signal terminal Gn.

[0087] refer to Figure 3 , Figures 5 to 7 The pixel driving circuit 10 is configured to, after threshold compensation (threshold compensation stage) of the gate voltage of the driving transistor T0, switch the first reference voltage provided by the first voltage terminal Vref1 from the first voltage to the second voltage to bias the threshold-compensated gate voltage. Compared with biasing without threshold voltage compensation, in this example, a smaller bias voltage value is required, and the voltage in the pixel driving circuit 10 is more prone to saturation. PVDD saturation is easier, and the PVDD voltage setting value can be appropriately reduced.

[0088] The pixel driving circuit provided in this embodiment makes it easier to compensate for the voltage drop of the display panel and results in a more uniform display effect.

[0089] In one alternative implementation, the voltage transition of the first voltage terminal Vref1 occurs before the falling edge of the voltage of the third control signal terminal Reset.

[0090] Continue to refer to Figures 5 to 7 The pixel driving circuit 10 is configured such that, before resetting the first electrode (source) voltage of the driving transistor T0 (third reset stage), the first reference voltage provided by the first voltage terminal Vref1 changes from the first voltage to the second voltage to bias the threshold-compensated gate voltage. It is understood that the voltage transition edge of the first voltage terminal Vref1 can be shifted forward or backward as needed, so that other transition edges change accordingly, dynamically adjusting the control timing.

[0091] In one optional embodiment, the switching transistor in the pixel driving circuit 10 includes an N-type transistor and / or a P-type transistor. It should be noted that the switching transistor in this embodiment is described using an N-type transistor as an example, but it is not limited to N-type transistors and can also be replaced with a P-type transistor. For an N-type transistor, the on-state level is high and the off-state level is low. That is, when the gate of the N-type transistor is high, its first and second terminals are connected; when the gate of the N-type transistor is low, its first and second terminals are off. For a P-type transistor, the on-state level is low and the off-state level is high. That is, when the control terminal of the P-type transistor is low, its first and second terminals are connected; when the control terminal of the P-type transistor is high, its first and second terminals are off. In specific implementation, the gate of each of the aforementioned switching transistors serves as its control electrode. Furthermore, depending on the signal and type of the gate of each switching transistor, its first electrode can be used as the source and its second electrode as the drain, or vice versa; no distinction is made here. Additionally, the on-level and off-level in this embodiment are general terms. On-level refers to any level that enables the transistor to conduct, and off-level refers to any level that enables the transistor to turn off / disconnect / turn off. Regarding the selection of different types of switching transistors and changes in circuit connection methods, those skilled in the art can adjust the design according to specific circumstances. As long as the first voltage terminal Vref1 is electrically connected to the second capacitor C2, and the second capacitor C is electrically connected to the gate of the driving transistor, the implementation method of the P-type transistor will not be described in detail here.

[0092] Those skilled in the art will understand that the pixel driving circuit provided by the present invention may include other known structures in addition to the circuits and components provided in the above embodiments. To avoid obscuring the focus of the technical solution of the present invention, these known structures will not be further described.

[0093] In one embodiment, the present invention provides a display panel. (See reference) Figure 14 , Figure 14 This is a schematic diagram of a display panel structure provided in one embodiment of the present invention. The display panel 00 includes the pixel driving circuit 10 provided in the above embodiment. Specifically, as shown... Figure 14 The display panel 00 includes multiple pixel driving circuits 10 and multiple light-emitting devices 20. The multiple pixel driving circuits 10 are arranged in an array, and the pixel driving circuits 10 drive the light-emitting devices 20 to emit light in order to display image information. Those skilled in the art should understand that the display panel provided by this invention can be applied to various display devices, and in addition to the structures provided in the above embodiments, it may also include some other known structures. To avoid obscuring the focus of the technical solution of this invention, these known structures will not be further described.

[0094] In one embodiment, the present invention provides a display device. (See reference) Figure 15 , Figure 15 This is a schematic diagram of a display device according to an embodiment of the present invention. The display device 0 includes the display panel 00 provided in the above embodiment. The display device 0 provided in this embodiment of the present invention can be as follows: Figure 15 The mobile phone shown can also be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop monitors, tablets, digital cameras, smart bracelets, smart glasses, automotive displays, industrial control equipment, medical displays, touch interactive terminals, etc. This application embodiment does not impose any special limitations on these categories. The display panel and display device provided in this embodiment of the invention have the beneficial effects of the pixel driving circuit provided in this embodiment of the invention. For details, please refer to the specific descriptions of the pixel driving circuit in the above embodiments; these descriptions will not be repeated here.

[0095] In summary, this invention provides a pixel driving circuit, a display panel, and a display device, which, compared with the prior art, achieves at least the following beneficial effects: by adjusting the gate voltage of the driving transistor through voltage switching and capacitive coupling, not only can voltage losses in the pixel driving circuit be compensated, but also the switching between positive and negative ranges of the output data voltage of the driving chip can be avoided. This achieves a uniform and stable image display on the display panel.

[0096] It should be understood that the specific circuit structures provided in the accompanying drawings of the embodiments of the present invention are merely examples and are not intended to limit the present invention. Furthermore, the above embodiments provided by the present invention can be combined with each other unless there is contradiction.

[0097] It should be clarified that the various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. According to the embodiments of the present invention described above, these embodiments do not exhaustively describe all details, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to make good use of the present invention and modifications based on it. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A pixel driving circuit, characterized by The application relates to a light-emitting drive branch, comprising a drive transistor (T0), a first electrode of the drive transistor (T0) being electrically connected with a first node (N1), a second electrode of the drive transistor (T0) being electrically connected with a second node (N2), a gate of the drive transistor (T0) being electrically connected with a third node (N3), and the drive transistor (T0) being used for providing a drive current to a light-emitting device (20); a data voltage writing branch, comprising a first switch transistor (T1), a second switch transistor (T2) and a first capacitor (C1), and the data voltage writing branch being used for threshold compensation of the drive transistor (T0); wherein a first electrode of the first switch transistor (T1) is electrically connected with a data voltage terminal (Vdata), a second electrode of the first switch transistor (T1) is electrically connected with the first node (N1) or the second node (N2), a first electrode of the second switch transistor (T2) is electrically connected with the third node (N3), a second electrode of the second switch transistor (T2) is electrically connected with the second node (N2) or the first node (N1), a gate of the first switch transistor (T1) and a gate of the second switch transistor (T2) are electrically connected with a first control signal terminal (Gn), a first plate of the first capacitor (C1) is electrically connected with the third node (N3), and a second plate of the first capacitor (C1) is electrically connected with an anode of the light-emitting device (20) through a fourth node (N4); and a second capacitor (C2), a first plate of the second capacitor (C2) being electrically connected with a first voltage terminal (Vref1), and a second plate of the second capacitor (C2) being electrically connected with the third node (N3); wherein the second capacitor (C2) is configured to couple the third node (N3) in response to voltage jump of the first voltage terminal (Vref1), and to adjust the gate potential of the drive transistor (T0). The data voltage range of the data voltage terminal (Vdata) is full positive voltage; In response to the potential jump of the first voltage terminal (Vref1), the second capacitor (C2) couples the third node (N3), and a negative bias value is superimposed on the potential of the third node (N3). The data voltage range of the data voltage terminal (Vdata) is full negative voltage; In response to the potential jump of the first voltage terminal (Vref1), the second capacitor (C2) couples the third node (N3), and a positive bias value is superimposed on the potential of the third node (N3). Further comprising a first reset branch, comprising a third switch transistor (T3); 2. The pixel driving circuit according to claim 1, characterized in that Wherein a first electrode of the third switch transistor (T3) is electrically connected with the first voltage terminal (Vref1), a second electrode of the third switch transistor (T3) is electrically connected with the third node (N3), and a gate of the third switch transistor (T3) is electrically connected with a second control signal terminal (Gn-1). Further comprising a second reset branch, and the second reset circuit comprises a fourth switch transistor (T4); 3. The pixel driving circuit of claim 1, wherein ​ ​ 4. The pixel driving circuit of claim 1, wherein ​ ​ 5. The pixel driving circuit of claim 4, wherein ​ The first electrode of the fourth switch transistor (T4) is electrically connected with the second voltage terminal (Vref2), the second electrode of the fourth switch transistor (T4) is electrically connected with the fourth node (N4), and the gate electrode of the fourth switch transistor (T4) is electrically connected with the third control signal terminal (Reset).

6. The pixel driving circuit of claim 5, wherein The light-emitting driving branch further comprises a fifth switch transistor (T5) and a sixth switch transistor (T6); The first electrode of the fifth switch transistor (T5) is electrically connected with the first power voltage terminal (PVDD), the second electrode of the fifth switch transistor (T5) is electrically connected with the second node (N2), and the gate electrode of the fifth switch transistor (T5) is electrically connected with the fourth control signal terminal (EMn). The first electrode of the sixth switch transistor (T6) is electrically connected with the first node (N1), the second electrode of the sixth switch transistor (T6) is electrically connected with the anode of the light-emitting device (20), and the gate electrode of the sixth switch transistor (T6) is electrically connected with the fifth control signal terminal (EMn-1). The cathode of the light-emitting device (20) is electrically connected with the second power voltage (PVEE).

7. The pixel driving circuit of claim 6, wherein The pixel driving circuit drives the light-emitting device (20) to emit light in one frame of display picture, which comprises a light-emitting stage, a first reset stage, a second reset stage, a threshold compensation stage, a bias stage and a third reset stage. In the light-emitting stage, the fifth switch transistor (T5) and the sixth switch transistor (T6) are turned on, and the first switch transistor (T1), the second switch transistor (T2), the third switch transistor (T3) and the fourth switch transistor (T4) are turned off. In the first reset stage, the fourth switch transistor (T4) and the fifth switch transistor (T5) are turned on, and the first switch transistor (T1), the second switch transistor (T2), the third switch transistor (T3) and the sixth switch transistor (T6) are turned off. In the second reset stage, the third switch transistor (T3) and the fourth switch transistor (T4) are turned on, and the first switch transistor (T1), the second switch transistor (T2), the fifth switch transistor (T5) and the sixth switch transistor (T6) are turned off. In the threshold compensation stage, the first switch transistor (T1), the second switch transistor (T2) and the fourth switch transistor (T4) are turned on, and the third switch transistor (T3), the fifth switch transistor (T5) and the sixth switch transistor are turned off. In the bias stage, the voltage of the first voltage terminal jumps, the fourth switch transistor (T4) is turned on, and the first switch transistor (T1), the second switch transistor (T2), the third switch transistor (T3), the fifth switch transistor (T5) and the sixth switch transistor (T6) are turned off. In the third reset stage, the sixth switch transistor (T6) is turned on, and the first switch transistor (T1), the second switch transistor (T2), the third switch transistor (T3), the fourth switch transistor (T4) and the fifth switch transistor (T5) are turned off.

8. The pixel driving circuit of claim 1, wherein The voltage of the first voltage terminal (Vref1) jumps once in a frame in which the pixel driving circuit drives the light emitting device (20) to emit light.

9. The pixel driving circuit of claim 8, wherein The jump edge of the voltage of the first voltage terminal (Vref1) is a falling edge.

10. The pixel driving circuit of claim 8, wherein The jump edge of the voltage of the first voltage terminal (Vref1) is a rising edge.

11. The pixel driving circuit of claim 8, wherein The jump edge of the voltage of the first voltage terminal (Vref1) is after a falling edge of the voltage of the first control signal terminal (Gn).

12. The pixel driving circuit of claim 11, wherein The jump edge of the voltage of the first voltage terminal (Vref1) is before a falling edge of the voltage of the third control signal terminal (Reset).

13. The pixel driving circuit of claim 1, wherein The switch transistor comprises an N-type transistor and / or a P-type transistor.

14. A display panel, characterized by The pixel driving circuit comprises any one of claims 1 to 13.

15. A display device comprising The display panel comprises claim 14.

Images