Method for adjusting threshold voltage of memory cell device of embedded flash memory

Abstract

The present invention relates to a method for adjusting the threshold voltage of a memory cell device of an embedded flash memory, the flash memory comprising a memory array area and a peripheral logic area, the memory array area comprising at least one memory cell, the memory cell comprising: a pair of stacked gates and a pair of select transistors, the stacked gates comprising: a floating gate gate oxide, a floating gate, a dielectric layer, and a control gate; the peripheral logic area comprising high voltage and low voltage logic areas, the high voltage or low voltage logic areas comprising at least one standard logic transistor, the standard logic transistor comprising: a logic gate oxide and a logic gate; the method for adjusting the threshold voltage of the memory device of the flash memory comprising two global ion implantations, the first global ion implantation being performed before the formation of the floating gate gate oxide, the dose of the implanted ions being such that the threshold voltage of the memory cell device reaches a desired value; the second global ion implantation being performed after the formation of the floating gate and before the formation of the logic gate oxide; the two implanted ions being of opposite type but having the same dose.

Description

Technical Field

[0001] This invention relates to a method for adjusting the threshold voltage of a storage cell device in a non-volatile memory, and more particularly to a method for adjusting the threshold voltage of a storage cell device in a non-volatile embedded flash memory. Background Technology

[0002] Embedded flash memory (eFlash) is used in widely used electronic products such as microcontrollers (MCUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), and programmable logic devices (PLDs). Compared with traditional EEPROM solutions, flash memory has advantages such as fast read and write speeds, small size, and low power consumption, and is playing an increasingly important role in current Internet of Things (IoT) and automotive electronics applications.

[0003] In embedded flash memory, the fabrication process of the memory cell array in the storage region is compatible with that of the logic devices in the peripheral logic region. Typically, the memory cell array and the peripheral logic devices are formed in the same fabrication process. Because the gate oxide layer thickness of the memory cell devices often differs from that of the peripheral logic devices, and because the need to reduce the size of the memory array results in a smaller channel length for the devices compared to the peripheral logic devices, the required ion concentration for the channel of the memory cell devices differs from that of the peripheral logic devices, necessitating separate adjustment of the threshold voltage. Otherwise, without adjustment, for example, the threshold voltage (Vt) of the memory cell device will be too low, leading to a low breakdown voltage and a tendency for leakage.

[0004] In existing embedded flash memory (eFlash) manufacturing technologies, dedicated photomasks are typically used to adjust the threshold voltage of memory cell devices and improve their breakdown characteristics and reliability. These photomasks are used to add dopant ions to the channels of the memory cell devices during fabrication to achieve the required threshold and breakdown voltage specifications. However, the use of such dedicated photomasks increases manufacturing costs and limits the application of flash memory in customers with low-cost requirements. Summary of the Invention

[0005] This invention provides a novel method for adjusting the threshold voltage of a memory cell device in embedded flash memory. This method does not use a mask, but instead employs a two-stage global ion implantation process to adjust the threshold voltage of the memory cell device. The ions are P-type or N-type doped ions used in the semiconductor industry. The global implantation involves uniformly implanting doped ions across the entire area of ​​the semiconductor device or structure.

[0006] In the method for adjusting the threshold voltage of the embedded flash memory cell device of the present invention, the embedded flash memory includes: a memory array region and a peripheral logic region. The memory array region contains at least one memory cell. The memory cell includes: two adjacent stacked gates and two selection transistors, which are respectively located on both sides of the adjacent stacked gates. Each stacked gate includes, from bottom to top, a floating gate oxide layer, a floating gate, a dielectric layer, and a control gate. Each selection transistor includes, from bottom to top, a selection gate oxide layer, a selection gate lower portion, and a selection gate upper portion. The peripheral logic region includes high-voltage and low-voltage logic regions. The high-voltage or low-voltage logic region contains at least one standard logic transistor, which includes, from bottom to top, a logic gate oxide layer and a logic gate.

[0007] The method for adjusting the threshold voltage of the embedded flash memory cell device includes the following steps:

[0008] a. First global ion implantation: Before the formation of the floating gate oxide layer and the logic gate oxide layer, the first global ion implantation is performed simultaneously in the memory array region and the peripheral logic region. The electrical properties of the implanted ions are opposite to those of the common source. The dosage of the implanted ions is such that the threshold voltage of the memory cell device reaches the required value.

[0009] b. Second global ion implantation: After the formation of the floating gate and the lower part of the select gate, and before the formation of the dielectric layer and the logic gate oxide layer, a second global ion implantation is performed simultaneously on the memory array region and the peripheral logic region. The electrical properties of the implanted ions are opposite to those of the first implanted ions, and the implantation dose is the same as that of the first implantation.

[0010] In a preferred embodiment, the memory array region, the high-voltage logic region, and the low-voltage logic region each have a well located in the substrate and respectively house the memory cells and standard logic transistors of that region; the first global ion implantation is performed after the wells of the memory array region are formed, and the wells of the memory array region are preferably formed together with the wells of the same charge as those of the high-voltage logic region.

[0011] In another preferred embodiment, the re-global ion implantation is performed before the formation of the dielectric layer. More preferably, the formation of the dielectric layer precedes the formation of the logic gate oxide layer.

[0012] In another preferred embodiment, the re-global ion implantation is performed while retaining the previously formed floating gate oxide layer on the substrate of the peripheral logic region.

[0013] In another preferred embodiment, the floating gate threshold voltage in the memory cell is the same as the selection transistor threshold voltage after adjustment.

[0014] The method of this invention eliminates the need for dedicated masks for adjusting the threshold voltage of traditional memory cell devices, as well as related processes such as resist application, photolithography, and resist removal. It is simple and easy to operate, reducing manufacturing costs, simplifying the process flow, and improving preparation efficiency. Furthermore, the method of this invention does not affect the electrical performance of the flash memory cells and logic devices, and the product yield and reliability remain unaffected. Attached Figure Description

[0015] The same numbers in the accompanying drawings indicate the same or similar elements.

[0016] Figure 1 This is a partial top view of a specific embodiment of the embedded flash memory described in this invention.

[0017] Figure 2 yes Figure 1 The diagram shows a schematic of the flash memory substrate along the BB section before the memory cells and logic devices begin to be formed.

[0018] Figure 3 Is Figure 2 The diagram shows a memory array N-well and a high-voltage logic region N-well formed in the substrate.

[0019] Figure 4 Yes Figure 3 The diagram shows a schematic of the first global ion implantation performed on the substrate shown.

[0020] Figure 5 Is Figure 4 The diagram shows a floating gate oxide layer and a deposited floating gate material layer formed sequentially on the substrate.

[0021] Figure 6a Is Figure 5 This diagram illustrates the process of etching a layer of floating gate material deposited within the memory array region of the structure shown, in preparation for etching to form the partition PC between the floating gates of adjacent cells in each row of memory cells.

[0022] Figure 6b yes Figure 6a The diagram shows the memory array region after etching to form the PC (polycarbonate) between the floating gates of adjacent cells in each row of memory cells, and after etching to remove the deposited floating gate material layer in the logic region.

[0023] Figure 6c yes Figure 1 The diagram shows the memory array region after initial global ion implantation, formation of the floating gate oxide layer, and deposition of the floating gate material layer, ready for etching to form the floating gate and the under-select gate portion; where PC is the partition between the floating gates of adjacent cells in each row of memory cells, and the partition between the under-select gate portions of adjacent cells.

[0024] Figure 6d yes Figure 6cThe diagram shows the memory array region after etching to form the floating gate and the lower part of the select gate.

[0025] Figure 7 Yes Figure 6b The diagram shows a schematic of a second global ion implantation performed on the structure shown.

[0026] Figure 8a Is Figure 7 A schematic diagram showing the deposition of dielectric layers on the memory array region and logic region of the structure shown.

[0027] Figure 8b yes Figure 6d The diagram shows a dielectric layer deposited in the memory array region after a second global ion implantation.

[0028] Figure 9 Is Figure 8a A schematic diagram of etching away the deposited dielectric layer in the logic region of the structure shown.

[0029] Figure 10a Is Figure 9 The diagram shows N-wells and P-wells forming low-voltage (LV) logic regions and P-wells forming high-voltage (HV) logic regions in the substrate of the structure shown.

[0030] Figure 10b Is Figure 10a The diagram shows a schematic of the structure after removing the residual floating gate oxide layer in the low-voltage and high-voltage logic regions.

[0031] Figure 11 Is Figure 10b The diagram shows a low-voltage logic gate oxide layer and a high-voltage logic gate oxide layer formed in the low-voltage and high-voltage logic regions of the structure shown.

[0032] Figure 12 Is Figure 11 The diagram shows a schematic of an upper gate material being deposited on the dielectric layer of the memory array region and the logic gate oxide layer of the logic region.

[0033] Figure 13a yes Figure 1 The diagram shows the structure of a memory cell along the CC section line in a flash memory before the upper portion of the control gate and select gate is etched.

[0034] Figure 13b yes Figure 1 The diagram shows the structure of a memory cell in a flash memory along the CC section line after etching to form the control gate and select gate portions.

[0035] Figure 13c yes Figure 1The diagram shows the structure of the low-voltage logic device in the flash memory along the DD section line before the low-voltage logic gate is etched.

[0036] Figure 13d yes Figure 1 The diagram shows the structure of the low-voltage logic device in the flash memory along the DD section line after etching to form the low-voltage logic gate.

[0037] Figure 13e yes Figure 1 The diagram shows the structure of the high-voltage logic device in the flash memory along the EE section line before etching to form the high-voltage logic gate.

[0038] Figure 13f yes Figure 1 The diagram shows the structure of the high-voltage logic device in the flash memory along the EE section line after etching to form the high-voltage logic gate.

[0039] Figure 14a yes Figure 1 The diagram shows the structure of a memory cell in a flash memory along the CC section line after the gate outer isolation wall and source / drain ion implantation are formed in sequence.

[0040] Figure 14b yes Figure 1 The diagram shows the structure of a memory cell in a flash memory along the CC section line after the floating gate oxide layer above the source and drain electrodes has been removed. Detailed Implementation

[0041] The relevant definitions in this application are described below.

[0042] The term "up and down" as used in this article refers to the vertical relationship along a direction perpendicular to the substrate surface of the memory array.

[0043] The "corresponding gates of memory cells in each row / or column" mentioned herein refers to gates in each memory cell that are oriented in the same position within that row / or column, and these gates can be directly connected in a straight line along the direction of that row / or column. The gates can be: a select gate, a control gate, a floating gate, the upper portion of a select gate, or the lower portion of a select gate.

[0044] The embedded flash memory of this invention further includes a substrate on which the memory array region and the peripheral logic region are located. The memory array region and the logic region also have wells, both located within the substrate, which respectively house the memory cells in the memory array and the logic devices in the logic region.

[0045] In the embedded flash memory, the storage cells form a storage array area, and the standard logic transistors (also referred to as standard logic devices, or simply logic transistors or logic devices) surrounding it form a logic area.

[0046] The peripheral logic region can include a low-voltage region and a high-voltage region. The low-voltage region can contain multiple low-voltage standard logic transistors, which can be of different types depending on the application, and the type of well they occupy also varies. Similarly, the high-voltage region can contain multiple high-voltage standard logic transistors, which can be of different types depending on the application, and the type of well they occupy also varies. Typically, both N-wells and P-wells coexist in the low-voltage logic region and the high-voltage logic region.

[0047] In the memory array region, each memory cell is identical. There is only one well within the memory array region, located in the substrate, which houses all the memory cells. This well can be either an N-well or a P-well, depending on the electrical type of the transistor or device (or memory transistor, or memory device) in the memory cell. If the memory transistor or device is PMOS type, the well is an N-well; if the memory transistor or device is NMOS type, the well is a P-well. The devices in the memory cell include a stacked gate and a select transistor, which can also be called a select tube or select device.

[0048] Each memory cell has a left-right mirror symmetry structure. Each memory cell includes: a common source located in the substrate; a common line (COM) located on the substrate, directly above and connected to the common source; a pair of stacked gates located on the substrate, arranged left-right mirror symmetry on both sides of the common line, wherein each stacked gate includes a vertically stacked control gate (CG) and a floating gate (FG); and a pair of select gates (SG), located next to the non-common line side of the two stacked gates, aligned with the stacked gates, and arranged left-right mirror symmetry along the common line. On the side of each select gate not adjacent to the stacked gates, there is a drain in the substrate below it.

[0049] In the stacked gate, there is a dielectric layer between the control gate and the floating gate. The select gate is divided into upper and lower parts, which are formed by two different deposition steps. There may be a dielectric layer or no dielectric layer between the upper and lower parts of the select gate, preferably no dielectric layer, and the upper and lower parts are directly connected as one unit.

[0050] Below the floating gate and the select gate, there are floating gate oxide layers and select gate oxide layers, respectively, located on the substrate surface. The floating gate oxide layers and select gate oxide layers are preferably made of the same material and have the same thickness, and are preferably formed together in the same fabrication step.

[0051] The gate oxide layer of the logic device is formed separately in subsequent steps, preferably after the dielectric layer of the memory device is formed, to avoid the gate oxide layer of the logic device being affected by the memory device fabrication process. Similarly, the well of the logic region is also preferably formed after the dielectric layer in the memory cell is formed.

[0052] The materials of the floating grid and the lower portion of the selection grid are preferably the same, the same thickness, and preferably formed together in the same preparation step.

[0053] The control gate, the select gate portion, and the logic gate are preferably made of the same material, have the same thickness, and are preferably formed together in the same fabrication step. That is, a layer of gate material is deposited simultaneously in the memory array region and the logic region, and then etched separately in the memory array region and the logic region to form the gate.

[0054] The preferred fabrication process of the embedded flash memory described in this invention is as follows: forming a well for the memory array region → forming a gate oxide layer for the floating gate and select gate of the memory cell → forming a lower portion of the floating gate and select gate → forming a dielectric layer → forming a well for the logic region → forming a logic gate oxide layer → forming a control gate, an upper portion of the select gate, and a logic gate.

[0055] Memory devices are generally high-voltage devices. In this case, the wells in the high-voltage logic region that have the same electrical charge as the memory array region are preferably formed together with the wells in the memory array region. If the memory device is a low-voltage device, the wells in the low-voltage logic region that have the same electrical charge as the memory array region are preferably formed together with the wells in the memory array region.

[0056] The method for adjusting the threshold of the memory cell device according to the present invention is embedded in the flash memory manufacturing process. Details are as follows.

[0057] First global ion implantation

[0058] Preferably, after the formation of the trap in the memory array region and before the formation of the floating gate oxide layer and the logic gate oxide layer, the first global ion implantation is performed simultaneously into the memory array region and the peripheral logic region on the substrate surface; the electrical type of the implanted ions is opposite to that of the memory cell device, and the dose of the implanted ions is such that the threshold of the memory cell device reaches the required value.

[0059] The type of ion initially implanted is opposite to the electrical type of the storage device. In the case of a P-type storage device, the initially implanted ion is an N-type dopant, such as phosphorus, sodium, potassium, lithium, arsenic, and their organic compounds. In the case of an N-type storage device, the initially implanted ion is a P-type dopant, such as boron, aluminum, or halogen compounds.

[0060] The relationship between ion implantation dose and the obtained threshold voltage can be determined by ordinary technicians based on their industry knowledge and common sense. For example, for 5V high-voltage storage devices in embedded flash memory cells, a threshold voltage of 0.7-1.5V is typically required, necessitating an ion implantation dose of 2 × 10⁻⁶. 12 - 6×10 12 / cm 2This implantation dose range is applicable to N-type or P-type doped ions, such as phosphorus, sodium, potassium, lithium, arsenic, boron, and aluminum. Those skilled in the art can also determine the required implantation energy based on industry knowledge and common sense, according to the ion implantation dose. For the above ion implantation dose of 2 × 10⁻⁶, 12 - 6×10 12 / cm 2 The corresponding ion implantation energies are 8-210 keV. For example, the implantation energy for phosphorus ions is 30-90 keV, for boron ions it is 10-30 keV, and for arsenic ions it is 60-200 keV.

[0061] Full-domain ion implantation again

[0062] After the formation of the floating gate and the lower part of the selected gate, and before the formation of the logic gate oxide layer, global ion implantation is performed again on the memory array region and the peripheral logic region. The electrical type of the implanted ions is opposite to that of the first implanted ions, and the implantation dose is the same as that of the first implantation.

[0063] The formation of the floating gate and the lower portion of the select gate refers to the following: the pattern of the floating gate and the lower portion of the select gate formed at this time is exactly the same as the pattern of the floating gate and the lower portion of the select gate in the memory cell of the embedded flash memory product; subsequently, a second regional ion implantation is performed. In this way, in the region outside the lower portion of the floating gate and the select gate, the re-implanted ions have opposite charges but the same dosage as the first implanted ions, and the two implanted ions neutralize each other. In the region of the lower portion of the floating gate and the select gate, the re-implanted ions are only implanted into the gate surface. Because in the conventional formation process of the lower portion of the floating gate and the select gate, the gate also needs to be doped with ions of the same type as those in the source and drain electrodes to improve conductivity; therefore, the re-implanted ions implanted into the gate surface do not affect the performance of the floating gate and the select gate, but rather enhance their electrical performance.

[0064] Performing ion implantation again before forming the logic gate oxide layer can avoid adverse effects of ion implantation on the logic gate oxide layer.

[0065] The second ion implantation is preferably performed before the formation of the dielectric layer in the memory device. This avoids adverse effects of ion implantation on the performance of the dielectric layer. More preferably, the formation of the dielectric layer precedes the formation of the logic gate oxide layer. This avoids the logic gate oxide layer being affected by the dielectric layer formation process.

[0066] The second global ion implantation is preferably performed while retaining the previously formed floating gate oxide layer on the substrate of the peripheral logic region. This avoids adverse effects of ion implantation on the logic device. The floating gate oxide layer retained on the substrate of the peripheral logic region will be removed in subsequent steps, and then a new logic gate oxide layer will be formed, followed by the formation of the logic gate.

[0067] The presence of a gate oxide layer on the substrate of the peripheral logic region does not affect the implantation of ions into the substrate below the gate oxide layer; however, the ion implantation depth will be shallower due to the thickness of the gate oxide layer. In this case, the energy of the implanted ions can be increased to compensate for the reduced depth caused by the gate oxide layer thickness. Those skilled in the art can determine the relationship between implantation depth and implantation energy for different types of ions based on industry-standard knowledge, and determine the increased energy according to the gate oxide layer thickness and the required compensation depth. These are all standard practices in the industry. For example, implanting ions into the substrate below a floating gate oxide layer (preferably silicon oxide, more preferably silicon dioxide) with a thickness of 85-105 angstroms requires an energy of 6-210 keV, an increase of 2-30 keV compared to when there is no such gate oxide layer. A specific example is: implanting ions into the substrate below a 100 angstrom thick floating gate oxide layer requires the following implantation energies: 13~36 keV for boron ions, 38~98 keV for phosphorus ions, and 70~210 keV for arsenic ions; compared to the case without the gate oxide layer, the increased energy values ​​are: 3 keV for boron ions, 8 keV for phosphorus ions, and 11 keV for arsenic ions.

[0068] In the memory cell, it is preferable that the floating gate threshold voltage is the same as the threshold voltage of the select transistor. Both memory devices can achieve the same threshold voltage using the method described above for adjusting the threshold voltage of the memory device. Specifically, the material and thickness of the floating gate and its gate oxide layer are the same as those of the select gate under portion and its gate oxide layer, and they undergo identical processes in fabrication and threshold voltage adjustment.

[0069] The threshold voltages of the two memory devices can also be different. In this case, during the initial global ion implantation step, a mask is needed to separate the floating gate region and the selected gate region, and different doses of dopant ions are implanted into the floating gate region and the selected gate region respectively to obtain the required different threshold voltages for different regions.

[0070] The storage array described in this invention includes rows and columns, and preferably, the storage cells in the array are arranged in the same direction.

[0071] The direction of the line connecting the same part of two select gates in a memory cell is defined as the column direction. The upper part of the select gate and the control gate of each memory cell in each row are connected along the row to form a strip. The floating gates of each memory cell in each row are not connected and are broken at the boundary between two adjacent memory cells to form a gap (PC).

[0072] In the case where there is no dielectric layer in the select gate, preferably: the upper portion of the select gate corresponding to each memory cell in each row is connected along the row to form a strip, while the lower portion of the select gate corresponding to each memory cell in each row is not connected, and similar to the floating gate, it is broken at the boundary between two adjacent memory cells to form a gap (PC). However, in each memory cell, the lower portion and the upper portion of each select gate are connected as a whole.

[0073] In the case where the select gate has a dielectric layer, preferably: the upper and lower portions of the select gate corresponding to each memory cell in each row are connected along the row to form a strip, and the lower portion of the select gate strip can be electrically connected to the top of the dielectric layer. More preferably: in each row, in the dielectric layer between the upper and lower portions of the vertically aligned select gate strips, there is at least one via, the bottom of which is electrically connected to the surface of the lower portion of the select gate strip, and the top of which is exposed to the top surface of the dielectric layer, so that the lower portion of the select gate strip can be electrically connected to the top of the dielectric layer; even more preferably: in each row, along the row, every 8-64, more preferably every 16-32 memory cells, in the dielectric layer between the upper and lower portions of the vertically aligned select gate strips, there is one via. In this case, it is more preferable that in the strip above the select gate, there is also a via at the position of each via in the dielectric layer below. The via is electrically insulated from the surrounding strip above the select gate, and its bottom is connected to the corresponding via in the dielectric layer below and is electrically connected internally. Its top is exposed above the top surface of the strip above the select gate, so that the via in the dielectric layer extends out to the top surface of the strip above the select gate.

[0074] In the memory array, the common source of the memory cell is connected to the common line (COM), the control gate is connected to the control line (CG'), and the drain of the select gate is connected to the bit line (BL). When the select gate has no dielectric layer, the upper and lower portions of the select gate are integral and connected to the word line (WL). When the select gate has a dielectric layer, if there are no vias in the upper portion of the select gate strip but vias in the dielectric layer, the lower portion of the select gate strip is electrically connected to the upper portion of the select gate strip through the vias in the upper dielectric layer, and is connected to the word line (WL). Alternatively, if there are vias in both the upper portion of the select gate strip and the dielectric layer, and these vias are vertically connected and electrically connected at their center, it is preferable that the lower portion of the select gate strip is connected to the word line (WL) through the upper portion of the select gate strip and the interior of the vias in the dielectric layer, while the upper portion of the select gate strip is not connected to the word line. In this case, it is preferable to select the vias in the strips above the gate and the vias in the dielectric layer below them, with an electrically insulating barrier on the inner surface, and a metal conductor at the center of the via. The metal conductor at the center of the via is electrically insulated from the strips above the gate outside the via by the barrier on the inner surface of the via.

[0075] In the memory array, when the connection direction of the same part of two select gates in the memory cell is column-oriented, the bit lines (BL) of each memory cell in each column are connected, and the word lines (WL), common lines (COM), and control lines (CG') of each memory cell in each row are connected respectively.

[0076] The embedded flash memory described in this invention has a programming channel from the channel region near the common source of the memory cell to the floating gate, and an erasing channel from the floating gate to the channel region in the underlying substrate. These are simple channels conventional in the industry, requiring no additional components to form new channels, such as erase gates or floating gate side bumps. In the memory array of this invention, all memory cells can be erased simultaneously, while programming is bit-selectable.

[0077] Threshold voltage testing method: The industry standard constant current threshold voltage extraction method is adopted.

[0078] The method for adjusting the threshold voltage of embedded flash memory devices according to the present invention will now be described in detail with reference to the accompanying drawings. However, the scope of the present invention is not limited to the specific embodiments shown in the drawings.

[0079] Figure 1 This is a partial top view of a specific embodiment of the embedded flash memory described in this invention. The figure only shows a portion of the flash memory's eight-cell memory array and the surrounding low-voltage and high-voltage logic regions. The memory array and the surrounding low-voltage and high-voltage logic regions share a single substrate.

[0080] Figure 1 All memory cells in the flash memory shown are identical. The memory devices within each cell are PMOS type, and the common source is P-type. All memory cells share a single N-well, constructed within the substrate. Figure 1 (Not shown). Figure 1 The logic transistors in the low-voltage and high-voltage logic regions shown are of different types; those located in N-wells are PMOS type, and those located in P-wells are NMOS type. The P-wells and N-wells of the logic devices in the logic region are also constructed within the substrate.

[0081] Figure 1 In this design, both the memory cells and peripheral logic transistors are constructed within the active regions (AA) on the substrate surface. On the substrate surface, the active regions are arranged alternately and parallel to each other with shallow channel isolation regions (STI).

[0082] Figure 1 In the memory array shown, all memory cells are arranged and oriented in the same way. The line connecting the identical portions of two select gates within a memory cell points in the column direction, and odd and even columns are separated by shallow channel isolation regions (STIs). The array shown has four memory cells per row and two memory cells per column.

[0083] The structure of the storage unit is as follows: Figure 14b As shown. Figure 14b yes Figure 1 The diagram shows the structure of a memory cell in a flash memory along a CC section. It includes: a P-type common source located in the substrate; a common line (COM) located directly above the common source and connected to it at the bottom; a pair of stacked gates on the substrate, arranged in a mirror-symmetrical configuration on both sides of the common line, each stacked gate including a vertically stacked control gate (CG) and a floating gate (FG), and a dielectric layer between them; and a pair of select gates (SG), located on the side of the stacked gates opposite to the common line, aligned with the stacked gates, and arranged in a mirror-symmetrical configuration along the common line. On the side of each select gate not adjacent to the stacked gates, there is a drain in the substrate below. Each select gate includes upper and lower parts connected as a single unit without a dielectric layer between them. The common source of the memory cell is connected to the common line (COM), and the control gate is connected to the control line (CG'). Figure 14b (Not shown in the image), select the gate drain connectivity bit line (BL); select the gate connectivity word line (WL).

[0084] In the illustrated memory array, the select gate upper portion and control gate corresponding to all memory cells in each row are connected along the row across the isolation region (STI) between adjacent columns, forming a stripe. These stripes are parallel to each other. However, the floating gate and select gate lower portion corresponding to each memory cell in each row are not connected. Between the floating gates or select gate lower portions corresponding to two adjacent cells in each row, there is an etched-away partition (PC) that is disconnected by the PC, as shown below. Figure 1 As shown.

[0085] The bit lines (BL) of each memory cell in each column are connected, and the word lines (WL), common lines (COM), and control lines (CG') of each memory cell in each row are connected respectively.

[0086] Figure 2-12 (remove Figures 6c-6d and Figure 8b ) are respectively Figure 1 The diagram shows a portion of the memory cells and logic devices in the flash memory along the BB cross-section during the fabrication process (the step before etching to form the control gate and logic gate). Figures 13a-13f The steps for forming the control gate and logic gate of the memory cell and logic device, as well as the steps for forming the source and drain, are shown respectively. The following is a detailed description in sequence with reference to these figures. Figure 1 The diagram illustrates the flash memory fabrication process and the process of adjusting the threshold voltage of the memory device.

[0087] A. A trap that provides a substrate and forms the memory cells:

[0088] Figure 2 yes Figure 1 The diagram shows a schematic of the substrate in a flash memory module along the bottom border (BB) before device fabrication begins. Active regions (AA) and shallow channel isolation regions (STI) are arranged alternately and adjacently on the substrate surface. Memory cells and logic devices are subsequently formed within the active regions. Figure 3 As shown, firstly, an N-well of the memory array is formed below a predetermined region of the memory array in the substrate. The memory devices in the memory cells are 5V high-voltage devices, and the N-wells in the high-voltage logic region are formed together with the N-wells of the memory array.

[0089] B. First global ion implantation:

[0090] like Figure 4 As shown, the first global ion implantation was performed simultaneously into the storage array region and the peripheral logic region. The implanted ions were N-type phosphorus ions, and the implantation dose was 4 × 10⁻⁶. 12 / cm 2 Energy of 60keV was injected.

[0091] C. Form the gate oxide layer of the memory device, and form the floating gate and the under-gate portion:

[0092] like Figure 5 As shown, a floating gate oxide layer is formed simultaneously on the substrate surface in the predetermined memory array region and logic region, followed by the deposition of a floating gate material layer. The floating gate oxide layer is approximately 85 Å thick, and the floating gate material layer is approximately 800 Å thick. The floating gate oxide layer formed in the select gate region constitutes the gate oxide layer of the select gate; the floating gate material layer deposited in the select gate region constitutes the material layer of the lower portion of the select gate.

[0093] Next, a high dose of P-type boron ions was implanted into the floating gate material layer to improve conductivity. The implantation dose was 2 × 10⁻⁶. 15 - 3×10 15 / cm 2 .

[0094] Then, as Figures 6a-6d As shown, a photomask with a pattern of floating gates and select gate under portions is used. In the memory array region, the floating gate material layer, excluding the floating gate and select gate under portion regions, is etched to form the floating gate and select gate under portion. The deposited floating gate material layer is then etched away in the logic regions (including low-voltage and high-voltage logic regions). Simultaneously, in the memory array, the boundary between corresponding floating gates of two adjacent memory cells in each row, or the boundary between corresponding select gate under portions, is etched to form a partition PC.

[0095] The etched floating gate and select gate under portion are exactly the same as the pattern of the floating gate and select gate under portion in the memory cell of the finished flash memory.

[0096] Figure 6aand Figure 6b They are Figure 1 The diagram shows the structure of a portion of the memory devices and logic devices in the flash memory along the BB section line, before and after etching to form the floating gates in each row and the PCs that separate them. Figure 6a The structure of the photomask placed on the deposited floating gate material layer along the BB profile is shown before etching, in which the PC area to be etched is exposed. Figure 6b The image shows the floating gates formed after etching, and the PC (partition block) between adjacent floating gates.

[0097] Figures 6c-6d They are Figure 1 The image shows a top view of the memory array in the flash memory before and after etching to form the floating gate and the lower portion of the select gate. Figure 6c The image shows a photomask (also called a photomask) placed on top of the floating gate material layer deposited in the memory array region before etching. The photomask has a pattern of floating gates and select gate under portions, exposing the portions to be etched other than the floating gates and select gate under portions, while also exposing the portions to be etched between the corresponding floating gates of two adjacent cells in each row, and the portions to be etched between the corresponding select gate under portions. Figure 6d The diagram shows a top view of the floating gate and its spacer PC formed after etching in the memory array, as well as the under-gate portion and its spacer PC; the area where the deposited material layer was etched away exposes the floating gate oxygen layer.

[0098] D. Re-implantation of ions across the entire domain:

[0099] A second global ion implantation was performed simultaneously on the storage array area and the peripheral logic area. The implanted ions were P-type boron ions, the implantation dose was the same as the first implantation, and the implantation energy was 6keV.

[0100] After two rounds of global ion implantation, the threshold voltage of the floating gate is 0.8V. The threshold voltage of the selected gate is the same.

[0101] E. Deposit a dielectric layer and etch it:

[0102] like Figure 8a and 8b As shown, a dielectric material layer, i.e., a dielectric layer, is deposited simultaneously in the floating gate region and the logic region formed in the memory array region. No dielectric material layer is deposited in the region below the select gate formed in the memory array region.

[0103] Then, as Figure 9 As shown, photomask etching is used to remove the dielectric layer deposited in the logic region.

[0104] F. Forming the traps and logic gate oxide layers in the logic region:

[0105] like Figure 10a As shown, in the logic region, low-voltage and high-voltage traps are formed respectively. Specifically, N-trap and P-trap are formed in the low-voltage region, and P-trap is formed in the high-voltage region.

[0106] Then, as Figure 10b As shown, the floating gate oxide layer that was previously formed along with the memory array and remains in the logic region is removed; and the logic gate oxide layer is regrown, as shown. Figure 11 As shown, there is a gap between the logic gate oxide layer of the regenerated logic region and the floating gate oxide layer of the memory array region. The thickness of the logic gate oxide layer differs between the low-voltage and high-voltage regions. The gate oxide layer in the low-voltage region is thinner, approximately 25 Å, while the gate oxide layer in the high-voltage region is thicker, approximately 125 Å.

[0107] G. Deposit the upper gate material layer and etch to form the control gate and the upper portion of the select gate:

[0108] like Figure 12 As shown, an upper gate material layer is deposited simultaneously on the dielectric layer of the memory array region and on top of the logic gate oxide layer of the logic region. The upper gate material constitutes the material of the upper portion of the control gate and the select gate, and this material is the same as the material of the lower portion of the floating gate and the select gate.

[0109] Then, in the memory array region, within each row of memory cells, a photomask is used to block predetermined portions of the select gate and control gate. Outside these portions, etching is performed down to the floating gate oxide layer to remove the upper gate material and dielectric layer from these portions, thereby forming strips of the select gate and control gate in each row. Each row has two select gate strips and two control gate strips, arranged parallel to each other along the row direction, as shown below. Figure 1 The storage array is shown in the figure.

[0110] Figures 13a-13b They are Figure 1 The diagram shows a memory cell in a flash memory, with its structure along the CC cross-section in the column direction, before and after the etching process to form the control gate and select gate portions. Figure 13a The image shows the portion of the memory cell that is covered by a photomask, specifically the portion where the select gate and control gate are to be formed. Figure 13b The image shows the upper portion of the select gate (SG) formed after etching in the memory cell, the control gate (CG) in the stacked gate, and the floating gate (FG).

[0111] Subsequently, in the logic region, a photomask is used to block the predetermined portions of the logic gate, and in the areas outside these portions, the upper gate material layer is etched away to form the logic gate. Figures 13c-13d They are shown respectively Figure 1The structure of the low-voltage logic device in the flash memory shown is along the DD section line, and the steps before and after etching to form the low-voltage logic gate. Figure 13e-13f They are shown respectively Figure 1 The diagram shows the steps before and after etching to form the high-voltage logic gate in the high-voltage logic device along the EE cross-section of the flash memory. Figure 13c and Figure 13e The photomask blocking areas are the locations where low-voltage logic gates and high-voltage logic gates are to be formed.

[0112] H. Forming source and drain electrodes:

[0113] On both sides of each gate formed by etching, an isolation wall is formed with an isolation dielectric material to serve as insulation.

[0114] Then, ions are implanted into the substrate in the active region on the substrate surface outside the isolation wall of each gate to form P-type source and drain electrodes (such as...) located on both sides of the select gate and the stacked gate in the memory cell. Figure 14a (as shown), and the source and drain of the logic transistor.

[0115] In the memory cell, the ion-implanted region formed in the substrate below the two stacked gates serves as the common source; the ion-implanted region formed in the substrate below the outer side of the select gate (the side not adjacent to the stacked gates) serves as the drain of the select transistor.

[0116] Subsequently, the residual floating gate oxide layer above each ion implantation region is removed with acid. A self-aligned polysilicide is formed above the common source of the memory cell and between the two stacked gates, constituting a common line (COM) that connects to the common source in the substrate below. The drain below the outer side of the select gate of the memory cell (the side not adjacent to the stacked gates) connects to the bit line (BL). The select gate connects to the word line (WL).

[0117] The flash memory fabrication method and the method for adjusting the threshold voltage of the memory device of the present invention are not limited to the specific examples described above.

Claims

1. A method for adjusting the threshold voltage of a storage cell device in an embedded flash memory, the embedded flash memory comprising: The storage array region includes a storage array region and a peripheral logic region. The storage array region contains at least one storage cell. The storage cell includes two adjacent stacked gates and two selection transistors, which are located on both sides of the adjacent stacked gates. Each stacked gate, from bottom to top, includes: a floating gate oxide layer, a floating gate, a dielectric layer, and a control gate; each select transistor, from bottom to top, includes: a select gate oxide layer, a select lower gate portion, and a select upper gate portion; the peripheral logic region includes high-voltage and low-voltage logic regions, each high-voltage or low-voltage logic region containing at least one standard logic transistor, the standard logic transistor including, from bottom to top, a logic gate oxide layer and a logic gate; The method for adjusting the threshold voltage of the embedded flash memory storage cell device is characterized in that: It includes the following steps: a. First global ion implantation: Before the formation of the floating gate oxide layer and the logic gate oxide layer, the first global ion implantation is performed simultaneously in the memory array region and the peripheral logic region. The electrical type of the implanted ions is opposite to that of the memory cell device. The dose of implanted ions is such that the threshold voltage of the memory cell device reaches the required value. b. Second global ion implantation: After the formation of the floating gate and the lower part of the selected gate, and before the formation of the logic gate oxide layer, a second global ion implantation is performed simultaneously on the memory array region and the peripheral logic region. The electrical type of the implanted ions is opposite to that of the first implanted ions, and the implantation dose is the same as that of the first implantation.

2. The method for adjusting the threshold voltage of the embedded flash memory storage cell device as described in claim 1, characterized in that: The memory array region, high-voltage logic region, and low-voltage logic region each have a well located in the substrate and respectively house the memory cells and standard logic transistors of that region. The first global ion implantation is performed after the formation of the traps in the storage array region, which are formed together with the traps of the same charge in the high-voltage logic region.

3. The method for adjusting the threshold voltage of the embedded flash memory storage cell device as described in claim 1, characterized in that: The second global ion implantation is performed before the formation of the dielectric layer.

4. The method for adjusting the threshold voltage of the embedded flash memory storage cell device as described in any one of claims 1-3, characterized in that: The dielectric layer is formed prior to the formation of the logic gate oxide layer.

5. The method for adjusting the threshold voltage of the embedded flash memory storage cell device as described in any one of claims 1-3, characterized in that: The aforementioned re-global ion implantation is performed while retaining the previously formed floating gate oxide layer on the substrate of the peripheral logic region.

6. The method for adjusting the threshold voltage of the embedded flash memory storage cell device as described in any one of claims 1-3, characterized in that: The floating gate threshold voltage in the memory cell is the same as the selection transistor threshold voltage after adjustment.

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