Probability-based error correction method, equipment and system suitable for memory
By bypassing the OD-ECC stage based on the probability P of the proportion of uncorrectable errors in DRAM memory and directly entering the RL-ECC stage, the problem of the imbalance between DRAM memory error correction performance and system overhead is solved, improving memory reliability and reducing power consumption and latency.
Patent Information
- Application Number
- CN202511321750.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-16
- Publication Date
- 2026-01-16
AI Technical Summary
Existing DRAM memory struggles to balance error correction performance with system overhead. Traditional error correction methods may lead to error correction and reduced memory reliability when the number of error bits exceeds the OD-ECC error correction capability.
Based on the probability P of the proportion of uncorrectable errors in the DRAM memory bank, the OD-ECC stage is bypassed and the error correction is directly entered into the RL-ECC stage, reducing the number of error corrections, improving the effectiveness of data in the RL-ECC stage, and reducing system power consumption and latency.
It effectively reduces error correction during the OD-ECC stage, improves the reliability of DRAM memory, and reduces overall system power consumption and latency.
Smart Images
Figure CN121354643A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of memory reliability, and more specifically, relates to a probability-based error correction method, device, and system applicable to memory. Background Technology
[0002] Due to its advantages such as high access speed, high bandwidth, and low manufacturing cost, Dynamic Random Access Memory (DRAM) has become an indispensable main memory component in various computing systems, widely used in personal computers, servers, high-performance computing platforms, and other fields. To increase storage density and reduce costs, manufacturers are constantly pushing DRAM technology towards smaller feature sizes and higher chip integration. However, this process evolution has also brought higher soft error rates and a greater susceptibility to single-bit flipping problems. Research shows that as the process node shrinks from 40nm to 10nm, the incidence of single-bit errors in DRAM increases exponentially, seriously threatening system stability and data reliability.
[0003] Error correction code (ECC) technology is a key mechanism for improving the fault tolerance of DRAM and ensuring data integrity. Traditional DRAM memory error correction includes two stages executed sequentially: OD-ECC (On-Die-ECC) and RL-ECC (Rank-Level-ECC). OD-ECC is on-chip error detection and correction, while RL-ECC is performed within the memory controller. Traditional Hamming codes can detect and correct single-bit errors and were widely used in early DRAM. As DRAM capacity increased and multi-bit errors became more common, Hamming codes gradually became insufficient for reliability requirements, but they are still used in the OD-ECC stage. Reed-Solomon (RS) codes possess strong multiple error correction capabilities and burst error resistance. By adding redundant symbols after grouping data, they support the simultaneous detection and correction of multiple error symbols, demonstrating significant advantages in harsh environments or high-reliability applications. However, the high error correction capability of RS codes is accompanied by significant encoding and decoding overhead, which poses a challenge in systems with stringent real-time requirements.
[0004] Therefore, while applying error correction code technology to improve DRAM reliability, how to strike a balance between error correction performance and system overhead has become a key issue in research. Summary of the Invention
[0005] In response to the shortcomings and improvement needs of existing technologies, this invention provides a probability-based error correction method, device and system suitable for memory. Its purpose is to achieve a balance between error correction performance and system overhead while improving DRAM reliability by applying error correction code technology.
[0006] To achieve the above objectives, according to one aspect of the present invention, a probability-based error correction method suitable for memory is provided, wherein the memory medium is DRAM, and the error correction method includes: S1: After reading 128 bits of data and the corresponding check bits from the memory bank, decide whether to bypass the OD-ECC stage. If yes, proceed to S3; otherwise, proceed to S2. S2: Use the error correction code and corresponding check bits from the OD-ECC stage to detect and correct errors in the read data, then proceed to S3; S3: Use the error correction codes and corresponding check bits in the RL-ECC stage to detect and correct errors in the read data; The probability P of bypassing the OE-ECC stage is equal to the proportion of uncorrectable errors in the memory bank.
[0007] Furthermore, the methods for calculating the proportion of uncorrectable errors in the memory bank include: Based on the historical error log of memory, count the total number of rows containing uncorrectable errors (Count1), and calculate the proportion of uncorrectable errors in the memory bank according to P=Count1 / Count2; Here, Count2 represents the total number of rows in the memory bank.
[0008] According to another aspect of the present invention, a probability-based error correction device suitable for memory is provided, comprising: Computer-readable media for storing computer programs; And a processor for reading a computer program from a computer-readable storage medium to implement the memory-based probability-based error correction method provided by the present invention.
[0009] According to another aspect of the present invention, a memory system is provided, comprising: DRAM memory, and a probability-based error correction device for memory provided by the present invention.
[0010] According to another aspect of the present invention, a reliability assessment method for the above-mentioned memory system is provided, comprising: T1: Select a memory bank as the bank to be evaluated; T2: Calculate the number of various operational faults based on the FIT values corresponding to various operational faults in the memory system; T3: Inject the corresponding number of operational faults into the Bank to be evaluated; T4: Generate a corresponding number of inherent faults based on the acceptable upper limit of bit error rate and inject them into the Bank to be evaluated; T5: After reading 128 bits of data and the corresponding check bits from the Bank to be evaluated, the probability-based error correction method for memory provided by this invention is used for error detection and correction. T6: Statistical indicators of the reliability of data after error detection and correction, enabling reliability assessment of the memory system.
[0011] Furthermore, reliability metrics include at least one of the following: Detectable but uncorrectable errors; Error correction.
[0012] Furthermore, operational faults include: single-bit errors, single-column errors, two-column errors, partial row errors, two-row errors, multiple row errors, and a single-row error superimposed with a single-bit error; Furthermore, the inherent fault is a single-bit fault.
[0013] According to another aspect of the present invention, a reliability evaluation device for a memory system is provided, comprising: A computer-readable storage medium for storing computer programs; And a processor for reading a computer program stored in a computer-readable storage medium to implement the reliability assessment method provided by the present invention.
[0014] In summary, based on the above technical solutions conceived in this invention, the following beneficial effects can be achieved: Due to the extremely scarce on-chip resources of DRAM memory, the error correction capability of OD-ECC is relatively small, only able to correct a limited number of errors. According to traditional DRAM memory error correction methods, data read from the memory bank sequentially passes through the OD-ECC stage and the RL-ECC stage. This invention discovers that when the number of erroneous bits in the read data exceeds the error correction capability of the error correction code used in the OD-ECC stage, continuing to use OD-ECC for error correction has a certain probability of resulting in error correction. That is, bits that do not need correction are corrected, causing correct bits to become erroneous bits, thus increasing the number of erroneous bits and reducing the performance of the DRAM. Regarding the reliability of data storage, this invention further discovers that the probability of error correction occurring is almost identical to the proportion of uncorrectable errors in the memory bank. Based on this, this invention uses the proportion of uncorrectable errors in the memory bank as the probability P, and when correcting data read from the memory bank, it bypasses the OD-ECC stage according to probability P and directly enters the RL-ECC stage. This effectively reduces the occurrence of error correction in the OD-ECC stage, increases the probability that data can be effectively corrected in the subsequent RL-ECC stage, and significantly reduces the overall energy consumption and latency of the system because some data does not go through the OD-ECC stage. Attached Figure Description
[0015] Figure 1 This is a schematic diagram of a probability-based error correction method applicable to memory, provided in an embodiment of the present invention.
[0016] Figure 2 This is a schematic diagram of the layout of chip data in DRAM during the RL-ECC stage of different RS code schemes provided in embodiments of the present invention.
[0017] Figure 3 This diagram illustrates the reduction in DUE resulting from the memory error correction method provided by the present invention.
[0018] Figure 4 This diagram illustrates the reduction in SDC resulting from the memory error correction method provided by the present invention. Detailed Implementation
[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.
[0020] In this invention, the terms "first," "second," etc. (if present) in the invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
[0021] DRAM: Dynamic Random Access Memory. In DRAM-based memory, DRAM chips are divided into multiple Ranks, each Rank is divided into Banks, and each Bank includes multiple arrays of memory cells, with each array consisting of multiple rows and columns.
[0022] FIT: Failures in time, the failure rate per billion hours.
[0023] ECC: Error Checking and Correcting.
[0024] OD-ECC: On-Die-ECC, on-chip ECC.
[0025] RL-ECC: Rank-Level-ECC, Rank-level ECC, ECC implemented in the memory controller.
[0026] Due to limited on-chip resources, the error correction codes selected in the OD-ECC stage have relatively weak error correction capabilities. In traditional memory error correction schemes, data read from the memory bank undergoes error detection and correction in the OD-ECC and RL-ECC stages sequentially. Without loss of generality, in the following embodiments, the DRAM memory involved uses SEC (136, 128) Hamming codes for error detection and correction in the OD-ECC stage, with an error correction capability of 1 bit; the RL-ECC stage uses RS codes for error detection and correction.
[0027] According to traditional memory error correction methods, for each Bank, 2 17 individual rows and 2 10 Each column is called a data block. The data block is divided into 16 blocks, each block corresponding to 64 columns. One column is selected from the corresponding position in each block, corresponding to 8 bits of data. The data read from the 16 blocks is 128 bits of data. In the OD-ECC encoding stage, an 8-bit check bit is generated according to the Hamming code rules and the 128 bits of data, finally resulting in 136 bits of data. The data and check bit are stored in the data chip and ECC chip respectively.
[0028] For each 128-bit data read from the memory bank, the OD-ECC stage uses Hamming code error correction and detection to check for errors. If a one-bit error is detected, meaning the error is within the error correction capability, it is corrected directly. If an error greater than one bit is detected, it may be a detectable but uncorrectable error (DUE) or an error correction error (SDC).
[0029] Data processed by OD-ECC needs to be transmitted to RL-ECC. The transmission rule is that one data entry in RL-ECC requires simultaneous reception of data from multiple OD-ECC transmissions, totaling 512 data bits and 128 parity bits, forming one data entry in RL-ECC. Upon receiving data from OD-ECC, the error correction code in the RL-ECC stage uses the corresponding RS code for error detection and correction.
[0030] This invention discovers that when the number of error bits in the read data exceeds the error correction capability of the error correction code used in the OD-ECC stage, continuing to use OD-ECC for error correction has a certain probability of error correction occurring, which could actually increase the number of error bits and reduce the reliability of DRAM memory. Using error correction codes with stronger error correction capabilities can improve DRAM reliability, but this also means higher encoding and decoding overhead. To address this issue, and to achieve a balance between error correction performance and system overhead while improving DRAM reliability using error correction code technology, this invention provides a probability-based error correction method, device, and system suitable for memory. The overall concept is that when an uncorrectable error occurs in the OD-ECC stage, error correction is likely to occur. The probability P of this occurrence is statistically calculated, allowing data read from the memory bank to bypass the OD-ECC stage and directly enter the RL-ECC stage according to probability P. This reduces the occurrence of error correction, improves DRAM memory reliability, and reduces overall system latency and power consumption.
[0031] The following is an example.
[0032] Example 1: A probability-based error correction method applicable to memory, where the memory medium is DRAM, such as... Figure 1 As shown, the error correction methods include: S1: After reading 128 bits of data and the corresponding check bits from the memory bank, decide whether to bypass the OD-ECC stage. If yes, proceed to S3; otherwise, proceed to S2. S2: Use the error correction code and corresponding check bits from the OD-ECC stage to detect and correct errors in the read data, then proceed to S3; S3: Use the error correction codes and corresponding check bits in the RL-ECC stage to detect and correct errors in the read data; The probability P of bypassing the OE-ECC stage is equal to the proportion of uncorrectable errors in the memory bank. The proportion of uncorrectable errors in the memory bank can be statistically analyzed at different granularities. To balance statistical complexity and accuracy, this embodiment uses a behavioral granularity for statistical analysis. Specifically, the method for calculating the proportion of uncorrectable errors in the memory bank includes: Based on the historical error log of memory, count the total number of rows containing uncorrectable errors (Count1), and calculate the proportion of uncorrectable errors in the memory bank according to P=Count1 / Count2; Here, Count2 represents the total number of rows in the memory bank.
[0033] Optionally, in this embodiment, when calculating the probability P, the selected historical error logs are specifically the error logs recorded in the Alibaba Cloud 2022 public dataset during eight months of DRAM usage. In the final statistical results, Count1=5680158, Count2=31850496, and the probability P=Count1 / Count2=17.83%. In practical applications, other datasets can also be selected to complete the corresponding statistics based on the DRAM memory usage.
[0034] This embodiment found that the probability of error correction occurring in OD-ECC is almost the same as the proportion of uncorrectable errors in the memory bank. This embodiment calculates this proportion as the probability P of data bypassing OD-ECC, and when performing error correction, the data bypasses the OD-ECC stage according to probability P and directly enters the RL-ECC stage. This can effectively reduce the occurrence of error correction in the OD-ECC stage and increase the probability that the data can be effectively corrected in the subsequent RL-ECC stage. At the same time, since some data does not go through the OD-ECC stage, the overall energy consumption and latency of the system can also be greatly reduced.
[0035] Example 2: A probability-based error correction device for memory, comprising: Computer-readable media for storing computer programs; And a processor for reading a computer program in a computer-readable storage medium to implement the memory-based error correction method provided in Embodiment 1 above.
[0036] Example 3: A memory system includes: DRAM memory, and the probability-based error correction device for memory provided in Embodiment 2 above.
[0037] Example 4: A reliability assessment method for the memory system provided in Embodiment 3 above includes: T1: Select a memory bank as the bank to be evaluated; T2: Calculate the number of various operational faults based on the FIT values corresponding to various operational faults in the memory system; T3: Inject the corresponding number of operational faults into the Bank to be evaluated; T4: Generate a corresponding number of inherent faults based on the acceptable upper limit of bit error rate and inject them into the Bank to be evaluated; T5: After reading 128 bits of data and the corresponding check bits from the Bank to be evaluated, the probability-based error correction method for memory provided by this invention is used for error detection and correction. T6: Statistical indicators of the reliability of data after error detection and correction, enabling reliability assessment of the memory system.
[0038] To comprehensively evaluate the reliability of DRAM memory, the selected operational faults in this embodiment specifically include: single-bit faults, single-column faults, two-column faults, partial-row faults, two-row faults, cluster-row faults, and single-row-plus-single-bit faults.
[0039] FIT (Failures in Time) refers to the failure rate per billion hours. For a specific type of operational failure, the corresponding number of errors can be calculated based on the corresponding FIT value. The specific calculation method is as follows: For example, there are now 10 6 There are several pieces of equipment, and the equipment has been in operation for 7 years. Therefore, the number of operating hours *m* of these pieces of equipment over those 7 years can be calculated as m = 10. 6 * 7 * Number of hours in a year; The number of faults, n, is calculated as follows: n = (FIT * m) / 10 9 .
[0040] Optionally, in this embodiment, the FIT values corresponding to various operational faults and the number of faults calculated according to the above method are as follows: Single-bit (FIT=25.18, 551 faults), Single-column (FIT=1.54, 34 faults), Two-column (FIT=0.49, 11 faults), Partial-row (FIT=19.52, 427 faults), Two-row (FIT=3.92, 86 faults), Cluster-row (FIT=2.44, 53 faults), and Single-row-plus-single-bit (FIT=0.76, 17 faults).
[0041] In this embodiment, the inherent faults (scaling faults) are specifically single-bit errors.
[0042] Typically, the size of a memory bank is approximately 10. 9 The acceptable bit error rate range is typically 10. -8 ~10 -2The corresponding error bit count is 10~10 7 In practical applications, the appropriate number of single-bit errors is injected into the memory bank based on the actual acceptable bit error rate. This results in a memory bank injected with Operational Faults and Scaling Faults. Data is read from this memory bank, and after error detection and correction, the reliability indicators of the statistical data are used to complete the reliability assessment of the DRAM memory.
[0043] In order to accurately reflect the reliability of DRAM memory, the selected reliability indicators in this embodiment specifically include: detectable but uncorrectable errors (DUE) and error-correctable errors (SDC).
[0044] The memory reliability assessment method provided in this embodiment actively injects operational faults and inherent faults into the memory bank, which can effectively simulate the actual use of memory and accurately assess memory reliability by using reasonably selected reliability indicators.
[0045] Example 5: A reliability evaluation device for the memory system provided in Embodiment 3 above includes: A computer-readable storage medium for storing computer programs; And a processor for reading a computer program stored in a computer-readable storage medium to implement the reliability assessment method provided in Embodiment 4 above.
[0046] The following analysis and verification of the beneficial effects that this invention can achieve are based on specific experimental results.
[0047] In the experiment, two different specifications of DRAM chips were selected, as detailed below; One specification consists of 8 data chips (64 bits each) and 2 check chips (ECCC chips), each 64 bits. For this type of DRAM chip, the RS code schemes used in the RL-ECC stage are: RS8(10,8), RS8(40,32), and RS16(40,32), denoted as 82-RS8(10,8), 82-RS8(40,32), and 82-RS16(40,32), respectively. Another specification has 4 data chips, each with 128 bits, and 1 check chip, each with 128 bits. The RS code schemes used for this specification of DRAM chip are: RS8(10,8), RS8(40,32), and RS16(40,32), which are respectively denoted as 41-RS8(10,8), 41-RS8(40,32), and 41-RS16(40,32).
[0048] Figure 2 The chip layout in the DRAM is shown in the 82-RS8 (10,8) scheme. Figure 2 In the chip layout shown, the symbol size is 8 (2×4), and the RS code used is RS(10,8), with a code length of 10 bits, an information bit length of 8 bits, and a check bit length of 2 bits. According to the RS code error correction rules, it can be used to correct an error in one symbol, but its error correction capability is relatively weak. It takes 8 iterations to read a single 640-bit RS code data. For each 80-bit data segment, it is determined whether it is DUE or SDC. If it is DUE, reading stops, and the 640-bit data segment is considered DUE. If it is SDC, it needs to be read completely 8 times, and if the remaining 80 bits of data are not DUE, the 640-bit data segment is considered SDC. Other schemes are similar and will not be shown here.
[0049] The reliability of these two chips was evaluated using the reliability assessment method provided in Example 5 above. Considering that DRAM data density will increase with technological advancements, extended experiments were conducted to test reliability at different probabilities P. Specifically, P=20%, P=40%, P=60%, P=80%, and P=100% were selected for comparison with P=0. P=0 represents the traditional scheme involving sequential OD-ECC and RL-ECC, hereinafter referred to as the baseline scheme. Finally, gem5 was used to test the DRAM's power consumption and latency. Furthermore, for each scheme, an error scale of 10 was selected sequentially. -8 10 -7 10 -6 10 -5 There are four sets of data in total.
[0050] The specific comparison results are as follows: Figure 3 and Figure 4 As shown. Figure 3 The diagram illustrates the reduction in DUE resulting from the memory error correction method provided by this invention. The two rows correspond to two different chip specifications, with each row representing an error scale of 10 from left to right. -8 10 -7 10-6 10 -5 ; Figure 4 The diagram illustrates the reduction in SDC (Site Code Density) resulting from the memory error correction method provided by this invention. The two rows correspond to two different chip specifications, with each row representing an error scale of 10 from left to right. -8 10 -7 10 -6 10 -5 .
[0051] according to Figure 3 and Figure 4 The results show that when P=20%, the reliability improvement brought by this invention is relatively limited. With a DRAM configuration of 8 data chips + 2 check chips, both DUE and SDC are reduced by approximately 20%. In a configuration of 4 data chips + 1 check chip, the reduction in SDC is also around 20%. In these scenarios, the improvement rates among the three RS encoding schemes are not significantly different.
[0052] When P=100%, this invention delivers a more significant reliability improvement and exhibits substantial differences between different RS encoding schemes. With a configuration of 8 data chips + 2 check chips, the DUE of the 82-RS16(40,32) scheme and the SDC of the 82-RS8(10,8) scheme are both reduced by an order of magnitude, while 82-RS16(40,32) is slightly better than 82-RS8(40,32) in terms of SDC reduction. In a configuration of 4 data chips + 1 check chip, the 41-RS8(10,8) scheme achieves the highest DUE reduction, up to 45%, while the SDC reduction is up to two orders of magnitude.
[0053] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A probability-based error correction method suitable for use with memory media, said memory media being DRAM, characterized in that, The error correction method comprises: S1: determining whether to bypass the OD-ECC stage after reading out 128-bit data and corresponding check bits from a memory bank, if yes, turning to S3; otherwise, turning to S2; S2: performing error detection and correction on the read-out data by using the error correction code and corresponding check bits of the OD-ECC stage, and turning to S3; S3: performing error detection and correction on the read-out data by using the error correction code and corresponding check bits of the RL-ECC stage. The probability P of bypassing the OD-ECC stage is equal to the proportion of uncorrectable errors in the memory bank.
2. The probability-based error correction method for memory as claimed in claim 1, wherein, The method for calculating the proportion of uncorrectable errors in the memory bank comprises: According to the historical error log of the memory, the total number Count1 of rows where uncorrectable errors are located is counted, and the proportion of uncorrectable errors in the memory bank is calculated according to P=Count1 / Count2. Count2 represents the total number of rows in the memory bank.
3. A probability-based error correction device suitable for use in a memory, characterized by, It comprises: A computer readable medium for storing a computer program; and a processor for reading the computer program in the computer readable storage medium to implement the probability-based error correction method for memory according to claim 1 or 2.
4. A memory system, comprising: It comprises: A DRAM memory and the probability-based error correction device for memory according to claim 3.
5. The method of claim 4, wherein It comprises: T1: selecting a memory bank as an evaluated bank; T2: calculating the number of each type of operation fault according to the FIT value corresponding to each type of operation fault of the memory in the memory system; T3: injecting a corresponding number of operation faults into the evaluated bank; T4: generating a corresponding number of inherent faults according to the upper limit of the acceptable bit error rate, and injecting the inherent faults into the evaluated bank; T5: after reading out 128-bit data and corresponding check bits from the evaluated bank, performing error detection and correction by using the probability-based error correction method for memory according to claim 1 or 2; T6: calculating the reliability index of the data after error detection and correction to realize reliability evaluation of the memory system.
6. The reliability assessment method of claim 5, wherein, The reliability index comprises at least one of: Detectable but uncorrectable errors; Error-corrected errors.
7. The reliability evaluation method according to claim 5 or 6, characterized by, The operation faults comprise single-bit errors, single-column errors, two-column errors, partial row errors, two-row errors, multi-row errors, and one-row error superimposed single-bit error. And the inherent fault is a single-bit fault.
8. The reliability evaluation device of a memory system according to Claim 4, wherein It comprises: A computer readable storage medium for storing a computer program; and a processor for reading the computer program stored in the computer readable storage medium to implement the reliability evaluation method according to any one of claims 5-7.