A load-insensitive reconfigurable inductance folding quadrature device

Abstract

The application discloses a load-insensitive reconfigurable inductance folding type quadrature device, characterized in that the device comprises a differential quadrature network, wherein the differential quadrature network comprises a first resistance array, a second resistance array, a third resistance array, a fourth resistance array, a first resistance, a second resistance, a first capacitance array, a second capacitance array, a first inductance and a second inductance. On one hand, the first inductance and the second inductance are introduced at a first positive output end and a first negative output end, so that the load capacity of the quadrature device can be enhanced, and the influence of the load on the quadrature signal can be reduced. On the other hand, the resistances are all variable resistance arrays, and the capacitances are all variable capacitance arrays. The resistance values and the capacitance values can be changed through the variable resistance arrays and the variable capacitance arrays, so that the quadrature center frequency of the quadrature device can be reconfigured, the reconfigurable characteristic of the quadrature frequency is realized, and the quadrature device can be widely applied to the technical field of integrated circuits.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a load-insensitive reconfigurable inductor folding quadrature device. Background Technology

[0002] As the core unit of a phased array system, the phase shifter's phase shifting accuracy and other characteristics determine the phased array's directivity and resolution. Similarly, the quadrature array, as the core unit of the RF phase shifter, determines the phase shifter's performance through its area and performance.

[0003] There are currently three methods for generating orthogonal networks: (1) through polyphase filter technology, but this method has a large insertion loss, and the characteristics of resistors and capacitors are significantly affected by the process, resulting in unstable performance; (2) through coupled lines, but this method is difficult to apply in the low-frequency band, and its operating bandwidth is very narrow; (3) through LC all-pass filters, but this method is more sensitive to the load, and changes in the load will affect its orthogonal performance. Existing orthogonal circuit designs have failed to achieve the reconfigurable characteristics of orthogonal frequencies, which to some extent limits their flexibility and adaptability in different application scenarios. Summary of the Invention

[0004] To address the aforementioned technical problems, the purpose of this application is to provide a reconfigurable inductor folding quadrature device that is insensitive to load, enabling the reconfigurable characteristics of quadrature frequencies.

[0005] To achieve the above objectives, one aspect of this application proposes a load-insensitive reconfigurable inductor-folded quadrature device, including a differential quadrature network. The differential quadrature network includes a first resistor array, a second resistor array, a third resistor array, a fourth resistor array, a first resistor, a second resistor, a first capacitor array, a second capacitor array, a first inductor, and a second inductor. The quadrature device includes a non-inverting input terminal, an inverting input terminal, a first positive output terminal, a second positive output terminal, a first negative output terminal, and a second negative output terminal, wherein:

[0006] One end of the first resistor array is connected to the non-inverting input terminal, and the other end of the first resistor array is connected to the first positive output terminal via the first capacitor array and the first inductor in sequence. One end of the third resistor array is connected to the non-inverting input terminal, and the other end of the third resistor array is connected to the second positive output terminal. One end of the fourth resistor array is connected to the inverting input terminal, and the other end of the fourth resistor array is connected to the first negative output terminal via the second capacitor array and the second inductor in sequence. One end of the second resistor array is connected to the inverting input terminal, and the other end of the second resistor array is connected to the second negative output terminal. One end of the first resistor is connected between the first capacitor array and the first inductor, and the other end of the first resistor is connected to the second negative output terminal. One end of the second resistor is connected between the second capacitor array and the second inductor, and the other end of the second resistor is connected to the second positive output terminal.

[0007] In some embodiments, the differential quadrature network further includes a transformer, which includes a primary inductor and a secondary inductor. One end of the primary inductor is connected to the inverting input terminal, and the other end of the primary inductor is connected to one end of the second resistor array. One end of the secondary inductor is connected to the non-inverting input terminal, and the other end of the secondary inductor is connected to one end of the third resistor array.

[0008] In some embodiments, the first resistor array, the second resistor array, the third resistor array, the fourth resistor array, the first resistor, and the second resistor are all equivalent resistors of a variable resistor array.

[0009] In some embodiments, the variable resistor array includes several groups of variable resistor units, each group of variable resistor units including a first switch and a resistor, the first switch and the resistor being connected in series, and each variable resistor unit being connected in parallel. By controlling the state of each first switch, the corresponding resistor is connected to or disconnected from the circuit to adjust the total resistance value of the variable resistor array.

[0010] In some embodiments, the first capacitor array and the second capacitor array are both equivalent capacitances of a variable capacitor array.

[0011] In some embodiments, the variable capacitor array includes several groups of variable capacitor units, each group of variable capacitor units including a second switch and a capacitor, the second switch and the capacitor being connected in series, and each variable capacitor unit being connected in parallel. By controlling the state of each second switch, the corresponding capacitor is connected to or disconnected from the circuit to adjust the total capacitance value of the variable capacitor array.

[0012] In some embodiments, the resistance values ​​of the first resistor array, the second resistor array, the third resistor array, and the fourth resistor array are all equal, and the resistance values ​​of the first resistor and the second resistor are equal.

[0013] In some embodiments, the capacitance values ​​of the first capacitor array and the second capacitor array are equal.

[0014] In some embodiments, the resistance values ​​of the first resistor array, the second resistor array, the third resistor array, the fourth resistor array, the first resistor, and the second resistor satisfy the following:

[0015] R s1 =R s2 =R s3 =R s4 =mR1=mR2;

[0016] Among them, R S1 R represents the resistance value of the first resistor array. S2 R represents the resistance value of the second resistor array. S3 R represents the resistance value of the third resistor array. S4 R1 represents the resistance value of the fourth resistor array, R2 represents the resistance value of the first resistor, and R2 represents the resistance value of the second resistor. <m<1。

[0017] In some embodiments, the orthogonal frequency of the orthogonal device is:

[0018]

[0019] Where ω0 represents the orthogonal frequency, L 11 L represents the inductance value of the primary-side inductor. 12 C1 represents the inductance value of the secondary inductor, C1 represents the capacitance value of the first capacitor array, and k represents the coupling coefficient between the primary inductor and the secondary inductor.

[0020] The beneficial effects of this application are as follows: The reconfigurable inductor-folded quadrature device of this application, which is insensitive to load, includes a differential quadrature network. The differential quadrature network includes a first resistor array, a second resistor array, a third resistor array, a fourth resistor array, a first resistor, a second resistor, a first capacitor array, a second capacitor array, a first inductor, and a second inductor. On the one hand, this application introduces a first inductor and a second inductor at the first positive output terminal and a first negative output terminal, thereby enhancing the load-carrying capacity of the quadrature device and reducing the influence of the load on the quadrature signal. On the other hand, since the resistors are all variable resistor arrays and the capacitors are all variable capacitor arrays, the resistance and capacitance values ​​can be changed by the variable resistor array and the variable capacitor array, thereby reconfiguring the quadrature center frequency of the quadrature device and realizing the reconfigurable characteristics of the quadrature frequency. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments of this application are described below. It should be understood that the drawings described below are only for the purpose of clearly illustrating some embodiments of the technical solutions in this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0022] Figure 1 A circuit schematic diagram of a load-insensitive reconfigurable inductor folding quadrature device provided in one embodiment of this application;

[0023] Figure 2 A circuit schematic diagram of an existing orthogonal circuit design scheme provided in one embodiment of this application;

[0024] Figure 3 This is a schematic diagram of the circuit structure of a modified orthogonal device provided in one embodiment of this application;

[0025] Figure 4 A comparison diagram of the load-carrying capacity of an existing orthogonal circuit design scheme provided in one embodiment of this application and the orthogonal device proposed in an embodiment of this application;

[0026] Figure 5 This is a schematic diagram of the structure of a variable resistor array provided in one embodiment of this application;

[0027] Figure 6 This is a schematic diagram of the structure of a variable capacitor array provided in one embodiment of this application;

[0028] Figure 7 This is an example diagram illustrating the reconstruction of the orthogonal center frequency by switching an array switch, as provided in one embodiment of this application.

[0029] Attached reference numerals: T1, transformer; L 11 Primary inductance; L12 Secondary inductance; R s1 First resistor array; R s2 Second resistor array; R s3 Third resistor array; R s4 Fourth resistor array; R1, first resistor; R2, second resistor; C1, first capacitor array; C2, second capacitor array; L1, first inductor; L2, second inductor. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0031] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various concepts, but unless otherwise stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the words “if,” “when,” or “in response to a determination” as used herein may be interpreted as “when…” or “when…” or “in response to a determination.”

[0032] As used in this application, the terms "at least one", "multiple", "each", "any", etc., "at least one" includes one, two or more, "multiple" includes two or more, "each" refers to each of the corresponding multiples, and "any" refers to any one of the multiples.

[0033] As the core unit of a phased array system, the phase shifter's phase shifting accuracy and other characteristics determine the phased array's directivity and resolution. Similarly, the quadrature array, as the core unit of the RF phase shifter, determines the phase shifter's performance through its area and performance.

[0034] There are currently three methods for generating orthogonal networks: (1) through polyphase filter technology, but this method has a large insertion loss, and the characteristics of resistors and capacitors are significantly affected by the process, resulting in unstable performance; (2) through coupled lines, but this method is difficult to apply in the low-frequency band, and its operating bandwidth is very narrow; (3) through LC all-pass filters, but this method is more sensitive to the load, and changes in the load will affect its orthogonal performance. Existing orthogonal circuit designs have failed to achieve the reconfigurable characteristics of orthogonal frequencies, which to some extent limits their flexibility and adaptability in different application scenarios.

[0035] In view of this, embodiments of this application propose a reconfigurable inductor-folded quadrature device that is insensitive to load, including a differential quadrature network. The differential quadrature network includes a first resistor array, a second resistor array, a third resistor array, a fourth resistor array, a first resistor, a second resistor, a first capacitor array, a second capacitor array, a first inductor, and a second inductor. On the one hand, this application introduces a first inductor and a second inductor at the first positive output terminal and a first negative output terminal, thereby enhancing the load-carrying capacity of the quadrature device and reducing the impact of the load on the quadrature signal. On the other hand, all resistors are variable resistor arrays, and all capacitors are variable capacitor arrays. By changing the resistance and capacitance values ​​through the variable resistor and capacitor arrays, the quadrature center frequency of the quadrature device can be reconfigured, achieving the reconfigurable characteristics of the quadrature frequency.

[0036] Reference Figure 1 , Figure 1 This is a circuit schematic diagram of a load-insensitive reconfigurable inductor folding quadrature device according to an embodiment of this application. The embodiment proposes a load-insensitive reconfigurable inductor folding quadrature device, including a differential quadrature network. The differential quadrature network includes a first resistor array, a second resistor array, a third resistor array, a fourth resistor array, a first resistor, a second resistor, a first capacitor array, a second capacitor array, a first inductor, and a second inductor. The quadrature device includes a non-inverting input terminal, an inverting input terminal, a first positive output terminal, a second positive output terminal, a first negative output terminal, and a second negative output terminal, wherein:

[0037] One end of the first resistor array is connected to the non-inverting input terminal, and the other end of the first resistor array is connected to the first positive output terminal through the first capacitor array and the first inductor in sequence. One end of the third resistor array is connected to the non-inverting input terminal, and the other end of the third resistor array is connected to the second positive output terminal. One end of the fourth resistor array is connected to the inverting input terminal, and the other end of the fourth resistor array is connected to the first negative output terminal through the second capacitor array and the second inductor in sequence. One end of the second resistor array is connected to the inverting input terminal, and the other end of the second resistor array is connected to the second negative output terminal. One end of the first resistor is connected between the first capacitor array and the first inductor, and the other end of the first resistor is connected to the second negative output terminal. One end of the second resistor is connected between the second capacitor array and the second inductor, and the other end of the second resistor is connected to the second positive output terminal.

[0038] Reference Figure 1 As an optional implementation, the differential quadrature network further includes a transformer, which includes a primary inductor and a secondary inductor. One end of the primary inductor is connected to the inverting input terminal, and the other end of the primary inductor is connected to one end of the second resistor array. One end of the secondary inductor is connected to the non-inverting input terminal, and the other end of the secondary inductor is connected to one end of the third resistor array.

[0039] It should be noted that, as Figure 2 The diagram shown is the circuit schematic of an existing orthogonal circuit design scheme. Figure 2 The 17j in the design uses a microstrip inductor, and the 20Ω resistor is used to reduce the Q value of the inductor and capacitor, thereby expanding the bandwidth and reducing the impact of the load on the orthogonal network. The inductor and capacitor form an orthogonal all-pass network. This LC all-pass filter introduces a resistor to reduce the Q value of the inductor and capacitor, thereby expanding the bandwidth and reducing the impact of the load. The load capacitance is at most 50% of the capacitance C (the capacitance value of the LC all-pass filter). However, the separated inductor occupies a significant amount of chip area. Furthermore, this device does not possess the characteristic of orthogonal frequency reconfigurability.

[0040] On the one hand, in the embodiments of this application, the positions of the inductor and capacitor are interchanged, and the deformed structure is as follows: Figure 3 As shown, by utilizing inductor folding technology, the two inductors are replaced with a transformer T1. The structure of transformer T1 is more compact than that of two independent inductors, significantly reducing the circuit's footprint without compromising circuit performance, thus achieving a space-saving effect. On the other hand, as... Figure 1 As shown, in this embodiment of the application, a first inductor L1 and a second inductor L2 are introduced at the first positive output terminal I+ and the first negative output terminal I-. When a load is connected to the output terminal of the quadrature device, the current will flow through these two inductors. Based on the damping effect of the inductors, the rapid change of the load current is effectively suppressed, thereby making the current output of the quadrature device more stable when under load, enhancing the load-carrying capacity of the quadrature device, and reducing the influence of the load on the quadrature signal. Figure 4 The figure shown is a comparison of the load-carrying capacity of existing orthogonal circuit designs and the orthogonal device proposed in the embodiments of this application. Figure 4 It is evident that, by improving upon existing orthogonal circuit design schemes, the orthogonal device proposed in this application embodiment has a stronger load-carrying capacity.

[0041] Specifically, Vin+ and Vin- are differential input terminals, and the primary inductance L of transformer T1... 11 One end is connected to the inverting input terminal Vin- of the input signal, and the primary inductance L of transformer T1 is... 11 The other end is connected to the second resistor array R s2 The second resistor array R s Simultaneously connect the second negative output terminal Q- to one end of the first resistor R1, and connect the other end of the first resistor R1 to one end of the first inductor L1. Also, connect the first capacitor array C1 to the first resistor array R. s1 The first resistor array R s1 The other end is connected to the non-inverting input terminal Vin+ of the input signal, and the other end of the first inductor L1 is connected to the first positive output terminal I+; the secondary inductance L of transformer T1 12 Connect the non-inverting input terminal Vin+, and the secondary inductance L of transformer T1 12 The other end is connected to the third resistor array R s3 The third resistor array R s3 Simultaneously connect the second positive output terminal Q+ to one end of the second resistor R2, and connect the other end of the second resistor R2 to one end of the second inductor L2. Also, connect the second capacitor array C2 to the fourth resistor array R. s4 The fourth resistor array R s4 The other end of the first inductor L1 is connected to the inverting input terminal Vin- of the input signal, and the other end of the second inductor L2 is connected to the first negative output terminal I-.

[0042] Reference Figure 5 , Figure 5 This is a schematic diagram of the structure of a variable resistor array provided in one embodiment of this application. Further, as an optional implementation, the first resistor array, the second resistor array, the third resistor array, the fourth resistor array, the first resistor, and the second resistor are all equivalent resistors of the variable resistor array.

[0043] As a further optional implementation, the variable resistor array includes several groups of variable resistor units. Each group of variable resistor units includes a first switch and a resistor. The first switch and the resistor are connected in series, and the variable resistor units are connected in parallel. By controlling the state of each first switch, the corresponding resistor is connected to or disconnected from the circuit to adjust the total resistance value of the variable resistor array.

[0044] Reference Figure 6 , Figure 6This is a schematic diagram of the structure of a variable capacitor array provided in one embodiment of this application. Further, as an optional implementation, the first capacitor array and the second capacitor array are both equivalent capacitors of the variable capacitor array.

[0045] As a further optional implementation, the variable capacitor array includes several groups of variable capacitor units. Each group of variable capacitor units includes a second switch and a capacitor. The second switch and the capacitor are connected in series, and the variable capacitor units are connected in parallel. By controlling the state of each second switch, the corresponding capacitor is connected to or disconnected from the circuit to adjust the total capacitance value of the variable capacitor array.

[0046] Specifically, the first resistor array R s1 Second resistor array R s2 The third resistor array R s3 Fourth resistor array R s4 The first resistor R1 and the second resistor R2 are both equivalent resistances of the variable resistor array, and the first capacitor array C1 and the second capacitor array C2 are both equivalent capacitances of the variable capacitor array. The values ​​of the first capacitor array C1 and the second capacitor array C2 are controlled by the second switch of the variable capacitor array, thereby reconstructing the orthogonal center frequency of the orthogonal device. The first switch of the variable resistor array controls the values ​​of the first resistor array R1 connected to the orthogonal network. s1 Second resistor array R s2 The third resistor array R s3 Fourth resistor array R s4 The values ​​of the first resistor R1 and the second resistor R2, and the design and switching of the switch array, must satisfy the following relationship:

[0047]

[0048] Among them, R S1 L represents the resistance value of the first resistor array. 11 L represents the inductance value of the primary side inductance. 12 C1 represents the inductance value of the secondary inductor, C1 represents the capacitance value of the first capacitor array, and k represents the primary inductance L. 11 and secondary inductor L 12 The coupling coefficient between them. For example... Figure 7 The diagram shown is an example of reconstructing the quadrature center frequency by switching an array of switches. Figure 7 As can be seen, the embodiments of this application can achieve the reconstruction of the orthogonal center frequency through different array configurations.

[0049] As a further optional implementation, the resistance values ​​of the first resistor array, the second resistor array, the third resistor array, and the fourth resistor array are all equal, and the resistance values ​​of the first resistor and the second resistor are equal.

[0050] Specifically, considering the balance and symmetry of the circuit, R is set... s1 =R s2 =R s3 =R s4 To reduce the Q value of the network and its sensitivity to load capacitance, thereby expanding the bandwidth of the quadrature device; R1 = R2 is set to ensure consistent signal transmission characteristics in the two branches.

[0051] As a further optional implementation, the capacitance values ​​of the first capacitor array and the second capacitor array are equal.

[0052] Specifically, considering the balance and symmetry of the circuit, C1 = C2 is also set.

[0053] As a further optional implementation, the resistance values ​​of the first resistor array, the second resistor array, the third resistor array, the fourth resistor array, the first resistor, and the second resistor satisfy the following:

[0054] R s1 =R s2 =R s3 =R s4 =mR1=mR2;

[0055] Among them, R S1 R represents the resistance value of the first resistor array. S2 R represents the resistance value of the second resistor array. S3 R represents the resistance value of the third resistor array. S4 R1 represents the resistance value of the fourth resistor array, R2 represents the resistance value of the first resistor, and R3 represents the resistance value of the second resistor. <m<1。

[0056] As a further optional implementation, the orthogonal frequency of the orthogonal device is:

[0057]

[0058] Where ω0 represents the quadrature frequency, L 11 L represents the inductance value of the primary side inductance. 12 C1 represents the inductance value of the secondary inductor, C1 represents the capacitance value of the first capacitor array, and k represents the coupling coefficient between the primary and secondary inductors.

[0059] Specifically, by employing the aforementioned quadrature device, the required inductance is reduced, and the chip area is further reduced due to the transformer design. Furthermore, the I-path can use a compensating inductor to further compensate for quadrature errors.

[0060] The structure and working principle of a load-insensitive reconfigurable inductor folding quadrature device according to an embodiment of this application have been described above. It can be recognized that, compared with existing quadrature circuit designs, this application has the following advantages:

[0061] 1. By swapping the positions of the inductors and capacitors and then using inductor folding technology to replace the two inductors with transformers, the circuit area can be significantly reduced without compromising circuit performance, thus achieving the effect of compressing the area.

[0062] Second, by introducing a first inductor L1 and a second inductor L2 into the first positive output terminal I+ and the first negative output terminal I-, the load-carrying capacity of the quadrature device can be enhanced and the influence of the load on the quadrature signal can be reduced.

[0063] Third, all resistors are made of variable resistor arrays and all capacitors are made of variable capacitor arrays. The resistance and capacitance values ​​can be changed by the variable resistor array and the variable capacitor array, thereby reconstructing the orthogonal center frequency of the orthogonal device and realizing the reconfigurable characteristics of the orthogonal frequency.

[0064] In the foregoing description of this specification, the references to terms such as "one embodiment," "another embodiment," or "some embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0065] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

[0066] The above is a detailed description of the preferred embodiments of this application, but this application is not limited to the embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application, and these equivalent modifications or substitutions are all included within the scope defined by the claims of this application.

Claims

1. A load-insensitive reconfigurable inductively folded quadrature device, characterized by, The differential quadrature network comprises a first resistor array, a second resistor array, a third resistor array, a fourth resistor array, a first resistor, a second resistor, a first capacitor array, a second capacitor array, a first inductor and a second inductor, and the quadrature device comprises a non-inverted input end, an inverted input end, a first positive output end, a second positive output end, a first negative output end and a second negative output end, wherein: one end of the first resistor array is connected to the non-inverted input end, the other end of the first resistor array is connected to the first positive output end through the first capacitor array and the first inductor in sequence, one end of the third resistor array is connected to the non-inverted input end, the other end of the third resistor array is connected to the second positive output end, one end of the fourth resistor array is connected to the inverted input end, the other end of the fourth resistor array is connected to the first negative output end through the second capacitor array and the second inductor in sequence, one end of the second resistor array is connected to the inverted input end, the other end of the second resistor array is connected to the second negative output end, one end of the first resistor is connected between the first capacitor array and the first inductor, the other end of the first resistor is connected to the second negative output end, one end of the second resistor is connected between the second capacitor array and the second inductor, and the other end of the second resistor is connected to the second positive output end.

2. The quadrature device of claim 1, wherein, The differential quadrature network further comprises a transformer, the transformer comprises a primary inductor and a secondary inductor, one end of the primary inductor is connected to the inverted input end, the other end of the primary inductor is connected to one end of the second resistor array, one end of the secondary inductor is connected to the non-inverted input end, and the other end of the secondary inductor is connected to one end of the third resistor array.

3. The quadrature device of claim 1, wherein, The first resistor array, the second resistor array, the third resistor array, the fourth resistor array, the first resistor and the second resistor are equivalent resistances of a variable resistor array.

4. The quadrature device of claim 3, wherein, The variable resistor array comprises a plurality of groups of variable resistor units, each group of the variable resistor units comprises a first switch and a resistor, the first switch and the resistor are connected in series, and each of the variable resistor units is connected in parallel, by controlling the state of each of the first switches, the corresponding resistor is connected to or disconnected from the circuit, so as to adjust the total resistance value of the variable resistor array.

5. The quadrature device of claim 1, wherein, The first capacitor array and the second capacitor array are equivalent capacitances of a variable capacitor array.

6. The quadrature device of claim 5, wherein, The variable capacitor array comprises a plurality of groups of variable capacitor units, each group of the variable capacitor units comprises a second switch and a capacitor, the second switch and the capacitor are connected in series, and each of the variable capacitor units is connected in parallel, by controlling the state of each of the second switches, the corresponding capacitor is connected to or disconnected from the circuit, so as to adjust the total capacitance value of the variable capacitor array.

7. The quadrature device of claim 1, wherein, The resistance values of the first resistor array, the second resistor array, the third resistor array and the fourth resistor array are equal, and the resistance values of the first resistor and the second resistor are equal.

8. The quadrature device of claim 1, wherein, Capacitance values of the first capacitance array and the second capacitance array are equal.

9. The quadrature device of claim 1, wherein, Resistance values of the first resistance array, the second resistance array, the third resistance array, the fourth resistance array, the first resistance, and the second resistance satisfy: R s1 = R s2 = R s3 = R s4 = mR1= mR2; wherein R S1 represents a resistance value of the first resistance array, R S2 represents a resistance value of the second resistance array, R S3 represents a resistance value of the third resistance array, R S4 represents a resistance value of the fourth resistance array, R1 represents a resistance value of the first resistance, R2 represents a resistance value of the second resistance, and 0 < m < 1.

10. The quadrature device of claim 2, wherein, An orthogonal frequency of the orthogonal device is: where ω0 represents the quadrature frequency, L 11 represents the inductance value of the primary inductor, L 12 represents the inductance value of the secondary inductor, C1 represents the capacitance value of the first capacitor array, and k represents the coupling coefficient between the primary inductor and the secondary inductor.

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