A voltage current oversampling and dynamic interpolation method, device and storage medium

Abstract

The application relates to a voltage-current oversampling and dynamic interpolation method, device and storage medium, wherein during output, a target voltage is used to calculate a DAC digital quantity, the DAC digital quantity is decomposed into an integer reference value and a decimal part, a decimal error is converted into a time domain adjustment parameter through coefficient quantization, and finally in a continuous output period, two adjacent levels are alternately output by the DAC according to the parameter, the output time proportion is accurately controlled, and the average voltage is forced to approach a set value. During back reading, voltage and current signals are synchronously collected in a fixed high-frequency period, high-signal-to-noise ratio intermediate data units are formed through real-time accumulation, a dynamic circular buffer is used to adaptively average a plurality of units, a high-precision conversion value is output, and the dynamic circular buffer is quickly reset when data suddenly changes. The application cooperates a common-precision ADC and a DAC through a pure software algorithm, effectively breaks through the limitation of inherent resolution of hardware, and improves the system measurement precision and output accuracy without increasing the hardware cost.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and in particular to a voltage and current oversampling and dynamic interpolation method, apparatus and storage medium. Background Technology

[0002] In fields such as precision instruments, industrial control, and automated testing, stringent requirements are placed on the accuracy of voltage and current signal acquisition and output. To achieve high-precision measurement, the industry generally focuses on optimizing hardware circuits. However, current methods mostly aim to fully exploit the performance potential of existing hardware, essentially optimizing existing chips. For a large number of cost-sensitive and already widely used low-to-medium precision hardware platforms, replacing high-bit-count chips to improve performance would significantly increase costs, making it neither economically viable nor scalable. Therefore, how to substantially improve the overall measurement and output accuracy of an ADC and DAC system while maintaining the same resolution bit depth through innovative signal processing and control system design has become a pressing technical problem in this field. Currently, there is a lack of an efficient, low-cost, and easily implemented hardware-software co-processing method to systematically overcome the limitations of inherent hardware quantization errors. Summary of the Invention

[0003] The main objective of this invention is to provide a voltage and current oversampling and dynamic interpolation method, device, and storage medium. By overclocking the number of readbacks and precisely controlling the DAC output duration ratio, the average output voltage is made close to the target value. Thus, the measurement accuracy and output accuracy exceeding the inherent resolution of the hardware are achieved in collaboration between the ADC sampling end and the DAC output end. A low-cost, high-precision integrated hardware and software measurement and control solution is constructed.

[0004] To achieve the above objectives, the present invention provides a voltage and current oversampling and dynamic interpolation method, comprising the following steps:

[0005] By performing analog-to-digital converter (ADC) sampling in a fixed first cycle, the original sampled values ​​of the original sampling sequence of voltage and current are obtained. Multiple consecutive original sampled values ​​are accumulated to form intermediate data corresponding to each first time span in the first cycle.

[0006] Multiple continuously acquired intermediate data are stored in a circular buffer. The effective conversion value is calculated and output based on the values ​​of the latest multiple intermediate data in the circular buffer. The circular buffer is reset when a sudden change in the original sampling sequence or an update of the target voltage setting value is detected.

[0007] Based on the reset circular buffer, the corresponding digital-to-analog converter (DAC) digital value is calculated according to the externally set target voltage value. The integer part is used as the reference value A and the fractional part. The fractional part is multiplied by the amplification factor N and rounded to obtain the adjustment parameter B.

[0008] Within N consecutive second cycles of the amplification factor, the DAC is controlled to alternately output the voltage corresponding to the reference value A and the voltage corresponding to the reference value A+1 according to the adjustment parameter B, so that the average output voltage approaches the target voltage value.

[0009] Furthermore, the step of detecting mutations in the original sampled sequence includes:

[0010] Calculate the difference between adjacent sampled values ​​in the original sampling sequence in real time;

[0011] When the difference exceeds a preset mutation determination threshold, a mutation in the sampled data is determined to have occurred.

[0012] Furthermore, the first period is 50 microseconds; the number of consecutive plurality is 20; and the first time span is 1 millisecond.

[0013] Furthermore, the number of intermediate data stored in the circular buffer is determined by the NPLC parameter, which is a multiple of the power frequency cycle.

[0014] The effective conversion value is calculated based on the values ​​of the latest multiple intermediate data in the circular buffer, and the arithmetic average is calculated based on the values ​​of the latest predetermined number of intermediate data.

[0015] The second cycle is a predetermined voltage output update time interval.

[0016] Furthermore, the NPLC parameter for the power frequency cycle multiple is 5; the amplification factor N is 25; and the second cycle is 100 microseconds.

[0017] Furthermore, the step of controlling the DAC to alternately output the voltage corresponding to the reference value A and the voltage corresponding to the reference value A+1 according to the adjustment parameter B includes:

[0018] Initialize a counter that cycles through the range of 0 to an amplification factor of N-1;

[0019] During the second cycle, the current count value of the counter is compared with the adjustment parameter B;

[0020] If the current count value is less than the adjustment parameter B, the DAC output is controlled to output the voltage corresponding to the reference value A+1; if the current count value is greater than or equal to the adjustment parameter B, the DAC output is controlled to output the voltage corresponding to the reference value A.

[0021] Furthermore, the calculation of the corresponding digital-to-analog converter (DAC) digital quantity yields an integer part as a reference value A and a fractional part. The fractional part is then multiplied by the amplification factor N and rounded to obtain the adjustment parameter B, including:

[0022] The corresponding DAC digital representation is calculated based on the proportional relationship between the target voltage value and the minimum quantization unit of the digital-to-analog converter (DAC).

[0023] The DAC digital representation is decomposed into an integer part and a fractional part;

[0024] The decimal part is multiplied by the amplification factor N and rounded to the nearest integer to generate the adjustment parameter B.

[0025] The present invention also provides a voltage and current oversampling and dynamic interpolation device, comprising:

[0026] The data acquisition module is used to perform analog-to-digital converter (ADC) sampling at a fixed first cycle to obtain the original sampling sequence of voltage and current, and to accumulate multiple consecutive original sampling values ​​to form intermediate data corresponding to each first time span in the first cycle.

[0027] The data processing module is used to store multiple continuously acquired intermediate data into a circular buffer, calculate and output a valid conversion value based on the latest values ​​of the multiple intermediate data in the circular buffer, and reset the circular buffer when a sudden change in the original sampling sequence or an update of the target voltage setting value is detected.

[0028] The interpolation calculation module is used to calculate the corresponding digital-to-analog converter (DAC) digital quantity based on the target voltage value. The integer part is used as the reference value A and the fractional part is used as the fractional part. The fractional part is multiplied by the amplification factor N and rounded to obtain the adjustment parameter B.

[0029] The output control module is used to control the DAC to alternately output the voltage corresponding to the reference value A and the voltage corresponding to the reference value A+1 according to the adjustment parameter B within N consecutive second cycles, so that the average output voltage approaches the target voltage value.

[0030] The present invention also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the voltage and current oversampling and dynamic interpolation method described above.

[0031] The present invention also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the voltage and current oversampling and dynamic interpolation methods described above. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the overall process of the oversampling method in one embodiment of the present invention;

[0033] Figure 2 This is a flowchart of the control logic of the dynamic interpolation algorithm in one embodiment of the present invention;

[0034] Figure 3 This is a schematic diagram of the DAC output error when the dynamic interpolation algorithm is not used according to an embodiment of the present invention;

[0035] Figure 4 This is a schematic diagram of the DAC output error after adopting a dynamic interpolation algorithm according to an embodiment of the present invention;

[0036] Figure 5 This is a schematic flowchart of a voltage and current oversampling and dynamic interpolation method according to an embodiment of the present invention;

[0037] Figure 6 This is a structural block diagram of a voltage and current oversampling and dynamic interpolation device according to an embodiment of the present invention;

[0038] Figure 7 This is a test data graph of an embodiment of the present invention without the use of oversampling;

[0039] Figure 8 This is a continuous readback fluctuation diagram of a conventional method according to an embodiment of the present invention;

[0040] Figure 9 This is a graph of test data after oversampling according to an embodiment of the present invention;

[0041] Figure 10 This is a continuous readback fluctuation diagram after oversampling according to an embodiment of the present invention;

[0042] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0044] Reference Figure 5 The diagram below illustrates the process of a voltage and current oversampling and dynamic interpolation method proposed in this invention, which includes the following steps:

[0045] S1, perform analog-to-digital converter (ADC) sampling through a fixed first cycle to obtain the original sample values ​​of the original sampling sequence of voltage and current, and accumulate multiple consecutive original sample values ​​to form intermediate data corresponding to each first time span in the first cycle;

[0046] S2, based on the multiple intermediate data obtained by continuous acquisition, store them in a circular buffer, calculate and output the effective conversion value based on the values ​​of the latest multiple intermediate data in the circular buffer, and reset the circular buffer when a sudden change in the original sampling sequence or an update of the target voltage setting value is detected.

[0047] S3, based on the reset circular buffer, calculate the corresponding digital-to-analog converter (DAC) digital value according to the externally set target voltage value, and use the integer part as the reference value A and the fractional part. Multiply the fractional part by the amplification factor N and round it to obtain the adjustment parameter B.

[0048] S4, within N consecutive second cycles of amplification factor, the DAC is controlled to alternately output the voltage corresponding to the reference value A and the voltage corresponding to the reference value A+1 according to the adjustment parameter B, so that the average output voltage approaches the target voltage value.

[0049] As described in step S1, voltage and current signals are synchronously acquired at a fixed period of 50 microseconds, and 20 consecutive sampled values ​​are accumulated to form a 1-millisecond intermediate data unit. Through high-frequency synchronous sampling and real-time accumulation, a high-density, low-noise raw data base is provided for ultra-precision processing, which solves the problems of sparse data and weak noise suppression capability of traditional low-frequency sampling.

[0050] As described in step S2, multiple intermediate data units are continuously collected and stored in a circular buffer based on the power frequency cycle multiple parameter. A high-precision conversion value is calculated and output based on the cumulative value of the latest 8 data units. The buffer is reset when a data mutation or set value update is detected to achieve dynamic adaptive averaging filtering, which can quickly respond to signal changes while suppressing noise and balancing steady-state accuracy and dynamic tracking speed.

[0051] As described in step S3, the target voltage is converted into a DAC digital quantity, the integer part A and the fractional part are separated, and the fractional part is multiplied by a preset coefficient of 25 and rounded to obtain the adjustment parameter B. This step quantizes the voltage fractional error that cannot be directly output into a control parameter in the time domain, providing the core calculation basis for achieving accuracy compensation on the low-order DAC.

[0052] As described in step S4, within 25 consecutive output cycles, the DAC is dynamically controlled to alternately output levels A and A+1 based on parameter B. By precisely controlling the ratio of their output durations, the average output voltage is brought close to the target value. The dynamic interpolation output mechanism converts the DAC's static quantization error into a high-frequency switching signal, which, after filtering, can achieve an output accuracy higher than the DAC's inherent resolution.

[0053] In one embodiment, step S1, which involves performing analog-to-digital converter (ADC) sampling through a fixed first cycle to obtain raw sample values ​​of the raw sampling sequence of voltage and current, and accumulating multiple consecutive sets of the raw sample values ​​to form intermediate data corresponding to each first time span in the first cycle, includes:

[0054] S11, fixed-period sampling based on hardware timing;

[0055] S12, multi-channel synchronous sampling and real-time accumulation;

[0056] S13, generation, storage and cyclic reset of intermediate data units.

[0057] In one embodiment, based on fixed-period sampling using hardware timing, the system generates interrupts via a high-precision hardware timer configured with a 50-microsecond period, with each interrupt triggering once. Figure 1 The operation marked with the 50µs sampling value group indicates that the ADC is started to synchronously sample the voltage and current channel signals in sequence. Then, the system proceeds to the multi-channel synchronous sampling and real-time accumulation. The system accumulates the raw values ​​of each channel acquired in this round into the corresponding accumulator and increments a group counter. The process then proceeds as shown in the attached diagram. Figure 1 The "whether 20 sets have been accumulated" judgment logic, as shown, if the number of sets is less than 20, returns to sampling and begins the next 50-microsecond sampling and accumulation cycle; once the number of accumulated 20 sets of sampled values ​​is determined, the generation, saving, and loop reset of the intermediate data unit are immediately executed. At this time, the value in each channel accumulator is the sum of all sampled points in the past 1 millisecond. The system uses this sum as a 1-millisecond intermediate data unit and executes the following... Figure 1 The operation marked by a data point is saved in 1ms, stored in the circular buffer, and then all accumulators and group counters are cleared, thus starting the next 1ms acquisition cycle.

[0058] In one embodiment, step S2, which involves storing multiple continuously acquired intermediate data points into a circular buffer, calculating and outputting a valid conversion value based on the latest values ​​of the intermediate data points in the circular buffer, and resetting the circular buffer when a sudden change in the original sampling sequence or an update to the target voltage setting is detected, includes:

[0059] S21, data acquisition and buffering based on multiples of power frequency cycles;

[0060] S22, Calculation and output of dynamic window average;

[0061] S23, mutation and instruction response and buffer reset.

[0062] Specifically, in the data acquisition and buffering based on the power frequency cycle multiple, the system continuously receives the 1-millisecond intermediate data unit from the high-frequency sampling and accumulation step according to the preset power frequency cycle multiple NPLC parameter NPLC being 5. For example... Figure 1 As shown, after completing the "save one data point every 1ms" step, the process immediately enters the judgment and accumulation stage of "the number of samples required to meet the NPLC setting value". The system sequentially stores the multiple intermediate data units received in succession into a circular buffer constructed as a first-in-first-out queue. Subsequently, the dynamic window average calculation and output are performed. The system continuously maintains and reads the value of the latest third number of intermediate data units in the circular buffer, and performs an arithmetic average operation on this set of values. This average value is calculated and output as the current valid conversion value. Based on the sliding window averaging method of the latest data slice, the system effectively suppresses periodic power frequency noise while ensuring the system's response speed to signal changes. At any given moment, the system executes the mutation and command response and buffer reset in parallel. The mutation detection mechanism monitors the input data in real time. If its rate of change exceeds a preset threshold, a mutation is determined to have occurred. At the same time, the system listens for external commands. Once a new target voltage setting value is received, it is determined to be a command update. When any of the above events is triggered, the system immediately executes the following... Figure 1 The logic of "updating the value of the AVER array according to the current state" refers to the AVER array being a circular buffer. Specifically, this involves clearing all historical data from the circular buffer and filling it with the most recently generated intermediate data unit as a clean starting point for subsequent calculations. The improvement in measurement accuracy brought about by the dynamic averaging and output steps can be quantitatively verified through comparison with test data, such as... Figure 7 As shown, without using the oversampling method of this invention, the fluctuation difference (difference = maximum value - minimum value) of the voltage readback values ​​obtained by collecting approximately 100 points of conventional low-frequency sampling within 100 milliseconds is approximately 0.91982. After applying this method, as... Figure 9 As shown, the number of sampling points increased to approximately 2000 within the same time period, resulting in significantly richer data density and detail. More importantly, the stability of continuous readback values ​​was fundamentally improved. Figure 8 As shown, the fluctuation difference of 200 consecutive readbacks using the traditional method is approximately 0.10824; however, after applying the oversampling method, under the same consecutive readback conditions, such as Figure 10The fluctuation difference shown was significantly reduced to approximately 0.06008. The data comparison from 0.10824 to 0.06008 directly and powerfully demonstrates that this step, through high-frequency sampling, real-time accumulation, and dynamic window averaging, effectively suppressed random noise, improved the signal-to-noise ratio and stability of the measurement signal, and laid a reliable data foundation for achieving high-precision measurement.

[0063] In one embodiment, step S3, based on the reset circular buffer, calculates the corresponding digital-to-analog converter (DAC) digital value according to the externally set target voltage value, uses the integer part as the reference value A and the fractional part as the reference value A, multiplies the fractional part by the amplification factor N and rounds it to obtain the adjustment parameter B, includes:

[0064] S31 receives voltage setting commands and calculates DAC digital values;

[0065] S32, decompose a digital quantity into an integer base value and a fractional part;

[0066] S33, the quantization fractional part is the time domain adjustment parameter.

[0067] In one embodiment, a voltage setting command is received and a DAC digital value is calculated in response to a target voltage setting instruction from the controller, such as... Figure 2 As shown in the "Receive Voltage Setting Command," the system calculates the high-precision floating-point DAC digital representation D required to achieve the target voltage based on the pre-calibrated precise voltage DAC conversion coefficient corresponding to each unit of digital code value. Subsequently, the digital value is decomposed into an integer base value and a fractional part, as follows... Figure 2 After "Calculating DAC Settings," the system proceeds to the logic described in the "Integer Part is A" path. Specifically, the system decomposes the floating-point number D: First, it performs a floor function to obtain the integer base value A, which represents the integer code value that the DAC can directly output that is closest to the target voltage. Then, it calculates the difference F = D - A to obtain the fractional part F (0 ≤ F < 1), which precisely characterizes the residual voltage error that cannot be directly output due to DAC resolution limitations. Finally, the fractional part is quantized into time-domain adjustment parameters, such as... Figure 2 The decimal part during conversion As defined in box B, the system multiplies the decimal part F by the preset amplification factor N = 25, and then performs a rounding operation on the product to obtain the integer adjustment parameter B, i.e., B = round(F). Through this calculation, the tiny voltage residual F in the analog domain is converted into a specific instruction parameter B in the digital domain, used to control the number of level switching cycles in the subsequent N output cycles. This fundamentally overcomes the limitations of test data. Figure 3The periodic output deviation presented, caused by the inherent quantization error of the DAC, provides a key algorithm kernel, thus laying an executable digital control foundation for subsequent super-resolution voltage synthesis through time-domain dynamic modulation.

[0068] In one embodiment, step S4, which controls the DAC to alternately output voltages corresponding to reference value A and reference value A+1 within N consecutive second cycles of amplification factor, so that the average output voltage approaches the target voltage value, includes:

[0069] S41, Dynamic interpolation period and counter initialization;

[0070] S42, level output decision and execution based on dynamic parameter B;

[0071] S43, Cycle count update and dynamic interpolation macro cycle management;

[0072] S44, Verification of Average Voltage Lock-in and Dynamic Conversion of Quantization Error.

[0073] In one embodiment, the system performs dynamic interpolation period and counter initialization. First, it configures a high-precision timer based on a preset second period, defining the update frequency of the DAC output voltage through the period. Simultaneously, the system initializes a cyclic counter and sets it to 0. This counter will cyclically increment within the range of 0 to N-1 (N is the amplification factor of 25), with each count value corresponding to an independent second period. The preparation phase involves implementing... Figure 2 The system establishes a counter-driven decision loop that begins after "taking the integer part as A". Subsequently, in each second-cycle timer interrupt, the system executes a level output decision based on parameter B, a decision process that strictly corresponds to and implements... Figure 2 The core logic of "whether the count value of the set number of times is ≤ B" involves the system comparing the current value of the loop counter with the adjustment parameter B calculated by the interpolation parameters in real time. Subsequently, the system performs loop count updates and DAC output. Based on the comparison result, the system enters... Figure 2 One of the two branches shown: If the current count value is less than B, then as follows Figure 2 As shown in the "Yes" branch, the system controls the DAC output to the higher voltage level corresponding to A+1; otherwise, if the current count value is greater than or equal to B, then... Figure 2As shown in the "No" branch, the system controls the DAC output to a lower voltage level corresponding to the reference value A. After outputting the corresponding voltage, the system increments the cycle counter by 1. If the counter value equals N after incrementing by 1, it is reset to 0, marking the end of a complete dynamic interpolation macrocycle containing N second cycles, and immediately starting the next macrocycle. In this macrocycle, the total number of times the DAC outputs A+1 is exactly equal to B times, and the total number of times it outputs A is NB times. Through precise modulation based on time ratio, the time average value of the DAC output is forcibly locked to A + B / N. Since B / N≈F, this value infinitely approximates the initial target voltage value A + F. Finally, the adjustment parameter B obtained from the interpolation parameter calculation is transformed into high-frequency, precise timing control of the DAC output. This mechanism dynamically transforms the static, discrete quantization error of the DAC into a high-frequency, small-amplitude voltage switch, for example, 1 / (25 (100µs) = 400Hz. This switching component can be filtered out by a simple post-stage analog filter, ultimately obtaining a DC voltage on the load with significantly higher accuracy than the DAC's own LSB. This directly verifies the results shown in the test data. Figure 4 Compared to Figure 3 The comparison results show that the error band between the output voltage and the set value is significantly narrowed, and the periodic sawtooth fluctuations are basically eliminated, achieving the output accuracy characteristics only found in high-bit DACs. Through the aforementioned dynamic interpolation output, the system achieves a fundamental improvement in output accuracy at the digital-to-analog conversion end. This method dynamically converts the static, discrete quantization error of the DAC into a high-frequency, small-amplitude 400Hz voltage switching signal. This high-frequency component can be easily filtered out by a simple analog filter at the back end, ultimately obtaining a smooth DC voltage with significantly higher accuracy than the DAC's minimum resolution at the load. This invention constructs a complete closed loop from "high-precision measurement" to "high-precision output": at the measurement end, such as... Figure 8 and Figure 10 The comparison and data showing a shift from 0.10824 to 0.06008 demonstrate that oversampling significantly reduces readback value fluctuations; at the output, dynamic interpolation effectively eliminates systematic errors caused by insufficient DAC resolution. (See attached image.) Figure 8 As shown, without this algorithm, the DAC output voltage exhibits a typical periodic sawtooth quantization error; however, after applying the dynamic interpolation algorithm of this invention, as... Figure 9 As shown, the output error band is significantly narrowed, the fluctuation is smoothed, and the quantization noise is effectively suppressed. Figure 8 and Figure 9 The direct comparison verifies that this step can achieve the output accuracy characteristics of a high-order DAC.

[0074] Reference Figure 6 The diagram above is a schematic block diagram of a voltage and current oversampling and dynamic interpolation device according to an embodiment of the present invention, comprising:

[0075] The data acquisition module is used to perform analog-to-digital converter (ADC) sampling at a fixed first cycle, acquire the original sampling sequence of voltage and current, and accumulate the original sampling values ​​of a first number of consecutive cycles to form an intermediate data unit.

[0076] The data processing module is used to continuously collect a second number of intermediate data units and store them sequentially into a circular buffer, calculate and output a valid conversion value based on the cumulative value of the latest third number of intermediate data units in the circular buffer, and reset the circular buffer when a sudden change in the sampled data or an update of the target voltage setting value is detected.

[0077] The interpolation calculation module is used to calculate the corresponding digital-to-analog converter (DAC) digital quantity based on the target voltage value, separate its integer part as the reference value A and its fractional part, and multiply the fractional part by the amplification factor N and round it to obtain the adjustment parameter B.

[0078] The output control module is used to control the DAC to alternately output the voltage corresponding to the reference value A and the voltage corresponding to A+1 according to the adjustment parameter B within N consecutive second cycles, so that the average output voltage approaches the target voltage value.

[0079] In summary, this invention synchronously acquires voltage and current signals at a fixed 50-microsecond cycle, and accumulates 20 consecutive sampled values ​​to form a 1-millisecond intermediate data unit. Multiple intermediate data units are continuously acquired based on a power frequency cycle multiple parameter and stored in a circular buffer. A high-precision conversion value is dynamically calculated and output based on the cumulative value of the latest 8 data units in the buffer, and the buffer is reset when a data mutation or setpoint update is detected. The corresponding DAC digital quantity is calculated based on the target voltage value, and its integer part is separated as a reference value A and a fractional part. The fractional part is multiplied by a coefficient of 25 and rounded to obtain the adjustment parameter B. Within 25 consecutive 100-microsecond output cycles, the DAC is controlled to alternately output levels A and A+1 based on parameter B. By precisely adjusting the ratio of their output durations, the average output voltage approaches the target value. Thus, measurement accuracy and output accuracy exceeding the inherent resolution of the hardware are achieved through the coordinated operation of the ADC sampling end and the DAC output end, constructing a low-cost, high-precision integrated hardware and software measurement and control solution.

[0080] In this embodiment, the specific implementation of each unit in the above device embodiment is described in the above method embodiment, and will not be repeated here.

[0081] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the present invention and embodiments can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual-rate SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM, etc.

[0082] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, apparatus, article, or method that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, apparatus, article, or method. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, apparatus, article, or method that includes that element.

[0083] The above description is merely a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A voltage current oversampling and dynamic interpolation method, characterized by, The application comprises the following steps: Performing analog-to-digital conversion (ADC) sampling at a fixed first period to obtain raw sampling values of a raw sampling sequence of voltage and current, accumulating a continuous plurality of the raw sampling values to form intermediate data corresponding to each first time span in a set in the first period; Storing a plurality of intermediate data obtained continuously in a circular buffer, calculating and outputting an effective conversion value based on the numerical values of the plurality of intermediate data in the circular buffer, and resetting the circular buffer when a mutation of the raw sampling sequence or a target voltage setting value is detected; Based on the circular buffer after resetting, calculating a corresponding digital-to-analog conversion (DAC) digital quantity according to an externally set target voltage value, taking an integer part as a reference value A and a decimal part, multiplying the decimal part by an amplification coefficient N and taking an integer to obtain an adjustment parameter B; In a continuous amplification coefficient N second period, controlling the DAC to alternately output a voltage corresponding to the reference value A and a voltage corresponding to the reference value A+1 according to the adjustment parameter B, so that the average output voltage approximates the target voltage value.

2. The voltage current oversampling and dynamic interpolation method of claim 1, wherein, The step of detecting a mutation of the raw sampling sequence comprises: Calculating the difference between adjacent sampling values in the raw sampling sequence in real time; When the difference exceeds a preset mutation determination threshold, determining that a sampling data mutation occurs.

3. The voltage current oversampling and dynamic interpolation method of claim 1, wherein, The first period is 50 microseconds; the continuous plurality of quantities is 20, and the first time span is 1 millisecond.

4. The voltage current oversampling and dynamic interpolation method of claim 1, wherein, The number of the plurality of intermediate data stored in the circular buffer is determined by a power frequency cycle multiple NPLC parameter; The effective conversion value is calculated based on the numerical values of the latest plurality of intermediate data in the circular buffer, and an arithmetic average operation is performed based on the numerical values of the latest predetermined number of intermediate data; The second period is a predetermined voltage output update time interval.

5. The voltage current oversampling and dynamic interpolation method of claim 4, wherein, The power frequency cycle multiple NPLC parameter is 5; the amplification coefficient N is 25; and the second period is 100 microseconds.

6. The voltage current oversampling and dynamic interpolation method of claim 1, wherein, The step of controlling the DAC to alternately output a voltage corresponding to the reference value A and a voltage corresponding to the reference value A+1 according to the adjustment parameter B comprises: Initializing a counter that cyclically counts in the range of 0 to amplification coefficient N-1; In the second period, comparing the current count value of the counter with the adjustment parameter B; If the current count value is less than the adjustment parameter B, controlling the DAC to output a voltage corresponding to the reference value A+1; if the current count value is greater than or equal to the adjustment parameter B, controlling the DAC to output a voltage corresponding to the reference value A.

7. The voltage current oversampling and dynamic interpolation method of claim 1, wherein, The calculation of the corresponding DAC digital quantity, the taking of an integer part as a reference value A and a decimal part, the multiplication of the decimal part by an amplification coefficient N and the taking of an integer to obtain an adjustment parameter B comprises: According to the proportional relationship between the target voltage value and the minimum quantization unit of the digital-to-analog converter (DAC), the corresponding DAC digital quantity representation is calculated; The DAC digital quantity representation is decomposed into an integer part and a decimal part; Performing multiplication by the amplification coefficient N and taking an integer on the decimal part to generate the adjustment parameter B.

8. A voltage current super-sampling and dynamic interpolation apparatus, characterized by, The application comprises the following steps: The data acquisition module is configured to perform analog-digital conversion (ADC) sampling at a fixed first period to obtain a raw sampling sequence of voltage and current, and accumulate a plurality of raw sampling values to form intermediate data corresponding to each first time span in the first period. The data processing module is configured to store a plurality of intermediate data obtained by continuous sampling in a circular buffer, calculate and output an effective conversion value based on the values of the latest plurality of intermediate data in the circular buffer, and reset the circular buffer when a mutation of the raw sampling sequence or an update of a target voltage setting value is detected. The interpolation calculation module is configured to calculate a corresponding digital-analog conversion (DAC) digital quantity according to the target voltage value, obtain an integer part as a reference value A and a decimal part, multiply the decimal part by an amplification coefficient N and take an integer to obtain an adjustment parameter B. The output control module is configured to control the DAC to alternately output a voltage corresponding to the reference value A and a voltage corresponding to the reference value A+1 in N continuous second periods according to the adjustment parameter B, so that an average output voltage approximates to the target voltage value. 9.A computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the computer device is configured to perform the method according to any one of claims 1-8. The processor executes the computer program to implement the steps of the voltage and current oversampling and dynamic interpolation method in any one of claims 1 to 7.

10. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the voltage and current oversampling and dynamic interpolation method in any one of claims 1 to 7.

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