A quantum-resistant password migration optimization method for satellite communication

Abstract

The application discloses a kind of anti-quantum password migration optimization methods for satellite communication, belong to satellite communication field.The application includes: the post-quantum cryptography operation between satellite client and server is executed in parallel by GPU;Signature and verification between satellite client and server are executed in parallel by GPU to reduce the calculation delay of signature and verification;The high-computing-intensive part of QUIC protocol is processed in parallel by GPU acceleration;By optimizing the memory architecture of Xavier chip, efficient memory resource sharing is achieved, reducing the memory bandwidth bottleneck between CPU and GPU, and improving the computing efficiency.The application effectively improves the execution efficiency of anti-quantum password algorithm in satellite communication system through GPU acceleration and ARM memory resource optimization, reduces system delay, and improves communication throughput and security.

Description

A quantum-resistant cryptographic migration optimization method for satellite communications Technical Field

[0001] This invention relates to the field of satellite communication, and more particularly to a method for accelerating computational tasks in the QUIC protocol using a GPU and optimizing memory resources using the ARM architecture of the Xavier chip to ensure low latency, high throughput, and efficient resource utilization in satellite communication. Specifically, it relates to a quantum-resistant cryptographic migration optimization method for satellite communication. Background Technology

[0002] Satellite communication, as a crucial component of modern communication, is widely used in military, aerospace, Earth observation, and internet connectivity. With increasing global communication demands and the rise of satellite internet, satellite communication faces higher requirements in terms of bandwidth, data transmission rates, and real-time performance. Security has always been a critical issue in traditional satellite communication systems, especially given the rapid development of quantum computing technology. Existing encryption algorithms (such as RSA and ECC) may be vulnerable to quantum computing threats. Therefore, quantum-resistant cryptography (such as MLKEM and MLDSA) is of great significance in ensuring the security of satellite communication data.

[0003] However, quantum-resistant encryption algorithms typically involve a large amount of computation, especially in computationally intensive operations such as key generation, encryption / decryption, and signature verification. This leads to increased communication latency, making it impossible to meet real-time requirements, particularly in satellite communication systems. To compensate for this deficiency, GPU acceleration (Graphics Processing Unit), as a highly efficient parallel computing technology, can significantly improve the processing speed of these computational tasks and outperform traditional CPU processing methods in multi-core computing capabilities.

[0004] Currently, most satellite communication systems use NVIDIA Xavier chips, which combine a powerful ARM architecture CPU and GPU and are widely used in satellite communication systems. As a high-efficiency embedded computing platform, the Xavier chip provides powerful computing resources for satellite communication, especially excelling in handling large-scale parallel tasks, where the GPU component performs exceptionally well. Based on the Xavier chip's high-efficiency computing power and flexible memory architecture, combined with accelerated processing of quantum-resistant cryptographic algorithms, the efficiency of key negotiation, encryption / decryption, and signature operations in satellite communication can be significantly improved. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention aims to provide a quantum-resistant cryptographic migration optimization method for satellite communication. Through two main parts—GPU acceleration and ARM memory resource optimization—it effectively improves the execution efficiency of quantum-resistant cryptographic algorithms in satellite communication systems, reduces system latency, and enhances communication throughput and security.

[0006] The objective of this invention is achieved through the following technical solution: a quantum-resistant cryptographic migration optimization method for satellite communication, comprising the following steps:

[0007] The post-quantum cryptographic operations between the satellite client and server are performed in parallel using a GPU, including batch generation of key pairs, key encapsulation and decapsulation to generate shared key pairs; the shared key pairs are stored using an ID pairing mechanism, and the shared key pairs are retrieved based on the ID in subsequent communications;

[0008] By using GPUs to perform signing and verification between satellite clients and servers in parallel, computational latency for signing and verification is reduced, ensuring data integrity and security.

[0009] The computationally intensive parts of the QUIC protocol are accelerated in parallel using GPUs.

[0010] Shared memory management enables the CPU and GPU to directly access key pairs and signature data, avoiding redundant copying;

[0011] An asynchronous computing model and zero-copy technology are used to optimize data transfer efficiency between the CPU and GPU.

[0012] Load balancing is achieved by dynamically scheduling computing resources and allocating tasks based on task priority and the load status of CPU and GPU.

[0013] Furthermore, the parallel execution of post-quantum cryptographic operations between the satellite client and server via GPU specifically involves:

[0014] The server uses the MLKEM algorithm to generate key pairs containing public and private keys in parallel and in batches, stores them in a local database, and assigns a unique key ID to each key pair;

[0015] The server sends the ID and public key to the satellite client. The satellite client generates a random message m, produces ciphertext c through the MLKEM algorithm encapsulation function, and derives the shared key K through the KDF function. The shared key K and the ID are stored in the client database.

[0016] The satellite client sends the ID and ciphertext c to the server. The server uses the private key sk to decrypt the ciphertext and obtains the same shared key K. The shared key K and the ID are stored in the server's database.

[0017] During the actual handshake, the satellite client retrieves the shared key K from the client database and sends its ID to the server. The server then retrieves the corresponding shared key K based on the ID, thus achieving a fast handshake.

[0018] Furthermore, the parallel execution of post-quantum cryptographic operations between the satellite client and server via GPU also includes:

[0019] A separate management thread in the satellite client periodically checks the number of shared key pairs stored in the database and maintains them at a preset threshold.

[0020] Furthermore, the parallel execution of signature and verification between the satellite client and server via GPU specifically involves:

[0021] Before being sent, QUIC protocol data is divided into multiple small blocks, each of which is signed in parallel by a satellite client GPU thread; each thread processes the signature of one data block to reduce computational bottlenecks in the signing process.

[0022] Once all data blocks have been signed, the GPU merges the signed data to generate the final signature result.

[0023] The server uses GPU parallel computing to verify the signature of each data block and ensure the validity of all signatures.

[0024] Furthermore, the computationally intensive components include: flow and congestion control, packet retransmission and error correction, multiplexing and data stream processing, header compression / decompression, flow scheduling and event processing, data acceleration and batch processing, and protocol state machine processing.

[0025] Furthermore, the method of enabling direct access to key pairs and signature data by the CPU and GPU through shared memory management includes: assigning importance values ​​to different tasks and prioritizing the allocation of memory bandwidth to tasks with higher importance values.

[0026] Furthermore, the optimization of data transfer efficiency between the CPU and GPU using an asynchronous computing model and zero-copy technology specifically involves: using an asynchronous computing model to enable the CPU and GPU to work in parallel in an asynchronous mode to handle different tasks during satellite communication; and using zero-copy technology to enable the CPU and GPU to access data through shared memory to reduce data copying operations.

[0027] Furthermore, the dynamic scheduling of computing resources and task allocation based on task priority and CPU and GPU load status includes: dynamically adjusting task allocation according to the real-time requirements of tasks, with GPUs prioritizing computationally intensive tasks and CPUs handling other tasks; and adjusting task allocation according to the load of GPUs and CPUs to avoid excessive resource concentration.

[0028] The present invention also provides an electronic device, including a memory and a processor, wherein the memory is coupled to the processor; wherein the memory is used to store program data, and the processor is used to execute the program data to implement the method.

[0029] The present invention also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method described thereon.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] 1. Significant Performance Improvement: By moving key generation and signature operations in quantum-resistant cryptography algorithms to GPUs for parallel computation, computation speed can be significantly improved, reducing protocol handshake latency and signature latency in satellite communication systems. GPU acceleration greatly enhances computationally intensive tasks and significantly optimizes system performance.

[0032] 2. Resource Optimization: This invention optimizes memory resource usage by combining the memory sharing and bandwidth optimization strategies of the Xavier chip's ARM CPU and GPU, avoiding memory bottlenecks and ensuring efficient computing even in resource-constrained environments.

[0033] 3. Low latency and high throughput: By optimizing memory access, task scheduling and asynchronous computing, data transmission latency is reduced, ensuring efficient communication and meeting the high requirements of low latency and high throughput in satellite communication.

[0034] 4. Quantum security guarantee: The use of quantum-resistant encryption algorithms (such as MLKEM and MLDSA) ensures the long-term security of the satellite communication system in the face of quantum computing threats, protecting sensitive data in satellite communication from being cracked by quantum attacks. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 is a flowchart of the present invention;

[0037] Figure 2 is a flowchart of the MLKEM GPU acceleration process in an embodiment of the present invention;

[0038] Figure 3 is a flowchart of MLDSA GPU acceleration in an embodiment of the present invention;

[0039] Figure 4 is a flowchart of the overall process of applying the GPU acceleration part to the QUIC protocol in an embodiment of the present invention. Detailed Implementation

[0040] To enable those skilled in the art to better understand the technical solutions in the embodiments of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art should fall within the protection scope of the embodiments of this application.

[0041] As shown in Figure 1, this embodiment of the invention provides a quantum-resistant cryptographic migration optimization method for satellite communication, comprising the following steps:

[0042] I. GPU Acceleration Section:

[0043] 1.1. Shared Key Generation (MLKEM): Post-quantum cryptographic operations between the satellite client and server are performed in parallel by the GPU, including batch generation of key pairs, key encapsulation and decapsulation to generate shared key pairs; the shared key pairs are stored through an ID pairing mechanism, and the shared key pairs are retrieved according to the ID in subsequent communications.

[0044] 1.2. Signature Verification (MLDSA): Signature and verification between the satellite client and server are performed in parallel by GPU to reduce computational latency and ensure data integrity and security.

[0045] 1.3. GPU acceleration in the QUIC protocol: The computationally intensive parts of the QUIC protocol are accelerated in parallel by using GPUs.

[0046] II. ARM Memory Resource Optimization:

[0047] 2.1. Memory Sharing and Optimization: Shared memory management enables the CPU and GPU to directly access key pairs and signature data, avoiding redundant copying.

[0048] 2.2. Asynchronous data transmission and zero-copy technology: The asynchronous computing model and zero-copy technology are used to optimize the data transmission efficiency between the CPU and GPU.

[0049] 2.3. Task scheduling and load balancing: Dynamically schedule computing resources and allocate tasks based on task priority and CPU and GPU load status to achieve load balancing.

[0050] Ultimately, password migration was achieved through optimized satellite client and server.

[0051] As a preferred embodiment, both the satellite and ground stations in this implementation use the NVIDIA Xavier chip platform, utilizing its built-in GPU for computational acceleration and ARM architecture for memory optimization.

[0052] (1) A GPU thread is solely responsible for batch generating key pairs (pk, sk) for the MLKEM algorithm. Key encapsulation and decapsulation are performed in advance, and after generating a shared key K, it is associated with a unique ID and stored in the satellite and ground databases respectively. During the QUIC handshake, both parties only need to retrieve the corresponding shared key based on the ID, without the need for real-time calculation.

[0053] (2) Before the data is sent, the satellite uses the GPU to cut the data into multiple small pieces and calculate the MLDSA signature in parallel. After the signature is completed, they are merged into the final signature. The ground station uses the GPU to complete the signature verification in parallel.

[0054] (3) Computationally intensive operations in the QUIC protocol, such as data stream processing, flow control, congestion control, packet loss retransmission, header compression, and state machine update, are significantly accelerated by GPU parallel computing.

[0055] (4) In terms of ARM memory optimization, the computing efficiency of satellite communication systems can be further improved and latency reduced by using shared memory architecture, zero-copy technology and dynamic memory bandwidth scheduling strategy.

[0056] As a preferred embodiment, the goal of step 1.1 is to accelerate the key generation, key encapsulation, and decapsulation process between the satellite client and the ground station (server) using GPU acceleration, and to achieve efficient key exchange. The generated shared key pairs are stored using an ID pairing mechanism, and retrieved based on the ID in subsequent communications. This optimization eliminates the need for real-time, time-consuming MLKEM encapsulation and decapsulation operations during the satellite communication handshake process, significantly improving system performance, making it particularly suitable for resource-constrained satellite communication scenarios.

[0057] On the Xavier chip platform, a dedicated thread on the GPU is responsible for the following specific tasks, as shown in Figure 2, which include the following sub-steps:

[0058] (1.1.1) The server uses the MLKEM algorithm to generate a large number of key pairs (public key pk and private key sk) in parallel and in batches, stores them in the local database, and assigns a unique key ID to each key pair.

[0059] (1.1.2) The satellite client performs key encapsulation operation in advance: the server sends the ID and public key to the client, the client generates a random message (m), generates ciphertext (c) through the encapsulation function of the MLKEM algorithm, and then derives the shared key K through the KDF function; this shared key K is stored together with the ID in the client database.

[0060] (1.1.3) The server performs key decapsulation operation in advance: The client sends the ID and ciphertext (c) to the server. The server uses its own private key sk to decapsulate and obtain the same shared key K. This shared key K and the same ID are stored in the server database.

[0061] (1.1.4) During the actual handshake (ClientHello), the client retrieves the shared key K from the database and sends its ID to the server. The server retrieves the corresponding shared key K based on the ID, thus achieving a fast handshake without the need for real-time calculation, which greatly reduces the latency of satellite communication.

[0062] (1.1.5) The client’s separate management thread will periodically check the number of shared key pairs stored in the database and maintain a certain scale (about 100 pairs) to ensure that both communicating parties can quickly retrieve the key at any time.

[0063] As a preferred embodiment, the goal of step 1.2 is to accelerate the MLDSA signature algorithm using GPUs, reduce the computational latency of signing and verification, and ensure data integrity and security. As shown in Figure 3, this specifically includes the following sub-steps:

[0064] (1.2.1) Data Segmentation and Parallel Signing: Before transmission, QUIC protocol data is segmented into multiple small blocks (e.g., 256KB per block), and each block is processed in parallel by a GPU thread on the satellite client. Each thread processes the signature of one data block, reducing the computational bottleneck in the signing process.

[0065] (1.2.2) Final signature generation: After all data blocks have been signed, the GPU merges these signatures to generate the final signature result, ensuring data integrity.

[0066] (1.2.3) Signature verification: The ground station uses GPU parallel computing to verify the signature of each data block and ensure the validity of all signatures.

[0067] As a preferred embodiment, as shown in Figure 4, step 1.3 specifically includes the following sub-steps:

[0068] (1.3.1) Flow control and congestion control

[0069] The QUIC protocol employs flow control and congestion control mechanisms to ensure network stability, especially in high-latency or unstable network environments such as satellite communication. Flow control and congestion control require a large amount of mathematical computation, and the parallel processing capabilities of GPUs can significantly improve the efficiency of these calculations.

[0070] Flow control: The flow control in the QUIC protocol continuously adjusts the data transmission rate to prevent network overload. GPUs can accelerate these computational tasks, especially in multiplexed connections, by adjusting the transmission rate of each stream more quickly through parallel computing.

[0071] Congestion Control: The QUIC protocol supports various congestion control algorithms (such as BBR, Cubic, etc.), which require processing large amounts of real-time data. GPUs can accelerate these complex computational processes and dynamically optimize transmission paths and rates, reducing latency and increasing throughput.

[0072] (1.3.2) Data packet retransmission and error correction

[0073] The QUIC protocol provides reliable transmission and supports packet loss recovery. When a packet is lost, the QUIC protocol quickly triggers a retransmission mechanism. GPUs can accelerate packet loss detection, retransmission request generation, and data retransmission processing.

[0074] Packet loss detection and retransmission: GPUs can process data packets from multiple connections in parallel, checking for packet loss in each connection and triggering fast retransmissions. The parallel processing of packet loss detection and retransmission tasks across multiple data streams by GPUs can significantly improve retransmission efficiency.

[0075] Error detection and correction: The QUIC protocol supports technologies such as forward error correction (FEC) and redundant transmission. GPUs can accelerate these complex computational tasks, perform error correction in real time, and reduce transmission latency and packet loss.

[0076] (1.3.3) Multiplexing and Data Stream Processing

[0077] One of the most significant features of the QUIC protocol is its support for multiplexing, which allows multiple data streams to be transmitted in parallel within a single connection. Each data stream has its own independent processing procedure and requires scheduling and management. GPUs can process the encryption, decryption, flow control, and transmission of multiple data streams in parallel, thereby improving system throughput.

[0078] Parallel data stream processing: GPUs can process protocol processing tasks of multiple data streams in parallel. For example, tasks such as data stream serialization and deserialization, flow control, and acknowledgment can be significantly accelerated by the parallel capabilities of GPUs.

[0079] Stream scheduling and management: Multiple parallel data streams can involve complex scheduling and resource allocation. GPUs can accelerate these scheduling algorithms, optimize stream allocation, and improve transmission efficiency.

[0080] (1.3.4) Header compression and decompression

[0081] The QUIC protocol uses HPACK (HTTP Header Compression) to compress and decompress header information to reduce the size of transmitted data. In QUIC, each HTTP request contains a large amount of header information, and especially in scenarios with multiple concurrent requests, header compression and decompression are computationally intensive tasks. GPUs can accelerate this process, improving overall performance.

[0082] Parallel compression / decompression: By porting the HPACK compression algorithm to the GPU, header information from multiple data streams can be processed simultaneously, reducing the CPU load and improving compression / decompression speed. The GPU's parallel computing capabilities can significantly accelerate this process.

[0083] (1.3.5) Traffic scheduling and event handling

[0084] In the QUIC protocol, multiple data streams are processed simultaneously within a single connection, and the priority and processing order of each data stream are managed through a scheduling algorithm. The parallel capabilities of GPUs can accelerate the data stream scheduling process, especially when there are a large number of concurrent streams.

[0085] Traffic scheduling: The QUIC protocol allows different data streams to have different priorities. By scheduling multiple streams in parallel through the GPU, bandwidth allocation can be dynamically optimized.

[0086] Event handling: The QUIC protocol triggers a series of events based on changes in network conditions (such as network congestion, latency, etc.). The GPU can process these events in parallel, improving the protocol's response speed and dynamic adaptability.

[0087] (1.3.6) Data acceleration and batch processing

[0088] The QUIC protocol typically processes network data streams, especially in high-concurrency scenarios where large batches of data may need to be processed. GPUs can handle batch data encoding / decoding, retransmission, acknowledgment, and other related operations in parallel, greatly improving data processing speed.

[0089] Batch processing: Data processing of multiple data streams can be parallelized on the GPU, reducing the workload of the CPU and improving the overall data throughput.

[0090] Network latency optimization: By accelerating the acknowledgment and processing of data packets that require long waiting times in the QUIC protocol using GPU, the network latency of the entire system can be reduced, and the efficiency of real-time data transmission can be optimized.

[0091] (1.3.7) Protocol state machine processing

[0092] The QUIC protocol includes multiple state machines to control the connection lifecycle, data transmission, handshake, and closing. GPUs can process the state machines of multiple connections in parallel, helping to reduce the protocol's computational latency, especially in environments with a large number of connections and high concurrency.

[0093] Parallel state machine updates: State machine updates for each connection (e.g., handshake phase, data transfer phase) can be performed in parallel on the GPU, reducing latency in state machine updates.

[0094] In a preferred embodiment, the goal of step 2.1 is to optimize the memory architecture of the Xavier chip to achieve efficient memory resource sharing, reduce memory bandwidth bottlenecks between the CPU and GPU, and improve computational efficiency. Specifically, this includes the following sub-steps:

[0095] (2.1.1) Shared Memory Management: The satellite and ground station use the shared memory architecture of the Xavier chip to store the generated key pairs and signature data in memory, ensuring that both the CPU and GPU can access this data efficiently. All key pairs and signature data are stored in shared memory, avoiding unnecessary memory copying operations.

[0096] (2.1.2) Memory bandwidth priority management: Allocate memory bandwidth according to the importance of the task (such as key generation, signature verification). High-priority tasks use more memory bandwidth to ensure the real-time performance of these tasks.

[0097] In a preferred embodiment, the goal of step 2.2 is to optimize data transfer efficiency between the CPU and GPU and reduce data transfer latency. Specifically, this includes the following sub-steps:

[0098] (2.2.1) Asynchronous computing model: In satellite communication systems, GPU threads perform tasks such as key generation and signature calculation, while CPU threads perform tasks such as protocol stack processing and data transmission. The GPU and CPU work in parallel through asynchronous mode to avoid blocking during the computing process.

[0099] (2.2.2) Zero-copy technology: Through zero-copy technology, the GPU and CPU can directly access data through shared memory, reducing unnecessary data copying operations and further improving data transfer speed and computing efficiency.

[0100] In a preferred embodiment, the goal of step 2.3 is to rationally schedule the computing tasks of the GPU and CPU to ensure efficient system operation with limited resources. Specifically, this includes the following sub-steps:

[0101] (2.3.1) Task priority scheduling: The allocation of tasks is dynamically adjusted according to the real-time requirements of the tasks. The GPU prioritizes processing computationally intensive tasks such as key generation and signature calculation, while the CPU processes other tasks, such as protocol stack processing and data transmission.

[0102] (2.3.2) Load balancing: Adjust task allocation reasonably according to the load of GPU and CPU to avoid excessive concentration of resources and ensure system load balance.

[0103] The present invention also provides an electronic device, including a memory and a processor, wherein the memory is coupled to the processor; wherein the memory is used to store program data, and the processor is used to execute the program data to implement the method.

[0104] The present invention also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method described thereon.

[0105] The computer-readable storage medium can be an internal storage unit of any data processing device described in any of the foregoing embodiments, such as a hard disk or memory. The computer-readable storage medium can also be any data processing device, such as a plug-in hard disk, smart media card (SMC), SD card, flash card, etc., equipped on the device. Furthermore, the computer-readable storage medium can include both internal storage units of any data processing device and external storage devices. The computer-readable storage medium is used to store the computer program and other programs and data required by the data processing device, and can also be used to temporarily store data that has been output or will be output.

[0106] The above implementation methods are simple and clear, and technicians can directly implement this invention, which significantly improves satellite communication efficiency and ensures quantum security.

[0107] It should be understood that the specific order or hierarchy of steps in the disclosed process is an example of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process may be rearranged without departing from the scope of this disclosure. The appended method claims provide elements of various steps in an exemplary order and are not intended to limit the scope to the specific order or hierarchy described.

Claims

1. A quantum-resistant cryptographic migration optimization method for satellite communication, characterized in that, include: Post-quantum cryptographic operations between satellite clients and servers are performed in parallel using GPUs, including batch generation of key pairs, key encapsulation and decapsulation to generate shared key pairs. The shared key pairs are stored using an ID pairing mechanism and retrieved based on the ID in subsequent communications. Signature and verification between the satellite client and server are performed in parallel using GPUs to reduce computational latency. The computationally intensive parts of the QUIC protocol are accelerated in parallel using GPUs. Shared memory management allows direct access to key pairs and signature data between the CPU and GPU. An asynchronous computing model and zero-copy technology optimize data transfer efficiency between the CPU and GPU. Computational resources and task allocation are dynamically scheduled based on task priority and CPU / GPU load status to achieve load balancing. Specifically, the parallel execution of post-quantum cryptographic operations between the satellite client and server using GPUs involves: the server using the MLKEM algorithm to generate key pairs containing public and private keys in batches, storing them in a local database, and assigning a unique key ID to each key pair; the server sending the ID and public key to the satellite client; the satellite client generating a random message m, producing ciphertext c through the MLKEM algorithm's encapsulation function, and deriving the shared key K through the KDF function; and storing the shared key K and ID in the client's database. The satellite client sends its ID and ciphertext c to the server. The server uses its private key sk to decrypt the ciphertext and obtains the same shared key K. The shared key K and the ID are stored in the server's database. During the actual handshake, the satellite client retrieves the shared key K from the client's database and sends its ID to the server. The server retrieves the corresponding shared key K based on the ID, thus achieving a fast handshake.

2. The method according to claim 1, characterized in that, The parallel execution of post-quantum cryptographic operations between the satellite client and the server via GPU also includes: a separate management thread in the satellite client periodically checks the number of shared key pairs stored in the database and maintains them at a preset threshold.

3. The method according to claim 1, characterized in that, The parallel execution of signing and verification between the satellite client and server via GPU is specifically as follows: QUIC protocol data is divided into multiple small blocks before transmission, and each small block is signed in parallel by the satellite client's GPU thread; each thread processes the signing of one data block to reduce computational bottlenecks during the signing process; after all data blocks have been signed, the GPU merges the completed signatures to generate the final signature result; the server uses GPU parallel computing to verify the signature of each data block and ensure the validity of all signatures.

4. The method according to claim 1, characterized in that, The computationally intensive components include: flow and congestion control, packet retransmission and error correction, multiplexing and data stream processing, header compression / decompression, flow scheduling and event processing, data acceleration and batch processing, and protocol state machine processing.

5. The method according to claim 1, characterized in that, The method of enabling direct access to key pairs and signature data by the CPU and GPU through shared memory management includes: assigning importance values ​​to different tasks, and prioritizing the allocation of memory bandwidth to tasks with higher importance values.

6. The method according to claim 1, characterized in that, The optimization of data transfer efficiency between the CPU and GPU using an asynchronous computing model and zero-copy technology specifically involves: using an asynchronous computing model to enable the CPU and GPU to work in parallel in an asynchronous mode to handle different tasks in the satellite communication process; and using zero-copy technology to enable the CPU and GPU to access data through shared memory to reduce data copying operations.

7. The method according to claim 1, characterized in that, The dynamic scheduling of computing resources and task allocation based on task priority and CPU and GPU load status includes: dynamically adjusting task allocation according to the real-time requirements of tasks, with GPUs prioritizing computationally intensive tasks and CPUs handling other tasks; and adjusting task allocation according to the load of GPUs and CPUs to avoid excessive resource concentration.

8. An electronic device comprising a memory and a processor, characterized in that, The memory is coupled to the processor; wherein the memory is used to store program data, and the processor is used to execute the program data to implement the method as described in any one of claims 1-7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the method as described in any one of claims 1-7.

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