Back thinning and polishing preparation method of infrared focal plane array chip assembly

Abstract

According to the back thinning and polishing preparation method for the infrared focal plane array chip assembly, indium columns are evenly distributed between the lower surface of an indium antimonide chip and the upper surface of a circuit, and filling glue is poured between the lower surface of the indium antimonide chip and the upper surface of the circuit in a vacuum mode; the back thinning and polishing preparation method comprises the steps of inverted interconnection, epoxy glue filling and curing, quartz substrate bonding, single-point diamond turning, chemical mechanical polishing, cleaning and corrosion. According to the method, a single-point turning machining mode is adopted, so that damage and crack are not generated, pit-shaped point stress damage is not generated, the PV value is smaller than 1 micron, the machining process is controllable, a traditional downward pressurization grinding mode is changed, the difficulties of pressurization cracking and non-uniform thickness faced by module surface type warping are overcome, and the method can be widely applied to infrared focal plane array chips.

Description

Technical Field

[0001] This invention relates to the fabrication technology of infrared focal plane detector components in semiconductor technology, and more particularly to a method for back-side thinning and polishing fabrication of infrared focal plane array chip components. Background Technology

[0002] Indium antimonide (IST), a group III-V narrow bandgap semiconductor, is a core material for 3-5μm mid-wave infrared detection and is widely used in high-sensitivity military and technological fields. It requires low-temperature operation to reduce dark current. The core requirements for IST chips in infrared focal plane arrays are: high uniformity, low defects, and ultra-thin structure, with a thickness of approximately 10μm after back thinning and polishing, to improve carrier collection efficiency.

[0003] Current mainstream thinning processes are based on the principle of rotary grinding: a hybrid indium antimonide chip is bonded to a quartz substrate, pressed against a grinding disc by a fixture, and pressure is manually applied while grinding slurry is supplied. Thinning is achieved by the rotation of the grinding disc and the rotation of the fixture. This process has significant drawbacks: High risk of damage and cracking: Long-term abrasive mechanical action can easily generate large particles and introduce stress, leading to cracking or stress point pitting damage; Indium antimonide has low hardness, with a Knoop hardness of 2.25-2.93 GPa. Large-size hybrid chips have a warped shape at the four corners and a concave shape in the center due to their own stress. Applying downward pressure can easily lead to uneven local stress, with a thickness difference of more than 3μm, and uneven electrical performance response.

[0004] Low efficiency and automation: The processing relies on the operator's experience, with a high proportion of manual labor and less than 10% equipment utilization; for example, it takes 3 to 4 hours to thin 500μm indium antimonide to 35μm, which is difficult to standardize.

[0005] Surface quality and contamination issues: Excessive back surface roughness (>1μm) will increase device noise and hinder the movement of Sb atoms, resulting in "orange peel" defects; excessive mechanical polishing chemical action cannot remove the surface softening layer, and the damage layer expands after lactic acid corrosion, leading to antireflection film breakage and increased leakage current; contamination by particles, organic impurities, and metal ions will affect the quality of the antireflection film and shorten carrier lifetime.

[0006] Risk of fracture due to temperature difference: After the chip is thinned to 15μm, it is susceptible to stress fracture, and the large temperature difference from room temperature of 300K to 77K will exacerbate the fracture, generate blind clusters, and cause the chip to be scrapped. Summary of the Invention

[0007] The purpose of the present application is to overcome the deficiencies in the prior art, provide a preparation method for back thinning and polishing of an infrared focal plane array chip assembly, which adopts a single-point mechanical machining method and does not produce cracks or pit-shaped stress damage, the PV value is less than 1 mu m, the machining process is controllable, the traditional downward pressure grinding method is changed, and the problems of pressure cracking and uneven thickness are overcome, which can be widely used in infrared focal plane array chips.

[0008] In order to achieve the above-mentioned purpose, the technical scheme adopted by the present application is as follows: a preparation method for back thinning and polishing of an infrared focal plane array chip assembly, the infrared focal plane array chip assembly is composed of an indium antimonide chip, an indium column, filling glue and a circuit, the indium column is uniformly distributed between the lower surface of the indium antimonide chip and the upper surface of the circuit, the filling glue is filled between the lower surface of the indium antimonide chip and the upper surface of the circuit by vacuum injection, the indium antimonide chip is cut into four small wafers from a 2-inch wafer, a step is arranged at the edge of the indium antimonide chip at 300 mu m, and the edge of the filling glue overflows and fills the step edge after solidification; the length and width of the infrared focal plane array chip assembly are both within 50mm*50mm; A preparation method for back thinning and polishing of an infrared focal plane array chip assembly, comprising the following steps: Step 1: flip-chip interconnection is carried out on the thickness of the silicon readout circuit with an indium column and the indium antimonide chip, and temperature, pressure and time interconnection parameters are set to carry out interconnection; Step 2: the combined assembly is placed in a vacuum environment, vacuumized to a vacuum degree of 0.08-0.1 MPa, and then the filling glue is slowly injected, the injection process is continuously observed to ensure that the filling amount of the filling glue completely covers the indium column and the indium antimonide chip step, and the bubbles are effectively removed in the vacuum environment during the filling process; after the filling is completed, the assembly is placed in a curing oven and cured at a temperature of 80-100 DEG C for 2-3 hours, the temperature uniformity in the oven is monitored in real time by using a temperature sensor during the curing process, and the temperature difference is controlled to be within ±2 DEG C by using a temperature control system; Step 3: the back surface profile of the circuit and the back surface profile of the indium antimonide chip are measured by using a laser interferometer, the initial profile before thinning is obtained, the initial thickness is measured by using a thickness measuring instrument, and the wafers are divided according to the initial conditions, and the thickness difference between the wafers on each wafer is less than 4 mu m; Step 4: the circuit back surface of the assembly is arranged on a quartz substrate wafer with a diameter of 105 mm by using an automatic chip mounter, the center of the quartz substrate wafer is taken as the center of a circle, and the circuit back surface is arranged in a circle and in the same direction in sequence clockwise, bubbles are discharged, and the assembly is bonded to obtain an infrared focal plane array chip, the total thickness difference between the wafers after bonding is less than 4 mu m, and the number of products bonded at a time is at least 6; Step 5: The back of the interconnected InSb focal plane array is thinned by diamond point cutting, the single-point machine is an ultra-precision profile machine, the maximum stroke of X and Z axes is 200mm, it is equipped with brushless linear motor driving system, air static pressure bearing, liquid static pressure guide rail, hydraulic oil supply system and spindle motor water cooling system, and the processing diameter is φ250mm; the diamond tool is selected as a chamfered arc tool with negative angle R0.3-0.6, and the thickness of the diamond is 1.3mm; the thinning process is divided into rough turning, semi-fine turning and fine turning, the rough turning parameters are 0.03x2x5, the thinning is 300μm, the stroke is 37.2, and the F number is 30; the semi-fine turning parameters are 0.01x2x8, the thinning is 160μm, the stroke is 37.2, and the F number is 30; the fine turning is divided into three times, the parameters are 0.007x1, 0.005x1 and 0.003x1 respectively, the total thinning is 15μm, and the F number is 30; the quartz substrate sheet is vacuum adsorbed on the Z-axis tooling, the diamond tool is installed on the X-axis, the surface is processed by spraying cooling oil, the tool is cut from the center of the quartz substrate to the assembly, and the cutting width is less than 50mm; the sample with a single processing whole disc diameter of ≤50mm, a quantity of at least 6 and an initial thickness difference between the sheets of ≤4μm is thinned, the thickness of the InSb chip after thinning is 35μm, and the thickness error between the sheets is 35±2μm; Step 6: The thinned infrared focal plane array chip assembly is first sprayed with InSb cleaning agent at 40℃ for 3 minutes, then washed with goose neck pipe for 8 minutes to remove particulate matter, and then subjected to planarization chemical mechanical polishing, the coarse polishing adopts corundum powder polishing liquid with particle size D50=1.089μm, the configuration ratio is water:A:B:C=88:10:1:1, and the time is less than 60 minutes; the fine polishing adopts silica sol polishing liquid, the configuration ratio is water:D:E:F=5:1:1:93, and the time is less than 90 minutes, the roughness is less than 3 nanometers; Step 7: The final thickness is measured by using a white light interference profiler, the thickness difference of the four edges of the InSb chip is less than 3μm, the surface PV value, that is, the damage layer depth is <1μm; when the sample diameter is ≤50mm, the total thickness deviation TTV in a single sample sheet is ≤2μm, when the sample diameter is 50mm Step 8: The polished infrared focal plane array chip assembly is placed in FA / O surfactant solution, washed with cold soft water, and then dried with a film spinner; the surface is coated with photoresist for protection and cured in a natural nitrogen cabinet for 24 hours, the assembly is taken out by heating and melting wax, soaked in a wax removal liquid, dissolved in acetone, and washed with cold soft water for 20 minutes, then placed in heated lactic acid to etch the oxide layer, and taken out, washed and dried. Further, the corundum powder polishing liquid used in the coarse polishing in step 6 is a finished product formula, and the surface flatness after fine polishing meets the use requirements of infrared detection. The beneficial effects of the present application are: no damage and risk of splitting: single-point diamond turning has no downward pressure, avoids uneven stress caused by surface warping, no pit-like stress damage, PV value <1 μm, no cracks and edge collapse under visual inspection.

[0009] High efficiency and automation: thinning 500 μm indium antimonide to 35 μm only takes 40 minutes, improves equipment utilization, and eliminates dependence on manual experience, which can be standardized.

[0010] High surface quality and uniformity: final roughness ≤3 nm, intra wafer TTV ≤6 μm, and inter wafer thickness difference ≤3 μm, avoiding defects of anti-reflective film and increased leakage current.

[0011] Low contamination: through precise cleaning process, control of particle, organic impurity and metal ion contamination, ensure carrier lifetime and device stability. BRIEF DESCRIPTION OF DRAWINGS

[0012] The present application will be further described below in conjunction with the drawings: Figure 1 is a top view structural schematic diagram of the present application; Figure 2 is Figure 1 is a A-A sectional view structural schematic diagram of the present application; Figure 3 is a schematic diagram of the polished surface of Example 1 of the present application under the differential condition of a metallographic microscope; Figure 4 is a schematic diagram of the polished surface of Example 2 of the present application under the differential condition of a metallographic microscope; Figure 5 is a combination diagram of a quartz substrate wafer and an infrared focal plane array chip assembly. DETAILED DESCRIPTION

[0013] The present application will be further described below in conjunction with the drawings: Example 1

[0014] Flip interconnection: select 320×256 array, pixel center distance 30 μm, silicon readout circuit 4 thickness 740 μm and indium antimonide chip 1 thickness 500 μm, interconnection temperature 40℃, pressure 900N. Epoxy glue filling and curing: after filling the epoxy glue, oven curing, laser interferometer measures the surface PV value 2.89 μm, thickness measuring instrument measures the initial thickness 1249 μm. Quartz substrate bonding: bonding temperature 60℃, bonding the assembly to the quartz substrate, inter wafer thickness difference <4 μm. Single point diamond turning: rough turning 0.03mmx2x5, semi-fine turning 0.01mmx2x8, fine turning 0.007 / 0.005 / 0.003mm each parameter processing, thinning to indium antimonide chip 1 remaining thickness 35μm, time 40 minutes; detection surface roughness <1μm, no cracks, edge collapse. Chemical mechanical polishing: coarse polishing: corundum polishing liquid, 60 minutes, fine polishing: silica sol polishing liquid, 90 minutes, final indium antimonide chip 1 thickness 10μm, four corner thickness difference 1.5μm. Cleaning and corrosion: FA / O surfactant cleaning, spin-drying to remove water marks; after removing wax and sol, cold soft water washing for 20 minutes; heating lactic acid to corrode the oxide layer, surface roughness <3nm. Example 2

[0015] The difference from example 1 is that single point diamond turning directly thins indium antimonide chip 1 to 15μm, only 1 chemical polishing in polishing, silica sol polishing liquid, to 10μm, no cracks, edge collapse, roughness <3nm. Example 3

[0016] The difference from example 1 is that single point diamond turning directly thins indium antimonide chip 1 to 10μm, omits chemical mechanical polishing; directly uses heating lactic acid to corrode the oxide layer, no cracks, edge collapse, surface roughness <5nm, meets the basic performance requirements.

[0017] The above only describes the preferred embodiments of the present application, and is not intended to limit the present application, any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for back-thinning and polishing an infrared focal plane array chip assembly, comprising: The infrared focal plane array chip assembly is composed of an indium antimonide chip (1), an indium column (2), a filling glue (3), and a circuit (4). The indium column (2) is uniformly distributed between the lower surface of the indium antimonide chip (1) and the upper surface of the circuit (4). The filling glue (3) is filled between the lower surface of the indium antimonide chip (1) and the upper surface of the circuit (4) by vacuum injection. The indium antimonide chip (1) is cut into four small wafers from a 2-inch wafer. A step is arranged at the edge of the indium antimonide chip (1) 300 μm away. After the filling glue (3) is solidified, the edge overflows and fills the step edge. The length and width of the infrared focal plane array chip assembly are both within 50 mm x 50 mm. ​ The back thinning and polishing preparation method comprises the following steps: Step 1: Flip-chip interconnection is performed on the silicon readout circuit (4) with an indium column (2) and the indium antimonide chip (1) in terms of thickness. The temperature, pressure, and time interconnection parameters are set to carry out interconnection. Step 2: The combined assembly is placed in a vacuum environment, and the vacuum degree is extracted to 0.08-0.1 MPa. Then the filling glue (3) is slowly injected. The injection process is continuously observed to ensure that the filling amount of the filling glue (3) completely covers the indium column (2) and the step of the indium antimonide chip (1). Bubbles are effectively removed through the vacuum environment during the filling process. After filling is completed, the assembly is placed in a curing oven and cured at a temperature of 80-100°C for 2-3 hours. The temperature sensor is used to monitor the uniformity of the oven temperature in real time during the curing process, and the temperature difference is controlled within ±2°C through the temperature control system. Step 3: The back surface profile of the circuit (4) and the back surface profile of the indium antimonide chip (1) are measured by a laser interferometer to obtain the initial profile before thinning. The initial thickness is measured by a thickness measuring instrument, and the wafer is divided according to the initial conditions. The thickness difference between the wafers on each wafer is less than 4 μm. Step 4: The circuit (4) back surface of the assembly is arranged on a 105 mm diameter quartz substrate wafer by a low-temperature wax using an automatic chip mounter. The quartz substrate wafer center is taken as the center of the circle, and the direction is consistent. The bubbles are discharged to complete the bonding to obtain an infrared focal plane array chip. The total thickness difference between the wafers after bonding is less than 4 μm, and the number of products bonded at a time is at least 6. Step 5: The back of the interconnected indium antimonide 1 focal plane array is thinned by diamond point cutting, the single-point machine is an ultra-precision contour machine tool, the maximum stroke of X and Z axes is 200mm, it is equipped with brushless linear motor driving system, air static pressure bearing, liquid static pressure guide rail, hydraulic oil supply system and spindle motor water cooling system, and the processing diameter is φ250mm; the diamond tool is selected to be a chamfered arc tool with negative angle R0.3-0.6, and the thickness of the diamond is 1.3mm; the thinning process is divided into rough turning, semi-fine turning and fine turning, the rough turning parameters are 0.03*2*5, the thinning is 300μm, the stroke is 37.2, and the F number is 30; the semi-fine turning parameters are 0.01*2*8, the thinning is 160μm, the stroke is 37.2, and the F number is 30; the fine turning is divided into three times, the parameters are 0.007*1, 0.005*1 and 0.003*1 respectively, the total thinning is 15μm, and the F number is 30; the quartz substrate sheet is vacuum adsorbed on the Z-axis tooling, the diamond tool is installed on the X-axis, the surface is processed by spraying cooling oil, and the tool is cut from the center of the quartz substrate to the assembly, and the cutting width is less than 50mm; the sample with a single processing whole disc diameter of ≤50mm, a quantity of at least 6 and an initial thickness difference between the sheets of ≤4μm is thinned, the thickness of the thinned indium antimonide chip (1) is 35μm, and the thickness error between the sheets is 35±2μm; Step 6: The thinned infrared focal plane array chip assembly is first sprayed with indium antimonide cleaning agent at 40℃ for 3 minutes, then washed with goose neck pipe for 8 minutes to remove particulate matter, and then subjected to planarization chemical mechanical polishing, the coarse polishing adopts corundum powder polishing liquid with particle size D50=1.089μm, the configuration ratio is water:A:B:C=88:10:1:1, and the time is less than 60 minutes; the fine polishing adopts silica sol polishing liquid, the configuration ratio is water:D:E:F=5:1:1:93, and the time is less than 90 minutes, and the roughness is less than 3 nanometers; Step 7: The final thickness is measured by using a white light interference profiler, the thickness difference of the four edges of the indium antimonide chip (1) is less than 3μm, the surface PV value, that is, the damage layer depth is <1μm; when the sample diameter is ≤50mm, the total thickness deviation TTV in a single sample sheet is ≤2μm, when the sample diameter is 50mm Step 8: The polished infrared focal plane array chip assembly is placed in FA / O surfactant solution, washed with cold soft water, and then dried with a film spinning machine; the surface is coated with photoresist for protection and cured in a natural nitrogen cabinet for 24 hours, the assembly is taken out by heating and melting wax, soaked in a wax removal liquid, acetone-dissolved photoresist and goose neck pipe cold soft water for 20 minutes, and then placed in heated lactic acid to corrode the oxide layer, and taken out, washed and dried.

2. The method of claim 1, wherein, ​

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