Light emitting unit and display substrate

Abstract

A light emitting unit and a display substrate, the light emitting unit including: a light emitting body including a first semiconductor layer, a light emitting layer, and a second semiconductor layer stacked in this order; the third semiconductor layer is arranged on one side, far away from the light-emitting layer, of the second semiconductor layer; the fourth semiconductor layer is arranged on one side, far away from the light-emitting layer, of the third semiconductor layer; the doping type of the fourth semiconductor layer is the same as that of the second semiconductor layer, and the doping type of the fourth semiconductor layer is different from that of the third semiconductor layer; a first connection electrode electrically connected to the first semiconductor layer; a second connection electrode electrically connected to the third semiconductor layer; and a third connection electrode connected to the fourth semiconductor layer.

Description

Light-emitting unit and display substrate TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, in particular to a light-emitting unit and a display substrate. BACKGROUND

[0002] Currently, an LED (Light Emitting Diode) generally has only two electrodes for control and only a light-emitting function; when a display substrate uses an LED as a light-emitting unit, a driving circuit needs to be set for the LED to control the LED to emit light, resulting in a complex process.

[0003] SUMMARY

[0004] The present disclosure aims to at least solve one of the technical problems existing in the prior art, and proposes a light-emitting unit and a display substrate.

[0005] The present disclosure provides a light-emitting unit, comprising:

[0006] a light-emitting body, the light-emitting body comprising a first semiconductor layer, a light-emitting layer and a second semiconductor layer stacked in sequence;

[0007] a third semiconductor layer disposed on a side of the second semiconductor layer away from the light-emitting layer;

[0008] a fourth semiconductor layer disposed on a side of the third semiconductor layer away from the light-emitting layer; the fourth semiconductor layer and the second semiconductor layer are of the same doping type, and the fourth semiconductor layer and the third semiconductor layer are of different doping types;

[0009] a first connection electrode electrically connected to the first semiconductor layer;

[0010] a second connection electrode electrically connected to the third semiconductor layer;

[0011] a third connection electrode connected to the fourth semiconductor layer.

[0012] In some embodiments, the fourth semiconductor layer and the second semiconductor layer are both N-type doped semiconductor materials or both P-type doped semiconductor materials; one of the second semiconductor layer and the third semiconductor layer is an N-type doped semiconductor material, and the other is a P-type doped semiconductor material.

[0013] The doping concentration of the third semiconductor layer is less than the doping concentration of any one of the second semiconductor layer and the fourth semiconductor layer.

[0014] In some embodiments, the thickness of the third semiconductor layer is less than the thickness of any one of the second semiconductor layer and the fourth semiconductor layer, and the volume of the second semiconductor layer is greater than the volume of the fourth semiconductor layer.

[0015] In some embodiments, the light emitting unit further comprises: a first transistor comprising a first gate electrode, a source electrode and a drain electrode, the drain electrode being electrically connected with the second connection electrode.

[0016] In some embodiments, the light emitting unit further comprises:

[0017] a first transistor comprising a first gate electrode, a source electrode and a drain electrode;

[0018] an eighth semiconductor layer disposed on a side of the fourth semiconductor layer away from the light emitting layer, and having a different doping type from the fourth semiconductor layer;

[0019] a ninth semiconductor layer disposed on a side of the eighth semiconductor layer away from the light emitting layer, and electrically connected with the third connection electrode; the ninth semiconductor layer has the same doping type as the fourth semiconductor layer; wherein the eighth semiconductor layer and the ninth semiconductor layer are connected between the third connection electrode and the fourth semiconductor layer;

[0020] a second gate electrode disposed around the eighth semiconductor layer and insulated from the eighth semiconductor layer;

[0021] wherein the second gate electrode is electrically connected with the drain electrode.

[0022] In some embodiments, the first transistor further comprises a fifth semiconductor layer, a sixth semiconductor layer and a seventh semiconductor layer disposed in sequence, the source electrode is electrically connected with the seventh semiconductor layer, and the drain electrode is electrically connected with the fifth semiconductor layer; the first gate electrode is disposed around the sixth semiconductor layer and the seventh semiconductor layer, and is insulated from the sixth semiconductor layer and the seventh semiconductor layer;

[0023] wherein one of the fifth semiconductor layer and the seventh semiconductor layer is disposed in the same layer as the second semiconductor layer, and the other is disposed in the same layer as the fourth semiconductor layer; the sixth semiconductor layer is disposed in the same layer as the third semiconductor layer.

[0024] In some embodiments, the first semiconductor layer is located on a side of the light emitting layer along a first direction, and the fifth semiconductor layer is located on a side of the sixth semiconductor layer along the first direction; the fifth semiconductor layer is disposed in the same layer as the second semiconductor layer, and the seventh semiconductor layer is disposed in the same layer as the fourth semiconductor layer;

[0025] or,

[0026] The drain electrode is electrically connected with the second connection electrode, the first semiconductor layer is located at one side of the light-emitting layer along a first direction, the fifth semiconductor layer is located at one side of the sixth semiconductor layer along a second direction, and the second direction is opposite to the first direction; the fifth semiconductor layer is arranged in the same layer as the fourth semiconductor layer, and the seventh semiconductor layer is arranged in the same layer as the second semiconductor layer.

[0027] In some embodiments, the sixth semiconductor layer and the third semiconductor layer have the same type of doping, the doping concentration of the sixth semiconductor layer is greater than the doping concentration of the third semiconductor layer, and the thickness of the sixth semiconductor layer is greater than the thickness of the third semiconductor layer.

[0028] In some embodiments, when the fifth semiconductor layer is arranged in the same layer as the second semiconductor layer, and the seventh semiconductor layer is arranged in the same layer as the fourth semiconductor layer, the doping concentration in the fifth semiconductor layer is greater than the doping concentration of the second semiconductor layer.

[0029] When the seventh semiconductor layer is arranged in the same layer as the second semiconductor layer, and the fifth semiconductor layer is arranged in the same layer as the fourth semiconductor layer, the doping concentration of the seventh semiconductor layer is greater than the doping concentration of the second semiconductor layer.

[0030] In some embodiments, the first transistor further includes a fifth semiconductor layer and a sixth semiconductor layer arranged in sequence, and the sixth semiconductor layer includes a first semiconductor part and a second semiconductor part arranged in intervals; the source electrode is electrically connected with the first semiconductor part, the drain electrode is connected between the third semiconductor layer and the second semiconductor part, the first gate electrode is located between the first semiconductor part and the second semiconductor part, and is insulated and spaced from the first semiconductor part, the second semiconductor part, and the fifth semiconductor layer.

[0031] The fifth semiconductor layer is arranged in the same layer as one of the second semiconductor layer and the fourth semiconductor layer, and the sixth semiconductor layer is arranged in the same layer as the third semiconductor layer.

[0032] In some embodiments, the first semiconductor layer is located at one side of the light-emitting layer along a first direction, and the fifth semiconductor layer is located at one side of the sixth semiconductor layer along the first direction; the fifth semiconductor layer is arranged in the same layer as the second semiconductor layer.

[0033] Or,

[0034] The first semiconductor layer is located at one side of the light-emitting layer along a first direction, the fifth semiconductor layer is located at one side of the sixth semiconductor layer along a second direction, the second direction is opposite to the first direction, and the fifth semiconductor layer is arranged in the same layer as the fourth semiconductor layer.

[0035] In some embodiments, the sixth semiconductor layer has a doping concentration greater than that in the third semiconductor layer.

[0036] The sixth semiconductor layer has a thickness greater than that of the third semiconductor layer.

[0037] In some embodiments, when the fifth semiconductor layer is disposed in the same layer as the second semiconductor layer, the fifth semiconductor layer has a doping concentration greater than that in the second semiconductor layer.

[0038] In some embodiments, the light emitting unit further comprises:

[0039] The first support portion comprises a first support layer disposed in the same layer as the first semiconductor layer and a second support layer disposed in the same layer as the light emitting layer; wherein the first transistor is located on a side of the second support layer away from the first support layer.

[0040] The first conductive member electrically connects the first support layer and the second support layer.

[0041] In some embodiments, a cross section of the first support portion perpendicular to its thickness direction gradually increases or stepwise increases in a direction away from the first transistor.

[0042] In some embodiments, the first transistor further comprises a fifth semiconductor layer, a sixth semiconductor layer and a seventh semiconductor layer stacked in sequence, the source electrode is electrically connected to the seventh semiconductor layer, and the drain electrode is electrically connected to the fifth semiconductor layer; the first gate electrode is disposed around the sixth semiconductor layer and the seventh semiconductor layer and is insulated and spaced apart from the sixth semiconductor layer and the seventh semiconductor layer; wherein,

[0043] The first semiconductor layer is located on one side of the light emitting layer along a first direction, and the fifth semiconductor layer is located on one side of the sixth semiconductor layer along the first direction; the fifth semiconductor layer is disposed in the same layer as the fourth semiconductor layer, the sixth semiconductor layer is disposed in the same layer as the eighth semiconductor layer, and the seventh semiconductor layer is disposed in the same layer as the ninth semiconductor layer.

[0044] Alternatively,

[0045] The first semiconductor layer is located on one side of the light emitting layer along a first direction, and the fifth semiconductor layer is located on one side of the sixth semiconductor layer along a second direction, the first direction and the second direction are opposite to each other; the fifth semiconductor layer is disposed in the same layer as the eighth semiconductor layer, the sixth semiconductor layer is disposed in the same layer as the fourth semiconductor layer, and the seventh semiconductor layer is disposed in the same layer as the third semiconductor layer.

[0046] In some embodiments, when the fifth semiconductor layer is arranged in the same layer as the eighth semiconductor layer, a projection of the ninth semiconductor layer on a reference plane covers projections of the fifth semiconductor layer and the eighth semiconductor layer on the reference plane, the reference plane being a plane perpendicular to a thickness direction of the light-emitting layer.

[0047] In some embodiments, the first transistor further includes a fifth semiconductor layer and a sixth semiconductor layer arranged in sequence, the sixth semiconductor layer including a first semiconductor portion and a second semiconductor portion arranged in a spaced manner; the source electrode is electrically connected to the first semiconductor portion, the drain electrode is connected between the third semiconductor layer and the second semiconductor portion; the gate electrode is located between the first semiconductor portion and the second semiconductor portion, and is insulated and spaced from the first semiconductor portion, the second semiconductor portion, and the fifth semiconductor layer.

[0048] The fifth semiconductor layer is arranged in the same layer as one of the fourth semiconductor layer and the ninth semiconductor layer, and the sixth semiconductor layer is arranged in the same layer as the eighth semiconductor layer.

[0049] In some embodiments, the first semiconductor layer is located on one side of the light-emitting layer along a first direction, and the fifth semiconductor layer is located on one side of the sixth semiconductor layer along the first direction; the fifth semiconductor layer is arranged in the same layer as the fourth semiconductor layer.

[0050] Alternatively, the first semiconductor layer is located on one side of the light-emitting layer along a first direction, and the fifth semiconductor layer is located on one side of the sixth semiconductor layer along a second direction, the first direction and the second direction pointing in opposite directions; the fifth semiconductor layer is arranged in the same layer as the ninth semiconductor layer.

[0051] In some embodiments, when the fifth semiconductor layer is arranged in the same layer as the fourth semiconductor layer,

[0052] The light-emitting unit further includes:

[0053] The second support portion includes a first support layer arranged in the same layer as the first semiconductor layer, a second support layer arranged in the same layer as the light-emitting layer, a third support layer arranged in the same layer as the second semiconductor layer, and a fourth support layer arranged in the same layer as the fourth semiconductor layer; wherein the first transistor is located on a side away from the fourth support layer and the first support layer.

[0054] The second conductive member electrically connects the first support layer, the second support layer, the third support layer, and the fourth support layer.

[0055] In some embodiments, a cross section of the second support portion perpendicular to a thickness direction thereof gradually increases or stepwisely increases in a direction away from the first transistor.

[0056] In some embodiments, the light emitting unit further comprises a capacitor comprising a first electrode plate and a second electrode plate oppositely arranged, and an insulating layer arranged between the first electrode plate and the second electrode plate, wherein the first electrode plate is in one body structure with the drain electrode of the first transistor.

[0057] When the drain electrode is electrically connected with the second connection electrode and the fourth semiconductor layer is a P-type semiconductor layer, the second electrode plate is connected with the third connection electrode.

[0058] When the drain electrode is electrically connected with the second connection electrode and the fourth semiconductor layer is an N-type semiconductor layer, the second electrode plate is electrically connected with the first connection electrode.

[0059] When the drain electrode is electrically connected with the second gate electrode, the second electrode plate is used to load a ramp signal.

[0060] In some embodiments, the light emitting layer is a quantum well layer, and the light emitting unit is an LED light emitting chip.

[0061] The present disclosure also provides a display substrate, comprising:

[0062] a substrate substrate;

[0063] a plurality of light emitting units as described above, arranged on the substrate substrate;

[0064] a first voltage line electrically connected with the first connection electrode;

[0065] a second voltage line electrically connected with the third connection electrode.

[0066] In some embodiments, the substrate substrate is a GaN substrate. BRIEF DESCRIPTION OF DRAWINGS

[0067] The accompanying drawings are included to provide a further understanding of the present disclosure and constitute a part of the specification, and are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation of the present disclosure. In the drawings:

[0068] FIG. 1A is a schematic diagram of a light emitting unit provided in some embodiments of the present disclosure.

[0069] FIG. 1B is a top view of a light emitting unit provided in some embodiments of the present disclosure.

[0070] FIG. 1C is an equivalent circuit diagram of the light emitting unit in FIG. 1A.

[0071] FIG. 2A is a schematic diagram of a light emitting unit provided in some embodiments of the present disclosure.

[0072] FIG. 2B is an equivalent circuit diagram of the light emitting unit in FIG. 2A.

[0073] FIG. 3A is a schematic diagram of a light emitting unit provided in some embodiments of the present disclosure.

[0074] FIG. 3B is an equivalent circuit diagram of the light emitting unit in FIG. 3A.

[0075] FIG. 4A is a schematic diagram of a light emitting unit provided in some embodiments of the present disclosure.

[0076] FIG. 4B is an equivalent circuit diagram of the light emitting unit in FIG. 4A.

[0077] FIG. 5 is a schematic diagram of a light emitting unit provided in some embodiments of the present disclosure.

[0078] FIG. 6A is a schematic diagram of a light emitting unit provided in some embodiments of the present disclosure.

[0079] FIG. 6B is an equivalent circuit diagram of the light emitting unit in FIG. 6A.

[0080] FIG. 7 is a schematic diagram of a light emitting unit provided in some embodiments of the present disclosure.

[0081] FIG. 8A is a schematic diagram of a light emitting unit provided in some embodiments of the present disclosure.

[0082] FIG. 8B is an equivalent circuit diagram of the light emitting unit in FIG. 8A.

[0083] FIG. 9A is a schematic diagram of a light emitting unit provided in some embodiments of the present disclosure.

[0084] FIG. 9B is an equivalent circuit diagram of the light emitting unit in FIG. 9A.

[0085] FIG. 10A is a schematic diagram of a light emitting unit provided in some embodiments of the present disclosure.

[0086] FIG. 10B is an equivalent circuit diagram of the light emitting unit in FIG. 10A.

[0087] FIG. 11 is a schematic diagram of a light emitting unit provided in some embodiments of the present disclosure.

[0088] FIG. 12A is a schematic diagram of a light emitting unit provided in some embodiments of the present disclosure.

[0089] FIG. 12B is an equivalent circuit diagram of the light emitting unit in FIG. 12A.

[0090] FIG. 13 is a schematic diagram of a display substrate provided in some embodiments of the present disclosure.

[0091] FIG. 14 is a schematic view of a display substrate provided in some other embodiments of the present disclosure. DETAILED DESCRIPTION

[0092] The specific embodiments of the present disclosure will be described below in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely intended to illustrate and explain the present disclosure, and are not intended to limit the present disclosure.

[0093] To make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present disclosure.

[0094] Unless otherwise defined, technical terms or scientific terms used in the embodiments of the present disclosure should be understood as having the same meaning as commonly understood by a person of ordinary skill in the art to which the present disclosure belongs. The terms “first”, “second” and similar terms used in the present disclosure do not indicate any order, number or importance, but are only used to distinguish different components. Similarly, “include” or “contain” and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, without excluding other elements or objects. “Connected” or “connected” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. “Up”, “down”, “left”, “right” and the like are only used to represent relative positional relationships, which may change accordingly when the absolute position of the described object changes.

[0095] As used herein, “parallel”, “perpendicular” includes the stated case and the approximately similar case to the stated case, the range of which is within an acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art considering the measurement being discussed and the error related to the measurement of a specific quantity (i.e., the limitation of the measurement system). For example, “parallel” includes absolute parallel and approximately parallel, wherein the acceptable deviation range of approximately parallel may be, for example, a deviation within 5°; “perpendicular” includes absolute perpendicular and approximately perpendicular, wherein the acceptable deviation range of approximately perpendicular may also be, for example, a deviation within 5°.

[0096] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or there can be an intermediate layer between the layer or element and the other layer or substrate.

[0097] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are schematic and are not intended to be ascribed to the limiting examples. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

[0098] The light emitting unit provided in various embodiments of the present disclosure is shown in FIG. 1A, FIG. 2A, FIG. 3A, FIG. 4A, FIG. 5, FIG. 6A, FIG. 7, FIG. 8A, FIG. 9A, FIG. 10A, FIG. 11, and FIG. 12A. As shown in FIG. 1A to FIG. 12A, the light emitting unit includes a light emitting body 10 including a first semiconductor layer 11, a light emitting layer 10a, and a second semiconductor layer 12 stacked in sequence. The first semiconductor layer 11 and the second semiconductor layer 12 are of different doping types. In addition, the light emitting unit further includes a third semiconductor layer 13, a fourth semiconductor layer 14, a first connection electrode 41, a second connection electrode 42, and a third connection electrode 43.

[0099] The third semiconductor layer 13 is disposed on a side of the second semiconductor layer 12 away from the light emitting layer 10a, and the fourth semiconductor layer 14 is disposed on a side of the third semiconductor layer 13 away from the light emitting layer 10a. The fourth semiconductor layer 14 is of the same doping type as the second semiconductor layer 12 and of a different doping type from the third semiconductor layer 13. The first connection electrode 41 is electrically connected to the first semiconductor layer 11, and the second connection electrode 42 is electrically connected to the third semiconductor layer 13. The third connection electrode 43 is connected to the fourth semiconductor layer 14, where the connection can be direct or indirect, and can be direct electrical connection or a switch or conductive channel that can be turned on and off between the third connection electrode 43 and the fourth semiconductor layer 14, and when the switch or conductive channel is turned on, the third connection electrode 43 is in conduction with the fourth semiconductor layer 14.

[0100] The fourth semiconductor layer 14 is of the same doping type as the second semiconductor layer 12 and of a different doping type from the third semiconductor layer 13 means that the fourth semiconductor layer 14 and the second semiconductor layer 12 are both N-type semiconductors or both P-type semiconductors, or one of the fourth semiconductor layer 14 and the third semiconductor layer 13 is an N-type semiconductor and the other is a P-type semiconductor.

[0101] It should be noted that the N-type semiconductor refers to an electron-type semiconductor, that is, an impurity semiconductor in which the free electron concentration is much greater than the hole concentration. The P-type semiconductor refers to a hole-type semiconductor, that is, an impurity semiconductor in which the hole concentration is much greater than the free electron concentration. In the embodiments of the present disclosure, the N-type semiconductor can be formed by doping an N-type element (such as nitrogen) in a semiconductor material, and the P-type gallium nitride can be formed by doping a P-type element (such as magnesium) in a semiconductor material. Of course, when forming an N-type semiconductor, N-type elements and P-type elements can also be doped in the semiconductor at the same time, as long as the doping amount of the N-type elements is greater than that of the P-type elements, so that the doped material as a whole exhibits the properties of an N-type semiconductor. When forming a P-type semiconductor, N-type elements and P-type elements can also be doped in the semiconductor at the same time, as long as the doping amount of the P-type elements is greater than that of the N-type elements, so that the doped material as a whole exhibits the properties of a P-type semiconductor.

[0102] The N-type element refers to an element that can be doped in a semiconductor material to make the doped semiconductor material exhibit the properties of an N-type semiconductor. The P-type element refers to an element that can be doped in a semiconductor material to make the doped semiconductor material exhibit the properties of a P-type semiconductor. For example, the semiconductor material is GaN, the N-type element is a group IV element such as nitrogen, and the P-type element is a group II element such as magnesium.

[0103] It should be noted that the "doping concentration" in a certain semiconductor layer described below refers to the doping concentration of the N-type element (or P-type element) that can make the semiconductor layer exhibit the corresponding N-type characteristics (or P-type characteristics).

[0104] In the embodiments of the present disclosure, the second semiconductor layer 12, the third semiconductor layer 13, and the fourth semiconductor layer 14 constitute a switching tube, so that the on-off of the light-emitting main body can be controlled, and the switching tube is integrated with the light-emitting main body 10, so that the driving circuit outside the light-emitting unit is reduced or even unnecessary, and then the same process can be used to form the switching tube and the light-emitting main body 10 on the growth substrate, thereby simplifying the process complexity.

[0105] In the embodiments of the present disclosure, one of the first semiconductor layer 11 and the second semiconductor layer 12 is an N-type semiconductor, and the other is a P-type semiconductor; the second semiconductor layer 12 and the fourth semiconductor layer 14 are both P-type semiconductors or both N-type semiconductors. One of the third semiconductor layer 13 and the fourth semiconductor layer 14 is an N-type semiconductor, and the other is a P-type semiconductor.

[0106] The light-emitting unit in the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0107] Fig. 1B is a top view of the light emitting unit shown in Fig. 1A, and Fig. 1C is an equivalent circuit diagram of the light emitting unit shown in Fig. 1A. As shown in Figs. 1A-1C, in some embodiments, the second semiconductor layer 12, the third semiconductor layer 13, and the fourth semiconductor layer 14 constitute a bipolar diode 20 (BJT). The second semiconductor layer 12 and the fourth semiconductor layer 14 are either both N-type doped semiconductor layers or both P-type doped semiconductor layers; one of the third semiconductor layer 13 and the fourth semiconductor layer 14 is an N-type doped semiconductor layer, and the other is a P-type doped semiconductor layer. The doping concentration of the third semiconductor layer 13 is less than that of either of the second semiconductor layer 12 and the fourth semiconductor layer 14, so as to obtain a larger current gain and thus provide a larger driving current for the light emitting body 10. It should be noted that in the light emitting units provided in the following embodiments, the doping concentration of the third semiconductor layer 13 can be set to be less than that of either of the second semiconductor layer 12 and the fourth semiconductor layer 14.

[0108] In some examples, the thickness of the third semiconductor layer 13 is less than that of either of the second semiconductor layer 12 and the fourth semiconductor layer 14, and the volume of the second semiconductor layer 12 is greater than that of the fourth semiconductor layer 14, so as to provide a reverse bias for the collector junction in the bipolar diode 20 and thus make the common-emitter current gain reach a larger value. In the light emitting units provided in the following embodiments, the thickness of the third semiconductor layer 13 can be set to be less than that of either of the second semiconductor layer 12 and the fourth semiconductor layer 14, and the volume of the second semiconductor layer 12 can be set to be greater than that of the fourth semiconductor layer 14.

[0109] In one example, the thickness of the third semiconductor layer 13 is between 30 nm and 300 nm; the thickness of the fourth semiconductor layer 14 is between 300 nm and 2 microns; and the thickness of the second semiconductor layer 12 is between 200 nm and 2 microns. The thickness of the light emitting layer 10a is between 10 nm and 300 nm; and the thickness of the first semiconductor layer 11 is between 200 nm and 2 microns. For example, the thickness of the third semiconductor layer 13 is 200 nm, the thickness of the fourth semiconductor layer 14 is 500 nm, the thickness of the second semiconductor layer 12 is 300 nm, the thickness of the light emitting layer 10a is 50 nm, and the thickness of the first semiconductor layer 11 is 300 nm. For example, the first semiconductor layer 11 of the light emitting body 10 is an N-type semiconductor layer, the thickness of the first semiconductor layer 11 is 1.2 microns, the thickness of the light emitting layer 10a is 180 nm, the thickness of the second semiconductor layer 12 is 160 nm, the thickness of the third semiconductor layer 13 is 80 nm, and the thickness of the fourth semiconductor layer 14 is 150 nm.

[0110] In some examples, the doping concentration of the first semiconductor layer 11 is between 1 x 1018cm-3and 1 x 1020cm-3. 16 cm -3 ~1 x 102020 cm -3 between, for example, the first semiconductor layer 11 has a doping concentration of 1 x 10 18 cm -3 ; the second semiconductor layer 12 has a doping concentration of 1 x 10 15 cm -3 ~ 1 x 10 19 cm -3 ; the third semiconductor layer 13 has a doping concentration of 1 x 10 14 cm -3 ~ 1 x 10 18 cm -3 ; and the fourth semiconductor layer 14 has a doping concentration of 1 x 10 17 cm -3 ~ 1 x 10 21 cm -3 . For example, the first semiconductor layer 11 has a doping concentration of 1 x 10 18 cm -3 , the second semiconductor layer 12 has a doping concentration of 1 x 10 17 cm -3 , the third semiconductor layer 13 has a doping concentration of 1 x 10 16 cm -3 , and the fourth semiconductor layer 14 has a doping concentration of 1 x 10 18 cm -3 .

[0111] In some examples, the light emitting body 10 can be formed on a substrate substrate SUB, for example, a GaN substrate. In this case, a GaN buffer layer can be formed on a growth substrate through an epitaxial growth process, and then the light emitting body 10 can be formed on the buffer layer. After that, the buffer layer can be separated from the growth substrate, and the buffer layer separated from the growth substrate serves as the substrate substrate SUB for carrying the light emitting body 10. In this case, when the light emitting body 10 is located on the side of the third semiconductor layer 13 close to the substrate substrate SUB, the first semiconductor layer 11 can be an N-type semiconductor layer, the second semiconductor layer 12 and the fourth semiconductor layer 14 can be P-type semiconductor layers, and the third semiconductor layer 13 can be an N-type semiconductor layer, because the lattice of the N-type semiconductor layer is more matched with the buffer layer during epitaxial growth. At this time, the second semiconductor layer 12, the third semiconductor layer 13, and the fourth semiconductor layer 14 constitute a PNP bipolar diode 20, and the equivalent circuit diagram of the light emitting body 10 is as shown in FIG. 1C.

[0112] For the PNP bipolar diode 20, when the voltage Ube between the base b and the emitter e is <0, and the voltage Ubc between the base b and the collector c is >0, the PNP bipolar diode 20 has the ability to amplify current. In addition, the fourth semiconductor layer 14 has a high hole doping concentration, the third semiconductor layer 13 has a small thickness and a low doping concentration, and the second semiconductor layer 12 has a low hole doping concentration but a large structure size. At this time, the fourth semiconductor layer 14 (emitter e) applies a high-level voltage Vdd, the third semiconductor layer 13 (base b) applies a base voltage Vb, when Ube <0, a large number of holes in the fourth semiconductor layer 14 move to the third semiconductor layer 13, and because the second semiconductor layer 12 (collector c) has a low hole doping concentration but a large structure size, when Ubc >0, a large number of holes flow into the second semiconductor layer 12. In this way, a low-level voltage is applied to the first connection electrode 41, the pressure difference between the second semiconductor layer 12 and the first semiconductor layer 11 is positive, the holes and the electrons recombine in the light-emitting layer 10a, and Ubc >0, thereby accelerating the movement of the holes and improving the hole injection efficiency. At the same time, the PNP bipolar diode 20 has a current discharge effect, and a small base current Ib can also obtain a large collector current Ic.

[0113] In some examples, as shown in FIGS. 1A and 1B, a portion of the first semiconductor layer 11 can not be covered by the light-emitting layer 10a, and the first connection electrode 41 is located on the portion of the first semiconductor layer 11 that is not covered by the light-emitting layer 10a; a portion of the third semiconductor layer 13 is not covered by the fourth semiconductor layer 14, and the second connection electrode 42 can be located on the portion of the third semiconductor layer 13 that is not covered by the fourth semiconductor layer 14. The third connection electrode 43 can be located on the side of the fourth semiconductor layer 14 away from the third semiconductor layer 13.

[0114] In the embodiment shown in FIG. 2A, in addition to the light-emitting unit including the light-emitting body 10, the third semiconductor layer 13, the fourth semiconductor layer 14, the first connection electrode 41, the second connection electrode 42, and the third connection electrode 43, the light-emitting unit can further include a first transistor 31, the first transistor 31 including a first gate electrode 311, a source electrode 312, and a drain electrode 313, the drain electrode 313 being electrically connected to the second connection electrode 42.

[0115] In FIG. 2A, the materials, thicknesses, and the like of the light-emitting body 10, the third semiconductor layer 13, and the fourth semiconductor layer 14 can be set as described above for FIG. 1A, and will not be described again here.

[0116] As shown in FIG. 2A, the first transistor 31 further includes a fifth semiconductor layer 15, a sixth semiconductor layer 16 and a seventh semiconductor layer 17. Among them, the source electrode 312 is electrically connected with the seventh semiconductor layer 17, and the drain electrode 313 is electrically connected with the fifth semiconductor layer 15; the first gate electrode 311 is arranged around the sixth semiconductor layer 16 and the seventh semiconductor layer 17, and is insulated and spaced apart from the sixth semiconductor layer 16 and the seventh semiconductor layer 17. The fifth semiconductor layer 15 and the sixth semiconductor layer 16 are different in doping type, and the same in doping type as the seventh semiconductor layer 17, forming a field effect transistor (FET). For example, the fifth semiconductor layer 15 and the seventh semiconductor layer 17 are both N-type semiconductor layers or both P-type semiconductor layers, and one of the fifth semiconductor layer 15 and the sixth semiconductor layer 16 is an N-type semiconductor layer and the other is a P-type semiconductor layer. When the first gate electrode 311 applies an opening voltage, an electric field is formed between the sixth semiconductor layer 16 and the seventh semiconductor layer 17 and between the sixth semiconductor layer 16 and the fifth semiconductor layer 15, thereby turning on the source electrode 312 and the drain electrode 313. For example, for an NPN type FET tube, the first gate electrode 311 applies a positive voltage, the electrons in the N-type semiconductor layer move to both sides, and the holes in the P-type semiconductor layer move to the middle, forming a current transmission path.

[0117] In some examples, the light emitting unit can further include a capacitor C1 including a first plate C11 and a second plate C12. The first plate C11 can be an integral structure with the drain electrode 313, and the second plate C12 can be electrically connected with the third connection electrode 43, both of which are used to load a high-level voltage Vdd; wherein the second plate C12 and the third connection electrode 43 can be an integral structure, of course, the second plate C12 and the third connection electrode 43 can also be arranged separately and connected to the same voltage line. It should be noted that the capacitor C1 in the drawings of the present disclosure is only schematic and does not represent the actual size of the plates of the capacitor C1.

[0118] Taking the sixth semiconductor layer 16 as an N-type semiconductor layer and the bipolar diode 20 as a PNP bipolar diode 20 as an example, an equivalent circuit diagram of the first transistor 31, the bipolar diode 20, and the capacitor C1 is shown in FIG. 2B. The first gate can be connected to a scan line, and the source electrode 312 is connected to a data line. When the scan signal Gate(n) on the scan line is at a high level, the data signal Data on the data line is written to the base of the bipolar diode 20. By controlling Ube<0 and Ubc>0, the bipolar diode 20 is in an amplification state, and high-current input light emission of the light emitting body 10 is achieved. The voltage value of the data signal Data can be controlled to control the size of Ube, thereby obtaining different base currents Ib, and further controlling the collector current Ic (i.e., the current flowing through the light emitting body 10, Ic=βIb); when Ube>0, the bipolar diode 20 is in a cut-off state, and the collector and the emitter are disconnected, and the light emitting body 10 does not emit light.

[0119] It can be understood that in the display substrate, a plurality of light emitting units can be arranged in an array, and a row of light emitting units can be connected to a scan line. When the display substrate displays, the driving circuit provides a scan signal to the scan line row by row. During the process in which the light emitting unit of a certain row emits light by receiving the scan signal to make the light emitting body 10 emit light, the data signal is written into the capacitor C1 for storage. Through the energy storage effect of the capacitor C1, the light emitting unit can still maintain the light emitting state after the end of the current scan line, until the next frame of display picture.

[0120] In some examples, one of the fifth semiconductor layer 15 and the seventh semiconductor layer 17 is arranged in the same layer as the second semiconductor layer 12, and the other is arranged in the same layer as the fourth semiconductor layer 14; and the sixth semiconductor layer 16 is arranged in the same layer as the third semiconductor layer 13. For example, in FIG. 2A, the first semiconductor layer 11 is located on one side of the light emitting layer 10a along the first direction, and the fifth semiconductor layer 15 is located on one side of the sixth semiconductor layer 16 along the first direction. At this time, the fifth semiconductor layer 15 is arranged in the same layer as the second semiconductor layer 12, and the seventh semiconductor layer 17 is arranged in the same layer as the fourth semiconductor layer 14.

[0121] It should be noted that in the embodiments of the present disclosure, the two semiconductor layers arranged in the same layer means that the two semiconductor layers can be formed by the same growth process, thereby simplifying the preparation process, but it does not mean that the distance of the two semiconductor layers to the substrate SUB is the same, and it also does not mean that the thickness and the doping concentration of the two semiconductor layers are consistent. For example, after forming the two semiconductor patterns by the growth process, a thinning process or an ion implantation process can be further performed, thereby obtaining two semiconductor layers with different thicknesses or different doping concentrations.

[0122] For example, in FIG. 2A, the sixth semiconductor layer 16 and the third semiconductor layer 13 have the same doping type, the doping concentration of the sixth semiconductor layer 16 is greater than that of the third semiconductor layer 13, and the thickness of the sixth semiconductor layer 16 is greater than that of the third semiconductor layer 13, so as to ensure the normal operation of the bipolar diode 20 and the field effect transistor.

[0123] For example, the doping concentration of the sixth semiconductor layer 16 is 1 x 10 17 cm -3 ~ 1 x 10 20 cm -3 , and the doping concentration of the third semiconductor layer 13 is 1 x 10 14 cm -3 ~ 1 x 10 18 cm -3 . For example, the doping concentration of the sixth semiconductor layer 16 is 1 x 10 18 cm -3 ~ 1 x 10 19 cm -3 , and the doping concentration of the third semiconductor layer 13 is 1 x 10 16 cm -3 .

[0124] For example, the thickness of the first semiconductor layer 13, the light-emitting layer 10a, the second semiconductor layer 12, the third semiconductor layer 13, and the fourth semiconductor layer 14 can be set in the range as described above with reference to FIG. 1A. For example, the thickness of the third semiconductor layer 13 is 30 nm ~ 300 nm, and the thickness of the sixth semiconductor layer 16 is 200 nm ~ 2 microns. For example, the thickness of the third semiconductor layer 13 is 80 nm, and the thickness of the sixth semiconductor layer 16 is 200 nm, 300 nm, or 400 nm, or 500 nm, or 1 micron, or 2 microns.

[0125] In some examples, the third semiconductor layer 13 is located on the side of the light emitting body 10 away from the substrate substrate SUB. In this case, in order to facilitate the connection between the drain electrode 313 of the first transistor 31 and the second connection electrode 42, as shown in FIG. 2A, the light emitting unit can further include a first support portion 61, and the fifth semiconductor layer 15 is supported on the first support portion 61. The first support portion 61 can include a first support layer 611 disposed in the same layer as the first semiconductor layer 11 and a second support layer 612 disposed in the same layer as the light emitting layer 10a, and the first transistor 31 is located on the side away from the first support layer 611 of the second support layer 612. The first support layer 611 and the first semiconductor layer 11 can be the same in material and thickness, and the second support layer 612 and the second semiconductor layer 12 can be the same in material and thickness. In addition, the light emitting unit can further include a first conductive member 51, and the first conductive member 51 electrically connects the first support layer 611 and the second support layer 612 to prevent the second support layer 612 from emitting light by mistake when the first transistor 31 is turned on.

[0126] The first conductive member 51 can be located on one side of the first support portion 61, or on opposite sides, or the first conductive member 51 can be disposed around the first support portion 61. The first conductive member 51 can be made of a metal material.

[0127] The first support portion 61 has the following advantages. First, compared with a P-type semiconductor layer, the lattice matching effect of an N-type semiconductor layer with the substrate substrate SUB is better, so that the first transistor 31 is disposed on the side of the first support portion 61 away from the substrate substrate SUB, which is beneficial to improve the growth effect of each semiconductor layer. Second, the patterning process can be performed after all semiconductor film layers are grown to form patterns of each semiconductor layer, thereby improving production efficiency.

[0128] In some examples, the cross section of the first support portion 61 gradually increases or steps up in the direction away from the first transistor 31, so that the first conductive member 51 formed can better adhere to the side surface of the first support layer 611 and the second support layer 612, thereby ensuring the electrical connection effect of the first support layer 611 and the second support layer 612. The cross section of the first support portion 61 is a cross section perpendicular to the thickness direction of the first support portion 61.

[0129] In some examples, as shown in FIG. 2A, the first conductive member 51 can be provided with a first insulating layer 71 on the side away from the substrate substrate SUB, and the drain electrode 313 of the first transistor 31 is located on the side of the first insulating layer 71 away from the substrate substrate SUB. The side of the drain electrode 313 away from the substrate substrate SUB is provided with a second insulating layer 72, and the second insulating layer 72 is provided with a receiving hole, and a part of the first gate electrode is located in the first receiving hole.

[0130] Taking the first semiconductor layer 11, the third semiconductor layer 13 and the sixth semiconductor layer 16 as N-type semiconductor layers as an example, the manufacturing process of the light emitting unit shown in FIG. 2A can include:

[0131] S21, sequentially growing a second N-type semiconductor layer, a light emitting material layer and a second P-type semiconductor layer, and performing ion implantation on a region of the second P-type semiconductor layer to be formed into the fifth semiconductor layer 15 to increase the P-type doping concentration of the region.

[0132] S22, growing a first N-type semiconductor layer, thinning a region of the first N-type semiconductor layer to be formed into the third semiconductor layer 13, and performing ion implantation on a region of the first N-type semiconductor layer to be formed into the sixth semiconductor layer 16; and then forming a first P-type semiconductor layer.

[0133] S23, performing a patterning process on the first P-type semiconductor layer to form the fourth semiconductor layer 14 and the seventh semiconductor layer 17, performing a patterning process on the first N-type semiconductor layer to form the third semiconductor layer 13 and the sixth semiconductor layer 16, performing a patterning process on the second P-type semiconductor layer to form the second semiconductor layer 12 and the fifth semiconductor layer 15, performing a patterning process on the light emitting material layer to form the light emitting layer 10a and the second support layer 612, and performing a patterning process on the second N-type semiconductor layer to form the first semiconductor layer 11 and the first support layer 611.

[0134] S24, forming the first connecting electrode 41, the first conductive member 51 and the first insulating layer 71.

[0135] S25, forming the drain electrode 313 of the first transistor 31, the first plate C11 of the capacitor C1 and the second connecting electrode 42. The second connecting electrode 42 is electrically connected to the drain electrode 313 of the first transistor 31.

[0136] S26, forming the second insulating layer 72 with a first accommodating hole, and then forming the source electrode 312, the first gate electrode 311, the second plate C12 of the first capacitor C1 and the third connecting electrode 43 of the first transistor 31. The first gate electrode 311 surrounds the sixth semiconductor layer 16 and the seventh semiconductor layer 17, and the second plate C12 is arranged opposite to the first plate C11 and is spaced apart by the second insulating layer 72.

[0137] In the embodiment shown in FIG. 3A, the light emitting unit includes the light emitting body 10, the third semiconductor layer 13, the fourth semiconductor layer 14, the first connecting electrode 41, the second connecting electrode 42 and the third connecting electrode 43, and can further include the first transistor 31 and the capacitor C1. The first transistor 31 includes the first gate electrode 311, the source electrode 312 and the drain electrode 313, and the drain electrode 313 is electrically connected to the second connecting electrode 42.

[0138] The embodiment shown in FIG. 3A is similar to FIG. 2A, and the differences between FIG. 3A and FIG. 2A are described below. In FIG. 3A, the first transistor 31 further includes a fifth semiconductor layer 15 and a sixth semiconductor layer 16. The sixth semiconductor layer 16 includes a first semiconductor portion 161 and a second semiconductor portion 162 arranged apart from each other, and the first semiconductor portion 161 and the second semiconductor portion 162 are connected to the fifth semiconductor layer 15. The source electrode 312 is electrically connected to the first semiconductor portion 161, and the drain electrode 313 is connected between the third semiconductor layer 13 and the second semiconductor portion 162. The first gate electrode 311 is located between the first semiconductor portion 161 and the second semiconductor portion 162 and is insulated and spaced apart from the first semiconductor portion 161, the second semiconductor portion 162, and the fifth semiconductor layer 15. For example, as shown in FIG. 3A, the sixth semiconductor layer 16 is located on the side of the fifth semiconductor layer 15 away from the substrate SUB, and the third insulating layer 73 is arranged between the first gate electrode 311 and the fifth semiconductor layer 15, between the first gate electrode 311 and the first semiconductor portion 161, and between the first gate electrode 311 and the second semiconductor portion 162.

[0139] The fifth semiconductor layer 15 and the sixth semiconductor layer 16 are of different doping types, for example, the fifth semiconductor layer 15 is a P-type semiconductor layer, and the sixth semiconductor layer 16 is an N-type semiconductor layer, and in this case, the first transistor 31 is an NMOS transistor. When the first gate electrode 311 applies an opening voltage, a conductive channel is formed between the fifth semiconductor layer 15 and the first semiconductor portion 161 and the second semiconductor portion 162, thereby turning on the source electrode 312 and the drain electrode 313.

[0140] When the first transistor 31 is an NMOS transistor, the capacitor C1 can also be arranged in the manner described in the above embodiments, the first plate C11 is in one body structure with the drain electrode 313 of the first transistor 31, and the second plate C12 is in one body structure with the third connection electrode 43. The equivalent circuit diagram of the light emitting unit is shown in FIG. 3B, and the process of controlling the light emitting body 10 to emit light is the same as that in FIG. 2B, which will not be described here.

[0141] In FIG. 3A, the fifth semiconductor layer 15 is arranged in the same layer as one of the second semiconductor layer 12 and the fourth semiconductor layer 14. In one example, as shown in FIG. 3A, the first semiconductor layer 11 is located on one side of the light emitting layer 10a along the first direction, and the fifth semiconductor layer 15 is located on one side of the sixth semiconductor layer 16 along the first direction. The fifth semiconductor layer 15 is arranged in the same layer as the second semiconductor layer 12.

[0142] As same as FIG. 2A, in FIG. 3A, the sixth semiconductor layer 16 is arranged in the same layer as the third semiconductor layer 13. Wherein, the sixth semiconductor layer 16 and the third semiconductor layer 13 are of the same doping type, the doping concentration of the sixth semiconductor layer 16 is greater than the doping concentration of the third semiconductor layer 13, and the thickness of the sixth semiconductor layer 16 is greater than the thickness of the third semiconductor layer 13, so as to ensure the normal operation of the bipolar diode 20 and the field effect transistor. The doping concentration of the sixth semiconductor layer 16 and the third semiconductor layer 13 is specifically described with reference to the description of FIG. 2A, which will not be repeated here.

[0143] As same as FIG. 2A, in FIG. 3A, the light emitting unit further comprises a first support part 61, a first conductive part 51 and a first insulating layer 71, which are specifically described with reference to the description of FIG. 2A, which will not be repeated here.

[0144] Taking the first semiconductor layer 11, the third semiconductor layer 13 and the sixth semiconductor layer 16 as N-type semiconductor layers for example, the manufacturing process of the light emitting unit shown in FIG. 3A can comprise:

[0145] S31, sequentially growing a second N-type semiconductor layer, a light emitting material layer and a second P-type semiconductor layer, and performing ion implantation on a region of the second P-type semiconductor layer to be formed into the fifth semiconductor layer 15, so as to increase the P-type doping concentration of the region.

[0146] S32, forming a first N-type semiconductor layer, thinning a region of the first N-type semiconductor layer to be formed into the third semiconductor layer 13, and performing ion implantation on a region of the first N-type semiconductor layer to be formed into the sixth semiconductor layer 16; and then forming a first P-type semiconductor layer.

[0147] S33, performing a patterning process on the first P-type semiconductor layer to form the fourth semiconductor layer 14, performing a patterning process on the first N-type semiconductor layer to form the third semiconductor layer 13 and the first semiconductor part 161 and the second semiconductor part 162 of the sixth semiconductor layer 16, performing a patterning process on the second P-type semiconductor layer to form the second semiconductor layer 12 and the fifth semiconductor layer 15, performing a patterning process on the light emitting material layer to form the light emitting layer 10a and the second support layer 612, and performing a patterning process on the second N-type semiconductor layer to form the first semiconductor layer 11 and the first support layer 611.

[0148] S34, forming the first conductive part 51, the first connecting electrode 41 and the second connecting electrode 42.

[0149] S35, forming the first insulating layer 71 and the third insulating layer 73.

[0150] S36, forming the drain electrode 313, the first gate electrode 311 and the source electrode 312 of the first transistor 31, the first plate C11 of the capacitor C1, and the third connecting electrode 43.

[0151] S37, a second insulating layer 72 is formed, and then a second plate C12 of the capacitor C1 is formed. The second plate C12 and the first plate C11 are spaced apart by the second insulating layer 72.

[0152] The light emitting unit shown in FIG. 4A is similar to the light emitting unit shown in FIG. 2A, and also includes the light emitting body 10, the third semiconductor layer 13, the fourth semiconductor layer 14, the first connection electrode 41, the second connection electrode 42, the third connection electrode 43, the first transistor 31, and the capacitor C1. Differences between FIG. 4A and FIG. 2A are described below.

[0153] In FIG. 4A, the light emitting unit can further include an eighth semiconductor layer 18 and a ninth semiconductor layer 19. The eighth semiconductor layer 18 is disposed on a side of the fourth semiconductor layer 14 away from the light emitting layer 10a, and has a different doping type from the fourth semiconductor layer 14. The ninth semiconductor layer 19 is disposed on a side of the eighth semiconductor layer 18 away from the light emitting layer 10a, and is electrically connected to the third connection electrode 43. The ninth semiconductor layer 19 has the same doping type as the fourth semiconductor layer 14. The second gate electrode 321 is disposed around the eighth semiconductor layer 18 and is insulated from the eighth semiconductor layer 18. The second gate electrode 321 is electrically connected to the drain electrode 313 of the first transistor 31. The fourth semiconductor layer 14, the eighth semiconductor layer 18, the ninth semiconductor layer 19, and the second gate electrode 321 form a field effect transistor, denoted as a second transistor 32. The second transistor 32 is connected in series between the bipolar diode 20 and the third connection electrode 43, i.e., in this embodiment, the fourth semiconductor layer 14 is indirectly connected to the third connection electrode 43.

[0154] In one example, one of the fifth semiconductor layer 15 and the sixth semiconductor layer 16 is an N-type semiconductor layer, and the other is a P-type semiconductor layer. One of the fourth semiconductor layer 14 and the eighth semiconductor layer 18 is an N-type semiconductor layer, and the other is a P-type semiconductor layer. In FIG. 4A, the eighth semiconductor layer 18 and the sixth semiconductor layer 16 are taken as examples of N-type semiconductor layers, and the fourth semiconductor layer 14, the ninth semiconductor layer 19, the fifth semiconductor layer 15, and the seventh semiconductor layer 17 are taken as examples of P-type semiconductor layers. At this time, the first transistor 31 and the second transistor 32 are both PNP-type field effect transistors (FETs).

[0155] In one example, the first plate C11 of the capacitor C1 is electrically connected to the drain electrode 313 of the first transistor 31, and the second plate C12 is used to load a sweep signal. For example, the first plate C11 can be integrated with the drain electrode 313 of the first transistor 31, and the position of the second plate C12 is not limited, for example, the second plate C12 can be disposed in the same layer as the third connection electrode 43, or can be disposed in a different layer from the third connection electrode 43.

[0156] The equivalent circuit diagram of the light emitting unit shown in FIG. 4A is shown in FIG. 4B. The first gate electrode 311 can be connected to a scan line, and the source electrode 312 is connected to a data line. When a scan signal Gate(n) on the scan line is high, a data signal Data on the data line is written to the base of the bipolar diode 20. By controlling Ube<0 and Ubc>0, the bipolar diode 20 is in an amplification state, and high current input light emission of the light emitting body 10 is realized. By fixing the base current Ib, the on-off frequency of the second transistor 32 can be controlled by controlling the voltage value of the data signal Data, thereby controlling the on duration of the light emitting body 10, and further controlling the brightness of the light emitting body 10. Specifically, assuming that the turn-on voltage of the second transistor 32 is 0 V, and the second transistor 32 is turned on when the voltage is lower than 0 V; then, when the data signal Data writes V1, and V1 is greater than 0, the voltage VA at point A is V1, and the second transistor 32 is not turned on; due to the coupling effect of the capacitor C1, VA=V1+VSweep, so when the voltage VSweep of the ramp signal is -V1, VA=0, and the second transistor 32 reaches the turn-on threshold, and the on stage of the light emitting body 10 is t0 stage.

[0157] In the case where the light emitting unit comprises the second transistor 32, the same layer arrangement in FIG. 2A can still be adopted. That is, the fifth semiconductor layer 15 is arranged in the same layer as the second semiconductor layer 12, the sixth semiconductor layer 16 is arranged in the same layer as the third semiconductor layer 13, and the seventh semiconductor layer 17 is arranged in the same layer as the eighth semiconductor layer 18. The doping concentration relationship, thickness relationship, etc. between the film layers arranged in the same layer are as described above for FIG. 2A.

[0158] Taking the first semiconductor layer 11, the third semiconductor layer 13, the sixth semiconductor layer 16, and the eighth semiconductor layer 18 as N-type semiconductor layers as an example, the manufacturing process of the light emitting unit shown in FIG. 4A can comprise:

[0159] S41, sequentially growing a second N-type semiconductor layer, a light emitting material layer, and a second P-type semiconductor layer, and performing ion implantation on a region of the second P-type semiconductor layer to be formed into the fifth semiconductor layer 15 to increase the P-type doping concentration of the region.

[0160] S42, forming a first N-type semiconductor layer, thinning a region of the first N-type semiconductor layer to be formed into the third semiconductor layer 13, and performing ion implantation on a region of the first N-type semiconductor layer to be formed into the sixth semiconductor layer 16; and then forming a first P-type semiconductor layer, a third N-type semiconductor layer, and a third P-type semiconductor layer.

[0161] S43, performing a patterning process on the third P-type semiconductor layer to form a ninth semiconductor layer 19, performing a patterning process on the third N-type semiconductor layer to form an eighth semiconductor layer 18, performing a patterning process on the first P-type semiconductor layer to form a fourth semiconductor layer 14 and a seventh semiconductor layer 17, performing a patterning process on the first N-type semiconductor layer to form a third semiconductor layer 13 and a sixth semiconductor layer 16, performing a patterning process on the second P-type semiconductor layer to form a second semiconductor layer 12 and a fifth semiconductor layer 15, and performing a patterning process on the light emitting material layer to form a light emitting layer 10a and a second support layer 612, and performing a patterning process on the second N-type semiconductor layer to form a first semiconductor layer 11 and a first support layer 611.

[0162] S44, forming a first conductive member 51, a first connection electrode 41, and a second connection electrode 42.

[0163] S45, forming a first insulating layer 71.

[0164] S46, forming a drain electrode 313 of a first transistor 31, the first connection electrode 41, and a first plate C11 of a capacitor C1. The drain electrode 313 of the first transistor 31 and the first plate C11 can be an integral structure.

[0165] S47, forming a second insulating layer 72 having a first accommodating hole and a second accommodating hole, and then forming a source electrode 312 of the first transistor 31, a first gate electrode 311, a second gate electrode 321, a second plate C12 of the first capacitor C1, and a third connection electrode 43. A portion of the first gate electrode 311 is located in the first accommodating hole, and a portion of the second gate electrode 321 is located in the second accommodating hole and is electrically connected to the drain electrode 313 of the first transistor 31. The second plate C12 is arranged opposite to the first plate C11, and the two plates are separated by the second insulating layer 72.

[0166] The light emitting unit shown in FIG. 5 has a structure similar to that of the light emitting unit shown in FIG. 4A, except that the position of the first transistor 31 in FIG. 5 is different from that in FIG. 4A. As shown in FIG. 5, the fifth semiconductor layer 15 is arranged in the same layer as the fourth semiconductor layer 14, the sixth semiconductor layer 16 is arranged in the same layer as the eighth semiconductor layer 18, and the seventh semiconductor layer 17 is arranged in the same layer as the ninth semiconductor layer 19.

[0167] For example, the fifth semiconductor layer 15 has the same thickness as the fourth semiconductor layer 14, the sixth semiconductor layer 16 has the same thickness as the eighth semiconductor layer 18, and the seventh semiconductor layer 17 has the same thickness as the ninth semiconductor layer 19.

[0168] Different from FIG. 4A, in FIG. 5, the light emitting unit includes a second support part 62 and a second conductive part 52, the second support part 62 includes a first support layer 611, a second support layer 612, a third support layer 613 and a fourth support layer 614. Among them, the first support layer 611 is arranged in the same layer as the first semiconductor layer 11, the second support layer 612 is arranged in the same layer as the light emitting layer 10a, the third support layer 613 is arranged in the same layer as the second semiconductor layer 12, and the fourth support layer 614 is arranged in the same layer as the fourth semiconductor layer 14; wherein the first transistor 31 is located on the side away from the first support layer 611. The second conductive part 52 electrically connects the first support layer 611, the second support layer 612, the third support layer 613 and the fourth support layer 614 to prevent the second support layer 612 from emitting light by mistake when the first transistor 31 is turned on. The benefits of setting the second support part 62 are similar to setting the first support part 61, both of which are to achieve better lattice matching and improve production efficiency, which will not be repeated here.

[0169] The equivalent circuit diagram of the light emitting unit shown in FIG. 5 is the same as that of FIG. 4B, and the specific control of the light emitting process of the light emitting body 10 will not be repeated here.

[0170] The manufacturing process of the light emitting unit shown in FIG. 5 can include:

[0171] S51, sequentially growing a second N-type semiconductor layer, a light emitting material layer, a second P-type semiconductor layer, a first N-type semiconductor layer, a first P-type semiconductor layer, a third N-type semiconductor layer, and a third P-type semiconductor layer.

[0172] S52, performing a patterning process on the third P-type semiconductor layer to form a ninth semiconductor layer 19 and a seventh semiconductor layer 17; performing a patterning process on the third N-type semiconductor layer to form an eighth semiconductor layer 18 and a sixth semiconductor layer 16; performing a patterning process on the first P-type semiconductor layer to form a fifth semiconductor layer 15 and a fourth semiconductor layer 14; performing a patterning process on the first N-type semiconductor layer to form a third semiconductor layer 13 and a fourth support layer 614; performing a patterning process on the second P-type semiconductor layer to form a second semiconductor layer 12 and a third support layer 613; performing a patterning process on the light emitting material layer to form a light emitting layer 10a and a second support layer 612; and performing a patterning process on the second N-type semiconductor layer to form a first semiconductor layer 11 and a first support layer 611.

[0173] After that, steps S44-S46 can be performed.

[0174] The light emitting unit shown in FIG. 6A is similar to the light emitting unit shown in FIG. 4A, and the difference is that the first transistor 31 in the light emitting unit of FIG. 6A is an MOS tube, which includes a fifth semiconductor layer 15, a sixth semiconductor layer 16, a first gate electrode 311, a source electrode 312 and a drain electrode 313, the sixth semiconductor layer 16 includes a first semiconductor part 161 and a second semiconductor part 162 arranged at intervals, and the first semiconductor part 161 and the second semiconductor part 162 are connected with the fifth semiconductor layer 15. The source electrode 312 is electrically connected with the first semiconductor part 161, and the drain electrode 313 is connected between the third semiconductor layer 13 and the second semiconductor part 162; the first gate electrode 311 is located between the first semiconductor part 161 and the second semiconductor part 162, and is insulated and spaced apart from the first semiconductor part 161, the second semiconductor part 162 and the fifth semiconductor layer 15. For example, as shown in FIG. 6A, the sixth semiconductor layer 16 is located on the side of the fifth semiconductor layer 15 away from the substrate SUB, and the third insulating layer 73 is arranged between the first gate electrode 311 and the fifth semiconductor layer 15, between the first gate electrode 311 and the first semiconductor part 161, and between the first gate electrode 311 and the second semiconductor part 162.

[0175] The doping type of the fifth semiconductor layer 15 and the sixth semiconductor layer 16 is different, for example, the fifth semiconductor layer 15 is a P-type semiconductor layer, and the sixth semiconductor layer 16 is an N-type semiconductor layer, at this time, the first transistor 31 is an NMOS tube. When the first gate electrode 311 applies an opening voltage, a conductive channel is formed between the fifth semiconductor layer 15 and the first semiconductor part 161 and the second semiconductor part 162, thereby conducting the source electrode 312 and the drain electrode 313.

[0176] When the first transistor 31 is an NMOS tube, the setting mode of the capacitor C1 can be the same as that of the capacitor C1 in FIG. 4A, the first plate C11 is an integral structure with the drain electrode 313 of the first transistor 31, and the second plate C12 is used to load the sweep signal. The equivalent circuit diagram of the light emitting unit is shown in FIG. 6B, and the process of controlling the light emitting unit to emit light is similar to that of FIG. 4B, which will not be described here.

[0177] In FIG. 6A, the film layer position of the first transistor 31 can refer to the setting mode in FIG. 3A, and in one example, as shown in FIG. 6A, the first semiconductor layer 11 is located on one side of the light emitting layer 10a along the first direction, and the fifth semiconductor layer 15 is located on one side of the sixth semiconductor layer 16 along the first direction; the fifth semiconductor layer 15 is arranged in the same layer as the second semiconductor layer 12.

[0178] The sixth semiconductor layer 16 is arranged in the same layer as the third semiconductor layer 13. The sixth semiconductor layer 16 and the third semiconductor layer 13 have the same doping type, the doping concentration of the sixth semiconductor layer 16 is greater than that of the third semiconductor layer 13, and the thickness of the sixth semiconductor layer 16 is greater than that of the third semiconductor layer 13, so as to ensure the normal operation of the bipolar diode 20 and the field effect transistor. The doping concentration of the sixth semiconductor layer 16 and the third semiconductor layer 13 is described in detail with reference to FIG. 2A, and will not be described here.

[0179] As shown in FIG. 3A, the light emitting unit further includes a first support portion 61, a first conductive member 51, and a first insulating layer 71. The first support portion 61, the first conductive member 51, and the first insulating layer 71 are described in detail with reference to FIG. 2A, and will not be described here.

[0180] Taking the first semiconductor layer 11, the third semiconductor layer 13, the eighth semiconductor layer 18, and the sixth semiconductor layer 16 as N-type semiconductor layers as an example, the manufacturing process of the light emitting unit shown in FIG. 6A can include:

[0181] S61, sequentially growing a second N-type semiconductor layer, a light emitting material layer, and a second P-type semiconductor layer, and performing ion implantation on a region of the second P-type semiconductor layer to be formed into the fifth semiconductor layer 15, so as to increase the P-type doping concentration of the region.

[0182] S62, forming a first N-type semiconductor layer, thinning a region of the first N-type semiconductor layer to be formed into the third semiconductor layer 13, and performing ion implantation on a region of the first N-type semiconductor layer to be formed into the sixth semiconductor layer 16; and then forming a first P-type semiconductor layer, a third N-type semiconductor layer, and a third P-type semiconductor layer.

[0183] S63, performing a patterning process on the third P-type semiconductor layer to form the ninth semiconductor layer 19, performing a patterning process on the third N-type semiconductor layer to form the eighth semiconductor layer 18, performing a patterning process on the first P-type semiconductor layer to form the fourth semiconductor layer 14, performing a patterning process on the first N-type semiconductor layer to form the third semiconductor layer 13 and the first semiconductor portion 161 and the second semiconductor portion 162 of the sixth semiconductor layer 16, performing a patterning process on the second P-type semiconductor layer to form the second semiconductor layer 12 and the fifth semiconductor layer 15, performing a patterning process on the light emitting material layer to form the light emitting layer 10a and the second support layer 612, and performing a patterning process on the second N-type semiconductor layer to form the first semiconductor layer 11 and the first support layer 611.

[0184] S64, forming the first conductive member 51, the first connecting electrode 41, and the second connecting electrode 42.

[0185] S65, forming the first insulating layer 71 and the third insulating layer 73.

[0186] S66, forming the drain electrode 313, the first gate electrode 311 and the source electrode 312 of the first transistor 31, the first plate C11 of the capacitor C1 and the third connection electrode 43. For example, the second plate C12 is in an integrated structure with the drain electrode 313 of the first transistor 31.

[0187] S67, forming the second insulating layer 72 with the second accommodating hole, and forming the second gate electrode 321 of the second transistor 32, the second plate C12 of the capacitor C1. Wherein, the second gate electrode 321 is electrically connected with the drain electrode 313 of the first transistor, the second plate C12 is oppositely arranged with the first plate C11, and both are spaced apart by the second insulating layer 72.

[0188] The light emitting unit shown in FIG. 7 is similar to the light emitting unit in FIG. 6A, the difference is that the position of the first transistor 31 in FIG. 7 is different from that in FIG. 6A. As shown in FIG. 7, the fifth semiconductor layer 15 is arranged in the same layer as the fourth semiconductor layer 14, and the sixth semiconductor layer 16 is arranged in the same layer as the eighth semiconductor layer 18.

[0189] For example, the fifth semiconductor layer 15 and the fourth semiconductor layer 14 have the same thickness, and the sixth semiconductor layer 16 and the eighth semiconductor layer 18 have the same thickness.

[0190] Different from FIG. 6A, in FIG. 7, the light emitting unit includes a second support part 62 and a second conductive part 52, the second support part 62 includes a first support layer 611, a second support layer 612, a third support layer 613 and a fourth support layer 614. Wherein, the first support layer 611 is arranged in the same layer as the first semiconductor layer 11, the second support layer 612 is arranged in the same layer as the light emitting layer 10a, the third support layer 613 is arranged in the same layer as the second semiconductor layer 12, and the fourth support layer 614 is arranged in the same layer as the fourth semiconductor layer 14; wherein the first transistor 31 is located on the side of the fourth support layer 614 away from the first support layer 611. The second conductive part 52 electrically connects the first support layer 611, the second support layer 612, the third support layer 613 and the fourth support layer 614, so as to prevent the second support layer 612 from mis-emitting light when the first transistor 31 is turned on.

[0191] In addition, different from FIG. 6A, in FIG. 7, the first insulating layer 71 can not be arranged, but the second insulating layer 72 is arranged directly, the second insulating layer 72 exposes the second semiconductor part 162 and has a second accommodating hole; part of the second gate electrode 321 is located on the layer of the second insulating layer 72 away from the substrate substrate SUB, and the other part of the second gate electrode 321 is located in the second accommodating hole.

[0192] The equivalent circuit diagram of the light emitting unit shown in FIG. 7 is the same as FIG. 6B, and the specific control of the light emitting process of the light emitting body 10 will not be repeated here.

[0193] The manufacturing process of the light emitting unit shown in FIG. 7 can include:

[0194] S71, sequentially growing a second N-type semiconductor layer, a light emitting material layer, a second P-type semiconductor layer, a first N-type semiconductor layer, a first P-type semiconductor layer, a third N-type semiconductor layer, and a third P-type semiconductor layer.

[0195] S72, performing a patterning process on the third P-type semiconductor layer to form a ninth semiconductor layer 19; performing a patterning process on the third N-type semiconductor layer to form an eighth semiconductor layer 18 and a sixth semiconductor layer 16; performing a patterning process on the first P-type semiconductor layer to form a fifth semiconductor layer 15 and a fourth semiconductor layer 14; performing a patterning process on the first N-type semiconductor layer to form a third semiconductor layer 13 and a fourth support layer 614; performing a patterning process on the second P-type semiconductor layer to form a second semiconductor layer 12 and a third support layer 613; performing a patterning process on the light emitting material layer to form a light emitting layer 10a and a second support layer 612; and performing a patterning process on the second N-type semiconductor layer to form a first semiconductor layer 11 and a first support layer 611.

[0196] S73, forming a first conductive member 51, a first connection electrode 41, and a second connection electrode 42.

[0197] S74, forming a first insulating layer 71, which exposes the second semiconductor portion 162 and is provided with a second accommodating hole.

[0198] S75, forming a third insulating layer 73.

[0199] S76, forming a first gate electrode 311, a source electrode 312, and a drain electrode 313 of a first transistor 31, a first electrode plate of a capacitor C1, a second gate electrode 321 of a second transistor 32, and a third connection electrode 43. The second gate electrode 321 is electrically connected to the drain electrode 313 of the first transistor 31, and at least a portion of the second gate electrode 321 is located in the second accommodating hole.

[0200] S77, respectively forming a second insulating layer 72 and a second electrode plate C12 of the capacitor C1. The second electrode plate C12 is arranged opposite to the first electrode plate C11, and the second electrode plate C12 and the first electrode plate C11 are spaced apart by the second insulating layer 72.

[0201] The light emitting unit shown in FIG. 8A is similar to the light emitting unit shown in FIG. 2A, and both include the light emitting body 10, the third semiconductor layer 13, the fourth semiconductor layer 14, and the first transistor 31 including the first gate electrode 311, the source electrode 312, the drain electrode 313, the fifth semiconductor layer 15, the sixth semiconductor layer 16, and the seventh semiconductor layer 17. In FIG. 8A, the thickness and the doping concentration of the semiconductor layers in the ambipolar diode 20 are described with reference to FIG. 2A. The difference between FIG. 8A and FIG. 2A is in the relative positional relationship between the first transistor 31 and the light emitting body 10 and the doping type of each semiconductor layer.

[0202] Specifically, in FIG. 8A, the first semiconductor layer 11, the third semiconductor layer 13, and the sixth semiconductor layer 16 are P-type semiconductor layers, and the second semiconductor layer 12, the fourth semiconductor layer 14, the fifth semiconductor layer 15, and the seventh semiconductor layer 17 are N-type semiconductor layers. Since the N-type semiconductor layer is more lattice-matched to the substrate SUB in the growth process of the semiconductor layer, when the first semiconductor layer 11 is a P-type semiconductor layer, the light emitting body 10 is disposed on the side of the third semiconductor layer 13 away from the substrate SUB, and the fourth semiconductor layer 14 can be in contact with the substrate SUB.

[0203] In FIG. 8A, the first semiconductor layer 11 is located on one side of the light emitting layer 10a in a first direction, and the fifth semiconductor layer 15 is located on one side of the sixth semiconductor layer 16 in a second direction, the first direction being opposite to the second direction. At this time, the fifth semiconductor layer 15 is disposed in the same layer as the fourth semiconductor layer 14, the sixth semiconductor layer 16 is disposed in the same layer as the third semiconductor layer 13, and the seventh semiconductor layer 17 is disposed in the same layer as the second semiconductor layer 12.

[0204] In one example, the doping concentration of the sixth semiconductor layer 16 is greater than the doping concentration of the third semiconductor layer 13, and the thickness of the sixth semiconductor layer 16 is greater than the thickness of the third semiconductor layer 13. For example, the doping concentration of the sixth semiconductor layer 16 is between 1 x 1018cm-3and 1 x 1020cm-3, and the doping concentration of the third semiconductor layer 13 is between 1 x 1018cm-3and 1 x 1020cm-3. 17 cm -3 20 cm -3 14 cm -3 18 cm -3 18 cm -3 19 cm -3 16 cm -3 . ​​​​​​

[0205] In one example, the doping concentration in the seventh semiconductor layer 17 can be greater than the doping concentration in the second semiconductor layer 12.

[0206] As in FIG. 2A, in FIG. 8A, the drain electrode 313 of the first transistor 31 is provided with the second insulating layer 72 away from one side of the substrate substrate SUB, the second insulating layer 72 is provided with a first accommodating hole, and at least part of the first gate electrode 311 is located in the first accommodating hole. The light emitting unit further comprises a capacitor C1, the first plate C11 of the capacitor C1 can be connected as an integral structure with the drain electrode 313 of the first transistor 31, and the second plate C12 of the capacitor C1 is located away from the substrate substrate SUB on the second insulating layer 72, and is provided opposite to the first plate C11.

[0207] Different from FIG. 2A, in FIG. 8A, the third connection electrode 43 is loaded with a low-level voltage, and the second plate C12 and the first connection electrode 41 are both loaded with a high-level voltage; for example, the second plate C12 can be connected as an integral structure with the third connection electrode 43, or the second plate C12 can be a separate structure from the third connection electrode 43, both of which are electrically connected to the same voltage line.

[0208] The equivalent circuit diagram of the light emitting unit shown in FIG. 8A is shown in FIG. 8B. When the scan signal Gate(n) on the scan line is high, the data signal Data on the data line is written to the base of the bipolar diode 20, and by controlling Ube>0, Ubc<0, the bipolar diode 20 has the ability to amplify current. When Gate(n) is high, the Data signal is written to point b, and by controlling Ube>0, Ubc<0, the bipolar diode 20 is in an amplification state, realizing high current input light emission of the light emitting body 10. Different Ib can be obtained by controlling the voltage value of the data signal Data, thereby controlling Ic (i.e., the current flowing through the LED, Ic=β*Ib); when Ube<0, the bipolar diode 20 is in a cut-off state, and the anode and the cathode are disconnected, realizing the closing of the light emitting body 10. Through the energy storage effect of the capacitor C1, the light emitting unit can still maintain the light emitting state after the end of the current scanning, until the next frame of display picture.

[0209] Compared with FIG. 2A, in FIG. 8A, the first support part 61 and the first conductive part 51 are not required, so that the structure of the light emitting unit and the manufacturing process are simpler.

[0210] The manufacturing process of the light emitting unit shown in FIG. 8A can include:

[0211] S81, sequentially grow the first N-type semiconductor layer and the first P-type semiconductor layer; thin the region of the first P-type semiconductor layer to be the third semiconductor layer 13, and perform ion implantation on the region of the first P-type semiconductor layer to be the sixth semiconductor layer 16 to increase the doping concentration of the region.

[0212] S82, grow the second N-type semiconductor layer, and perform ion implantation on the region of the second N-type semiconductor layer to be the seventh semiconductor layer 17 to increase the doping concentration of the region. Then, sequentially grow the luminescent material layer and the second P-type semiconductor layer.

[0213] S83, perform a patterning process on the second P-type semiconductor layer to form the first semiconductor layer 11 of the light-emitting body 10; perform a patterning process on the luminescent material layer to form the light-emitting layer 10a; perform a patterning process on the second N-type semiconductor layer to form the second semiconductor layer 12 and the seventh semiconductor layer 17; perform a patterning process on the first P-type semiconductor layer to form the third semiconductor layer 13 and the sixth semiconductor layer 16; and perform a patterning process on the first N-type semiconductor layer to form the fourth semiconductor layer 14 and the fifth semiconductor layer 15.

[0214] S84, form the first insulating layer 71 and the third connecting electrode 43. The third connecting electrode 43 can be located on the side of the fourth semiconductor layer 14 away from the substrate SUB, for example, a part of the fourth semiconductor layer 14 is not covered by the third semiconductor layer 13, and the third connecting electrode 43 is located on the part of the fourth semiconductor layer 14 not covered by the third semiconductor layer 13.

[0215] S85, form the drain electrode 313 of the first transistor 31, the first plate C11 of the capacitor C1, and the second connecting electrode 42, and the second connecting electrode 42 is electrically connected to the drain electrode 313 of the first transistor 31.

[0216] S86, form the second insulating layer 72 with a first accommodating hole, and then form the source electrode 312, the first gate electrode 311, the first connecting electrode 41 of the first transistor 31, and the second plate C12 of the capacitor C1. At least part of the first gate electrode 311 is located in the first accommodating hole, and the second plate C12 of the capacitor C1 is arranged opposite to the first plate C11, and the two are separated by the second insulating layer 72.

[0217] The light-emitting unit shown in FIG. 9A is similar to the light-emitting unit shown in FIG. 8A, and the main difference is that in FIG. 9A, the first transistor 31 is a PMOS transistor.

[0218] As shown in FIG. 9A, the first transistor 31 includes a first gate electrode 311, a source electrode 312, a drain electrode 313, a fifth semiconductor layer 15 and a sixth semiconductor layer 16, and the fifth semiconductor layer 15 and the sixth semiconductor layer 16 are different in doping type. For example, the fifth semiconductor layer 15 is an N-type semiconductor layer, and the sixth semiconductor layer 16 is a P-type semiconductor layer. The sixth semiconductor layer 16 includes a first semiconductor part 161 and a second semiconductor part 162 which are spaced apart, and the first semiconductor part 161 and the second semiconductor part 162 are both connected with the fifth semiconductor layer 15. The first gate electrode 311 is insulated and spaced apart from the fifth semiconductor layer 15, the first semiconductor part 161 and the second semiconductor part 162, for example, a third insulating layer 73 is arranged between the first gate electrode 311 and the fifth semiconductor layer 15, between the first gate electrode 311 and the first semiconductor part 161, and between the first gate electrode 311 and the second semiconductor part 162. The source electrode 312 of the first transistor 31 is electrically connected with the first semiconductor part 161, and the drain electrode 313 is electrically connected with the second semiconductor part 162.

[0219] As shown in FIG. 9A, the fifth semiconductor layer 15 is arranged in the same layer as the fourth semiconductor layer 14, and the sixth semiconductor layer 16 is arranged in the same layer as the third semiconductor layer 13. The thickness of the sixth semiconductor layer 16 is greater than the thickness of the third semiconductor layer 13, and the doping concentration of the sixth semiconductor layer 16 is greater than the doping concentration of the third semiconductor layer 13. For details, refer to the description of FIG. 8A above.

[0220] The manufacturing process of the light emitting unit shown in FIG. 9A can include:

[0221] S91, sequentially growing a first N-type semiconductor layer, a first P-type semiconductor layer; thinning the region of the first P-type semiconductor layer to be formed into the third semiconductor layer 13, and ion implantation is performed on the region of the first P-type semiconductor layer to be formed into the sixth semiconductor layer 16 to increase the doping concentration of the region.

[0222] S92, sequentially growing a second N-type semiconductor layer, a light emitting material layer and a second P-type semiconductor layer.

[0223] S93, performing a patterning process on the second P-type semiconductor layer to form the first semiconductor layer 11 of the light emitting body 10; performing a patterning process on the light emitting material layer to form the light emitting layer 10a; performing a patterning process on the second N-type semiconductor layer to form the second semiconductor layer 12; performing a patterning process on the first P-type semiconductor layer to form the third semiconductor layer 13 and the sixth semiconductor layer 16; and performing a patterning process on the first N-type semiconductor layer to form the fourth semiconductor layer 14 and the fifth semiconductor layer 15.

[0224] S94, a third connection electrode 43, a first insulating layer 71, and a third insulating layer 73 are formed. The third connection electrode 43 can be located on a side of the fourth semiconductor layer 14 away from the substrate substrate SUB, for example, a portion of the fourth semiconductor layer 14 is not covered by the third semiconductor layer 13, and the third connection electrode 43 is located on the portion of the fourth semiconductor layer 14 not covered by the third semiconductor layer 13. At least part of the first insulating layer 71 is located between the first transistor 31 and the bipolar diode 20. The third insulating layer 73 is located on a side of the fifth semiconductor layer 15 away from the substrate substrate SUB.

[0225] S95, a first connection electrode 41, a second connection electrode 42, a drain electrode 313, a source electrode 312, and a first gate electrode 311 of the first transistor 31, and a first plate C11 of the capacitor C1 are formed. The second connection electrode 42 is electrically connected to the drain electrode 313 of the first transistor 31. The first plate C11 and the drain electrode 313 can be connected as an integral structure.

[0226] S96, a second insulating layer 72 and a second plate C12 of the first transistor 31 are sequentially formed, the second plate C12 is arranged opposite to the first plate C11 and is spaced apart by the second insulating layer 72.

[0227] The light emitting unit shown in FIG. 10A is similar to FIG. 4A, both of which include a first transistor 31, a light emitting body 10, a bipolar diode 20, and a second transistor 32, and the difference from FIG. 4A is that in FIG. 9A, the first semiconductor layer 11 is a P-type semiconductor layer, the second semiconductor layer 12 is an N-type semiconductor layer, the bipolar diode 20 is an NPN type, and the second transistor 32 is an NPN type FET tube. In addition, the same layer arrangement of the film layers in the light emitting unit is different.

[0228] Specifically, the first transistor 31 includes a fifth semiconductor layer 15, a sixth semiconductor layer 16, and a seventh semiconductor layer 17. The second transistor 32 includes a fourth semiconductor layer 14, an eighth semiconductor layer 18, and a ninth semiconductor layer 19, the second semiconductor layer 12, the fourth semiconductor layer 14, the ninth semiconductor layer 19, and the sixth semiconductor layer 16 are all N-type semiconductor layers; the third semiconductor layer 13, the eighth semiconductor layer 18, the fifth semiconductor layer 15, and the seventh semiconductor layer 17 are all P-type semiconductor layers.

[0229] The fifth semiconductor layer 15 is arranged in the same layer as the eighth semiconductor layer 18, the sixth semiconductor layer 16 is arranged in the same layer as the fourth semiconductor layer 14, and the seventh semiconductor layer 17 is arranged in the same layer as the third semiconductor layer 13; the thickness of the seventh semiconductor layer 17 is greater than the thickness of the third semiconductor layer 13, and the doping concentration of the seventh semiconductor layer 17 is greater than the doping concentration of the third semiconductor layer 13.

[0230] For example, the doping concentration of the seventh semiconductor layer 17 is 1 x 1017 cm -3 ~1x10 20 cm -3 between 1x10 14 cm -3 ~1x10 18 cm -3 between 1x10 18 cm -3 ~1x10 19 cm -3 between 1x10 16 cm -3 .

[0231] For example, the thickness of the first semiconductor layer 13, the light-emitting layer 10a, the second semiconductor layer 12, the third semiconductor layer 13 and the fourth semiconductor layer 14 can all be set in the range described above with reference to FIG. 1A. For example, the thickness of the third semiconductor layer 13 is between 30 nm and 300 nm, and the thickness of the seventh semiconductor layer 17 is between 200 nm and 2 microns. For example, the thickness of the third semiconductor layer 13 is 80 nm, the thickness of the seventh semiconductor layer 17 is 200 nm, 300 nm, or 400 nm, or 500 nm, or 1 micron, or 2 microns.

[0232] The normal projection of the ninth semiconductor layer 19 on a reference plane can cover the normal projection of the first transistor 31 on the reference plane, the reference plane being perpendicular to the plane in which the light-emitting layer 10a is located; that is, the first transistor 31 is located on the side of the ninth semiconductor layer 19 away from the substrate SUB. The advantage of this arrangement is that, first, the lattice matching effect of an N-type semiconductor layer with the substrate SUB is better than that of a P-type semiconductor layer, so arranging the first transistor 31 on the side of the ninth semiconductor layer 19 away from the substrate SUB is conducive to improving the growth effect of each semiconductor layer. Second, this allows the patterning process to be performed after all the semiconductor film layers have been grown, forming patterns of each semiconductor layer, thereby improving production efficiency.

[0233] The equivalent circuit diagram of the light emitting unit in FIG. 10A is shown in FIG. 10B, in which the second plate C12 of the capacitor C1 is used to load a sweep signal, and the sweep signal increases from 0 to V0 when the second transistor 32 is an NPN type FET tube. By fixing the base current Ib, the on-off frequency of the second transistor 32 can be controlled by controlling the voltage value of the data signal Data, so as to control the opening time of the light emitting body 10, and further control the brightness of the light emitting body 10. Specifically, assuming that the opening voltage of the second transistor 32 is 0V, and the second transistor 32 is turned on when the voltage is higher than 0V; then when the data signal Data writes -V1, and V1 is greater than 0, the voltage VA at point A is -V1, and the second transistor 32 is not turned on; due to the coupling effect of the capacitor C1, VA = -V1 + VSweep, so when the voltage VSweep of the sweep signal is V1, VA = 0, and the second transistor 32 reaches the opening threshold, and the opening stage of the light emitting body 10 is t0 stage.

[0234] The manufacturing process of the light emitting unit in FIG. 10A can include:

[0235] S101, sequentially grow a first N-type semiconductor layer, a first P-type semiconductor layer, a second N-type semiconductor layer, and a second P-type semiconductor layer; thin the region of the second P-type semiconductor layer to be formed into the third semiconductor layer 13, and ion implant the region of the second P-type semiconductor layer to be formed into the seventh semiconductor layer 17 to increase the doping concentration of the region.

[0236] S102, sequentially form a third N-type semiconductor layer, a light emitting material layer, and a third P-type semiconductor layer.

[0237] S103, perform a patterning process on the third P-type semiconductor layer to form the first semiconductor layer 11 of the light emitting body 10; perform a patterning process on the light emitting material layer to form the light emitting layer 10a; perform a patterning process on the third N-type semiconductor layer to form the second semiconductor layer 12; perform a patterning process on the second P-type semiconductor layer to form the third semiconductor layer 13 and the seventh semiconductor layer 17; perform a patterning process on the second N-type semiconductor layer to form the fourth semiconductor layer 14 and the sixth semiconductor layer 16; and perform a patterning process on the first P-type semiconductor layer to form the eighth semiconductor layer 18 and the fifth semiconductor layer 15.

[0238] For the first N-type semiconductor layer, the patterning process can not be performed.

[0239] S104, form a third connection electrode 43, and the third connection electrode 43 is electrically connected with the ninth semiconductor layer 19.

[0240] S105, forming the first insulating layer 71; then forming the drain electrode 313 of the first transistor 31, the first plate C11 of the capacitor C1 and the second gate electrode 321 of the second transistor 32. Wherein, the drain electrode 313 is electrically connected with the first plate C11, and is electrically connected with the second gate electrode 321. The second gate electrode 321 penetrates the part of the first insulating layer 71, and is arranged around the eighth semiconductor layer 18.

[0241] S106, respectively forming the second connection electrode 42, the second insulating layer 72, the first connection electrode 41, the first gate electrode 311, the source electrode 312. The second insulating layer 72 is provided with a first accommodating hole, and at least part of the first gate electrode 311 is located in the first accommodating hole and arranged around the sixth semiconductor layer 16 and the seventh semiconductor layer 17.

[0242] S107, forming the second plate C12, which is arranged opposite to the first plate C11 and is spaced apart by the second insulating layer 72.

[0243] The light emitting unit shown in FIG. 11 is similar to FIG. 10A, both of which include the first transistor 31, the light emitting body 10, the bipolar diode 20 and the second transistor 32, and the main difference between them is that in FIG. 11, the first transistor 31 is a PMOS transistor, and in addition, the arrangement mode of the same layer of the film layer in the light emitting unit is different.

[0244] Specifically, as shown in FIG. 11, the first transistor 31 includes the first gate electrode 311, the source electrode 312 and the drain electrode 313, and the fifth semiconductor layer 15 and the sixth semiconductor layer 16, the fifth semiconductor layer 15 is an N-type semiconductor layer, the sixth semiconductor layer 16 is a P-type semiconductor layer and includes the first semiconductor part 161 and the second semiconductor part 162 arranged at intervals, the first semiconductor part 161 is electrically connected with the source electrode 312, and the second semiconductor part 162 is electrically connected with the drain electrode 313. The first gate electrode 311 is located between the first semiconductor part 161 and the second semiconductor part 162, and there is at least the third insulating layer 73 between the first gate electrode 311 and the first semiconductor part 161, between the first gate electrode 311 and the second semiconductor part 162, and between the first gate electrode 311 and the fifth semiconductor layer 15.

[0245] In addition, the orthogonal projection of the ninth semiconductor layer 19 on the reference surface can not overlap with the orthogonal projection of the first transistor 31 on the reference surface. Specifically, in FIG. 11, the fifth semiconductor layer 15 is arranged in the same layer as the ninth semiconductor layer 19, and the sixth semiconductor layer 16 is arranged in the same layer as the eighth semiconductor layer 18.

[0246] In FIG. 11, the thickness, the doping concentration of the film layer in the bipolar diode 20, and the doping concentration and the thickness of each semiconductor layer in the light emitting body 10 can be set according to the foregoing embodiments.

[0247] The equivalent circuit diagram of the light emitting unit shown in FIG. 11 is the same as that of FIG. 10B, and the process of controlling the light emitting body 10 to emit light is described with reference to FIG. 10B.

[0248] The manufacturing process of the light emitting unit in FIG. 11 can include:

[0249] S111, sequentially growing a first N-type semiconductor layer, a first P-type semiconductor layer, a second N-type semiconductor layer, a second P-type semiconductor layer, a third N-type semiconductor layer, a light emitting material layer, and a third P-type semiconductor layer.

[0250] S112, forming the first semiconductor layer 11, the light emitting layer 10a, the second semiconductor layer 12, the third semiconductor layer 13, the fourth semiconductor layer 14, the eighth semiconductor layer 18, and the sixth semiconductor layer 16, the ninth semiconductor layer 19, and the fifth semiconductor layer 15 by etching each semiconductor layer.

[0251] S113, respectively forming a third connection electrode 43 electrically connected to the ninth semiconductor layer 19, a first insulating layer 71, and a third insulating layer 73. At least part of the first insulating layer 71 is located between the first transistor 31 and the second transistor 32, and the third insulating layer 73 is located on the side of the fifth semiconductor layer 15 away from the substrate SUB.

[0252] S114, forming a second connection electrode 42, a second gate electrode 321, a first gate electrode 311, a source electrode 312, and a drain electrode 313 of the first transistor 31, and a first plate C11 of a capacitor C1. The second gate electrode 321 penetrates at least part of the first insulating layer 71, and the drain electrode 313 of the first transistor 31 is electrically connected to the first gate electrode 311.

[0253] S115, respectively forming a second insulating layer 72 and a second plate C12 of the capacitor C1. The second plate C12 is arranged opposite to the first plate C11, and the two are separated by the second insulating layer 72.

[0254] The light emitting unit shown in FIG. 12A is similar to that in FIG. 11, both including the first transistor 31, the light emitting body 10, the bipolar diode 20, and the second transistor 32. The main difference between FIG. 12A and FIG. 11 is that in FIG. 12A, the first transistor 31 is an NMOS tube, and in addition, the same layer arrangement of the film layers in the light emitting unit is different.

[0255] Specifically, as shown in FIG. 12A, the first transistor 31 includes a first gate electrode 311, a source electrode 312, and a drain electrode 313, and a fifth semiconductor layer 15 and a sixth semiconductor layer 16, the fifth semiconductor layer 15 is a P-type semiconductor layer, the sixth semiconductor layer 16 is an N-type semiconductor layer and includes a first semiconductor portion 161 and a second semiconductor portion 162 arranged at intervals, the first semiconductor portion 161 is electrically connected to the source electrode 312, and the second semiconductor portion 162 is electrically connected to the drain electrode 313. The first gate electrode 311 is located between the first semiconductor portion 161 and the second semiconductor portion 162, and there is at least a third insulating layer 73 between the first gate electrode 311 and the first semiconductor portion 161, between the first gate electrode 311 and the second semiconductor portion 162, and between the first gate electrode 311 and the fifth semiconductor layer 15.

[0256] In addition, in FIG. 12A, the orthographic projection of the ninth semiconductor layer 19 on the reference surface overlaps with the orthographic projection of the first transistor 31 on the reference surface, specifically, the first transistor 31 is located on the side of the ninth semiconductor layer 19 away from the substrate substrate SUB. The fifth semiconductor layer 15 is arranged in the same layer as the eighth semiconductor layer 18, and the sixth semiconductor layer 16 is arranged in the same layer as the fourth semiconductor layer 14. In the structure of FIG. 12A, the third connection electrode 43 connected by the ninth semiconductor layer 19 is used to load a low-level signal VSS, and will not affect the on-off state of the first transistor 31.

[0257] The equivalent circuit diagram of the light emitting unit shown in FIG. 12A is shown in FIG. 12B, and the principle of controlling light emission is the same as that of FIG. 10B, which will not be described here.

[0258] The manufacturing process of the light emitting unit in FIG. 12A can include:

[0259] S111, sequentially growing a first N-type semiconductor layer, a first P-type semiconductor layer, a second N-type semiconductor layer, a second P-type semiconductor layer, a third N-type semiconductor layer, a light emitting material layer, and a third P-type semiconductor layer.

[0260] S112, performing a patterning process on the third P-type semiconductor layer to form the first semiconductor layer 11 of the light emitting body 10; performing a patterning process on the light emitting material layer to form the light emitting layer 10a; performing a patterning process on the third N-type semiconductor layer to form the second semiconductor layer 12; performing a patterning process on the second P-type semiconductor layer to form the third semiconductor layer 13; performing a patterning process on the second N-type semiconductor layer to form the fourth semiconductor layer 14 and the sixth semiconductor layer 16; and performing a patterning process on the first P-type semiconductor layer to form the eighth semiconductor layer 18 and the fifth semiconductor layer 15. The first N-type semiconductor layer can not be subjected to the patterning process, and the whole is used as the ninth semiconductor layer 19.

[0261] S113, a third connection electrode 43 electrically connected to the ninth semiconductor layer 19, a first insulating layer 71, and a third insulating layer 73 are formed, respectively. At least part of the first insulating layer 71 is located between the first transistor 31 and the second transistor 32, and the third insulating layer 73 is located on the side of the fifth semiconductor layer 15 away from the substrate substrate SUB.

[0262] The N-type semiconductor layer involved in the above-mentioned embodiments of the present disclosure can be an N-type GaN layer, and the P-type semiconductor layer is a P-type GaN layer. The material of the light-emitting layer 10a can be a multiple quantum well (MQW) layer, with a thickness of, for example, between 10-300 nm, for example, 50 nm. The light-emitting unit is an LED light-emitting chip, for example, a Micro-LED light-emitting chip, or a Mini-LED light-emitting chip. The Mini LED chip refers to a light-emitting diode chip with a grain size of about 100-300 microns. The MicroLED chip refers to a light-emitting diode chip with a grain size of less than 100 microns. The MiniLED / MicroLED display device has the advantages of low power consumption, high brightness, high resolution, high color saturation, fast response speed, long service life, high efficiency, etc.

[0263] FIG. 13 is a schematic diagram of a display substrate provided in some embodiments of the present disclosure. As shown in FIG. 13, the display substrate includes a substrate substrate SUB and a plurality of light-emitting units disposed on the substrate substrate SUB. The light-emitting unit is the light-emitting unit in any of the above-mentioned embodiments. In addition, the display substrate further includes a first voltage line and a second voltage line, the first voltage line is electrically connected to the first connection electrode 41, and the second voltage line is electrically connected to the third connection electrode 43. The substrate substrate SUB can be a semiconductor substrate, for example, a gallium nitride substrate.

[0264] According to the above description of the light-emitting unit, when the fourth semiconductor layer 14 is a P-type semiconductor layer and the first semiconductor layer 11 is an N-type semiconductor layer, the first connection electrode 41 is used to load a low-level signal; the third connection electrode 43 is used to load a high-level signal Vdd. When the fourth semiconductor layer 14 is an N-type semiconductor layer and the first semiconductor layer 11 is a P-type semiconductor layer, the first connection electrode 41 is used to load a high-level signal Vdd, and the third connection electrode 43 is used to load a low-level signal Vss.

[0265] When the light-emitting unit further includes a second transistor 32, and the drain electrode 313 of the first transistor 31 is electrically connected to the second gate electrode 321, the display substrate further includes a ramp signal line and a third voltage line, the ramp signal line is electrically connected to the second plate C12 of the capacitor C1, and is used to load a ramp signal for the capacitor C1. The third voltage line is electrically connected to the second connection electrode 42, and is used to provide a fixed voltage for the base of the bipolar diode 20.

[0266] In each of the above embodiments, when the drain electrode 313 of the first transistor 31 is electrically connected to the second connection electrode 42 and the fourth semiconductor layer 14 is a P-type semiconductor layer, the second plate C12 of the capacitor is connected to the third connection electrode 43. When the drain electrode 313 of the first transistor 31 is electrically connected to the second connection electrode 42 and the fourth semiconductor layer 14 is an N-type semiconductor layer, the second plate C12 is electrically connected to the first connection electrode 41.

[0267] FIG. 14 is a schematic view of a display substrate provided in some other embodiments of the present disclosure, which differs from FIG. 13 in that the light emitting unit in FIG. 14 needs to be transferred to a substrate substrate SUB, such as a glass substrate, or a flexible substrate made of a flexible material. In FIG. 14, the first connection electrode 41, the second connection electrode 42, and the third connection electrode 43 are all located on the side of the respective connected film layers facing the substrate substrate SUB. The light emitting unit further includes an insulating layer 70, and the substrate substrate SUB is provided with a driving circuit layer 90 including a first bonding electrode 91, a second bonding electrode 92, and a third bonding electrode 93, the first bonding electrode 91 is bonded to a first transfer electrode 911, the first transfer electrode 911 is electrically connected to the first connection electrode 41 through a via hole in the insulating layer 70; the second bonding electrode 92 is bonded to a second transfer electrode 921, the second transfer electrode 921 is electrically connected to the second connection electrode 42 through a via hole in the insulating layer 70; and the third bonding electrode 93 is bonded to the third connection electrode 43.

[0268] For the display substrate of FIG. 14, when prepared, the light emitting unit needs to be prepared on the growth substrate, and then transferred to the substrate substrate SUB.

[0269] It should be noted that FIG. 14 is only an example of using the light emitting unit in FIG. 1A to illustrate the setting method of the light emitting unit on the substrate substrate SUB. In actual connection, the specific structure of the light emitting unit can be adjusted. When the vertical distance between a connection electrode and the corresponding bonding electrode is close, the connection electrode can be directly bonded to the corresponding bonding electrode. If the distance between a connection electrode and the corresponding bonding electrode is far and cannot be contacted, a transfer electrode is used for transfer.

[0270] The above is the description of the light emitting unit and the display substrate provided by the embodiments of the present disclosure. It can be seen that in the embodiments of the present disclosure, the bipolar diode 20 is integrated in the light emitting unit, so that small signal input and large current output can be realized, thereby improving the current flowing through the light emitting body 10 and improving the hole injection efficiency. In addition, in the light emitting unit, the driving circuit (for example, the transistor, the bipolar diode 20 in each of the above embodiments) for driving the light emitting body 10 and the light emitting body 10 adopt the same process, and a complex transfer and bonding process is not needed. In addition, when a second transistor 32 is connected in series on the branch of the light emitting body 10, the light emitting time of the light emitting body 10 can be controlled, thereby increasing the number of gray scales that can be realized.

[0271] It can be understood that the above embodiments are only exemplary embodiments adopted for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Various modifications and improvements can be made by those of ordinary skill in the art without departing from the spirit and essence of the present disclosure, and these modifications and improvements are also considered to be within the protection scope of the present disclosure.

Claims

1. An illumination unit, comprising: an illumination body, comprising a first semiconductor layer, an illumination layer, and a second semiconductor layer stacked in sequence; a third semiconductor layer disposed on a side of the second semiconductor layer away from the illumination layer; a fourth semiconductor layer disposed on a side of the third semiconductor layer away from the illumination layer; the fourth semiconductor layer and the second semiconductor layer are of the same doping type, and the fourth semiconductor layer and the third semiconductor layer are of different doping types; a first connection electrode electrically connected to the first semiconductor layer; a second connection electrode electrically connected to the third semiconductor layer; a third connection electrode connected to the fourth semiconductor layer.

2. The light emitting unit according to claim 1, wherein the fourth semiconductor layer and the second semiconductor layer are of N-type or P-type; one of the second semiconductor layer and the third semiconductor layer is of N-type, and the other is of P-type; a doping concentration of the third semiconductor layer is less than a doping concentration of any one of the second semiconductor layer and the fourth semiconductor layer.

3. The light emitting unit according to claim 2, wherein a thickness of the third semiconductor layer is less than a thickness of any one of the second semiconductor layer and the fourth semiconductor layer, and a volume of the second semiconductor layer is greater than a volume of the fourth semiconductor layer.

4. The light emitting unit of claim 1, wherein, the illumination unit further comprises a first transistor, the first transistor comprising a first gate electrode, a source electrode, and a drain electrode, the drain electrode being electrically connected to the second connection electrode.

5. The light emitting unit of claim 1, wherein, the illumination unit further comprises: a first transistor, the first transistor comprising a first gate electrode, a source electrode, and a drain electrode; an eighth semiconductor layer disposed on a side of the fourth semiconductor layer away from the illumination layer, and of a different doping type from the fourth semiconductor layer; a ninth semiconductor layer disposed on a side of the eighth semiconductor layer away from the illumination layer, and electrically connected to the third connection electrode; the ninth semiconductor layer is of the same doping type as the fourth semiconductor layer; wherein the eighth semiconductor layer and the ninth semiconductor layer are connected between the third connection electrode and the fourth semiconductor layer; a second gate electrode disposed around the eighth semiconductor layer and insulated from the eighth semiconductor layer; wherein the second gate electrode is electrically connected to the drain electrode.

6. The light emitting unit according to claim 4 or 5, wherein the first transistor further comprises a fifth semiconductor layer, a sixth semiconductor layer, and a seventh semiconductor layer stacked in sequence, the source electrode is electrically connected to the seventh semiconductor layer, and the drain electrode is electrically connected to the fifth semiconductor layer; the first gate electrode is disposed around the sixth semiconductor layer and the seventh semiconductor layer, and is insulated from the sixth semiconductor layer and the seventh semiconductor layer; wherein one of the fifth semiconductor layer and the seventh semiconductor layer is disposed in the same layer as the second semiconductor layer, and the other is disposed in the same layer as the fourth semiconductor layer; the sixth semiconductor layer is disposed in the same layer as the third semiconductor layer. 7.The illumination unit of claim 6, wherein The first semiconductor layer is located on one side of the light-emitting layer along a first direction, and the fifth semiconductor layer is located on one side of the sixth semiconductor layer along the first direction; the fifth semiconductor layer is arranged in the same layer as the second semiconductor layer, and the seventh semiconductor layer is arranged in the same layer as the fourth semiconductor layer Set; Or, The drain electrode is electrically connected with the second connection electrode, the first semiconductor layer is located on one side of the light-emitting layer along a first direction, the fifth semiconductor layer is located on one side of the sixth semiconductor layer along a second direction, and the second direction is opposite to the first direction; The fifth semiconductor layer is arranged in the same layer as the fourth semiconductor layer, and the seventh semiconductor layer is arranged in the same layer as the second semiconductor layer.

8. The light emitting unit of claim 6, wherein, The sixth semiconductor layer and the third semiconductor layer have the same doping type, the doping concentration of the sixth semiconductor layer is greater than the doping concentration of the third semiconductor layer, and the thickness of the sixth semiconductor layer is greater than the thickness of the third semiconductor layer.

9. The light emitting unit according to claim 8, wherein When the fifth semiconductor layer is arranged in the same layer as the second semiconductor layer and the seventh semiconductor layer is arranged in the same layer as the fourth semiconductor layer, the doping concentration in the fifth semiconductor layer is greater than the doping concentration of the second semiconductor layer. When the seventh semiconductor layer is arranged in the same layer as the second semiconductor layer and the fifth semiconductor layer is arranged in the same layer as the fourth semiconductor layer, the doping concentration of the seventh semiconductor layer is greater than the doping concentration of the second semiconductor layer.

10. The light emitting unit according to claim 4 or 5, wherein The first transistor further includes a fifth semiconductor layer and a sixth semiconductor layer which are sequentially stacked, the sixth semiconductor layer includes a first semiconductor part and a second semiconductor part which are spaced apart, the source electrode is electrically connected with the first semiconductor part, the drain electrode is connected between the third semiconductor layer and the second semiconductor part, the first gate electrode is located between the first semiconductor part and the second semiconductor part, and is insulated and spaced apart from the first semiconductor part, the second semiconductor part and the fifth semiconductor layer; Among them, the fifth semiconductor layer is arranged in the same layer as one of the second semiconductor layer and the fourth semiconductor layer, and the sixth semiconductor layer is arranged in the same layer as the third semiconductor layer.

11. The light-emitting unit of claim 10, wherein, The first semiconductor layer is located on one side of the light-emitting layer along a first direction, and the fifth semiconductor layer is located on one side of the sixth semiconductor layer along the first direction; the fifth semiconductor layer is arranged in the same layer as the second semiconductor layer; Or, The first semiconductor layer is located on one side of the light-emitting layer along a first direction, and the fifth semiconductor layer is located on one side of the sixth semiconductor layer along a second direction, and the second direction is opposite to the first direction; The fifth semiconductor layer is arranged in the same layer as the fourth semiconductor layer.

12. The light emitting unit of claim 10, wherein, The doping concentration of the sixth semiconductor layer is greater than the doping concentration in the third semiconductor layer; The thickness of the sixth semiconductor layer is greater than the thickness of the third semiconductor layer.

13. The light emitting unit of claim 12, wherein, When the fifth semiconductor layer is arranged in the same layer as the second semiconductor layer, the doping concentration of the fifth semiconductor layer is greater than the doping concentration in the second semiconductor layer.

14. The light emitting unit according to claim 4 or 5, wherein The light emitting unit further comprises: The first support part comprises a first support layer arranged in the same layer as the first semiconductor layer and a second support layer arranged in the same layer as the light emitting layer; wherein the first transistor is located on the side of the second support layer away from the first support layer; The first conductive member electrically connects the first support layer and the second support layer. The cross section of the first support part perpendicular to the thickness direction gradually increases or stepwisely increases in the direction away from the first transistor.

15. The light emitting unit of claim 14, wherein, The first transistor further comprises a fifth semiconductor layer, a sixth semiconductor layer and a seventh semiconductor layer arranged in sequence, the source electrode is electrically connected with the seventh semiconductor layer, and the drain electrode is electrically connected with the fifth semiconductor layer; the first gate electrode is arranged around the sixth semiconductor layer and the seventh semiconductor layer and is insulated and spaced from the sixth semiconductor layer and the seventh semiconductor layer; wherein 16. The light emitting unit of claim 5, wherein, The first semiconductor layer is located on one side of the light emitting layer along a first direction, and the fifth semiconductor layer is located on one side of the sixth semiconductor layer along the first direction; the fifth semiconductor layer is arranged in the same layer as the fourth semiconductor layer, the sixth semiconductor layer is arranged in the same layer as the eighth semiconductor layer, and the seventh semiconductor layer is arranged in the same layer as the ninth semiconductor layer; Or, The first semiconductor layer is located on one side of the light emitting layer along a first direction, and the fifth semiconductor layer is located on one side of the sixth semiconductor layer along a second direction, the first direction and the second direction are opposite to each other; the fifth semiconductor layer is arranged in the same layer as the eighth semiconductor layer, the sixth semiconductor layer is arranged in the same layer as the fourth semiconductor layer, and the seventh semiconductor layer is arranged in the same layer as the third semiconductor layer. When the fifth semiconductor layer is arranged in the same layer as the eighth semiconductor layer, the orthographic projection of the ninth semiconductor layer on a reference surface covers the orthographic projection of the fifth semiconductor layer and the eighth semiconductor layer on the reference surface, and the reference surface is a plane perpendicular to the thickness direction of the light emitting layer.

17. The light emitting unit of claim 16, wherein, The first transistor further comprises a fifth semiconductor layer and a sixth semiconductor layer arranged in sequence, and the sixth semiconductor layer comprises a first semiconductor part and a second semiconductor part arranged in sequence; the source electrode is electrically connected with the first semiconductor part, the drain electrode is connected between the third semiconductor layer and the second semiconductor part, and the gate electrode is located between the first semiconductor part and the second semiconductor part and is insulated and spaced from the first semiconductor part, the second semiconductor part and the fifth semiconductor layer; 18. The light emitting unit of claim 5, wherein, Wherein, the fifth semiconductor layer is arranged in the same layer as one of the fourth semiconductor layer and the ninth semiconductor layer, and the sixth semiconductor layer is arranged in the same layer as the eighth semiconductor layer; Or, the fifth semiconductor layer is arranged in the same layer as the eighth semiconductor layer, and the sixth semiconductor layer is arranged in the same layer as the fourth semiconductor layer.

19. The light emitting unit of claim 18, wherein ​ The first semiconductor layer is located on one side of the light-emitting layer along a first direction, and the fifth semiconductor layer is located on one side of the sixth semiconductor layer along the first direction; the fifth semiconductor layer is arranged in the same layer as the fourth semiconductor layer; Alternatively, the first semiconductor layer is located on one side of the light-emitting layer along a first direction, and the fifth semiconductor layer is located on one side of the sixth semiconductor layer along a second direction, the first direction and the second direction are opposite to each other; The fifth semiconductor layer is arranged in the same layer as the ninth semiconductor layer; Alternatively, the first semiconductor layer is located on one side of the light-emitting layer along a first direction, and the fifth semiconductor layer is located on one side of the sixth semiconductor layer along a second direction, the first direction and the second direction are opposite to each other; The fifth semiconductor layer is arranged in the same layer as the eighth semiconductor layer, and the sixth semiconductor layer is arranged in the same layer as the fourth semiconductor layer.

20. The light emitting unit according to claim 16 or 19, wherein When the fifth semiconductor layer is arranged in the same layer as the fourth semiconductor layer, The light-emitting unit further comprises: A second support portion, the second support portion comprises: a first support layer arranged in the same layer as the first semiconductor layer, a second support layer arranged in the same layer as the light-emitting layer, a third support layer arranged in the same layer as the second semiconductor layer, and a fourth support layer arranged in the same layer as the fourth semiconductor layer; wherein the first transistor is located on the side away from the first support layer of the fourth support layer; A second conductive member, the second conductive member electrically connects the first support layer, the second support layer, the third support layer, and the fourth support layer.

21. The light emitting unit of claim 20, wherein, The cross section of the second support portion perpendicular to the thickness direction gradually increases or stepwisely increases in the direction away from the first transistor.

22. The light-emitting unit according to any one of claims 4 to 21, wherein The light-emitting unit further comprises: a capacitor, the capacitor comprises a first electrode plate and a second electrode plate arranged opposite to each other, and an insulating layer is arranged between the first electrode plate and the second electrode plate, wherein the first electrode plate and the drain electrode of the first transistor are an integral structure; When the drain electrode is electrically connected with the second connection electrode, and the fourth semiconductor layer is a P-type semiconductor layer, the second electrode plate is connected with the third connection electrode; When the drain electrode is electrically connected with the second connection electrode, and the fourth semiconductor layer is an N-type semiconductor layer, the second electrode plate is electrically connected with the first connection electrode; When the drain electrode is electrically connected with the second gate electrode, the second electrode plate is used to load a ramp signal.

23. The light-emitting unit according to any one of claims 1 to 22, wherein The light-emitting layer is a quantum well layer, and the light-emitting unit is an LED light-emitting chip.

24. A display substrate, wherein, Comprise: A substrate substrate; A plurality of light-emitting units as claimed in any one of claims 1 to 23, the light-emitting units are arranged on the substrate substrate; A first voltage line, the first voltage line is electrically connected with the first connection electrode; A second voltage line, the second voltage line is electrically connected with the third connection electrode. 25.The display substrate of claim 24, wherein, The substrate substrate is a GaN substrate.

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