Circuit board and semiconductor package including same

Abstract

An embodiment of the present invention provides a circuit board including: a first insulating layer; a first circuit pattern layer disposed on the first insulating layer; a second insulating layer disposed on the first insulating layer and the first circuit pattern layer and including a cavity; a second circuit pattern layer disposed on the second insulating layer; a semiconductor device disposed in the cavity; and a resin portion disposed in the cavity and surrounding the semiconductor device, in which an upper surface of the resin portion and an upper surface of the second insulating layer form a step portion.

Description

TECHNICAL FIELD

[0001] Embodiments according to the present application relate to a circuit board and a semiconductor package. BACKGROUND

[0002] As the performance of electrical / electronic products advances, technologies for attaching a large number of packages to a substrate of limited size have been proposed and studied. However, since the general package is based on mounting a single semiconductor chip, there is a limit to obtaining the desired performance.

[0003] A general circuit board or package substrate has a processor package in which a processor chip is disposed and a memory package to which a memory chip is attached as an integrally connected form. Such a package substrate has an advantage in that, by manufacturing a processor chip and a memory chip as a single integrated package, the mounting area of the chips can be reduced, and the path can be shortened to enable high-speed signal transmission. Due to such an advantage, the above-described package substrate is widely used in mobile devices and the like.

[0004] Meanwhile, in recent years, as the specifications of electronic devices such as mobile devices are continuously increasing and HBM (High Bandwidth Memory) is adopted, the package size is continuously increasing. In addition, as the functions required for an application processor increase, it is necessary to configure the application processor as a separate processor chip according to the corresponding functions and provide a circuit board capable of mounting the processor chip. In this case, even when the application processor is divided into two processor chips according to the functions, the number of terminals disposed in each processor chip is increasing.

[0005] In addition, due to 5G, Internet of Things (IoT), higher display resolution, increased communication speed, etc., the number of terminals on the processor chip is gradually increasing as the power and the number of signals increase. Therefore, the area and thickness of the circuit board and the density of the circuit pattern are also increasing. When the area or thickness of the circuit board increases, there can be problems such as non-reliability such as product miniaturization difficulty, warpage of the circuit board, and an increase in product cost. Therefore, it is more advantageous in terms of product cost, reliability against warpage, and product miniaturization to increase the density of the circuit pattern rather than to increase the area or thickness of the circuit board. Therefore, miniaturization of the circuit pattern and the through electrode is required.

[0006] In addition, the number (or total number) of input / output (I / O) terminals disposed in each processor chip is increasing, and the number of chips mounted on the substrate is also increasing. Therefore, it is necessary to increase the total number of input / output of the circuit board to cope with such an increase in the number of chip terminals and chips. SUMMARY

[0007] Technical Problem

[0008] Embodiments of the present application provide a circuit board and a semiconductor package including the same, in which the total number of inputs / outputs is improved without an additional interposer by a cavity provided in a portion of an insulating layer.

[0009] In addition, embodiments can provide a circuit board and a semiconductor package including the same, in which a limitation of improving the total number of inputs / outputs is improved by additionally forming an insulating layer on an upper portion of a semiconductor device mounted in the cavity.

[0010] In addition, embodiments can provide a circuit board and a semiconductor package including the same, in which reliability is improved by a molding member surrounding the semiconductor device.

[0011] In addition, embodiments can provide a circuit board and a semiconductor package including the same, in which heat dissipation performance is improved by a heat dissipation member configured to transfer heat from a semiconductor device mounted in the cavity and from a chip provided above the semiconductor device to the outside.

[0012] The object to be solved by the embodiments is not limited to the above-described object, and will include an object and effects that can be identified from the solution of the object and the embodiments described below.

[0013] Technical Solution

[0014] The circuit board according to an embodiment of the present application includes a first insulating layer, a first circuit pattern layer disposed on the first insulating layer, a second insulating layer disposed on the first insulating layer and the first circuit pattern layer and including a cavity, a second circuit pattern layer disposed on the second insulating layer, a semiconductor device disposed in the cavity, and a resin portion disposed in the cavity and configured to surround the semiconductor device, wherein an upper surface of the resin portion and an upper surface of the second insulating layer form a stepped portion.

[0015] The circuit board can include a filling member disposed in the cavity and positioned between the first insulating layer and a connection portion of the semiconductor device.

[0016] The filling member can have a width that gradually increases from the semiconductor device toward the first insulating layer.

[0017] The circuit board can include a connection portion disposed between the semiconductor device and the first insulating layer.

[0018] The circuit board can include a resin portion configured to surround the semiconductor device in the cavity.

[0019] The resin portion can be in contact with a side surface or a bottom surface of the cavity.

[0020] The second insulating layer can include an edge portion located outside the cavity.

[0021] A height from a bottom surface of the cavity to an upper surface of the edge portion can be different from a height from the bottom surface of the cavity to an upper surface of the resin portion.

[0022] The circuit board can include a third insulating layer disposed on the second insulating layer and the second circuit pattern layer, and a third circuit pattern layer disposed on the third insulating layer.

[0023] The circuit board can include a heat dissipation member disposed on the semiconductor device, wherein an upper surface of the heat dissipation member can be located above an upper surface of the edge portion, a lower surface of the third insulating layer can be in contact with an upper surface of the resin portion, and the resin portion can be disposed between the third insulating layer and the semiconductor device.

[0024] Advantageous effects

[0025] Embodiments of the present application achieve a circuit board in which the total number of inputs / outputs can be improved without an additional interposer by a cavity disposed in a portion of an insulating layer, and a semiconductor package including the same.

[0026] In addition, embodiments can achieve a circuit board in which a limitation of improving the total number of inputs / outputs is additionally formed on an upper portion of a semiconductor device mounted in a cavity to improve the total number of inputs / outputs, and a semiconductor package including the same.

[0027] In addition, embodiments can achieve a circuit board in which reliability is improved by a molding member surrounding a semiconductor device, and a semiconductor package including the same.

[0028] In addition, embodiments can achieve a circuit board in which heat dissipation performance is improved by a heat dissipation member configured to transfer heat from a semiconductor device mounted in a cavity and from a chip disposed above the semiconductor device to the outside, and a semiconductor package including the same.

[0029] Various advantages and effects of the present application are not limited to the above description, and can be more easily understood through a description of specific embodiments of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 is a conceptual view of a circuit board according to an embodiment.

[0031] Figure 2 is a view of a circuit board according to a first embodiment.

[0032] Figure 3 is a partial enlarged view of Figure 2 .

[0033] Figure 4 is a plan view of a circuit board according to the first embodiment.

[0034] Figures 5 to 7 is a flowchart showing a method of manufacturing a circuit board according to the first embodiment.

[0035] Figure 8 is a view of a circuit board according to the second embodiment.

[0036] Figure 9 is a partial enlarged view of Figure 8

[0037] Figure 10 is a modified example of Figure 9

[0038] Figure 11 is a plan view of a circuit board according to the second embodiment.

[0039] Figure 12 is a view of a circuit board according to the third embodiment.

[0040] Figure 13 is a partial enlarged view of Figure 12

[0041] Figure 14 is a cross-sectional view showing a semiconductor package according to the first embodiment.

[0042] Figure 15 is a cross-sectional view showing a semiconductor package according to the second embodiment. DETAILED DESCRIPTION

[0043] While the application is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit the application to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the application.

[0044] It should be understood that, although the terms “second,” “first,” etc. can be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another. For example, a first component could be termed a second component, and, similarly, a second component could be termed a first component, without departing from the scope of the application. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0045] ​​​It will be understood that when a component is referred to as being "connected" or "coupled" to another component, it can be directly connected or coupled to the other component or intervening components can be present. In contrast, when a component is referred to as being "directly connected" or "directly coupled" to another component, there are no intervening components present.

[0046] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. In this application, the use of "including", "comprising", "having" and / or "containing" will be understood to be open-ended, and will be taken to mean that "comprising", "including" and / or "containing" and / or "having" and the like, is inclusive of almost all components, integers, steps, operations, elements, and / or groups thereof. "Comprising" or "comprising" or "having" will be understood to imply the inclusion of a stated integer or step or group of integers or steps but not to the exclusion of any other integer or step or group of integers or steps.

[0047] Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. It should also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0048] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Regardless of the reference numerals, the same reference numerals refer to the same components throughout the drawings description, and the description of the same components will not be repeated.

[0049] Before describing the embodiments, an electronic device to which a semiconductor package of the embodiments is applied will be briefly described. The electronic device includes a main board (not shown). The main board can be physically and / or electrically connected to various components. For example, the main board can be connected to a semiconductor package of the embodiments. Various semiconductor devices can be mounted in the semiconductor package.

[0050] The semiconductor device can include an active device and / or a passive device. The active device can be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions of devices are integrated in one chip. The semiconductor device can be a logic chip, a memory chip, etc. The logic chip can be a central processing unit (CPU), a graphics processing unit (GPU), etc. For example, the logic chip can be an application processor (AP) chip including at least one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor, a cryptographic processor, a microprocessor, and a microcontroller, can be an analog-to-digital converter, an ASIC (application-specific IC), etc., or can be a chipset including a specific combination of those listed so far.

[0051] The memory chip can be a stacked memory such as an HBM. Also, the memory chip can include a memory chip such as a volatile memory (e.g., a DRAM), a non-volatile memory (e.g., a ROM), a flash memory, etc.

[0052] Meanwhile, a product group of the semiconductor package to which the embodiment is applied can be any one of a CSP (Chip Scale Package), an FC-CSP (Flip Chip-Chip Scale Package), an FC-BGA (Flip Chip Ball Grid Array), a POP (Package On Package), and a SIP (System In Package), but the present application is not limited thereto.

[0053] In addition, the electronic device can be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, etc. However, the electronic device is not limited thereto, and can be any other electronic device that processes data other than these devices.

[0054] Figure 1 is a conceptual diagram of a circuit board according to an embodiment.

[0055] First, referring to Figure 1 , the circuit board includes an electrode part 120 for electrical connection and an insulating layer 110 for preventing electrical short connection between the electrode parts 120. Referring to Figure 1 , the insulating layer 110 can include an upper surface on which a semiconductor device will be mounted and a lower surface corresponding to the upper surface and configured to connect the circuit board CB to a main board or the like, and the insulating layer 110 can have a structure in which a plurality of insulating layers 111 and 112 are stacked between the upper surface and the lower surface. The upper insulating layer 112 forming the upper surface of the circuit board and the lower insulating layer 112 forming the lower surface of the circuit board can be referred to as an outer stacking area, and an area stacked between the upper insulating layer and the lower insulating layer can be referred to as an inner stacking area.

[0056] The electrode portion 120 is provided for electrical connection between a main board or the like and the semiconductor device SD, and includes a circuit pattern (or a circuit pattern layer), a pad, and a via electrode. Also, the circuit pattern can be designed in various forms for signal and / or power transmission with the semiconductor device SD, and is provided in each insulating layer 110 of the vertical stack.

[0057] The via electrodes 121b and 122b are provided for vertically connecting the circuit patterns provided in the insulating layers of the vertical stack, and pass through at least a portion of each insulating layer. That is, the insulating layers can include a via for disposing the via electrode. Also, the width of the via electrode can be greater than that of the circuit pattern for impedance optimization or heat dissipation, but is not limited thereto, and can be freely designed.

[0058] The pads 121a and 122a can include an external pad 122a provided in the outer stack region and an internal pad 121a provided in the inner stack region. The external pad 122a is for bonding to the semiconductor device SD and / or a main board or a substrate CB. The external pad can be bonded by solder, a wire, a conductive adhesive, or the like, and can be provided to have a width greater than that of the circuit pattern to secure yield. However, the present application is not limited thereto, and the pad can have the same width as the circuit pattern according to the technical limitations of the bonding process. The internal pad 121a is for connecting the via electrode to the circuit pattern. When the via electrode is provided to have a width greater than that of the circuit pattern, a pad having a width greater than that of the circuit pattern is provided to secure position alignment during a manufacturing process of forming the via electrode on each circuit pattern. Thus, each via electrode can have an upper surface in direct contact with and lying on the same plane as a lower surface of an upper pad, and a lower surface in direct contact with and lying on the same plane as an upper surface of a lower pad. Here, the lower surface of the upper pad and the upper surface of the lower pad do not necessarily mean a flat surface, but should be understood to include a concave surface or a convex surface depending on various manufacturing processes.

[0059] Also, the via electrode and the pad can be integrally formed according to the process. That is, the pad can include a protrusion for electrically connecting the circuit patterns provided in each insulating layer of the stack, and the protrusion can be regarded as a via electrode electrically connecting the circuit patterns stacked adjacent to each other. That is, according to the process, the via electrode and the pad can be distinguished as different components, or the via electrode can be distinguished as a protrusion of the pad. Also, the pad can correspond to a protruding portion of the via electrode. For example, after forming the via, the via electrode and the pad can be formed by plating. Thereafter, an etching process, for example, chemical mechanical polishing (CMP), can be performed.

[0060] The circuit board can further include a protective layer RL. The protective layer RL can be used to protect the pads from external moisture or contaminants, and can prevent short circuit problems between adjacent conductive bonding members during bonding between the semiconductor device and / or the main board and the circuit board. For example, the protective layer RL can be provided as a solder resist. Specifically, the semiconductor device and / or the main board can have a plurality of terminals to be connected to the circuit board. Also, the plurality of terminals can be provided in a high density. For example, when the plurality of terminals are bonded to the pads of the circuit board, solder can be used as the conductive bonding member. When solder is used, a solder short circuit (bridging) problem can occur between the high density terminals, and in order to solve such a short circuit problem, a solder resist having poor wettability with the solder can be provided. Also, for electrical connection, the protective layer RL can be formed of a material having insulating properties. Accordingly, the protective layer RL can be referred to as an "insulating layer", and can be one of the components of the insulating layer 110 described above.

[0061] Also, the insulating layer 112 or the protective layer RL located in the outer stacking area of the circuit board can have an opening OP. Through the opening OP, electrical connection with another semiconductor device, a circuit board, or the like can be achieved.

[0062] The circuit board can be classified into a package substrate and a interposer according to its function. The package substrate is used to mount a semiconductor device and / or an interposer. Due to an increase in data, as the area of the circuit board becomes larger or the number of stacked insulating layers increases, the yield of the circuit board can be significantly reduced. Accordingly, in order to improve the yield of the circuit board having a large number of stacked layers, the circuit board can be divided into an interposer and a package substrate, thereby improving the yield of the circuit board. Also, the interposer can be used as a buffer between the pad size and / or spacing of the package substrate and the fine terminal pattern size and / or spacing of the semiconductor device. Specifically, as the pitch and size of the terminals of the semiconductor device decrease and the terminal density increases, it can be difficult to implement pads having a size and / or pitch corresponding to the terminals of the semiconductor device on the package substrate. Accordingly, by providing an interposer having a pad size and / or spacing between the package substrate and the semiconductor device, electrical connection between the semiconductor device and the package substrate can be facilitated.

[0063] The package substrate and the interposer described above can be classified into a core substrate and a coreless substrate according to the configuration of the insulating layer. In the case of the core substrate, the insulating layer can include a core layer, and the core layer can refer to a layer including a reinforcing member among the stacked insulating layers. The reinforcing member can refer to glass fibers. The core layer can be provided to be thicker than the other insulating layers to prevent warping of the circuit board or the like during a process. However, the core layer can cause problems such as voltage drop and signal loss, or can cause it to be difficult to implement thinning. Accordingly, according to the application field, a coreless substrate in which the insulating layer of the circuit board does not include a core layer can be used.

[0064] The insulating layer of the circuit board is formed of any insulating resin such as a thermosetting resin and / or a light-cured resin. As the thermosetting resin, ABF (Ajinomoto Build-up Film), which is a product released by Ajinomoto Co., Inc., or a Prepreg (PPG) including glass fibers can be used. As the light-cured resin, an insulating resin such as a PID (Photo Imageable Dielectric) resin can be used. The above-described insulating resin can exemplarily be an epoxy resin, a BT (Bismaleimide Triazine) resin, a phenol resin, or the like, and can include an inorganic filler such as silica. When the insulating resin is used as the core, the insulating resin can include a reinforcing material such as glass fibers or aramid fibers.

[0065] Figure 2 is a view of a circuit board according to the first embodiment, Figure 3 is Figure 2 is a partial enlarged view of Figure 4 is a plan view of a circuit board according to the first embodiment.

[0066] Referring to Figures 2 to 4 , the circuit board 100A according to the embodiment can include an insulating layer 110, an electrode portion 120, a semiconductor device SD, a connection portion SB, and a molded member MP. In each embodiment, unless otherwise described below, the description given with reference to Figure 1 can be applied to the insulating layer and the electrode portion.

[0067] The circuit board 100A according to the embodiment can include a second insulating layer 112 having a cavity CV. In the circuit board according to the embodiment of the present application, the concept of the circuit pattern layer can be understood to include Figure 1 described in the description.

[0068] First, the insulating layer 110 can be formed of an insulating material. The insulating layer 110 can be formed in at least one layer. When the insulating layer 110 has a multi-layer structure, the plurality of insulating layers 110 can include the same insulating material, but the present application is not limited thereto. For example, at least one of the plurality of insulating layers 110 can include a different insulating material from at least one other insulating layer 110.

[0069] The insulating layer 110 of the circuit board 100A can be rigid or flexible. For example, the insulating layer 110 of the circuit board 100A can include glass or plastic. For example, the insulating layer 110 of the circuit board can include chemically strengthened / semi-toughened glass such as soda lime glass or aluminosilicate glass. For example, the insulating layer 110 of the substrate can include reinforced or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). For example, the insulating layer 110 of the circuit board can include sapphire. For example, the insulating layer 110 of the substrate can include an optically isotropic film. For example, the insulating layer 110 of the substrate can include COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA). For example, the insulating layer 110 of the substrate can be formed of a material including a filler and an insulating resin. For example, the insulating layer 110 of the substrate can have a structure in which a filler of silica or alumina is disposed in a thermosetting resin or a thermoplastic resin.

[0070] The insulating layer 110 can have a structure in which a plurality of different insulating materials are stacked, and exemplary arrangement structures thereof will be described in greater detail below.

[0071] In one embodiment, the insulating layer 110 can include a core layer having a reinforcing member or a coreless layer.

[0072] For example, as illustrated, the insulating layer 110 can include a core layer. Such a core layer can refer to an insulating layer including a reinforcing member and having a thickness exceeding 30 µm in a stacking direction (X-axis direction) thereof. Further, the insulating layer can include a plurality of layers disposed above and below the core layer, respectively, and not including a reinforcing member. In this case, the circuit board can be a core substrate. The reinforcing member can also be referred to as a reinforcing fiber or a glass fiber.

[0073] The reinforcing member can refer to a glass fiber material extending in a horizontal direction of the insulating layer, and can have a different meaning from a filler spaced apart from each other.

[0074] In another embodiment, the insulating layer 110 of the substrate can be a coreless substrate that does not include a core layer. For example, the insulating layer 110 of the substrate can include an organic material that does not have a reinforcing member, thereby exhibiting excellent processability, allowing the circuit board to be thinned, and enabling the electrode portion of the circuit board to be miniaturized. For example, as the insulating layer 110 of the substrate, ABF (Ajinomoto Build-up Film), which is a product released by Ajinomoto Co., Inc., FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. can be used as examples. For example, the insulating layer 110 can include a plurality of layers composed of ABF.

[0075] In an embodiment, the insulating layer 110 can include a first insulating layer 111 and a second insulating layer 112. The second insulating layer 112 can be disposed on the first insulating layer 111.

[0076] The first insulating layer 111 can be a part of a copper clad laminate (CCL). Alternatively, the first insulating layer 111 can correspond to a copper clad laminate. For example, the first insulating layer 111 and the first electrode portion 121 located on the first insulating layer 111 can be a copper clad laminate (CCL). The first insulating layer 111 and the first circuit pattern layer 121a can be a copper clad laminate (CCL).

[0077] Further, the first insulating layer 111 can include an insulating material in the inner stacking region of the circuit board 100A. The first insulating layer 111 can be formed of a plurality of layers, and the plurality of layers can be made of the same material or different materials. Depending on the analysis method, the interface between the first insulating layer 111 and the second insulating layer 112 above the first insulating layer 111 can be distinguished or not distinguished. The description of the interface can be equally applied to each insulating layer within the first and second insulating layers. Further, the first insulating layer 111 can be located between the upper and lower second insulating layers 112. The second insulating layer 112 can be disposed on the upper and lower surfaces of the first insulating layer 111.

[0078] During the cavity-forming etching process, the first insulating layer 111 and the first electrode portion 121 can not be easily removed by etching. That is, even when the cavity CV is formed in the second insulating layer 112, the first insulating layer 111 and the first electrode portion 121 are easily left behind.

[0079] Further, the second insulating layer 112 can have a via due to the cavity. In other words, the cavity CV can include a via of the second insulating layer 112 and an upper surface of the first insulating layer 111. Further, in another example, the cavity can be formed to pass through a partial area of the second insulating layer 112. That is, the cavity can correspond to a groove of the second insulating layer 112.

[0080] Further, the second insulating layer 112 can be a single layer or a plurality of layers. In this case, the cavity can correspond to a hole (or a groove) passing through a part or all of the single layer. Further, when the second insulating layer 112 is a plurality of layers, the cavity can correspond to a hole (or a groove) passing through some of the plurality of layers or passing through all of the plurality of layers.

[0081] Further, the second insulating layer 112 can be disposed on the first insulating layer 111 and the first circuit pattern layer 121a. The second insulating layer 112 can correspond to an outer stacking area of the circuit board 100A.

[0082] The second insulating layer 112 can be formed of at least one layer. As illustrated, the second insulating layer 112 can be formed of a plurality of layers. Further, as described above, the second insulating layer 112 can include an ABF (Ajinomoto Build-up Film) or a prepreg (PPG) including a glass fiber.

[0083] The second insulating layer 112 can be located on at least one of an upper surface and a lower surface of the first insulating layer 111. Hereinafter, a description will be made based on a stacking direction (X-axis direction).

[0084] Further, as described above, a protective layer (not shown) can be further disposed on the second insulating layer 112. The protective layer (not shown) can be a solder resist layer. The solder resist layer, due to having low solder wettability, can have a function of preventing solder from flowing during solder bonding, or can have a function of preventing moisture or contaminants from penetrating into the circuit board from the outside.

[0085] Further, the protective layer (not shown) can be a solder resist layer including an organic polymer material. As an example, the protective layer (not shown) of the circuit board can include a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acryl monomer, etc. Further, the protective layer (not shown) can include one of a photo solder resist layer, a cover-lay, and a polymer material.

[0086] The electrode portion 120 can include a first electrode portion 121 and a second electrode portion 122. The first electrode portion 121 can be located in the first insulating layer 111. The second electrode portion 122 can be located in the second insulating layer 112.

[0087] The first electrode portion 121 can include a first circuit pattern layer 121a and a first through electrode 121b. The second electrode portion 122 can include a second circuit pattern layer 122a and a second via electrode 122b. As described above, each circuit pattern layer can refer to a pad (or trace) and a circuit pattern including an electrode portion. Also, the circuit pattern layer can be disposed on a corresponding stack insulating layer, and the via electrode can be disposed between the circuit pattern layers located in different layers to provide an electrical connection between the circuit pattern layers. Also, the through electrode can electrically connect a plurality of circuit pattern layers disposed on different layers.

[0088] The first circuit pattern layer 121a can be disposed on the first insulating layer 111. In an embodiment, the first circuit pattern layer 121a can be disposed on each of the upper and lower surfaces of the first insulating layer 111. Alternatively, the first circuit pattern layer 121a can be disposed on the upper surface of the first insulating layer 111. The first through electrode 121b can pass through the first insulating layer 111 and can be in contact with the first circuit pattern layer 121a.

[0089] The second circuit pattern layer 122a can be disposed on the second insulating layer 112. The second circuit pattern layer 122a can be disposed on each of the upper and lower surfaces of the second insulating layer 112. The second through electrode 122b can pass through the second insulating layer 112 and can be in contact with the second circuit pattern layer 122a.

[0090] As described above, the first circuit pattern layer 121a and the second circuit pattern layer 122a can be located in the first insulating layer 111 and the second insulating layer 112, respectively. Also, as described above, since the circuit pattern layer is a concept including a circuit pattern and a pad, the circuit pattern layer can be located in each insulating layer and can not be directly connected to the via electrode or the through electrode. However, each circuit pattern layer can be electrically connected to any one of the via electrodes.

[0091] Also, the first insulating layer 111 and the second insulating layer 112 can include vias or through holes V1 and V2. The through holes can include a first through hole V1 passing through the first insulating layer 111 and a second through hole V2 passing through the second insulating layer 112. Also, the through electrodes of the electrode portions can be located in the through holes V1 and V2. For example, the first through electrode 121b can be located in the first through hole V1. The second through electrode 122b can be located in the second through hole V2.

[0092] In an embodiment, the first via V1 of the first insulating layer 111 and the second via V2 of the second insulating layer 112 can have an inclined surface in the stacking direction. That is, the area of the adjacent first via V1 and second via V2 can increase or decrease in one direction. For example, based on the upper region of the circuit board 100A, the area of the first via V1 and the second via V2 can increase in the stacking direction. Here, the upper region of the circuit board 100A corresponds to a region located on the stacking direction side among regions obtained by bisecting the first insulating layer 111 in the stacking direction.

[0093] In addition, since the second insulating layer 112 is formed of a plurality of insulating layers, the second via V2 can also be formed of a plurality of vias. The area of each of the plurality of second vias V2 can increase or decrease in one direction. Based on the upper region of the circuit board 100A, the area of the plurality of second vias V2 can increase in the stacking direction.

[0094] In addition, the second insulating layer 112 can cover at least a portion of the first circuit pattern layer 121a. Further, a protective layer (not shown) can cover at least a portion of the second circuit pattern layer 122a. The protective layer (not shown) can include an opening for electrical connection with a semiconductor device, an interposer, or the like. The second circuit pattern layer 122a can be exposed by the opening. A shielding layer, which will be described later, can be located on the third insulating layer.

[0095] The second insulating layer 112 can include a cavity CV. The second insulating layer 112 can include the cavity CV and an edge portion EG outside the cavity CV. The edge portion EG can correspond to a "peripheral portion", a "wall portion", a "side wall", or the like. Further, the second electrode portion 122 can be located on the edge portion. In an embodiment of the present application, the cavity CV can be variously referred to as a "groove", a "recess", a "hole", or a "via", or the like. Further, the cavity CV can have various shapes, such as a circular shape and a rectangular shape.

[0096] The cavity CV can be located in the second insulating layer 112. That is, the cavity CV can be located on the first insulating layer 111 and the first electrode portion 121.

[0097] Further, the cavity CV can have various shapes according to the shape of a semiconductor device or a chip mounted therein. For example, generally, when viewed in a plane perpendicular to the stacking direction, the semiconductor device or the chip can have a rectangular shape. Accordingly, when viewed in a plane perpendicular to the stacking direction, the cavity CV can also have a rectangular shape.

[0098] Further, by providing a mounting space of a semiconductor device or a chip inside the cavity CV, and by providing the second electrode portion 122 in the second insulating layer 112 outside the cavity CV, a circuit pattern having a small line width can be easily provided in the second insulating layer 112. Accordingly, the circuit board according to the embodiment can provide an improved total number of input / output (I / O).

[0099] A portion 111E of the first insulating layer can be exposed by the cavity CV. A portion 121E of the first circuit pattern layer 121a can be exposed by the cavity CV.

[0100] In addition, at least a portion of the first circuit pattern layer 121a can be exposed by the cavity CV.

[0101] The connection portion SB can be provided on a plurality of electrode portions (first electrode portions) of the circuit board, respectively. In particular, the connection portion SB can be provided on the first circuit pattern layer exposed by the cavity in the circuit board.

[0102] The connection portion SB can have a spherical shape. For example, a cross-section of the connection portion SB can have a circular or semi-circular shape. For example, a cross-section of the connection portion SB can have a partial circular or a full circular shape. For example, a cross-sectional shape of the connection portion SB can be planar on one side surface and curved on the other side surface. The connection portion SB can be a solder ball, but is not limited thereto.

[0103] In addition, in the circuit board according to the embodiment, the connection portion SB can be located between the semiconductor device SD and the first insulating layer 111. That is, a terminal for electrical connection of the semiconductor device SD can be positioned toward the first insulating layer 111. Alternatively, the terminal of the semiconductor device SD can extend downward.

[0104] The semiconductor device SD can be mounted in the cavity CV. The semiconductor device SD can be provided on the connection portion SB. The semiconductor device SD can be a processor chip. For example, the semiconductor device SD can be an application processor (AP) chip including at least one of a central processing unit (e.g., CPU), a graphics processing unit (e.g., GPU), a digital signal processor, a cryptographic processor, a microprocessor, and a microcontroller. Further, the semiconductor device SD can also be referred to as a "chip" or the like.

[0105] At this time, the terminal can be included in a lower surface of the semiconductor device SD, and the terminal can be electrically connected to the first electrode portion (first circuit pattern layer) of the circuit board through the connection portion SB.

[0106] Meanwhile, the circuit board of the embodiment can include a plurality of chips spaced apart from each other at a predetermined interval. For example, the semiconductor device SD can include a first chip and a second chip spaced apart from each other.

[0107] For example, the circuit board can include a plurality of cavities spaced apart from each other in a width direction or a length direction. Also, the first chip and the second chip can be disposed in the plurality of cavities, respectively. In this case, at least one terminal of the first chip can be connected to at least one terminal of the second chip. Also, the first chip and the second chip can be different types of application processor (AP) chips. Meanwhile, the first chip and the second chip can be spaced apart from each other by a predetermined interval distance on the circuit board. Accordingly, electrical reliability can be ensured. Also, the distance between the first chip and the second chip can prevent signal transmission loss between the first chip and the second chip or signal transmission loss to each of the first chip and the second chip.

[0108] Also, an insulating layer for protecting a terminal of the semiconductor device SD can be additionally disposed between the semiconductor device SD and the first insulating layer 111.

[0109] Also, the circuit board 100A can further include a filling member FP disposed below the semiconductor device SD to surround the connection portion SB. The filling member FP can be formed of a resin. Also, the filling member FP can include an insulating material.

[0110] In an embodiment, the filling member FP can be disposed in the cavity CV and can be located between the connection portion of the semiconductor device SD and the first insulating layer. A width of the filling member FP can gradually increase from the semiconductor device SD toward the first insulating layer. In other words, the width of the filling member FP can increase in a direction opposite to the stacking direction, or from the second insulating layer toward the first insulating layer. For example, in a region in contact with the first insulating layer, the width of the filling member FP can be greater than the width of the semiconductor device SD.

[0111] The resin portion MP can be located in the cavity CV. The resin portion MP can be disposed to surround the semiconductor device SD. Accordingly, the resin portion MP can be in contact with a side surface CVS and / or a bottom surface CVB of the cavity CV. For example, the resin portion MP can be located on an upper surface of the semiconductor device SD. Also, the resin portion MP can be located between the semiconductor device SD and the side surface CVS of the cavity. The resin portion MP can also be referred to as a "molding member", a "molding portion", a "resin member", or the like.

[0112] The resin portion MP can also be referred to as a molding layer, a resin layer, a bottom filling, or the like. The resin portion MP can fill an inside of the cavity and can improve structural reliability of the circuit board. For example, the resin portion MP can reduce structural deformation (e.g., warpage).

[0113] Further, a height h2 from the bottom surface CVB of the cavity CV to the upper surface EGU of the edge portion EG can be the same as or different from a height h1 from the bottom surface CVB of the cavity CV to the upper surface MPU of the resin portion MP.

[0114] In an embodiment, the height h1 from the bottom surface CVB of the cavity CV to the upper surface MPU of the resin portion MP can be set to various heights to improve structural reliability.

[0115] For example, the height h2 from the bottom surface CVB of the cavity CV to the upper surface EGU of the edge portion EG can be the same as the height h1 from the bottom surface CVB of the cavity CV to the upper surface MPU of the resin portion MP. Thus, the arrangement of the additional underlay or the addition of the insulating layer can be easily performed. Further, the adhesion between the semiconductor device SD and the cavity (or the insulating layer) can be appropriately maintained by the resin portion MP.

[0116] Alternatively, the height h2 from the bottom surface CVB of the cavity CV to the upper surface EGU of the edge portion EG can be different from the height h1 from the bottom surface CVB of the cavity CV to the upper surface MPU of the resin portion MP.

[0117] In an embodiment, the upper surface MPU of the resin portion MP and the upper surface of the second insulating layer 112 (or the upper surface EGU of the edge portion EG) can form a stepped portion. For example, the upper surface MPU of the resin portion MP can be located above the upper surface of the second insulating layer 112.

[0118] In other words, the height h2 from the bottom surface CVB of the cavity CV to the upper surface EGU of the edge portion EG can be greater than the height h1 from the bottom surface CVB of the cavity CV to the upper surface MPU of the resin portion MP.

[0119] With this configuration, deformation due to a difference in a coefficient of thermal expansion between a component disposed in the cavity CV and the insulating layer can be minimized.

[0120] Alternatively, the height h2 from the bottom surface CVB of the cavity CV to the upper surface EGU of the edge portion EG can be less than the height h1 from the bottom surface CVB of the cavity CV to the upper surface MPU of the resin portion MP.

[0121] Further, the upper surface MPU of the resin portion MP can be located below the upper surface of the circuit pattern layer 122a. For example, the upper surface MPU of the resin portion MP can be located between the upper surface of the circuit pattern layer 122a and the first insulating layer 111.

[0122] In an embodiment, the upper surface MPU of the resin portion MP can have a first height difference DH1 from the upper surface of the circuit pattern layer 122a. In addition, the upper surface EGU of the edge portion EG can have a second height difference DH2 from the upper surface of the circuit pattern layer 122a. In addition, as described above, the upper surface MPU of the resin portion MP can be varied with respect to the upper surface EGU of the edge portion. Accordingly, the first height difference DH1 can be the same as or different from the second height difference DH2.

[0123] Further, the bottom surface CVB of the cavity CV can correspond to the exposed upper surface 111E of the first insulating layer. In addition, the bottom surface CVB of the cavity CV can correspond to the exposed first electrode portion or the exposed first circuit pattern layer. Accordingly, the electrical connection between the semiconductor device or chip mounted in the cavity CV and the second electrode portion 122 can be easily achieved.

[0124] Figures 5 to 7 is a flowchart illustrating a method of manufacturing a circuit board according to the first embodiment.

[0125] Referring to Figure 5 A copper-clad laminate having copper foils on both surfaces and including a first insulating layer 111 is prepared. In addition, a via or a through-hole is formed in the first insulating layer 111. The via or the through-hole can be formed by a laser drilling method, a punching method, an etching method (mechanical drilling, chemical etching, or any other suitable mechanism), or the like.

[0126] In addition, a first through-electrode can be formed in the first through-hole. Thereafter, a first circuit pattern layer can be formed on an upper portion of the first insulating layer 111 by patterning.

[0127] Further, a second insulating layer 112 can be stacked on both surfaces of the first insulating layer 111. In addition, a via or a through-hole can be formed in the second insulating layer, and a second through-electrode can be formed. However, one region of the second insulating layer 112 can be formed only of an insulating layer without a second electrode portion. Such one region can correspond to the above-described cavity region.

[0128] Each circuit pattern layer can be formed by an Additive Process, a Subtractive Process, a MSAP (Modified Semi Additive Process), a SAP (Semi Additive Process), or the like, which are printed circuit board manufacturing processes.

[0129] Further, a dry film or the like can be used to form a pattern.

[0130] Referring to Figure 6A cavity CV can be formed inside the second insulating layer 112 in the above region by a method such as a laser drilling method, a punching method, an etching method, or the like. The cavity CV can pass through the central region of the second insulating layer 112. The cavity CV can be surrounded by the second electrode portion. A portion of the first insulating layer 111 and a portion of the first electrode portion 121 can be exposed by the cavity CV.

[0131] Referring to Figure 7 A semiconductor device SD and a connection portion SB can be provided in the cavity CV. The connection portion SB can be provided on each of a plurality of electrode portions (first electrode portions) of the circuit board, and can be provided on the first circuit pattern layer exposed by the cavity CV.

[0132] Further, a resin portion MP can be filled in the cavity CV to cover the semiconductor device SD.

[0133] The resin portion MP can be formed of a molding resin, and for example, can be an EMC (Epoxy molding compound). The resin portion MP can also be formed of various other molding resins other than the EMC.

[0134] Figure 8 is a view of a circuit board according to a second embodiment, Figure 9 is Figure 8 is a partial enlarged view of Figure 10 is Figure 9 is a modification of Figure 11 is a plan view of a circuit board according to the second embodiment.

[0135] Referring to Figures 8 to 11 The circuit board 100B according to the second embodiment can include an insulating layer 110, an electrode portion 120, a semiconductor device SD, a connection portion SB, and a resin portion MP.

[0136] The above description can be applied in the same manner unless otherwise described below.

[0137] The insulating layer 110 can include a third insulating layer 113 provided on the second insulating layer 112 and the second circuit pattern layer 122a.

[0138] Further, the electrode portion 120 can include a third electrode portion 123. The third electrode portion 123 can be provided in the third insulating layer 113. The third electrode portion 123 can include a third circuit pattern layer 123a and a third via electrode 123b.

[0139] Further, a third circuit pattern layer 123a can be provided on the third insulating layer 113. The third circuit pattern layer 123a can be provided on the upper surface and the lower surface of the third insulating layer 113. The third through electrode 123b can pass through the third insulating layer 113 and can be in contact with the third circuit pattern layer 123a.

[0140] The third insulating layer 113 can include an upper surface 113US and a lower surface 113BS. The lower surface 113BS of the third insulating layer 113 can be in contact with the upper surface of the second insulating layer 112.

[0141] The lower surface 113BS of the third insulating layer 113 can be in contact with the resin portion MP above the cavity CV. For example, the lower surface 113BS of the third insulating layer 113 can be in contact with the upper surface MPU of the resin portion MP. With this configuration, heat dissipation of the circuit board can be improved and structural reliability can be enhanced. Further, the total number of inputs / outputs can be increased by the third insulating layer 113.

[0142] Further, the resin portion MP can be provided between the third insulating layer 113 and the semiconductor device SD. Accordingly, the resin portion MP can overlap a portion of the third insulating layer 113 in the stacking direction. Accordingly, the third electrode portion and the resin portion MP can partially overlap in the stacking direction. With this configuration, the support force of the resin portion MP on the third insulating layer 113 can be ensured.

[0143] In a modification example, the upper surface MPU of the resin portion MP and the lower surface 113BS of the third insulating layer 113 can be provided to be spaced apart (gap) from each other. With this configuration, the expansion space of the resin portion MP can be easily ensured.

[0144] Figure 12 is a view of a circuit board according to the third embodiment, Figure 13 is Figure 12 is a partial enlarged view of

[0145] Referring to Figure 12 and Figure 13 , the circuit board 100C according to the third embodiment can include an insulating layer 110, an electrode portion 120, a semiconductor device SD, a connection portion SB, and a resin portion MP. The above description can be applied in the same manner unless otherwise described below.

[0146] Further, the circuit board 100C can further include a heat dissipation member HM provided in the cavity CV. The heat dissipation member HM can be located in the resin portion MP. In addition, the heat dissipation member HM can be referred to as a heat sink. Further, the heat dissipation member HM can be provided on the semiconductor device SD. Further, the heat dissipation member HM can be located between the semiconductor device SD and the third insulating layer 113. Further, the heat dissipation member HM can be in contact with the third insulating layer 113 and the semiconductor device SD. For example, the heat dissipation member HM can be in contact with the semiconductor device SD, or can be in contact with the lower surface 113BS of the third insulating layer 113.

[0147] Accordingly, heat generated from the semiconductor device SD or heat generated from the external substrate, or the like can be easily transferred to the outside. For example, heat generated from the external substrate / chip can be easily transferred downward in the circuit board. Accordingly, heat concentrated in a partial region can be easily dispersed.

[0148] In addition, as an example, the upper surface of the heat dissipation member HM can be the same as or different from the upper surface of the edge portion EG. For example, the upper surface of the heat dissipation member HM can be located above the upper surface of the edge portion EG. Accordingly, the heat dissipation effect can be improved.

[0149] Further, the side surface CVS of the cavity CV can be an inclined surface. The side surface CVS of the cavity CV can be inclined at a predetermined angle with respect to the bottom surface of the cavity CV.

[0150] Further, the second insulating layer 112 overlapping the cavity CV in the horizontal direction can be formed of a plurality of insulating layers. Further, the side surface of the cavity CV can be inclined at different angles in at least two of the plurality of insulating layers of the second insulating layer 112. For example, based on an upper portion of the plurality of insulating layers of the second insulating layer 112, the side surface CVS of the cavity CV can include a plurality of side surfaces, such as a first side surface CVS1, a second side surface CVS2, and a third side surface CV3. Further, of the plurality of side surfaces CV1, CV2, and CV3, at least two side surfaces can have different inclination angles with respect to the bottom surface of the cavity CV. Hereinafter, a description will be made on the assumption that all of the plurality of side surfaces have different inclination angles with respect to the bottom surface of the cavity CV.

[0151] The inclination angle of the side surface CVS of the cavity CV can increase toward the lower side or the bottom surface. For example, the inclination angle θ1 of the first side surface CVS1 with respect to the bottom surface of the cavity can be smaller than the inclination angle θ2 of the second side surface CV2 with respect to the bottom surface of the cavity. Further, the inclination angle θ2 of the second side surface CV2 can be smaller than the inclination angle θ3 of the third side surface CV3.

[0152] With this configuration, it is possible to facilitate embedding of the resin portion MP (including the insulating layer) into the cavity CV. Further, by covering the insulating layer of the side wall of the cavity with the resin portion MP, it is also possible to improve the reliability of the structure.

[0153] In the modification example, as described above, the inclination angle of the first side surface CVS1 with respect to the bottom surface of the cavity can be smaller than the inclination angle of the third side surface CVS3 with respect to the bottom surface of the cavity. In addition, the inclination angle of the second side surface CVS2 with respect to the bottom surface of the cavity can be equal to the inclination angle of the first side surface CV1 or the inclination angle of the third side surface CV3.

[0154] Therefore, the width of the cavity CV can decrease toward the bottom surface of the cavity. In other words, the separation distance W1, W2, W3 between the vertically-overlapped second electrode portion 122 (or the second via electrode) and the side surface CVS of the cavity CV can increase.

[0155] For example, the separation distance W1 in the horizontal direction between the first side surface CVS1 and the second electrode portion 122 can increase toward the bottom surface of the cavity CV. The separation distance W2 in the horizontal direction between the second side surface CVS2 and the second electrode portion 122 can increase toward the bottom surface of the cavity CV. In addition, the separation distance W3 in the horizontal direction between the third side surface CVS3 and the second electrode portion 122 can increase toward the bottom surface of the cavity CV.

[0156] Further, the separation distance W1 in the horizontal direction between the first side surface CVS1 and the second electrode portion 122 can be smaller than or equal to the separation distance W2 in the horizontal direction between the second side surface CVS2 and the second electrode portion 122. In addition, the separation distance W2 in the horizontal direction between the second side surface CVS2 and the second electrode portion 122 can be smaller than or equal to the separation distance W3 in the horizontal direction between the third side surface CVS3 and the second electrode portion 122. In this way, the separation distance between the second electrode (or the second through electrode) and the side surface CVS of the cavity CV can gradually increase toward the bottom surface of the cavity CV or toward the lower insulating layer. Therefore, it is possible to prevent damage to the second electrode portion (or the second via electrode) during cavity formation, and it is possible to more precisely and accurately adjust or form the mounting position or the buried position of the chip SD in the cavity. In other words, it is possible to improve the precision and accuracy of the embedding position.

[0157] The above description can also be applied to the circuit board according to other embodiments.

[0158] Figure 14 is a cross-sectional view illustrating a semiconductor package according to a first embodiment.

[0159] Reference Figure 14In this case, the semiconductor package can have a structure in which the second circuit board 700 is directly bonded on the circuit board. For example, in an embodiment, the pad specification of the second circuit board 700 corresponds to the pad specification of the first circuit board, and thus, an additional circuit board (hereinafter, referred to as "second circuit board 700") can be directly connected or bonded to the circuit board (used interchangeably with "first circuit board") according to the various embodiments described above. To this end, the second circuit board 700 can include a plurality of insulating layers. The second circuit board 700 can include at least one insulating layer 710.

[0160] Further, the second circuit board 700 can include circuit pattern layers 720, 730 disposed on a surface of the at least one insulating layer 710. The circuit pattern layers 720, 730 of the second circuit board 700 can electrically connect the chip SD mounted on the first circuit board and the memory chip 740 mounted on the second circuit board 700.

[0161] Meanwhile, a cavity can or can not exist in the second circuit board 700. In this regard, the above description can be applied in the same manner.

[0162] Meanwhile, the insulating layer 710 of the second circuit board 700 can include a prepreg or the like. Further, the insulating layer of the second circuit board 700 can be formed of various insulating materials.

[0163] In addition, a semiconductor device (for example, a memory chip) 740 can be attached on the insulating layer 710 of the second circuit board 700. In this case, an adhesive layer (not shown) can be additionally disposed between the insulating layer 710 and the semiconductor device 740.

[0164] Meanwhile, the semiconductor device 740 can include a connection member 750 electrically connecting a terminal 745 of the semiconductor device 740 and the circuit pattern layers 720, 730. The connection member 750 can be a lead, but the present application is not limited thereto.

[0165] Meanwhile, the semiconductor package can include a conductive bonding member (not shown) located in an opening or a hole of the outermost insulating layer of the first circuit board.

[0166] In this case, the conductive bonding member (not shown) can be a solder ball, but is not limited thereto. In an embodiment, the uppermost end of the conductive bonding member (not shown) can be higher than the uppermost end of the semiconductor device SD. With this configuration, damage to the circuit board can be prevented. Further, a space for additionally disposing a package substrate or a circuit board upward can be easily secured.

[0167] Further, an embodiment can include an additional conductive bonding member disposed in an opening of the protective layer or the second insulating layer. The additional conductive bonding member can be used to bond the semiconductor package to a main board (or a motherboard) of an external device.

[0168] Figure 15 is a cross-sectional view illustrating a semiconductor package according to a second embodiment.

[0169] The above description of the semiconductor package can be equally applied to the semiconductor package according to the second embodiment. However, the conductive bonding member (not shown) can be located on the third insulating layer or provided on the protective layer disposed on the third insulating layer. That is, the second circuit board 700 can be located on the third insulating layer. Accordingly, a space for electrical connection between the third insulating layer and the second circuit board 700 can be improved.

[0170] Meanwhile, when the circuit board having the above-described features of the present application is used for an IT device or a home appliance such as a smart phone, a server computer, a TV, etc., a function such as signal transmission or power supply can be stably performed. For example, when the circuit board having the features of the present application performs a semiconductor packaging function, it can be used to safely protect a semiconductor chip from external moisture or contaminants, or can solve a problem of a leakage current, an electrical short between terminals, and an electrical disconnection of a terminal provided to the semiconductor chip. In addition, when a function of signal transmission is in use, a noise problem can be solved. Thereby, the circuit board having the above-described features of the present application can maintain a stable function of the IT device or the home appliance, so that the entire product and the circuit board to which the present application is applied can achieve functional consistency or technical interlocking with each other.

[0171] When the circuit board having the above-described features of the present application is used for a transportation device such as a vehicle, a problem of signal distortion transmitted to the transportation device can be solved, or safety of the transportation device can be further improved by safely protecting a semiconductor chip controlling the transportation device from external influences and solving a problem of a leakage current or an electrical short between terminals or an electrical disconnection of a terminal provided to the semiconductor chip. Accordingly, the transportation device and the circuit board to which the present application is applied can achieve functional integrity or technical interlocking with each other.

[0172] The features, structures, effects, etc. described in the above-described embodiments are included in at least one embodiment, and are not necessarily limited to only one embodiment. In addition, the features, structures, effects, etc. shown in each embodiment can be combined or modified by those of ordinary skill in the art to which the embodiments belong for other embodiments. Accordingly, what is related to such combination and modification should be interpreted as included in the scope of the embodiments.

[0173] While the embodiments have been described above, it is to be understood that they have been presented by way of example only, and are not intended to limit the scope of the disclosure, and that various modifications and changes can be implemented by persons skilled in the art without departing from the essential features of the embodiments. For example, each component specifically shown in the embodiments can be implemented by modification. Furthermore, it should be understood that differences related to these modifications and applications are included in the scope of the embodiments defined in the appended claims.

Claims

1. A circuit board comprising: a first insulating layer; a first circuit pattern layer disposed on the first insulating layer; a second insulating layer disposed on the first insulating layer and the first circuit pattern layer and including a cavity; a second circuit pattern layer disposed on the second insulating layer; a semiconductor device disposed in the cavity; and a resin portion disposed in the cavity and configured to surround the semiconductor device, wherein an upper surface of the resin portion and an upper surface of the second insulating layer form a stepped portion.

2. The circuit board according to claim 1, comprising a filling member disposed in the cavity and between the first insulating layer and a connecting portion of the semiconductor device. The filling member has a width that gradually increases from the semiconductor device toward the first insulating layer.

3. The circuit board of claim 2, wherein, 4. The circuit board according to claim 1, comprising a connecting portion disposed between the semiconductor device and the first insulating layer.

5. The circuit board according to claim 1, comprising the resin portion configured to surround the semiconductor device in the cavity. The resin portion is in contact with a side surface or a bottom surface of the cavity.

6. The circuit board of claim 5, wherein, The second insulating layer includes an edge portion located outside the cavity.

7. The circuit board of claim 5, wherein, A height from the bottom surface of the cavity to an upper surface of the edge portion is different from a height from the bottom surface of the cavity to an upper surface of the resin portion.

8. The circuit board of claim 7, wherein, 9. The circuit board according to claim 5, comprising: a third insulating layer disposed on the second insulating layer and the second circuit pattern layer; and a third circuit pattern layer disposed on the third insulating layer.

10. The circuit board according to claim 9, comprising a heat dissipation member disposed on the semiconductor device, an upper surface of the heat dissipation member is located above an upper surface of an edge portion, a lower surface of the third insulating layer is in contact with an upper surface of the resin portion, wherein the resin portion is disposed between the third insulating layer and the semiconductor device. ​ ​

Images