Negative temperature compensation type dielectric ceramic chip capacitor material and preparation method and application thereof

Abstract

The invention discloses a negative temperature compensation type dielectric ceramic chip capacitor material and a preparation method and application thereof, and relates to the technical field of ceramic materials, the ceramic chip capacitor material comprises a material prepared from a principal crystalline phase, a modifier and a sintering aid, the principal crystalline phase comprises a composite system of SrTiO3, CaTiO3 and BaTiO3, and the modifier is a composite system of SrTiO3, CaTiO3 and BaTiO3. The structural formula of the composite system is Sr (1-x-y) CaxBayTiO3, x is more than 0.05 and less than 0.2, and y is more than 0 and less than 0.23. BaTiO3 with a high dielectric constant is added into a composite system SrTiO3 and CaTiO3 for compounding to form a SrTiO3-CaTiO3-BaTiO3 ternary composite system, and the dielectric constant and the capacitance temperature coefficient are adjusted by adjusting the ratio of Sr / Ca / Ba, so that the dielectric ceramic material for the high-dielectric chip capacitor with the dielectric constant of 1000 + / -100, the dielectric loss of less than 22 * 10 <-4 > and the capacitance temperature coefficient of (-3300 + / -500) ppm / DEG C is obtained.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of ceramic materials, in particular to a negative temperature compensation type dielectric ceramic chip capacitor material, a preparation method and application thereof. BACKGROUND

[0002] The negative temperature compensation type dielectric ceramic material is a functional ceramic with a negative dielectric constant temperature coefficient, and the dielectric constant thereof decreases with the increase of temperature and changes linearly. The capacitor prepared from this ceramic material is mainly used in high-frequency circuits, oscillation circuits or filter circuits to compensate for the positive temperature coefficient elements, so as to maintain the stability of the system frequency. The main application scenarios are filter and resonance circuit in 5G base station and satellite communication, compensation of temperature compensation crystal oscillator and constant temperature crystal oscillator, temperature sensitive circuit lamp of generator control unit in automobile electronics and radar system.

[0003] With the continuous development of 5G communication and high-frequency electronic equipment, new energy vehicles and automobile electronics, aerospace, industrial automation and consumer electronics, the demand for negative temperature compensation capacitors has increased significantly in recent years. The main advantages of this type of capacitor are: 1) high temperature stability, which can accurately compensate for the temperature drift of other components in the circuit, thereby maintaining the stability of the overall circuit performance; 2) excellent high-frequency performance, with low dielectric loss, suitable for high-frequency applications; 3) improving circuit reliability, this type of dielectric material remains linear within -55℃~125℃, avoiding circuit failure caused by temperature fluctuations, suitable for harsh conditions such as automobile electronics and aerospace; 4) simplifying circuit design, directly compensating for temperature effects through the negative temperature characteristics of the capacitor, reducing the complexity of additional temperature compensation circuits, reducing cost and PCB space occupation; 5) good long-term stability, compared with ordinary capacitors (such as X7R / Y5V), the negative temperature compensation capacitor has less aging, suitable for devices that need to work stably for a long time; 6) precise matching requirements, different negative temperature characteristics of capacitors (such as -33ppm / ℃, -750ppm / ℃, -1500ppm / ℃, -3300ppm / ℃, etc.) can be selected to flexibly match the temperature compensation requirements of different circuits, realizing precise design. The typical ceramic systems of this type of dielectric ceramic material are SrTiO3 system, CaTiO3 system, MgTiO3-CaTiO3 system, etc. The dielectric constant and capacity temperature coefficient are different, and the main crystal phase system is different.

[0004] The current negative temperature compensation type dielectric ceramic material (such as C0G / NP0 ceramic material) usually has a small dielectric constant, which is difficult to meet the demand of large capacity and small size. Replacing it with X7R, Y5V dielectric material will sacrifice its stability, and different compensation lines require different temperature characteristics. Therefore, the preparation of a negative temperature capacitor temperature coefficient dielectric ceramic material with a large dielectric constant not only meets the demand of small size and large capacity, but also has high stability at high frequency, which can meet the use in high-frequency circuits.

[0005] In view of this, the present application is proposed. SUMMARY

[0006] The present application aims to provide a negative temperature compensation type dielectric ceramic chip capacitor material, a preparation method and application thereof, which solves the problem that the negative temperature compensation type dielectric ceramic material cannot have a large dielectric constant by adding a high dielectric constant SrTiO3 to a composite system of SrTiO3 and CaTiO3.

[0007] Firstly, the present application provides a negative temperature compensation type dielectric ceramic chip capacitor material, which comprises a material prepared from a main crystal phase, a modifier and a sintering aid, wherein the main crystal phase comprises a composite system of SrTiO3, CaTiO3 and BaTiO3, and the structural formula of the composite system is Sr 1-x-y Ca x Ba y TiO3, wherein 0.05 < x < 0.2 and 0 < y < 0.23.

[0008] SrTiO3 and CaTiO3 are typical negative temperature compensation type dielectric materials, wherein the dielectric constant of SrTiO3 is about 250, the capacitance temperature coefficient is about -3000 ppm / ℃, and the dielectric loss is (2~4)×10 -4 -4)×10 -4 By compounding SrTiO3 and CaTiO3 in a certain proportion, the dielectric constant and the capacitance temperature coefficient can be adjusted, but the dielectric constant of the compound of the two is less than 250. Therefore, the present application selects BaTiO3 with a dielectric constant of 2000 to form a SrTiO3-CaTiO3-BaTiO3 ternary composite system, and adjusts the dielectric constant and the capacitance temperature coefficient by adjusting the proportion of Sr / Ca / Ba.

[0009] As an optional implementation, the modifier comprises one or a combination of Bi2O3, MnCO3, Nb2O5, ZrO2 and CeO2, and the sintering aid comprises at least one of SiO2 and ZnO.

[0010] As an optional implementation, the proportion of the modifier and the sintering aid is as follows: 8.00wt%~14wt%Bi2O3, 0wt%~0.3wt%MnCO3, 0wt%~0.8wt%Nb2O5, 0.1wt%~1.2wt%ZrO2, 0wt%~0.4wt%CeO2, 0.1wt%~0.5wt%SiO2, 0wt%~0.2wt%ZnO.

[0011] Secondly, the embodiment of the present application provides a preparation method of the negative temperature compensation type dielectric ceramic chip capacitor material, comprising the following steps: S1: sequentially performing first ball milling, drying, calcining and second ball milling on raw materials to obtain a ceramic material; S2: adding the ceramic material into paraffin for granulation, using a hydraulic press to press into a round sheet, then discharging the paraffin and then sintering to obtain a dielectric material.

[0012] As an optional implementation, the parameters of the first ball milling in step S1 include material: ball: water = 1: (4~6): (1.5~2.5), and the ball milling time is (5~8) h.

[0013] As an optional implementation, the parameters of the second ball milling in step S1 include material: ball: water = 1: (4~6): (1~1.5), the ball milling time is (35~40) h, the drying temperature in step S1 is (120~170) ℃, and the calcining temperature is (1100±20) ℃.

[0014] As an optional implementation, the amount of paraffin added in step S2 is (7~8) wt%, and the discharging of the paraffin includes discharging the paraffin at a speed of (1.5~2.5) ℃ / min to (450~550) ℃.

[0015] As an optional implementation, the sintering in step S2 includes increasing the temperature to (1220±20) ℃ at a speed of (2.5~3.5) ℃ / min, and sintering for (2~4) h.

[0016] Finally, the embodiment of the present application also provides an application of the negative temperature compensation type dielectric ceramic chip capacitor material, and the dielectric material is prepared into a chip capacitor.

[0017] As an optional implementation, the preparation includes sintering, and the sintering temperature is (1150~1250) ℃.

[0018] Compared with the prior art, the embodiment of the present application has the following advantages and beneficial effects: 1. In this embodiment, BaTiO3 with a high dielectric constant is added to the composite system of SrTiO3 and CaTiO3 to form a ternary composite system of SrTiO3-CaTiO3-BaTiO3. The dielectric constant and temperature coefficient of capacitance are adjusted by regulating the ratio of Sr / Ca / Ba, resulting in a dielectric constant of 1000±100 and a dielectric loss of <22×10⁻⁶. -4 High dielectric ceramic material for chip capacitors with a capacitance temperature coefficient of (-3300±500)ppm / ℃.

[0019] 2. In this embodiment of the invention, Bi₂O₃ is added to replace the Sr site in the ternary composite system, utilizing Bi₂O₃... 3+ The dielectric constant is improved by the larger ionic displacement polarization ability of the ions and the lattice distortion caused by the difference in valence and ionic radius. In addition, the addition of Bi can also reduce the sintering temperature.

[0020] 3. In this embodiment of the invention, the addition of doped and modified materials Nb2O5, ZrO2, MnCO3, and CeO2 refines the grains, homogenizes the microstructure, and improves the density of the ceramic body. This reduces grain boundaries, lattice defects, and pores, thereby reducing dielectric loss and improving insulation performance. The addition of SiO2 and ZnO as sintering aids forms a low-melting-point liquid phase during sintering. The liquid phase diffusion accelerates mass transfer, thereby lowering the sintering temperature. Simultaneously, the liquid phase fills the grain gaps, driving capillary forces to rearrange the particles, thus reducing pores. Furthermore, the liquid phase encapsulates the grains, inhibiting grain growth and refining the grains. This ensures low dielectric loss and high insulation resistance, ultimately resulting in a dielectric ceramic material with a dielectric constant of 1000±100 at high frequencies and a capacitance temperature characteristic of (-3300±500) ppm / ℃, meeting the 1DL characteristics in GB / T 5596. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 SEM image of the dielectric material prepared in Example 6; Figure 2 This is an external view of the chip capacitor prepared in Example 6. Detailed Implementation

[0023] In order to make the objects, technical solutions, and advantages of the embodiments of the present application clearer, the following will be combined with the accompanying drawings of the embodiments of the present application to make a clear and complete description of the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the accompanying drawings can be arranged and designed in various different configurations.

[0024] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative labor are within the scope of protection of the present application.

[0025] It should be noted that: similar reference numerals and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0026] In the description of the present application, it should be noted that the terms "first", "second", "third", and the like are only used to distinguish description, and cannot be understood as indicating or implying relative importance. Embodiments

[0027] The embodiments of the present application provide a preparation method of a negative temperature compensation type dielectric ceramic chip capacitor material, comprising the following contents: I. Preparation of raw materials (1) main crystal phase raw materials: SrTiO3, CaTiO3, BaTiO3, prepared according to stoichiometric ratio, to ensure the formation of Sr 1-x- y Ca x Ba y TiO3 (wherein 0.05 < x < 0.2, 0 < y < 0.23).

[0028] (2) modifier: Bi2O3: 8.00 wt%~14wt%; MnCO3: 0wt% ~0.3 wt%; Nb2O5: 0 wt%~0.8 wt%; ZrO2: 0.1wt%~1.2 wt%; CeO2: 0wt%~0.4 wt%; (3) sintering aid: SiO2: 0.1wt% ~0.5 wt%; ZnO: 0wt% ~0.2 wt%; (4) Other auxiliary materials: Ball for ball milling (material: zirconium oxide) Paraffin wax.

[0029] II. Vibration mixing (1) The main crystal phase material, modifier, sintering aid, ball for ball milling, and water are weighed according to the ratio of material:ball:water = 1:(4-6):(1.5-2.5); (2) The above-mentioned materials and ball for ball milling are placed in a vibration ball mill, and the vibration ball mill is turned on. The mixing time is (5-8) h, and the materials are fully mixed and uniformly distributed.

[0030] (3) After mixing, the mixed material is taken out and placed in a drying oven to dry at a temperature of (120-170) °C to remove water, obtaining dry mixed material powder.

[0031] III. Calcination (1) The dried mixed material powder is placed in a crucible and placed in a muffle furnace for calcination.

[0032] (2) The calcination temperature is set to (1100±20) °C, and the heating rate is about 5 °C / min. When the temperature reaches the set value, the material is kept at high temperature for (2-4) h to form the required crystal phase structure through solid-phase reaction.

[0033] (3) After calcination, the muffle furnace is turned off, and the calcined material is taken out after natural cooling to room temperature.

[0034] IV. Vibration ball milling (1) The calcined material, ball for ball milling, and water are placed in a vibration ball mill according to the ratio of material:ball:water = 1:(4-6):(1-1.5).

[0035] (2) The vibration ball mill is turned on, and the ball milling time is (35-40) h to further refine the material particles, improve the uniformity and activity of the material, and make the material reach the required particle size distribution. (3) After ball milling, the material is taken out and filtered to remove the ball for ball milling, obtaining the ball-milled slurry.

[0036] V. Granulation and molding (1) The ball-milled slurry is dried to obtain dry powder; (2) Paraffin wax is weighed according to a proportion of (7-8) wt%, and added to the dry powder for granulation, so that the powder particles are coated with a layer of paraffin wax, which is convenient for subsequent molding operation; (3) The granulated powder is pressed into a round sheet using a hydraulic machine. According to the size and shape requirements of the required round sheet capacitor, the appropriate pressure and mold are set to ensure that the molded round sheet has good shape and size accuracy.

[0037] Six. Wax removal and sintering (1) Put the formed disc into the sintering furnace, and heat at a speed of (1.5-2.5) ℃ / min to (450-550) ℃, keep the temperature for a period of time, so that the paraffin is fully removed, and the paraffin does not produce adverse effects in the subsequent high-temperature sintering process; (2) After the wax removal is completed, continue to heat at a speed of (2.5-3.5) ℃ / min to (1220±20) ℃, and sinter at the temperature, the sintering time is (2-4) hours, so that the disc is densified at high temperature to form a dense ceramic structure, and the required medium material test sample is obtained.

[0038] Example 1: The present application provides a preparation method of a negative temperature compensation type dielectric ceramic chip capacitor material, which comprises the following contents: I. Raw material preparation (1) Main crystal phase raw material: SrTiO3, CaTiO3, BaTiO3, prepared according to the stoichiometric ratio, to ensure the formation of Sr 0.92 Ca 0.08 Ba 0.03 TiO3 (wherein x=0.08, y=0.03), the content of the main crystal phase is 87.61wt%.

[0039] (2) Modifier: Bi2O3: 13.37 wt%; MnCO3: 0 wt%; Nb2O5: 0wt%; ZrO2: 0.17wt%; CeO2: 0 wt%; (3) Sintering aid: SiO2: 0.12 wt%; ZnO: 0.10 wt%; (4) Other auxiliary raw materials: ball milling ball (material: zirconium oxide) paraffin.

[0040] II. Vibration mixing (1) The main crystal phase raw material, modifier, sintering aid, ball milling ball and water are weighed according to the ratio of 1:5:2; (2) Put the above raw materials and ball milling balls into the vibration ball mill, start the vibration ball mill, and mix for 7h to ensure that the raw materials are fully mixed and uniform.

[0041] (3) After the mixing is completed, the mixture is taken out and placed in a drying oven to dry at a temperature of (120-170) °C to remove moisture, to obtain dry mixture powder.

[0042] III. Calcination (1) The dry mixture powder after drying is placed in a crucible and placed in a box-type resistance furnace for calcination.

[0043] (2) The calcination temperature is set to 1100 °C, and the heating rate is about 5 °C / min. When the temperature reaches the set value, keep it for 3 hours, so that the raw materials undergo solid-phase reaction at high temperature to form the required crystal phase structure.

[0044] (3) After calcination is completed, it is naturally cooled to room temperature, and the calcined material is taken out.

[0045] IV. Vibratory ball milling (1) The calcined material, ball milling balls, and water are placed in a vibratory ball mill in a ratio of material:ball:water = 1:5:1.2.

[0046] (2) Turn on the vibratory ball mill, and the ball milling time is 37 h, to further refine the material particles, improve the uniformity and activity of the material, and make the material reach the required particle size distribution. (3) After ball milling is completed, the material is taken out and filtered to remove the ball milling balls, to obtain the ball-milled slurry.

[0047] V. Granulation and molding (1) The ball-milled slurry is dried to obtain dry powder. (2) Paraffin is weighed according to a proportion of 7.5 wt%, and added to the dry powder for granulation, so that the powder particles are wrapped with a layer of paraffin, to facilitate subsequent molding operation. (3) The granulated powder is pressed into a round sheet using a hydraulic machine, and appropriate pressure and mold are set according to the size and shape requirements of the required round sheet capacitor, to ensure that the molded round sheet has good shape and size precision.

[0048] VI. Paraffin removal and sintering (1) The molded round sheet is placed in a sintering furnace, and heated to 500 °C at a rate of 2 °C / min, and kept at this temperature for a period of time to allow the paraffin to be fully removed, to avoid adverse effects of paraffin in the subsequent high-temperature sintering process. (2) After paraffin removal is completed, continue to heat to 1220 °C at a rate of 3 °C / min, and sinter at this temperature for 3 hours, so that the round sheet undergoes densification reaction at high temperature to form a dense ceramic structure, to obtain the required dielectric material test sample.

[0049] The process steps of other embodiments and comparative examples are the same as those of Example 1, only the formulations are different, see Table 1 below for details: Table 1 List of medium ceramic material formulations

[0050] Test: The medium material test samples prepared in Examples 1-10 and Comparative Examples 1-4 above were tested for dielectric constant and dielectric loss using an impedance analyzer, and the capacitance temperature coefficient was tested using a high-low temperature chamber, and the insulation resistance and insulation strength of the product were tested using an insulation resistance meter and a voltage resistance meter. The test frequency of the dielectric constant, dielectric loss, and capacitance temperature coefficient was 1 MHz. The test results are shown in Table 2 below: Table 2 List of medium ceramic material properties

[0051] Figure 1 The SEM picture of the medium material test sample prepared in Example 6 is shown in Figure 1. Figure 1 As can be seen, the ceramic grains are oval in shape, the grains are small, and the compactness is good. Referring to Table 2, the comprehensive performance of Example 6 is better.

[0052] Among them, it can be known from the comparison between Comparative Example 1 and Examples 1-10 that when BaTiO3 is not added to the main crystal phase, the dielectric constant of the material is smaller (<800), and due to the high dielectric constant of BaTiO3, the dielectric constant of the system is improved.

[0053] It can be known from the comparison between Comparative Example 2 and Examples 1-10 that after the addition of Nb2O5, the capacitance temperature coefficient of the crystal is reduced, which is because Nb 5+ acts as a donor ion doping and replaces Ti 4+ ions, introducing free electrons and titanium ion vacancies. These defects form random pinning centers, destroying the long-range cooperative polarization of Ti 4+ ions, thereby suppressing the paraelectric behavior of the Sr 1-x-y Ca x Ba y TiO3 system and turning it to a relaxor transition, "flattening" the dielectric constant-temperature curve, thereby achieving the effect of reducing the capacitance temperature coefficient.

[0054] It can be known from the comparison between Comparative Example 3 and Examples 1-10 that when x is greater than 0.2, the dielectric constant, dielectric loss, and dielectric constant are all reduced, which is because the dielectric constant of CaTiO3 is 140-150, the capacitance temperature coefficient is about -1500 ppm / ℃, and the dielectric loss is (2-4) ×10 -4 Therefore, the greater the content, the smaller the dielectric constant, and therefore 0.05 < x < 0.2 is more appropriate.

[0055] From the comparison of Comparative Example 4 and Example 1-10, when y is greater than 0.23, the dielectric constant increases significantly, and the capacity temperature coefficient also increases significantly, because BaTiO3 is a typical type II porcelain with high dielectric characteristics, so the greater the content, the greater the dielectric constant, but it has a clear Curie peak, and the change rate is large, which will also lead to the increase of the capacity temperature coefficient, so 0 < y < 0.23 is more optimal.

[0056] From the comparison of Example 9 and Example 6, when the amount of doped Bi2O3 is too small, the dielectric constant decreases, and the capacity temperature coefficient increases, because Bi 3+ ions have a high ion polarizability, and after being doped, they can improve the polarizability of the crystal, thereby increasing the dielectric constant, and at the same time, Bi 3+ and Sr / Ca / Ba are heterovalent substitutions, which introduce effective positive charges in the crystal lattice, and to compensate for these positive charges, oxygen vacancies and other defects are generated, on the one hand, defect dipole pairs are formed and migrate and rearrange under alternating electric field, forming space charge polarization to increase the dielectric constant, on the other hand, these random charge centers and the difference in ion size produce a strong random field in the crystal lattice, leading to the formation of polar nanodomains, and because the phase transition temperature of the polar nanodomains is dispersedly distributed, the dependence of the dielectric constant on temperature is reduced, achieving the effect of reducing the capacity temperature coefficient, so the amount of doped Bi2O3 needs to be more than 8.00wt% for better results.

[0057] From the comparison of Example 10 and Example 6, when the amount of doped Bi2O3 is too large, charge compensation and Bi 3+ ions together lead to a sharp increase in oxygen vacancies, thereby significantly increasing the dielectric loss, so the amount of doped Bi2O3 needs to be less than 14.00wt% for better results.

[0058] The dielectric material test sample prepared in Example 6 is used to prepare a chip capacitor, which specifically includes the following contents: (1) batching: according to the design requirements of the chip capacitor, an appropriate amount of the prepared dielectric material powder and other possible additives are weighed and batched.

[0059] (2) film rolling: the prepared raw materials are placed into a film rolling machine, and the raw materials are prepared into a film with a certain thickness and uniformity through the film rolling process. The thickness of the film is accurately controlled according to the capacitance value and other parameters of the chip capacitor.

[0060] (3) slicing: the rolled film is cut into square green sheets according to the size requirements.

[0061] (4) sintering: the cut green sheets are placed into a sintering furnace and sintered at a temperature of (1150-1250) ℃ to further densify the green sheets and form a stable ceramic structure.

[0062] (5) Grinding: the sintered substrate may have a certain size deviation and surface roughness, and needs to be ground to achieve the required size accuracy and surface quality requirements.

[0063] (6) Upper electrode: the upper electrode material is coated on the surface of the ground substrate by screen printing process, and the electrode of the chip capacitor is formed by silver burning process to ensure good electrical contact performance between the electrode and the ceramic substrate.

[0064] (7) Cutting: finally, the chip capacitor with the upper electrode is cut according to the actual needs to obtain a single chip capacitor product for subsequent packaging and testing.

[0065] The capacitor product is expanded to verify the volume, and the substrate green body is prepared by film rolling process, then sintered into porcelain at 1200℃, ground into 0.14mm thickness, prepared electrode, and cut into 0.50mm*2.90mm chip capacitors (as shown in Figure 2 ), randomly selected 10 to test capacitance, loss angle, capacitance temperature coefficient, insulation resistance and breakdown voltage, and the test results are shown in Table 3 below: Table 3 Chip dielectric electrical properties

[0066] As Figure 2 can be seen from the chip capacitor appearance diagram, the electrode is uniform and has no leakage, and as can be seen from Table 3, the chip capacitor prepared by the embodiment of the application meets the characteristics of high dielectric constant 1000±100, low dielectric loss (<22×10 -4 ), and capacitance temperature coefficient (-3300±500) ppm / ℃, which is beneficial to the development of such capacitors and the localization of porcelain materials.

[0067] The above only describes the preferred embodiments of the application and is not used to limit the application. For those skilled in the art, the application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the application shall be included in the protection scope of the application. It should be noted that the structures or components illustrated in the drawings are not necessarily drawn to scale, and the application omits the description of known components and processing technologies and processes to avoid unnecessary limitation of the application.

Claims

1. A material for a negative temperature coefficient type dielectric ceramic chip capacitor, characterized by, A material prepared from a host crystal phase, a modifier, and a sintering aid, the host crystal phase comprising a composite system of SrTiO3, CaTiO3, and BaTiO3, the composite system having a formula of Sr 1-x-y Ca x Ba y TiO3, where 0.05 < x < 0.2, 0 < y < 0.

23.

2. The material of negative temperature coefficient of capacitance of claim 1, wherein, The modifier includes one or a combination of Bi2O3, MnCO3, Nb2O5, ZrO2 and CeO2, and the sintering aid includes at least one of SiO2 and ZnO.

3. The negative temperature compensated dielectric ceramic chip capacitor material according to claim 2, characterized in that, The proportions of the modifier and the sintering aid are as follows: 8.00wt%~14wt% Bi2O3, 0wt%~0.3wt% MnCO3, 0wt%~0.8wt% Nb2O5, 0.1wt%~1.2wt% ZrO2, 0wt%~0.4wt% CeO2, 0.1wt%~0.5wt% SiO2, 0wt%~0.2wt% ZnO.

4. A method of producing the negative temperature compensating dielectric ceramic chip capacitor material according to any one of claims 1 to 3, characterized by, The method includes the following steps: S1: sequentially performing first ball milling, drying, calcination and second ball milling on raw materials to obtain a porcelain material; S2: adding the porcelain material to paraffin for granulation, using a hydraulic press to press into a round sheet, then discharging the paraffin and sintering to obtain a dielectric material.

5. The method of claim 4, wherein the method further comprises the step of: The parameters of the first ball milling in step S1 include material: ball: water = 1: (4~6): (1.5~2.5), and the ball milling time is (5~8) h. ​ 6. The method of claim 5, wherein the method further comprises the step of: The parameters of the second ball milling in step S1 include material: ball: water = 1: (4~6): (1~1.5), the ball milling time is (35~40) h, the drying temperature in step S1 is (120~170) ℃, and the calcination temperature is (1100±20) ℃. ​ 7. The method of claim 4, wherein the method further comprises the step of: The amount of paraffin added in step S2 is (7~8) wt%, and the paraffin discharging includes increasing the temperature to (450~550) ℃ at a speed of (1.5~2.5) ℃ / min to discharge the paraffin. ​ 8. The method of claim 7, wherein the method further comprises the step of: The sintering in step S2 includes increasing the temperature to (1220±20) ℃ at a speed of (2.5~3.5) ℃ / min, and sintering for (2~4) h. ​ 9. Use of a material for negative temperature coefficient chip capacitors according to any one of claims 1 to 3, characterized in that The dielectric material is prepared into a chip capacitor.

10. The use of a negative temperature coefficient of capacitance material according to claim 9, wherein The preparation includes sintering, and the sintering temperature is (1150~1250) ℃.

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