VF-TLP test system for semiconductor devices and calibration method thereof

Abstract

The application relates to the technical field of semiconductors, and provides a VF-TLP test system for a semiconductor device and a calibration method thereof. The system comprises a VF-TLP tester, a test probe and a VF-TLP test board. The VF-TLP test board comprises a device bearing area and a lead connection area, the device bearing area is used for bearing a semiconductor device to be tested, and target pins of the semiconductor device to be tested can be connected to the lead connection area. One end of the test probe is connected to the VF-TLP tester, and the other end is connected to the lead connection area. The first position of the target pins connected to the lead connection area is the same as the second position of the other end of the test probe connected to the lead connection area. The application can not only guarantee the accuracy and reliability of test results, but also enable test probes with one pitch to be compatible with semiconductor devices with different pitches to perform VF-TLP tests under extremely narrow pulse widths.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a VF-TLP test system of a semiconductor device and a calibration method thereof. BACKGROUND

[0002] In a VF-TLP (Very Fast Transmission Line Pulse) test, since the pulse width of a test pulse is very narrow, as shown in a conventional test loop "VF-TLP tester 101→test probe 102→semiconductor device 103 (such as a chip) to be tested→test probe 102→VF-TLP tester 101", slight impedance in the test loop will have a very great impact on the test result, so the impedance requirement of the test loop is very high. The test probe is a key device that affects the impedance of the test loop, and a specially-made APT probe or a radio frequency probe is usually used. Figure 1

[0003] The test distance of the APT probe can be finely adjusted, and the APT probe can be compatible with more semiconductor devices with different pin pitches for VF-TLP testing. However, the test loop impedance is large when the APT probe is used under an extremely narrow pulse width (such as 1.25 ns), and it is difficult to ensure the accuracy and reliability of the test result. The test loop impedance is small when the radio frequency probe is used, and the accuracy and reliability of the test result under an extremely narrow pulse width (such as 1.25 ns) can be ensured. However, the radio frequency probe is very expensive, and the probe head pitch of the radio frequency probe is fixed, so the radio frequency probe cannot be compatible with semiconductor devices with different pin pitches for VF-TLP testing.

[0004] Therefore, how to ensure the accuracy and reliability of the VF-TLP test result of the semiconductor device and enable the test probe to be compatible with multiple semiconductor devices with different pin pitches for VF-TLP testing under an extremely narrow pulse width has become one of the technical problems to be solved at present. SUMMARY

[0005] Therefore, how to ensure the accuracy and reliability of the VF-TLP test result of the semiconductor device and enable the test probe to be compatible with multiple semiconductor devices with different pin pitches for VF-TLP testing under an extremely narrow pulse width has become one of the technical problems to be solved at present.

[0006] To achieve the above-mentioned application purposes, the technical solutions adopted by the present application are as follows:

[0007] In a first aspect, the embodiments of the present application provide a VF-TLP test system of a semiconductor device, comprising a VF-TLP tester, a test probe, and a VF-TLP test board.​

[0008] The VF-TLP test board comprises a device bearing area and a lead connection area, the device bearing area is used for bearing a semiconductor device to be tested, and target pins of the semiconductor device to be tested can be connected to the lead connection area;

[0009] One end of the test probe is connected to the VF-TLP tester, and the other end is connected to the lead connection area;

[0010] The first position at which the target pin is connected to the lead connection area is the same as the second position at which the other end of the test probe is connected to the lead connection area.

[0011] In a second aspect, the embodiments of the present application provide a VF-TLP test system calibration method of a semiconductor device, applied to the VF-TLP test system of the first aspect; the method comprises:

[0012] Open circuit calibration testing is performed on the VF-TLP test system to obtain a reflected voltage value, and loop impedance of the VF-TLP test system is corrected based on the reflected voltage value;

[0013] Short circuit calibration testing is performed on the VF-TLP test system to obtain a short circuit calibration result;

[0014] If the short circuit calibration result meets preset requirements, then the parasitic inductance and parasitic resistance of the VF-TLP test system are corrected based on the short circuit calibration result, and the calibration of the VF-TLP test system is completed.

[0015] Compared with the prior art, the technical scheme provided by the embodiments of the present application has at least the following beneficial effects: the VF-TLP test system provided by the embodiments of the present application comprises a VF-TLP tester, a test probe and a VF-TLP test board, wherein the VF-TLP test board comprises a device bearing area and a lead connection area, the device bearing area is used for bearing a semiconductor device to be tested, and target pins of the semiconductor device to be tested can be connected to the lead connection area; one end of the test probe is connected to the VF-TLP tester, and the other end is connected to the lead connection area; and the first position at which the target pin is connected to the lead connection area is the same as the second position at which the other end of the test probe is connected to the lead connection area. The VF-TLP test board can break through the limitation of different pin spacings of the semiconductor device to be tested, and realize indirect electrical connection between the semiconductor device to be tested and the test probe, so as to not only ensure the accuracy and reliability of the test result, but also enable the test probe to be compatible with multiple semiconductor devices with different pin spacings for VF-TLP testing under extremely narrow pulse width. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0017] Figure 1 is a schematic diagram of a traditional VF-TLP test circuit;

[0018] Figure 2 is a structural block diagram of a VF-TLP test system provided by the embodiments of the present application;

[0019] Figure 3 is a structural block diagram of a VF-TLP tester provided by the embodiments of the present application;

[0020] Figure 4 is a structural schematic diagram of a VF-TLP test board provided by the embodiments of the present application;

[0021] Figure 5 is a physical diagram of a VF-TLP test board provided by the embodiments of the present application;

[0022] Figure 6 is an enlarged view of a radio frequency probe under a high-power microscope provided by the embodiments of the present application;

[0023] Figure 7 is a schematic diagram of a connection mode of a radio frequency probe and a lead connection area of a VF-TLP test board provided by the embodiments of the present application;

[0024] Figure 8 is a schematic diagram of two adjacent pins in a semiconductor device to be tested;

[0025] Figure 9 is a schematic diagram of two non-adjacent pins in a semiconductor device to be tested;

[0026] Figure 10 is a schematic diagram of wire connection between a target pin and a lead connection area of a VF-TLP test board provided by the embodiments of the present application;

[0027] Figure 11 is a flowchart of a VF-TLP test system calibration method provided by the embodiments of the present application. DETAILED DESCRIPTION

[0028] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with embodiments. It should be understood that the specific embodiments described herein are only for explaining this application, but the implementation of this application is not limited thereto.

[0029] In VF-TLP testing of semiconductor devices (such as chips), the main method is to use a VF-TLP pulse generator to generate ultrafast transmission line pulses to simulate transient interference in a complex electromagnetic environment, thereby evaluating the electrostatic discharge (ESD) immunity and transient immunity of semiconductor devices, and verifying whether the key performance indicators (ESD and transient immunity) of semiconductor devices are qualified.

[0030] In VF-TLP testing of semiconductor devices, such as Figure 1 In the traditional test circuit shown, "VF-TLP tester 101 → test probe 102 → semiconductor device under test 103 (e.g., chip) → test probe 102 → VF-TLP tester 101", the test probe 102 and the semiconductor device under test 103 are directly electrically connected. The test probe is a key component affecting the impedance of this test circuit, and typically requires specialized APT probes or RF probes. While APT probes are compatible with a wider variety of semiconductor devices with different pin pitches for VF-TLP testing, they cannot avoid test result distortion due to high circuit impedance at extremely narrow pulse widths (e.g., 1.25ns). RF probes ensure accuracy and reliability of test results at extremely narrow pulse widths (e.g., 1.25ns), but they are very expensive and incompatible with semiconductor devices with different pin pitches for VF-TLP testing.

[0031] In view of this, embodiments of this application provide a VF-TLP test system and calibration method for semiconductor devices. The VF-TLP test system includes a VF-TLP test board. The VF-TLP test board can overcome the limitation of different pin pitches of the semiconductor device under test and realize indirect electrical connection between the pins of the semiconductor device under test and the test probe (RF probe). This not only ensures the accuracy and reliability of the test results, but also enables the test probe to be compatible with a variety of semiconductor devices with different pin pitches to perform VF-TLP testing under extremely narrow pulse widths.

[0032] Figure 2 This is a structural block diagram of a VF-TLP testing system provided in an embodiment of this application. Figure 3 This is a structural block diagram of a VF-TLP tester provided in an embodiment of this application. Figure 4 This is a schematic diagram of the structure of a VF-TLP test board provided in an embodiment of this application. Figure 5is a physical diagram of a VF-TLP test board provided by an embodiment of the present application.

[0033] Please refer to Figures 2-5 In a first aspect, the embodiment of the present application provides a VF-TLP test system. The VF-TLP test system provided by the embodiment of the present application comprises a VF-TLP tester 101, a test probe 102 and a VF-TLP test board 104. Wherein, the VF-TLP tester 101→ the test probe 102→ the VF-TLP test board 104→ the test probe 102→ the VF-TLP tester 101 forms a test loop.

[0034] The core function of the VF-TLP test system is to generate high-frequency transient pulses by the VF-TLP tester 101, and to act on the semiconductor device to be tested on the VF-TLP test board 104 through the test probe 102 and the VF-TLP test board 104, and then to capture the response signal of the semiconductor device to be tested through the VF-TLP tester 101, and to determine whether the semiconductor device to be tested meets the corresponding performance index requirements based on the response signal.

[0035] As an example, the VF-TLP tester 101 comprises a VF-TLP pulse generator 1011, a signal monitor 1012 and a display 1013. Wherein, the VF-TLP pulse generator 1011 is connected with the signal monitor 1012 and the display 1013 through electrical signals respectively.

[0036] The VF-TLP pulse generator 1011 is used to generate test pulse signals with adjustable parameters (such as voltage, current, pulse width or rising edge), and to accurately control the waveform of the test pulse signals, so as to support multiple test modes (HBM / CDM) and match different industry standards.

[0037] The signal monitor 1012, also known as an oscilloscope, is used to collect the test pulse signals output by the VF-TLP pulse generator 1011 and the response signals (such as electrical response signals representing abnormal device functions and breakdown) output by the semiconductor device to be tested, and to determine the performance index test results of the semiconductor device to be tested based on the collected response signals. For example, according to the response signal, it is determined whether the electrostatic discharge (ESD) capability and the transient immunity of the semiconductor device to be tested meet the relevant standard requirements, for example, according to the response signal, it is determined whether the withstand voltage of the semiconductor device to be tested meets the relevant standard requirements.

[0038] The display 1013 is used to generate a test report and output according to the performance index test results. The display 1013 supports users to set the relevant parameters of the VF-TLP test by customizing.

[0039] As an example, the VF-TLP test board 104 includes a device bearing area 1041 for bearing a semiconductor device under test, and a lead connection area 1042 to which target pins of the semiconductor device under test can be connected by wire bonding. The device bearing area 1041 is provided with a copper skin.

[0040] In some embodiments, the semiconductor device under test is configured to receive a test pulse simulating an actual disturbance and output a response signal (e.g., an electrical response signal characterizing abnormal function or breakdown of the device). The semiconductor device under test can be a die (an unpackaged chip cut from a wafer), a wafer, or a packaged chip. The specific type of the semiconductor device under test is not limited in the present application.

[0041] One end of the test probe 102 (not shown in the figure) is connected to the VF-TLP tester 101, and the other end (not shown in the figure, usually a probe head) is connected to the lead connection area 1042. The target pins are connected to the first position of the lead connection area 1042, and the other end of the test probe 102 is connected to the second position of the lead connection area 1042.

[0042] By connecting (e.g., plugging or abutting) the other end of the test probe 102 to the lead connection area 1042, the contact loss between the test probe and the lead connection area can be reduced, thereby achieving undistorted transmission of high-frequency pulses and avoiding interference from parasitic parameters.

[0043] As an example, the VF-TLP test board 104 can be a custom COB (Chip On Board) board, which can be connected to the target pins of the semiconductor device under test by wire bonding and can be used in conjunction with the test probe to achieve indirect electrical connection between the test probe and the semiconductor device under test, thereby breaking through the limitation of different pin pitches of the semiconductor device under test, allowing a test probe with one pitch to be compatible with multiple semiconductor devices with different pitches for VF-TLP testing at extremely narrow pulse widths, and reducing the procurement cost of the test probe.

[0044] The technical scheme provided by the embodiments of the present application can break through the limitation of different pin pitches of the semiconductor device under test and achieve indirect electrical connection between the semiconductor device under test and the test probe, which not only ensures the accuracy and reliability of the test results, but also allows the test probe to be compatible with multiple semiconductor devices with different pin pitches for VF-TLP testing at extremely narrow pulse widths, and reduces the procurement cost of the test probe.

[0045] In some embodiments, please continue to refer to Figure 4The lead connection area 1042 includes at least two connection points 10421, which are adjacently arranged or not adjacently arranged. The point spacing between the at least two connection points 10421 (the spacing between two adjacently arranged connection points, or the spacing between two not adjacently arranged connection points) is equal to the probe head spacing (such as the spacing between two probe heads) of the test probe 102. In this way, the stable connection of the test probe 102 and the connection points 10421 in the lead connection area 1042 can be ensured, and the impedance of the test loop can be reduced.

[0046] In some embodiments, the test probe is a radio frequency probe. For example, the radio frequency probe can be a radio frequency probe including two probe heads, and the structure type is G-S (ground-signal) or S-G (signal-ground), the signal end of the radio frequency probe of the structure type is adjacent to the ground end, and the needle spacing is usually 50-200 µm. The radio frequency probe can also be a radio frequency probe including three probe heads, and the structure type is G-S-G (ground-signal-ground) or S-G-S (signal-ground-signal), the signal end of the radio frequency probe of the structure type is in the middle, the ground ends are symmetrically distributed on both sides, or the double signal ends are symmetrically distributed, and the ground end is in the middle, and the needle spacing is usually 25-150 µm.

[0047] Figure 6 is an enlarged view of a radio frequency probe provided by an embodiment of the present application under a high-power microscope. Figure 6 The radio frequency probe in is a radio frequency probe of G-S (ground-signal) structure, including a probe head 1 and a probe head 2.

[0048] Figure 7 is a schematic diagram of a connection mode of a radio frequency probe and a lead connection area of a VF-TLP test board provided by an embodiment of the present application. As shown in Figure 7 , the probe head 1 and the probe head 2 of the radio frequency probe are in contact with two adjacently arranged connection points (pad1 and pad2) of the lead connection area, and the probe spacing between the probe head 1 and the probe head 2 is equal to the point spacing between the two adjacently arranged connection points (connection point 1 (pad1) and connection point 2 (pad2)) of the lead connection area.

[0049] In some embodiments, the connection points on the lead connection area 1042 are gold-plated points, which can reduce the impedance of the test loop.

[0050] In some embodiments, the device carrying area 1041 can be a grounded pad or a non-grounded pad. The device carrying area 1041 is used to carry a semiconductor device to be tested.

[0051] In some embodiments, please refer to Figure 4 and Figure 5The lead connection area 1042 is arranged at the peripheral area of the device bearing area 1041. Of course, the layout of the lead connection area 1042 and the device bearing area 1041 can also be other manners, and preferably, the layout of the lead connection area 1042 and the device bearing area 1041 is as close as possible, so that the bonding between the lead connection area 1042 and the device bearing area 1041 is as short as possible, thereby reducing interference.

[0052] In some embodiments, referring to Figure 8 , Figure 9 The target pins can be two adjacent pins (such as pins B and C as shown in Figure 8 ) or two non-adjacent pins (such as pins D and E as shown in Figure 9 ) on the semiconductor device 103 to be tested.

[0053] In some embodiments, referring to Figure 10 The target pins and the lead connection area 1042 of the VF-TLP test board 104 can be connected by gold wire bonding, which can reduce the impedance of the test loop.

[0054] Figure 11 is a flowchart of a VF-TLP test system calibration method provided by an embodiment of the present application. Referring to Figure 11 The VF-TLP test system calibration method provided by the embodiment of the present application is applied to the VF-TLP test system described above, and the method comprises the following steps:

[0055] S1101, open circuit calibration test is performed on the VF-TLP test system to obtain a reflected voltage value, and the loop impedance of the VF-TLP test system is corrected based on the reflected voltage value;

[0056] S1102, short circuit calibration test is performed on the VF-TLP test system to obtain a short circuit calibration result;

[0057] S1103, if the short circuit calibration result meets the preset requirement, the parasitic inductance and the parasitic resistance of the VF-TLP test system are corrected based on the short circuit calibration result, and the calibration of the VF-TLP test system is completed.

[0058] As an example, the short circuit calibration test of the VF-TLP test system comprises the following steps:

[0059] Step 1, preliminary preparation and device connection:

[0060] Test environment: operate in a shielded environment with a temperature of 23±2℃ and a humidity of 45%-65%.

[0061] Equipment list: VF-TLP pulse generator, RF probe (a pair of probe heads), VF-TLP test board, high-bandwidth oscilloscope (≥6GHz), voltage probe, current probe.

[0062] VF-TLP test system setup: First, set up the test loop. According to the "VF-TLP pulse generator → RF probe → VF-TLP test board → RF probe → VF-TLP pulse generator → display" setup, ensure that the contact pressure of the RF probe and the VF-TLP test board is stable. Then, connect the high-bandwidth oscilloscope (i.e. signal monitor). Connect the high-bandwidth oscilloscope (≥6GHz) to the VF-TLP pulse generator through the voltage probe and the current probe, and set the sampling rate of the high-bandwidth oscilloscope to 20GS / s or above.

[0063] Step 2, display adjustment of high-bandwidth oscilloscope (general settings, subsequent calibration reuse):

[0064] Channel settings: Set the voltage channel (CH1) attenuation ratio to 1:10, and turn off the bandwidth limit; set the current channel (CH2) to match the current probe range (e.g. 10A / V).

[0065] Time base adjustment: According to the pulse width (e.g. 1.25ns), set the time base to 1ns / div, to ensure complete display of the pulse rising edge (0.2ns), flat top and falling edge.

[0066] Trigger settings: Use the voltage channel as the trigger source, set the trigger level to 30% of the pulse peak value, and use single trigger mode to avoid signal jitter.

[0067] Waveform optimization: Turn on the oscilloscope averaging function (16 times average) to reduce noise; adjust the vertical gain so that the waveform occupies 2 / 3 of the screen height, making it easier to read.

[0068] Step 3, open circuit calibration test:

[0069] Open circuit connection: Connect the probe head 1 and the probe head 2 of the RF probe to the connection point 1 (pad1) and the connection point 2 (pad2) in the first position of the lead connection area 1042 of the VF-TLP test board 104, respectively, and connect the wire 1 and the wire 2 to the connection point 1 (pad1) and the connection point 2 (pad2), respectively. The wire 1 and the wire 2 are suspended (open circuit).

[0070] Pulse settings: Set the output parameters of the VF-TLP pulse generator to pulse width 10ns, rising edge 0.2ns, voltage 10V, and output single pulse.

[0071] Waveform verification: Observe the voltage channel (CH1) without obvious current and the current channel (CH2) close to 0A through the oscilloscope, and the voltage spike caused by parasitic capacitance is ≤2%; record the reflected voltage value, and correct the loop impedance of the VF-TLP test system based on the reflected voltage value. The loop impedance here includes the impedance of the VF-TLP pulse generator, the oscilloscope, the test probe itself, and the impedance of the test loop. Correcting the loop impedance of the VF-TLP test system based on the reflected voltage value is the parameter matching process of the VF-TLP tester and the test probe, which can be realized by automatic calibration of the calibration system matched with the VF-TLP test system. Through open circuit calibration test, the waveform output by the VF-TLP test system can be smoother, and parasitic interference can be eliminated as much as possible.

[0072] Step 4, short circuit calibration test of VF-TLP test system:

[0073] Open circuit connection: contact the probe head 1 and the probe head 2 of the radio frequency probe with the connection point pad 1 and the connection point pad 2 in the first position in the lead connection area 1042 of the VF-TLP test board 104 respectively, and connect the wire 1 and the wire 2 with the connection point pad 1 and the connection point pad 2 respectively, and short the wire 1 and the wire 2.

[0074] Pulse setting: set the output parameters of the VF-TLP pulse generator as follows: pulse width 10 ns, rise time 0.2 ns, voltage 10 V, and output single pulse.

[0075] Data acquisition and judgment:

[0076] First, read the pulse peak current through the current channel (CH2) I _short (3 times average), and read the measured voltage through the voltage channel (CH1) U _short Then, calculate according to formula (1) .

[0077] (1);

[0078] In formula (1), represents the short circuit calibration resistance value.

[0079] If I _short meets the theoretical trend of “ U _set / R _short ( R _short ≈0.1Ω below)” and R _meas≤1Ω (allowing a small deviation caused by parasitic parameters), it is determined that the short-circuit calibration result of the VF-TLP test system meets the preset requirement (e.g., the short-circuit calibration resistance value is less than or equal to 1Ω). Wherein, U _set represents a pulse voltage, R _short represents a short-circuit resistance.

[0080] Next, based on the short-circuit calibration result, the parasitic inductance and the parasitic resistance of the VF-TLP test system are corrected. This process can be automatically adjusted by the calibration system of the VF-TLP test system to output the phase of the waveform based on the short-circuit calibration result obtained during calibration, so as to eliminate parasitic interference as much as possible.

[0081] For example, 5 parallel tests are performed according to the above steps, and the short-circuit calibration results of each group are shown in Table 1. In Table 1, TLP Curr represents the measured current (i.e., the actual captured current), represents a short-circuit calibration resistance value.

[0082] Table 1

[0083]

[0084] As can be seen from Table 1, the loop impedance (i.e., the short-circuit calibration resistance value) of the VF-TLP test system provided by the embodiments of the present application is less than 1Ω.

[0085] If the short-circuit calibration result does not meet the preset requirement (e.g., the short-circuit calibration resistance value is less than or equal to 1Ω), it indicates that the loop impedance of the VF-TLP test system is large (greater than 1Ω), which is not suitable for VF-TLP test. At this time, the structure or material of the VF-TLP test board can be adjusted or transformed to reduce the loop impedance of the F-TLP test system.

[0086] In some embodiments, the VF-TLP test system calibration method described above further comprises:

[0087] The semiconductor device to be tested is fixed in the device bearing area of the VF-TLP test board, and the target pin of the semiconductor device to be tested is wire-connected with the lead connection area of the VF-TLP test board.

[0088] The VF-TLP test instrument is used to perform VF-TLP test on the semiconductor device to be tested, and the VF-TLP test result is obtained and output.

[0089] For ease of description, the above example is continued to be used, referring to Figure 7 and Figure 10The semiconductor device to be tested is fixed in the device bearing area 1041 of the VF-TLP test board, and the target pin of the semiconductor device to be tested is wire-connected with two adjacent connection points (pad1 and pad2) of the lead connection area 1042 of the VF-TLP test board.

[0090] The response signal (such as response voltage, response current, etc.) returned by the semiconductor device to be tested is collected by the VF-TLP tester 101, and according to the response signal, the electrostatic discharge (ESD) capability and the transient immunity of the semiconductor device to be tested are determined.

[0091] In the foregoing manner, before the VF-TLP test system is used to perform VF-TLP testing on the semiconductor device to be tested, the VF-TLP test system is calibrated first, so as to ensure the accuracy and reliability of the test results.

[0092] The above examples are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing examples, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing examples, or make equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A VF-TLP testing system for semiconductor devices, characterized in that, include: VF-TLP tester, test probes, and VF-TLP test board; The VF-TLP test board includes a device carrying area and a lead connection area. The device carrying area is used to carry the semiconductor device under test, and the target pin of the semiconductor device under test can be connected to the lead connection area. One end of the test probe is connected to the VF-TLP tester, and the other end is connected to the lead connection area; The target pin is connected to the first position in the lead connection area at the same position as the other end of the test probe is connected to the second position in the lead connection area.

2. The VF-TLP testing system for semiconductor devices according to claim 1, characterized in that, The lead connection area includes at least two connection points, which may be arranged adjacently or non-adjacently. The distance between the at least two connection points is equal to the distance between the probe tips of the test probe.

3. The VF-TLP testing system for semiconductor devices according to claim 2, characterized in that, The connection points are gold-plated.

4. The VF-TLP testing system for semiconductor devices according to claim 1, characterized in that, The device's bearing area is either a grounded pad or an ungrounded pad.

5. The VF-TLP testing system for semiconductor devices according to claim 1, characterized in that, The lead connection area is located in the outer region of the device bearing area.

6. The VF-TLP testing system for semiconductor devices according to claim 1, characterized in that, The test probe is a radio frequency probe.

7. The VF-TLP testing system for semiconductor devices according to claim 6, characterized in that, The radio frequency probe includes two probe tips or three probe tips.

8. The VF-TLP testing system for semiconductor devices according to claim 1, characterized in that, The target pins are two adjacent or non-adjacent pins on the semiconductor device under test.

9. A calibration method for a VF-TLP test system for semiconductor devices, characterized in that, Applied to the VF-TLP testing system as described in any one of claims 1 to 8; the method includes: An open-circuit calibration test is performed on the VF-TLP test system to obtain the reflected voltage value, and the loop impedance of the VF-TLP test system is corrected based on the reflected voltage value. The VF-TLP test system was subjected to a short-circuit calibration test to obtain the short-circuit calibration results; If the short-circuit calibration result meets the preset requirements, the parasitic inductance and parasitic resistance of the VF-TLP test system are corrected based on the short-circuit calibration result, and the calibration of the VF-TLP test system is completed.

10. The calibration method for the VF-TLP test system of semiconductor devices according to claim 9, characterized in that, The method further includes: The semiconductor device under test is fixed in the device carrier area of ​​the VF-TLP test board, and the target pin of the semiconductor device under test is wire-connected to the lead connection area of ​​the VF-TLP test board. The VF-TLP tester is used to perform VF-TLP testing on the semiconductor device under test, and the VF-TLP test results are obtained and output.

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