A cost-effective storage expansion method and system based on field programmable gate array

Abstract

The application belongs to the field of information security, and specifically discloses a high cost performance storage expansion method and system based on a field programmable gate array, wherein a memory controller writes data transmitted by the field programmable gate array into a pseudo-static random access memory in a burst data stream case, reads one packet of data in the pseudo-static random access memory after processing the last packet of data; meanwhile, in a high concurrency multi-user case, stores security parameters into the pseudo-static random access memory, reads the security parameters in the pseudo-static random access memory when processing user data, updates the security parameters after processing and writes the updated security parameters back into the pseudo-static random access memory; meanwhile, in a bit width decomposition case, decomposes N-bit data into M data segments, and writes the M data segments into the pseudo-static random access memory at the same time, reads out the data in the M pieces of pseudo-static random access memory at the same time when processing data, and combines the data into N-bit width data. The application has the characteristics of low cost and high cost performance.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of information security, and relates to a high cost-effective storage expansion method and system based on a field programmable gate array, which is especially suitable for processing high-speed, burst, non-continuous data flow, requiring a large number of intermediate number cache, authentication and other security systems. BACKGROUND

[0002] In the field of information security, improving the performance of a system is a very important issue. At present, network communication interface rates are developing at a high speed, and a gigabit interface has become a standard configuration of various network devices. This requires that an information processing system must have very high data throughput capacity. However, there are two common and core technical contradictions in the existing system: 1. The continuous processing throughput of the algorithm core or complex signal processing flow in the system is far lower than the interface rate, and the data flow has a burst characteristic, that is, the data reaches at the highest rate allowed by the interface in a very short time, and then there is an idle period. In the case of no back pressure mechanism of the interface, the algorithm processing speed in the field programmable gate array cannot meet the user's demand in the face of a large amount of data, and there are problems of packet loss, packet error, low channel utilization rate and overall communication efficiency; 2. The storage amount of security parameters is large in the multi-user parallel processing. In many working modes, each independent data flow or session needs a unique initialization vector (IV). When the system needs to process multiple concurrent user sessions, the memory capacity required to store these IVs will be very large, and the on-chip resources are difficult to provide a large amount of storage space, resulting in that the system cannot support a high number of concurrent users, which limits its application scenarios.

[0003] Based on the above problems, the existing solutions are: selecting a field programmable gate array with a large on-chip RAM (Random Access Memory) or even a higher level chip to obtain on-chip storage resources, which will greatly increase the hardware cost, area and power consumption, and is not economically feasible; selecting to use an externally expanded DDR (Double Data Rate) or synchronous dynamic random access memory SDRAM (such as DDR3) to provide very high bandwidth and huge capacity, but the interface timing of such chips is strict, and a complex controller and physical layer interface are required, which has a large design difficulty, a long development cycle, and other problems such as high cost and high power consumption; and the middle and low-end field programmable gate arrays generally do not support external DDR. SUMMARY

[0004] In view of the defects of the prior art, the purpose of the present application is to provide a high cost-effective storage expansion method and system based on a field programmable gate array, which aims to solve the problem of packet loss and packet error caused by the fact that the algorithm processing speed in the field programmable gate array cannot reach the interface transmission speed in the face of a large amount of burst data in the case of no back pressure mechanism of the interface.

[0005] The first aspect of the present application relates to a cost-effective storage expansion system based on a field programmable gate array, which communicates with a data processing core module, comprising: a field programmable gate array, a pseudo-static random access memory and a memory controller; the memory controller is arranged in the field programmable gate array, and the pseudo-static random access memory is connected with the field programmable gate array through a bus interface;

[0006] The memory controller is used to write the data transmitted by the field programmable gate array into the pseudo-static random access memory in the case of burst data flow, and read a packet of data in the pseudo-static random access memory into the data processing core module after the data processing core module has processed the previous packet of data.

[0007] Meanwhile, the memory controller is used to store security parameters into the pseudo-static random access memory in the case of high-concurrency multi-user, read the security parameters in the pseudo-static random access memory when processing user data, update the security parameters after processing and write them back to the pseudo-static random access memory.

[0008] Meanwhile, the memory controller is used to decompose N-bit data into M data segments through parallel logic control in the case of bit width decomposition, and write the M data segments into M independent pseudo-static random access memories, and read out the data in the M pseudo-static random access memories simultaneously when the data processing core module processes data, and combine the data into N-bit width data.

[0009] Wherein, N and M are integers greater than or equal to 2, and N is an integer multiple of M.

[0010] In some embodiments, the memory controller comprises a first unit and a second unit.

[0011] When data needs to be stored, the first unit is used to enter a ready-to-write-a-packet flag state, and transmit a write request, a data write address and data to the second unit, and the second unit is used to sequentially transmit a read-write command, an address and data to the pseudo-static random access memory for data writing, and stop writing when the data count reaches the set data length.

[0012] When sending packet acquisition information, the first unit is used to enter a ready-to-read-a-packet flag state, and send a read address and a read request to the second unit; the second unit is used to sequentially transmit a read-write command and an address to the pseudo-static random access memory; and the first unit is used to store the data read from the pseudo-static random access memory into its buffer.

[0013] In some embodiments, in the case of high-concurrency multi-user, if a new user session is established, the pseudo-static random access memory is used to allocate a unique storage unit for storing the security parameters of the user.

[0014] In some embodiments, the pseudo-static random access memory is used to partition the storage data according to the size of the data as needed, and store the data in each partition respectively; the interval size is determined by the maximum packet length of the data packet to be cached.

[0015] In some embodiments, in the case of burst data stream, the pseudo-static random access memory is used to store data in a ring buffer mode; in the case of high concurrency multi-user, the pseudo-static random access memory is used to store security parameters in a fixed position buffer mode.

[0016] In some embodiments, a plurality of interfaces are provided on the memory controller to connect a plurality of PSRAMs for simultaneous reading and writing.

[0017] The second aspect of the present application relates to a cost-effective storage expansion method based on a field programmable gate array, specifically:

[0018] In the case of burst data stream, the data transmitted by the field programmable gate array is sequentially written into the pseudo-static random access memory by the memory controller, and after the data processing core module processes the previous packet of data, a read instruction is sent to the memory controller, and the memory controller sequentially reads a packet of data from the pseudo-static random access memory and outputs it to the data processing core module;

[0019] In the case of high concurrency multi-user, the security parameters are stored in the pseudo-static random access memory by the memory controller, and the security parameters in the pseudo-static random access memory are read when processing user data, and the security parameters are updated and written back to the pseudo-static random access memory after processing the user data;

[0020] In the case of bit width decomposition, the memory controller decomposes N-bit data into M data segments through parallel logic control, and writes them into M independent pseudo-static random access memories simultaneously, and when the data processing core module processes the data, the memory controller reads the data from the M pseudo-static random access memories simultaneously and combines them into N-bit width data; wherein N and M are integers greater than or equal to 2, and N is an integer multiple of M.

[0021] In some embodiments, the method for the pseudo-static random access memory to store data through the memory controller is:

[0022] When the first unit enters the state of preparing to write a packet of data, the write request, write address and data are transmitted to the second unit;

[0023] The second unit sequentially transmits the read and write commands, addresses and data to the pseudo-static random access memory for data writing, and stops writing when the count of written data reaches the set data length.

[0024] In some embodiments, the method for reading data in the pseudo-static random access memory by the data processing core module is as follows:

[0025] When the data processing core module sends a data packet acquisition signal, the first unit enters a ready-to-read-out-a-packet flag state, and sends a read request and a read address to the second unit;

[0026] The second unit sequentially transmits the read-write command and the address to the pseudo-static random access memory, and stores the data read out from the pseudo-static random access memory into the buffer of the first unit.

[0027] In some embodiments, in the case of burst data flow, the pseudo-static random access memory stores data in a ring buffer mode; and in the case of high-concurrency multi-user, the pseudo-static random access memory stores security parameters in a fixed-position buffer mode.

[0028] In some embodiments, the pseudo-static random access memory is partitioned according to the size of the data to be stored, and the data to be stored is stored in each partition; and the size of the partition is determined by the maximum packet length of the data packet to be buffered.

[0029] Overall, compared with the prior art, the above technical solutions conceived by the present application have the following beneficial effects:

[0030] The high-performance storage expansion system provided by the present application has low development complexity, short development cycle, low power consumption, low resource consumption, and is easy to integrate into various master control platforms, and has a wide range of applications. More specifically, compared with using a DDR storage chip, for example, using DDR3, in the same project, the resource consumption of PSRAM is about 1.4% of that of DDR3, and the development cycle and development cost of designing and debugging the DDR3 port are much higher than those of the pseudo-static random access memory PSRAM, and the command set of DDR3 is more complex, and a single access needs to go through multiple steps such as precharge, read-write, and precharge, which will bring more power consumption overhead; for user data caching applications, it can alleviate the defects of the system without back pressure mechanism, while improving channel utilization and overall communication efficiency; for security parameter storage applications, it can support a large number of users for concurrent sessions, expanding the application fields and scenarios of the system; for high-throughput application scenarios, it can use multiple low-end field programmable gate array chips in parallel to process high-throughput data, reducing the hardware cost and design threshold of the information security system. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 is a hardware structure diagram for user data caching applications provided by an embodiment of the present application.

[0032] Figure 2Figure 1 is a hardware structure diagram of an IV value storage application provided by an embodiment of the present application.

[0033] Figure 3 Figure 2 is a hardware structure diagram of a bit width resolution application provided by an embodiment of the present application.

[0034] Figure 4 Figure 3 is a structure diagram of a PSRAM control module provided by an embodiment of the present application.

[0035] Figure 5 Figure 4 is a first unit processing flowchart provided by an embodiment of the present application.

[0036] Figure 6 Figure 5 is a second unit processing flowchart provided by an embodiment of the present application. DETAILED DESCRIPTION

[0037] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application.

[0038] In the present application, the term "and / or" is used to describe the association relationship between the associated objects, which means that there can be three relationships, for example, A and / or B, which means that there are three cases of A alone, A and B together, and B alone. In the present application, the symbol " / " represents the relationship of or, for example, A / B represents A or B.

[0039] In the present application, the terms "first" and "second" are used to distinguish different objects, not to describe the specific order of the objects.

[0040] In the present application, the term "electrically connected" can be direct circuit connection or signal transmission through a communication protocol.

[0041] In the embodiments of the present application, the words "exemplary" or "for example" are used to mean serving as an example, instance or illustration. Any embodiment or design solution described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or having more advantages than other embodiments or design solutions. Rather, the use of "exemplary" or "for example" is intended to present the relevant concept in a specific manner.

[0042] In the description of the embodiments of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0043] The embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application.

[0044] First, the technical terms involved in the embodiments of the present application are introduced.

[0045] The psram_ctrl module (memory controller) is a digital logic circuit module, which is used as a data processing core module and coordinates with a pseudo static random access memory chip.

[0046] The PSRAM memory (Pseudo Static Random Access Memory) is a hybrid memory, which combines the high density, low cost of DRAM and the interface simplicity of SRAM.

[0047] FPGA: Field-Programmable Gate Array, field programmable gate array

[0048] FIFO: First In, First Out, first in first out, a basic data management method or storage buffer

[0049] DDR memory chip: Double Data Rate, a kind of high-speed synchronous dynamic random access memory

[0050] In view of the problems of burst data flow, high concurrency multi-user number and high bit width data interface, the application provides a high cost performance storage expansion method and system based on a middle and low end field programmable gate array. On the one hand, for the burst data flow scene, a low-cost external PSRAM memory chip (such as 32MB memory) is introduced as a buffer band, which effectively smooths the rate difference between high-speed data reception and low-speed data processing core, thereby ensuring the reception of burst data within a certain range. On the one hand, for the scene of high concurrency multi-user number, the parameter storage function is realized; by using PSRAM memory as a large amount of intermediate storage space (such as IV), the system supports safe processing of high concurrency multi-user; on the other hand, for the high throughput application scene, by connecting multiple PSRAM memories in parallel, the storage space is greatly expanded, and the clock of the field programmable gate array controlling the PSRAM memory interface is not pulled up, solving the problem that the middle and low end field programmable gate array cannot meet the high clock frequency (generally 150MHz). In summary, the application avoids using large capacity field programmable gate array chips or high speed, large capacity external DDR memory chips.

[0051] The application provides a high cost performance storage expansion system based on a field programmable gate array, which comprises an external pseudo static random access memory and a memory controller; the field programmable gate array and the external pseudo static random access memory are connected through a bus interface, and the number of connected PSRAM memories can be changed according to the characteristics of the stored data, so that the storage is flexibly expanded in parallel.

[0052] For burst data stream scene, the application can be applied to user data buffer, the whole framework as shown in Figure 1 , the field programmable gate array writes the data sent by the user into PSRAM through the memory controller in turn, after the data processing core module processes the previous data, the data processing core module sends a related signal to the memory controller, and starts to sequentially read the data content of a data packet in PSRAM and outputs to the data processing core module;

[0053] For high concurrency multi-user scene, the application can be applied to the buffer of initial vector of security parameter (IV value), the whole framework as shown in Figure 2 ; a large number of parameters (such as IV) required by the system are stored into the extended PSRAM through the memory controller, when the data processing core module needs to process multiple concurrent sessions, the corresponding security parameters are read or updated from the PSRAM as needed; the specific process is as follows: when a new user session is established, a unique storage unit is allocated from the parameter area of the external PSRAM for storing the IV parameter of the session; when the data of a user needs to be processed, the core processing module reads the corresponding IV in the extended PSRAM through the memory controller when executing the algorithm; after processing a data packet, the updated IV value is written back to the corresponding storage unit in the external PSRAM;

[0054] For high throughput application scenario, the application can be applied to bit width decomposition, the whole framework as shown in Figure 3 , first, the input data of high bit width (N bits) is received, the memory controller decomposes the N-bit data into M data segments through parallel logical control, and simultaneously writes the M data segments into M independent PSRAM chips; when the data processing core module is ready to process data, the memory controller is requested to read out the data in the M PSRAM chips simultaneously, combine the original N-bit data, and then transmit the data to the data processing core module for data processing;

[0055] The internal structure of the memory controller is shown in Figure 4 , which mainly consists of two units, psram_pkt_ctrl and psram_fifo_ctrl, which are referred to as the first unit and the second unit, the processing flow of the two units is shown in Figure 5 , Figure 6 ; specifically, the data to be stored first enters the first unit, the first unit enters the WR_ONE (ready to write a packet flag) state, that is, it starts to prepare to write a data packet, and the write request, data write address and data are transmitted to the second unit, the second unit reads the data in PSRAM through Figure 6The first unit transmits the read-write command, the address and the data to the PSRAM in sequence to write data, and ends the writing when the count of the written data reaches the set data length (the data length needs to be greater than the maximum data packet length of the data packet type in the scene), and finally returns to the initial state IDLE.

[0056] When the data processing core module sends a data packet acquisition signal, the first unit enters the RD_ONE (ready to read one packet) state, that is, starts to prepare to read one packet of data, and sends the read address and the read request to the second unit. The second unit transmits the read-write command and the address to the pseudo-static random access memory in sequence, obtains the read data and transmits it to the first unit, and stores it in the fifo (buffer) in the first unit, and matches the rate with the subsequent data processing core module.

[0057] The method divides the pseudo-static random access memory according to the size of the data to be stored for two different scenes, and stores the data in each partition. The interval size is determined by the maximum packet length of the buffered data packet. However, the two have different buffering methods. The burst data stream scene is ring buffering, that is, the last data can be overwritten after buffering. The parameter buffer is fixed position buffering, and the user's parameters will be in the specified partition. At the same time, if multiple PSRAMs are needed to store data, multiple interfaces are designed in the memory controller to connect multiple PSRAMs to perform read-write functions at the same time.

[0058] Compared with the prior art, the present application has the following advantages:

[0059] The present application has the characteristics of low cost and high cost performance. Compared with using a high-performance field programmable gate array chip, the cost of PSRAM is lower.

[0060] The high cost performance storage expansion system provided by the application has low development complexity, short development period, low power consumption, low resource consumption and easy integration into various master control platforms, and has a wide range of applications. Compared with using DDR storage chips, for example, using DDR3 in the same project, the resource consumption of PSRAM is about 1.4% of that of DDR3, and the development period and development cost of designing and debugging the DDR3 port are much higher than those of PSRAM, and the command set of DDR3 is more complex, and a single access needs to go through multiple steps such as writing, reading and pre-charging, which will bring more power consumption overhead. For user data cache applications, the defects of the system without back pressure mechanism can be alleviated, and the channel utilization and overall communication efficiency can be improved. For security parameter storage applications, a large number of users can be supported for concurrent sessions, which expands the application fields and scenarios of the system. For high-throughput application scenarios, multiple low-end field programmable gate array chips can be connected in parallel to process high-throughput data, reducing the hardware cost and design threshold of the information security system.

[0061] Embodiment

[0062] Taking a burst data stream scenario as an example, after the user data is input to the field programmable gate array through the gigabit network port, the data is first packaged in the field programmable gate array. After each data packet is packaged, a flag signal is sent to the memory controller. When the memory controller receives the signal and the PSRAM is not full, the first unit enters the WR_ONE (ready to write a packet flag) state from the IDLE state (initial state), and starts to request the upper module to transmit the packet data. The chip selection signal is pulled high, and then the address to be written, the write signal and the data to be written are transmitted to the second unit. The second unit receives the signals and writes the data into the PSRAM in sequence. The address written by the first unit is incremented by a fixed partition size (for example, the packet length is 1700B, and the partition size can be selected as 2K).

[0063] When the data processing core module enters the idle state, a flag signal is sent to the memory controller. When the memory controller receives the signal and the PSRAM memory is not empty, the first unit enters the RD_ONE (ready to read a packet flag) state from the IDLE state, and starts to pull the chip selection signal high. Then the address to be read and the read signal are transmitted to the second unit. The second unit receives the signals and reads the data from the PSRAM memory in sequence. The read data is stored in the buffer of the first unit. After a packet of data is completely written, the data processing core module is read out at the same time.

[0064] It should be understood that the terms such as "include" and "may include" used in the present application represent the presence of the disclosed functions, operations or constituent elements, and do not limit one or more additional functions, operations and constituent elements. In the present application, terms such as "include" and / or "have" can be interpreted to mean that a specific characteristic, number, operation, constituent element, component or a combination thereof is present, but cannot be interpreted to exclude the presence or possibility of one or more other characteristics, numbers, operations, constituent elements, components or combinations thereof.

[0065] In the description of the embodiments of the present application, it should be noted that unless specifically defined and limited otherwise, the term "connection" should be interpreted broadly, for example, "connection" can be detachable connection, or can be non-detachable connection, can be direct connection, or can be indirect connection through intermediate medium.

[0066] The above description is merely specific embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A cost-effective storage extension system based on field programmable gate array, which communicates with a data processing core module, characterized in that, The memory controller is arranged in the field programmable gate array, and the pseudo-static random access memory is connected with the field programmable gate array through a bus interface. The memory controller is used for writing data transmitted by the field programmable gate array into the pseudo-static random access memory in a burst data stream case, and reading one packet of data in the pseudo-static random access memory into the data processing core module after the data processing core module processes the last packet of data. Meanwhile, the memory controller is used for storing security parameters into the pseudo-static random access memory in a high-concurrency multi-user case, reading the security parameters in the pseudo-static random access memory when user data is processed, updating the security parameters and writing them back into the pseudo-static random access memory after the user data is processed. Meanwhile, the memory controller is used for decomposing N-bit data into M data segments through parallel logic control and writing the M data segments into M independent pseudo-static random access memories in a bit-width decomposition case, and reading out the data in the M pseudo-static random access memories and combining the data into N-bit data when the data processing core module processes the data. N and M are integers greater than or equal to 2, and N is an integer multiple of M. The memory controller comprises a first unit and a second unit.

2. The cost-effective storage expansion system of claim 1, wherein, When data needs to be stored, the first unit is used to enter a state of preparing to write one packet of data, and transmit a write request, a data write address and data to the second unit. When a data packet acquisition signal is sent, the first unit is used to enter a state of preparing to read out one packet of data, and send a read-out address and a read request to the second unit. The second unit is used to sequentially transmit a read-write command and an address to the pseudo-static random access memory, and the first unit is used to store data read out from the pseudo-static random access memory in a buffer thereof. In a high-concurrency multi-user case, if a new user session is established, the pseudo-static random access memory is used to allocate a unique storage unit for storing security parameters of the user.

3. The cost-effective storage expansion system of claim 1, wherein, The pseudo-static random access memory is partitioned according to the size of data to be stored, and the data is stored in each partition.

4. The cost-effective storage extension system according to any of claims 1 to 3, characterized in that, The interval size is determined by the maximum packet length of the buffered packet. In a burst data stream case, the pseudo-static random access memory is used to store data in a ring buffer mode, and in a high-concurrency multi-user case, the pseudo-static random access memory is used to store security parameters in a fixed-position buffer mode.

5. The cost-effective storage expansion system of claim 1, wherein, The memory controller is provided with a plurality of interfaces for connecting a plurality of pseudo-static random access memories for simultaneous reading and writing.

6. The cost-effective storage expansion system of claim 1, wherein, Specifically, 7. A cost-effective storage expansion method based on field programmable gate array, characterized in that, In a burst data stream case, the memory controller is used to sequentially write data transmitted by the field programmable gate array into the pseudo-static random access memory, and send a read instruction to the memory controller after the data processing core module processes the last packet of data, and the memory controller is used to sequentially read one packet of data in the pseudo-static random access memory and output the packet of data to the data processing core module. ​ In the case of high concurrency multi-user, the memory controller stores the security parameters into the pseudo-static random access memory, reads the security parameters in the pseudo-static random access memory when processing user data, and updates the security parameters and writes them back to the pseudo-static random access memory after processing the user data. In the case of bit width decomposition, the memory controller decomposes N-bit data into M data segments through parallel logic control, and writes them into M independent pseudo-static random access memories simultaneously. When the data processing core module processes the data, the memory controller reads the data in the M pseudo-static random access memories simultaneously, and combines them into N-bit width data. Wherein, N and M are integers greater than or equal to 2, and N is an integer multiple of M.

8. The cost-effective storage extension method of claim 7, wherein, The method for the pseudo-static random access memory to store data through the memory controller is as follows: When the first unit enters the ready-to-write-a-packet flag state, the write request, write address and data are transmitted to the second unit; The second unit transmits the read-write command, address and data to the pseudo-static random access memory in sequence to write data, and stops writing when the write data count reaches the set data length.

9. The cost-effective storage extension method of claim 7, wherein, The method for the data processing core module to read data in the pseudo-static random access memory is as follows: When the data processing core module sends a data packet acquisition signal, the first unit enters the ready-to-read-a-packet flag state, and sends the read address and read request to the second unit; The second unit transmits the read-write command and address to the pseudo-static random access memory in sequence, and stores the data read from the pseudo-static random access memory into the buffer of the first unit.

10. The cost-effective storage extension method of claim 7, wherein, In the case of burst data flow, the pseudo-static random access memory stores data in a ring buffer mode; in the case of high concurrency multi-user, the pseudo-static random access memory stores security parameters in a fixed position buffer mode.

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