Network-on-chip system based on cache consistency

Abstract

The invention discloses an on-chip network system based on cache consistency, belongs to the technical field of computer network communication, and aims to solve the technical problems of global consistency flow overload, on-chip network scheduling delay, directory node load imbalance and too high core resource occupation of a traditional router architecture. Comprising a multi-core cluster, distributed directory nodes, a multi-channel network-on-chip and a hardware acceleration module, cores are connected through a bus, and local cache consistency is achieved based on an MSI protocol; a directory node divides a physical address space into a plurality of fragments based on an address hash fragmentation mechanism, each directory node maintains a sparse directory table, and when the length of a request queue of any directory node exceeds a set threshold value, a dynamic load balancing mechanism is triggered; the multi-channel network-on-chip provides a control channel, a data channel and a configuration channel, and each channel performs message scheduling based on a dynamic priority mechanism; and the hardware acceleration module is used for processing three types of consistent transactions.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer network communication, in particular to an on-chip network system based on cache consistency. BACKGROUND

[0002] With the continuous progress of semiconductor technology, the number of single-chip integrated processor cores grows exponentially, and large-scale multi-core processors have become the core computing power carriers in the fields of high-performance computing, data centers and artificial intelligence. However, the explosive growth of the number of cores poses unprecedented challenges to the inter-core communication and data consistency management within the chip. The traditional bus-based or centralized directory-based on-chip interconnection architecture exposes many performance bottlenecks that are difficult to overcome when the scale is expanded, which seriously restricts the improvement of the overall energy efficiency and computing efficiency of the system.

[0003] Traditional multi-core architecture mostly adopts a global cache consistency strategy (such as a centralized directory protocol): regardless of the distance of inter-core communication, all consistency messages (such as read requests of local cores and write invalidation commands) need to be transmitted to the centralized directory node for processing through the global NoC, and then returned through the global link. This design can simplify the logic when the number of cores is small, but in the large-scale multi-core scenario, high-frequency local communication (such as adjacent cores sharing data) is forced to be included in the global traffic, resulting in the occupation of global NoC bandwidth by invalid traffic, and the congestion of real cross-node key communication due to insufficient bandwidth.

[0004] In addition, the centralized directory node needs to create entries for all main memory data blocks, which occupies storage resources even if the data is not cached, and the storage cost is extremely high; at the same time, the hotspots of data access (such as array traversal and shared variable access) cause the load of some directory nodes to be saturated, while other nodes are idle, forming serious load imbalance. More importantly, traditional consistency transactions (such as invalidation command processing and repeated read request initiation) rely on the computing power of the core or software interrupts to complete, and the core needs to pause the processing of the computing task to handle the communication transaction, resulting in the occupation of part of the computing resources, and the significant decrease of the system energy efficiency.

[0005] The problems of global consistency traffic overload, on-chip network scheduling delay, directory node load imbalance and high occupation of core resources in the traditional router architecture are technical problems that need to be solved. SUMMARY

[0006] The technical task of the present application is to solve the problems of global consistency traffic overload, on-chip network scheduling delay, directory node load imbalance and high occupation of core resources in the traditional router architecture by providing an on-chip network system based on cache consistency in view of the above shortcomings.

[0007] In a first aspect, the application discloses an on-chip network system based on cache coherence, which comprises a multi-core cluster, a distributed directory node, a multi-channel on-chip network and a hardware acceleration module.

[0008] The multi-core cluster comprises a plurality of homogeneous cores, the cores in the cluster are connected through a bus and realize local cache coherence based on an MSI protocol, each core has an independent L1 / L2 cache, a cluster gateway integrates an L3 cache slice, and a local physical address range register is configured, local coherence messages are filtered through a cluster interface, and a cross-cluster request is converted into a global NoC message format.

[0009] The directory node divides a physical address space into a plurality of slices based on an address hash slicing mechanism, each slice is uniquely mapped to a directory node, each directory node maintains a sparse directory table, the sparse directory table is only used to dynamically establish an entry for a data block that has been cached by at least one core, when the request queue length of any directory node exceeds a set threshold, a dynamic load balancing mechanism is triggered, and a scheduler is used to allocate an idle directory node to the overloaded directory node for entry migration, in the entry migration process, a shadow directory is processed and synchronized to the new directory node.

[0010] The multi-channel on-chip network provides a plurality of channels including a control channel, a data channel and a configuration channel, control messages including invalidation commands and read requests are transmitted through the control channel, read responses with data and write requests are transmitted through the data channel, and burst transmission is supported, configuration messages including directory node load balancing and routing table updating are transmitted through the configuration channel, and each channel is scheduled based on a dynamic priority mechanism.

[0011] The hardware acceleration module is located between the core and the L2 cache and is used for processing three types of coherence transactions, namely invalidation command processing, read miss merging and deadlock detection and recovery.

[0012] Preferably, in the multi-core cluster, the state transition logic between the cores is as follows:

[0013] Read operation: the core sends a read request through the bus, other cores in the cluster listen to the read request, detect the local L2 cache, if the local L2 cache has the data specified in the read request, the data is returned through the bus, all cores holding the related data update the state to S, if the local L2 cache of any core in the cluster does not have the data specified in the read request, the L3 cache slice of the cluster gateway returns the data, and if the L3 cache slice of the cluster gateway does not have the data specified in the read request, a global request is triggered;

[0014] Write operation: the core sends a write request through the bus, other cores in the cluster listen to the write request, and update the cache state of the local corresponding data to 1, and return an acknowledgement message through the bus. After all the cores in the cluster confirm, the core initiating the write operation updates the state to the modified state M.

[0015] As a preferred, when multiple cores in the cluster initiate read requests for the same data block, the cluster gateway combines the read requests on the local bus and judges whether the target address of the read request belongs to the local address range. If it belongs to the local address range, the cluster gateway reads the data from the L3 cache slice and forwards it to the local bus. If it does not belong to the local address range, the local message containing the core ID is converted into a global NoC message containing the cluster ID and the core ID, and the global NoC message is added with the priority mark of the read request.

[0016] As a preferred, the table entry contains the data block address, the state bit, the cluster shared mask, and the latest access timestamp;

[0017] The data block address is used to record the offset address in the slice;

[0018] The state bit marks the global state of the data block through a 2-bit state bit. The global state includes the invalid state, the shared state, the modified state, and the reserved state;

[0019] Among them, the invalid state I is represented as 00, indicating that the data block is not cached by any cluster, or has been invalidated by all clusters. When the data block is not accessed, the table entry state is the invalid state I, or when a cluster replaces the data block from the L3 cache, the directory node needs to be notified to update the state to the invalid state I. When the core initiates a read request, if the directory node returns the invalid state I, the core needs to load data from the main memory, and update the directory state to the shared state S or the modified state M;

[0020] The shared state S is represented as 01, indicating that the data block is cached by multiple clusters, and all copies are consistent with the main memory. When multiple clusters concurrently read the same data block, the directory node state is the shared state S, and the shared cluster mask records all holders. Or if a cluster attempts to upgrade the shared state S data block to the modified state M, but there are other sharers, an invalidation request needs to be sent first, and the state is changed to the modified state M after completion. When the directory node receives a read request, if the state is the shared state S, the data is returned directly, and the shared mask is updated. When the directory node receives a write request, it needs to send an invalidation command to all shared clusters, and the state is changed to the modified state M after confirmation.

[0021] The modified state M is represented as 10, indicating that the data block is cached by only one cluster, and the cluster has modified the data, and the main memory data is not updated. When a cluster obtains exclusive right of the data block through a write request, the state is changed to the modified state M. When the data block in the modified state M is replaced, the main memory needs to be written back first, and the state is restored to the shared state I. When the directory node receives a read request, if the state is the modified state M, the data needs to be written back to the main memory first, and then sent to the requesting cluster, and the state is changed to the shared state S. When the directory node receives a write request, if the state is the modified state M, the local modification is directly allowed without broadcasting.

[0022] The reserved state R is represented as 11, which is an expandable state.

[0023] As a preferred embodiment, when the length of the request queue of any directory node exceeds a set threshold, a dynamic load balancing mechanism is triggered, including the following steps:

[0024] Load detection: The directory node real-time counts the queue length, and if the queue length exceeds the set threshold for multiple times in succession, the directory node is determined as an overloaded node;

[0025] Shard migration: The overloaded node sends a migration request to the global configuration channel, the scheduler finds an idle node, and allocates a new address shard range, and performs table item migration to migrate the table items in the overloaded node to the new directory node;

[0026] Shadow directory temporary storage: During the table item migration process, the original directory node copies the table items to be migrated and creates a shadow directory. After receiving a new request, the table items are first processed by the shadow directory and synchronized to the new directory node. After all table items are migrated, the shadow directory is invalidated to ensure consistency during the migration process.

[0027] As a preferred embodiment, the consistency messages in the same channel are divided into three levels according to the urgency, from high to low, which are P0, P1 and P2.

[0028] The messages corresponding to the P0 level include invalidation confirmation and deadlock recovery. If the invalidation confirmation is delayed, the sender will always wait, causing a deadlock, so the current link can be directly preempted;

[0029] The messages corresponding to the P1 level include read requests and exclusive requests. The read request will block the execution of the core;

[0030] The messages corresponding to the P2 level include write-back data and state synchronization. Write-back is the transfer of data from cache to memory, which does not block the immediate operation of the core and can be delayed.

[0031] As a preferred embodiment, after receiving the invalidation message sent by the control channel, the hardware acceleration module directly parses the target cache line address, accesses the tag array of the L2 cache, updates the state to the invalid state I, and generates an acknowledgement message to send back to the source node, reducing the invalidation interruption of the core.

[0032] As preferred, the read missing merge is understood as: if the same core or other cores in the cluster initiate read requests for the same data block for multiple times in a short time, the hardware acceleration module will merge these requests into 1, send a query to the directory node only once, and then distribute the response to each core after receiving the response, reducing repeated read requests.

[0033] As preferred, the hardware acceleration module monitors the request queue of the L2 cache in real time, and if a request is waiting for more than a threshold period or more than a target delay, it is determined to be a deadlock, and a deadlock recovery request is immediately sent to the channel with a priority of P0 to force the release of the link.

[0034] The on-chip network system based on cache coherence has the following advantages: through the cooperative design of the multi-core cluster, the distributed directory node, the multi-channel on-chip network and the hardware acceleration module, the inter-core coherent communication is realized with high efficiency, flexibility and scalability. BRIEF DESCRIPTION OF DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0036] The present application will be further described below in conjunction with the drawings.

[0037] Figure 1 Figure 1 is a routing architecture diagram of an on-chip network system based on cache coherence according to an embodiment of the present application. DETAILED DESCRIPTION

[0038] The present application will be further described below in conjunction with the drawings and specific embodiments, so that those skilled in the art can better understand the present application and implement it. However, the embodiments are not limiting to the present application, and the technical features in the embodiments and the embodiments can be combined with each other without conflict.

[0039] The embodiment of the present application provides an on-chip network system based on cache coherence, which is used to solve the technical problems of global coherence traffic overload, on-chip network scheduling delay, directory node load imbalance and high occupation of core resources existing in the traditional router architecture.

[0040] Embodiment 1:

[0041] The on-chip network system based on cache coherence comprises a multi-core cluster, a distributed directory node, a multi-channel on-chip network and a hardware acceleration module.

[0042] The multi-core cluster includes multiple homogeneous cores, the cluster cores are connected through a bus and realize local cache consistency based on an MSI protocol, each core has an independent L1 / L2 cache, a cluster gateway integrates an L3 cache slice, and a local physical address range register is configured, local consistency messages are filtered through the cluster interface, and a cross-cluster request is converted into a global NoC message format.

[0043] In the embodiment, the multi-core cluster adopts local consistency and traffic isolation, in order to reduce global NoC traffic, multiple homogeneous cores are divided into a cluster, and a "local monitoring + global directory" hybrid consistency strategy is adopted in the cluster.

[0044] The communication between the four cores in the cluster is through a bus connection, and the local consistency is realized by adopting an MSI protocol, and the state conversion logic is as follows:

[0045] Read operation (I→S): the core sends a "read request" to the bus, and other cores monitor and check the local L2 cache - if the data exists (state M / S), the data is returned through the bus, and at the same time, all cores holding the data update the state to S; if no one holds it, the L3 slice of the cluster gateway returns the data (no L3 triggers a global request).

[0046] Write operation (S→M): the core sends a "write request" to the bus, and other cores monitor and update the local cache state of the data to I (invalidation) through the bus and return an "acknowledgment"; after all cores acknowledge, the core initiating the write operation updates the state to M, and the whole process does not need to access the global directory.

[0047] Cluster interface: responsible for filtering local consistency messages (not injected into global NoC), converting cross-cluster requests (such as accessing data of other clusters) into global NoC message format; when multiple cores in the cluster read the same data, the L3 cache slice is integrated, the target address is checked after receiving the message, if it is within the local address range, it is directly obtained from the L3 slice, and is directly forwarded to the local bus, avoiding repeated initiation of global read requests; if it is not (cross-cluster request), the local message format (including core ID) is converted into global format (including cluster ID + core ID), and a "priority mark" (such as read request mark P1) is added, to ensure that the global NoC is scheduled according to priority and some local messages are filtered out, and injected into the global NoC.

[0048] The directory node divides the physical address space into multiple shards based on an address hash sharding mechanism, each shard is uniquely mapped to a directory node, each directory node maintains a sparse directory table, the sparse directory table is only used to dynamically establish table entries for data blocks that have been cached by at least one core, when the request queue length of any directory node exceeds a set threshold, a dynamic load balancing mechanism is triggered, and the scheduler is used to allocate idle directory nodes to the overloaded directory nodes for table entry migration. During the table entry migration process, the shadow directory is processed and synchronized to the new directory node.

[0049] The distributed directory node in the embodiment adopts sparse storage and dynamic load balancing, involving address sharding and sparse directory table entries.

[0050] Address sharding: using address hash sharding, part of the bit width of the physical address is used as the shard index, which is mapped to the corresponding directory node, ensuring that the address-continuous data set (such as an array) is managed by the same node, reducing cross-node collaboration overhead.

[0051] Sparse directory table entries: only create table entries for data blocks that are "cached by at least one core", which reduces storage overhead and maintenance cost compared to traditional centralized table entries for all data blocks, and the table entry format is as follows:

[0052] (1) Data block address (Offset): used to record the offset address within the shard;

[0053] (2) Status bit: use 2-bit status bit to mark the global state of the data block: 00 (I: Invalid), 01 (S: Share), 10 (M: Modified), 11 (R: Reserved); the following is a detailed explanation:

[0054] 00 (I): Invalid state, indicating that the data block is not cached by any cluster, or has been invalidated by all clusters, the data block has not been accessed, the table entry state is invalid state I, or when a cluster replaces the data block from the L3 cache, it needs to notify the directory node to update the state to invalid state I, when the core initiates a read request, if the directory node returns invalid state I, the core needs to load data from the main memory, and update the directory state to shared state S or modified state M;

[0055] 01(S): Shared state, indicating that the data block is cached by multiple clusters, and all copies are consistent with the master. When multiple clusters concurrently read the same data block, the directory node state is shared state S, and the shared cluster mask records all holders. If a cluster attempts to upgrade the shared state S data block to the modified state M, but there are other sharers, an invalidation request needs to be sent first, and the state is changed to the modified state M after completion. When the directory node receives a read request, if the state is shared state S, the data is directly returned, and the shared mask is updated. When the directory node receives a write request, it needs to send an invalidation command to all shared clusters, and the state is changed to the modified state M after confirmation.

[0056] 10(M): Modified state, indicating that the data block is cached by only one cluster, and the cluster has modified the data. The master data is not updated. When a cluster obtains exclusive right to the data block through a write request, the state is changed to the modified state M. When the data block in the modified state M is replaced, the master needs to be written back first, and the state is restored to the shared state I. When the directory node receives a read request, if the state is the modified state M, the data needs to be written back to the master first, and then sent to the requesting cluster, and the state is changed to the shared state S. When the directory node receives a write request, if the state is the modified state M, local modification is directly allowed without broadcasting.

[0057] 11(R): Reserved state, extensible state.

[0058] The shared cluster mask marks which clusters hold the data.

[0059] The most recent access timestamp is used for LRU (Least Recently Used) eviction. When the directory node is full, the table entry with the earliest timestamp is evicted.

[0060] Dynamic load balancing: When the request queue length of a certain directory node exceeds the set threshold, dynamic load balancing is triggered, and the process is as follows:

[0061] (1) Load detection: The directory node real-time statistics queue length, if the queue length exceeds the set threshold for many times in a row, the directory node is determined to be an overloaded node;

[0062] (2) Sharding migration: The overloaded node sends a migration request to the global configuration channel, the scheduler finds an idle node, and allocates a new address shard range, and performs table entry migration to migrate the table entries in the overloaded node to the new directory node;

[0063] (3) Shadow directory staging: During table entry migration, the original directory node copies the table entries to be migrated and creates a shadow directory. After receiving a new request, the table entries are first processed by the shadow directory and synchronized to the new directory node. After all table entries are migrated, the shadow directory is invalidated to ensure that consistency is not interrupted during migration.

[0064] The multi-channel network-on-chip provides multiple channels including control channels, data channels and configuration channels, transmits control messages including invalidation commands and read requests through the control channels, transmits read responses and write requests with data through the data channels and supports burst transmission, and transmits configuration messages including directory node load balancing and routing table updating through the configuration channels, and each channel is based on a dynamic priority mechanism for message scheduling.

[0065] The conventional NoC transmits control messages and data messages through the same channel, which causes the control messages with small size and low delay requirement to be blocked by the data messages with large data volume, and the delay is increased. The architecture realizes fine scheduling of messages through multi-channel isolation and dynamic priority.

[0066] The multi-channel design of the embodiment provides control channels, data channels and configuration channels.

[0067] Control channel (C-Channel): dedicated to transmitting control messages such as invalidation commands and read requests, and priority is given to low delay;

[0068] Data channel (D-Channel): large bit width, used for transmitting messages with data such as read responses and write requests, and burst transmission is supported;

[0069] Configuration channel (P-Channel): used for configuration messages such as directory node load balancing and routing table updating, low priority but high reliability.

[0070] In the same channel, the consistency messages are divided into three levels (P0>P1>P2) according to the urgency, to ensure that the critical messages are transmitted in priority.

[0071] The messages corresponding to the P0 (highest) level include invalidation confirmation and deadlock recovery. If the invalidation confirmation is delayed, the sender will wait all the time, causing a deadlock, so the current link can be directly preempted;

[0072] The messages corresponding to the P1 (medium) level include read requests and exclusive requests, and the read requests will block the execution of the core;

[0073] The messages corresponding to the P2 (low) level include write-back data and state synchronization. The write-back is data from cache to memory, and does not block the immediate operation of the core, so the transmission can be delayed.

[0074] The hardware acceleration module is located between the core and the L2 cache, and is used for processing three types of consistency transactions, including invalidation command processing, read miss merging and deadlock detection and recovery.

[0075] Invalidation command processing: After receiving the invalidation message of C-Channel, the hardware acceleration module directly analyzes the target cache line address, accesses the tag array of L2 cache (without core intervention), updates the state to I, and generates a confirmation message to send back to the source node, reducing the invalidation interruption of the core.

[0076] Read missing merge: If multiple read requests for the same data block are initiated in a short period of time in the same core or other cores in the cluster, the hardware acceleration module will merge these requests into one, send a query to the directory node only once, and then distribute the response to each core after receiving the response, reducing repeated read requests.

[0077] Deadlock detection and recovery: The hardware acceleration module monitors the request queue of L2 cache in real time. If a request is waiting for more than a threshold period (or exceeds the target delay), it is determined to be a deadlock, and a "deadlock recovery request" is sent to the P0 level channel to force the release of the link.

[0078] The on-chip network system based on cache coherence provided by the present application is described in detail above, and the principles and implementation modes of the present application are described by applying specific examples. The above example is only used to help understand the method of the present application and its core idea; at the same time, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range will be changed, and the above description should not be understood as a limitation of the present application.

Claims

1. A cache coherence based network-on-chip system, comprising: The system comprises a multi-core cluster, a distributed directory node, a multi-channel on-chip network and a hardware acceleration module. The multi-core cluster comprises a plurality of homogeneous cores, the cores in the cluster are connected through a bus and realize local cache consistency based on an MSI protocol, each core has an independent L1 / L2 cache, a cluster gateway integrates an L3 cache slice, and a local physical address range register is configured, local consistency messages are filtered through the cluster interface, and a cross-cluster request is converted into a global NoC message format. The directory node divides the physical address space into a plurality of slices based on an address hash slicing mechanism, each slice is uniquely mapped to a directory node, each directory node maintains a sparse directory table, the sparse directory table is only used to dynamically establish an entry for a data block that has been cached by at least one core, when the request queue length of any directory node exceeds a set threshold, a dynamic load balancing mechanism is triggered, and a scheduler is used to allocate an idle directory node to the overloaded directory node for entry migration, in the entry migration process, a shadow directory is processed and synchronized to the new directory node. The multi-channel on-chip network provides a plurality of channels including a control channel, a data channel and a configuration channel, control messages including invalidation commands and read requests are transmitted through the control channel, read responses and write requests with data are transmitted through the data channel, and burst transmission is supported, configuration messages including directory node load balancing and routing table updating are transmitted through the configuration channel, and each channel is scheduled based on a dynamic priority mechanism. The hardware acceleration module is located between the core and the L2 cache and is used to process three types of consistency transactions, namely invalidation command processing, read miss merging and deadlock detection and recovery.

2. The cache coherence-based network-on-chip system of claim 1, wherein, In the multi-core cluster, the state transition logic between the cores is as follows: Read operation: the core sends a read request through the bus, other cores in the cluster listen to the read request, detect the local L2 cache, if the local L2 cache has the data specified in the read request, the data is returned through the bus, all cores holding the related data update the state to S, if the local L2 cache of any core in the cluster does not have the data specified in the read request, the L3 cache slice of the cluster gateway returns the data, and if the L3 cache slice of the cluster gateway does not have the data specified in the read request, a global request is triggered; Write operation: the core sends a write request through the bus, other cores in the cluster listen to the write request, update the cache state of the corresponding data to 1, return an acknowledgement message through the bus, after all cores in the cluster acknowledge, the core initiating the write operation updates the state to the modified state M.

3. The cache coherence-based network-on-chip system of claim 1, wherein, When multiple cores in the cluster initiate read requests for the same data block, the cluster gateway combines the read requests on the local bus, judges whether the target address of the read request belongs to the local address range, if it belongs to the local address range, the cluster gateway reads the data from the L3 cache slice and forwards it to the local bus, if it does not belong to the local address range, the local message containing the core ID is converted into a global NoC message containing the cluster ID and the core ID, and the global NoC message is added with a priority mark of the read request.

4. The cache coherence-based network-on-chip system of claim 1, wherein, The entry contains a data block address, a state bit, a cluster shared mask and a recent access timestamp. The data block address is used for recording an offset address in a fragment; The state bit marks a global state of the data block by a 2-bit state bit, and the global state includes an invalid state, a shared state, a modified state and a reserved state; The invalid state I is indicated by 00, indicating that the data block is not cached by any cluster or has been invalidated by all clusters, and the table entry state is the invalid state I when the data block is not accessed, or the data block is replaced from the L3 cache by a certain cluster, and the directory node needs to be notified to update the state to the invalid state I, and when the core initiates a read request, if the directory node returns the invalid state I, the core needs to load data from the main memory and update the directory state to the shared state S or the modified state M; The shared state S is indicated by 01, indicating that the data block is cached by multiple clusters and all copies are consistent with the main memory, and when multiple clusters concurrently read the same data block, the directory node state is the shared state S, and the shared cluster mask records all holders, or if a certain cluster attempts to upgrade the shared state S data block to the modified state M, but there are other sharers, an invalidation request needs to be sent first, and after completion, the state is changed to the modified state M, and when the directory node receives a read request, if the state is the shared state S, the data is directly returned and the shared mask is updated, and when the directory node receives a write request, an invalidation command needs to be sent to all shared clusters, and after confirmation, the state is changed to the modified state M; The modified state M is indicated by 10, indicating that the data block is only cached by one cluster, and the cluster has modified the data, and the main memory data is not updated, and after a certain cluster obtains exclusive right of the data block through a write request, the state is changed to the modified state M, and when the data block in the modified state M is replaced, the main memory needs to be written back first, and the state is restored to the shared state I, and when the directory node receives a read request, if the state is the modified state M, the data needs to be written back to the main memory first, and then sent to the requesting cluster, and the state is changed to the shared state S, and when the directory node receives a write request, if the state is the modified state M, local modification is directly allowed without broadcasting; The reserved state R is indicated by 11, which is an extensible state.

5. The cache coherence-based network-on-chip system of claim 1, wherein, When the request queue length of any directory node exceeds a set threshold, a dynamic load balancing mechanism is triggered, including the following steps: Load detection: The directory node real-time statistics queue length, if the queue length exceeds the set threshold for many times in succession, the directory node is determined as an overload node; Fragment migration: The overload node sends a migration request to the global configuration channel, the scheduler finds an idle node, and allocates a new address fragment range, and performs table entry migration to migrate the table entries in the overload node to the new directory node; Shadow directory temporary storage: During the table entry migration process, the original directory node copies the to-be-migrated table entries and creates a shadow directory, and after receiving a new request, the table entries are first processed by the shadow directory and synchronized to the new directory node, and after all table entries are migrated, the shadow directory is invalidated, ensuring that the consistency is not interrupted during the migration process.

6. The cache coherence-based network-on-chip system of claim 1, wherein, Consistency messages in the same channel are divided into three levels according to the urgency, from high to low, P0, P1 and P2; The P0 level corresponds to messages including invalidation confirmation and deadlock recovery, and if the invalidation confirmation is delayed, the sender will wait all the time, causing a deadlock, so the current link can be directly preempted; The messages corresponding to the P1 level include read requests and exclusive requests, and the read requests will block the execution of the core; The messages corresponding to the P2 level include write-back data and state synchronization, and the write-back is data from the cache to the memory, which does not block the immediate operation of the core and can be delayed transmission.

7. The cache coherence-based network-on-chip system of claim 1, wherein, After receiving the invalidation message sent by the control channel, the hardware acceleration module directly analyzes the target cache line address, accesses the tag array of the L2 cache, updates the state to the invalid state I, and generates an acknowledgement message to send back to the source node, thereby reducing the invalidation interruption of the core.

8. The cache coherence-based network-on-chip system of claim 1, wherein, The read missing merge is understood as: if the same core or other cores in the cluster initiate read requests for the same data block for multiple times in a short time, the hardware acceleration module will merge these requests into one, send a query to the directory node only once, and then distribute the response to each core after receiving the response, thereby reducing repeated read requests.

9. The cache coherence-based network-on-chip system of claim 6, wherein, The hardware acceleration module monitors the request queue of the L2 cache in real time, and if a request is waiting for more than a threshold period or exceeds the target delay, it is determined as a deadlock, and a deadlock recovery request is immediately sent to the channel with the priority of P0 to force release the link.

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