Power supply output circuit and display device

Abstract

The application provides a power supply output circuit and a display device, wherein the power supply output circuit is composed of a power supply circuit, a comparison circuit, a power output circuit, a first detection circuit, a second detection circuit and a logic control circuit; during hibernation, the comparison circuit stops outputting a first wake-up signal, the power output circuit stops outputting a starting voltage, the first detection circuit and the second detection circuit stop working, and the power consumption of the display device during hibernation is reduced; when the display device is woken up or low-voltage rebound of the power supply voltage or the power voltage occurs, the logic control circuit does not simultaneously receive the first wake-up signal, a second wake-up signal and a third wake-up signal, stops outputting a first enable signal, and the power management integrated circuit does not work, thereby preventing the circuit from being damaged and the picture from being abnormal due to the low-voltage rebound, and improving the working safety of the circuit and the display effect.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of display devices, and particularly relates to a power supply output circuit and a display device. BACKGROUND

[0002] In a display device, a main board is usually used to provide a driving circuit of a display panel with a power supply voltage. The driving circuit of the display panel can include a corresponding power management integrated circuit, a panel driving circuit, etc. The power management integrated circuit provides a working power supply for the display panel and a corresponding driving unit, and the panel driving circuit provides a corresponding row scanning signal for the display panel.

[0003] A display device such as a mobile phone, a smart watch, etc. needs to frequently enter a sleep mode. A plurality of state detection circuits are arranged in the display device, and the input state of the power supply voltage and the voltage state of the driving circuit of the display panel are detected respectively, and the display device is controlled to switch between the sleep state and the wake-up state. The plurality of state detection circuits are always in a working state, and the power consumption is increased.

[0004] When sleeping, the power supply voltage drops to a first power supply voltage, and the driving circuit of the display panel controls part of the load to switch to a low-power consumption or stop working. When waking up, in the process of the power supply voltage rising to a second power supply voltage, the voltage of the corresponding load of the driving circuit of the display panel reaches a threshold voltage for starting working, and the load is switched from a low-power consumption state to a high-power consumption state. The load instantaneously increases, the input voltage of the driving circuit of the display panel drops, that is, a low-voltage rebound occurs, and the sudden jump of the voltage will cause damage to the corresponding driving circuit and cause abnormal display of the display device. SUMMARY

[0005] The present application aims to provide a power supply output circuit, and aims to solve the problems of high power consumption in a conventional display device and low-voltage rebound of the driving circuit of the display panel causing circuit damage and abnormal display.

[0006] A first aspect of an embodiment of the present application provides a power supply output circuit, comprising:

[0007] A power supply circuit, an input end of the power supply circuit is used to input a power supply voltage, a first output end of the power supply circuit is connected with a driving circuit of a display panel, the power supply circuit is used to convert the power supply voltage into a power voltage, wherein when the display panel is switched from a sleep state to a wake-up state, the power supply voltage rises from a first power supply voltage to a second power supply voltage, the power voltage rises from a first power voltage to a second power voltage, the driving circuit of the display panel at least includes a power management integrated circuit, and the power management integrated circuit is used to start working when the power voltage and a first enable signal are received.

[0008] a comparison circuit connected to the input terminal of the power supply circuit, the comparison circuit configured to output a first wake-up signal when the power supply voltage reaches a first reference voltage, the first reference voltage being greater than the first power supply voltage and less than the second power supply voltage;

[0009] a power supply output circuit connected to the comparison circuit, the power supply output circuit configured to output a start voltage triggered by the first wake-up signal;

[0010] a first detection circuit connected to the input terminal of the power supply circuit and the power supply output circuit, the first detection circuit configured to output a second wake-up signal when the start voltage is received and the power supply voltage reaches the first reference voltage;

[0011] a second detection circuit connected to the first output terminal of the power supply circuit and the power supply output circuit, the second detection circuit configured to output a third wake-up signal when the start voltage is received and the power supply voltage is greater than a second reference voltage, the second reference voltage being greater than the first power supply voltage and less than the second power supply voltage;

[0012] a logic control circuit configured to output the first enable signal when the first wake-up signal, the second wake-up signal and the third wake-up signal are received simultaneously.

[0013] Optionally, the comparison circuit comprises a first comparator, a first capacitor, a first resistor and a second resistor.

[0014] The non-inverting input terminal of the first comparator, the first terminal of the first capacitor, the first terminal of the first resistor and the input terminal of the power supply circuit are connected, the inverting input terminal of the first comparator is configured to input the first reference voltage, the second terminal of the first capacitor and the second terminal of the first resistor are grounded, the output terminal of the first comparator and the first terminal of the second resistor are connected to constitute the output terminal of the comparison circuit, and the power supply terminal of the first comparator and the second terminal of the second resistor are connected and configured to input a positive voltage.

[0015] Optionally, the power supply output circuit comprises a first inverter, a first electronic switch tube.

[0016] The input terminal of the first inverter is connected to the output terminal of the comparison circuit, the output terminal of the first inverter is connected to the control terminal of the first electronic switch tube, the input terminal of the first electronic switch tube is configured to input a positive voltage, and the output terminal of the first electronic switch tube constitutes the output terminal of the power supply output circuit.

[0017] Optionally, the first detection circuit comprises a second comparator, a non-inverting amplifier, a second inverter, a third resistor, a fourth resistor and a second capacitor.

[0018] The non-inverting input terminal of the second comparator is connected with the input terminal of the power supply circuit, the inverting input terminal of the second comparator is used for inputting the first reference voltage, the power supply terminal of the second comparator is connected with the output terminal of the power supply output circuit, the output terminal of the second comparator is connected with the input terminal of the non-inverting amplifier, the output terminal of the non-inverting amplifier, the first terminal of the third resistor, the first terminal of the fourth resistor, the first terminal of the second capacitor and the input terminal of the second inverter are connected, the second terminal of the third resistor, the second terminal of the fourth resistor and the second terminal of the second capacitor are grounded, and the output terminal of the second inverter constitutes the output terminal of the first detection circuit.

[0019] Optionally, the second detection circuit comprises a third comparator, a third capacitor, a fifth resistor and a third inverter.

[0020] The non-inverting input terminal of the third comparator is used for inputting the second reference voltage, the first terminal of the third capacitor, the first terminal of the fifth resistor and the first output terminal of the power supply circuit are connected, the second terminal of the third capacitor is grounded, the second terminal of the fifth resistor is connected with the inverting input terminal of the third comparator, the power supply terminal of the third comparator is connected with the output terminal of the power supply output circuit, the output terminal of the third comparator is connected with the input terminal of the third inverter, and the output terminal of the third inverter constitutes the output terminal of the second detection circuit.

[0021] Optionally, the power management integrated circuit is further configured to stop working when a third enable signal is received.

[0022] The driving circuit of the display panel further comprises a gate driving circuit.

[0023] The power supply circuit further comprises a second output terminal, and the power supply circuit is further configured to convert the power supply voltage into a driving voltage and output the driving voltage through the second output terminal, wherein when the display panel is switched from a sleep state to a wake-up state, the driving voltage is increased from a first driving voltage to a second driving voltage.

[0024] The power supply output circuit further comprises:

[0025] A switch circuit is connected with the second output terminal of the power supply circuit and the gate driving circuit respectively, and the switch circuit is triggered to be turned on by a second enable signal and is triggered to be turned off by a fourth enable signal.

[0026] A third detection circuit is connected with the second output terminal of the power supply circuit and the power supply output circuit, and the third detection circuit is configured to output a fourth wake-up signal when the start voltage is received and the driving voltage is greater than a third reference voltage, the third reference voltage being greater than the first driving voltage and less than the second driving voltage.

[0027] The logic control circuit is configured to output the first and second enable signals when the first, second, third and fourth wake-up signals are received simultaneously, and output the third and fourth enable signals otherwise.

[0028] Optionally, the third detection circuit comprises a fourth comparator, a fourth capacitor, a sixth resistor and a fourth inverter.

[0029] The non-inverting input terminal of the fourth comparator is configured to input the third reference voltage, the first terminal of the fourth capacitor, the first terminal of the sixth resistor and the second output terminal of the power supply circuit are connected, the second terminal of the fourth capacitor is grounded, the second terminal of the sixth resistor is connected with the inverting input terminal of the fourth comparator, the power supply terminal of the fourth comparator is connected with the output terminal of the power supply output circuit, the output terminal of the fourth comparator is connected with the input terminal of the fourth inverter, and the output terminal of the fourth inverter constitutes the output terminal of the third detection circuit.

[0030] Optionally, the logic control circuit comprises an SR latch, an AND gate, a seventh resistor, an eighth resistor, a ninth resistor, a second electronic switch tube, a third electronic switch tube and a fourth electronic switch tube.

[0031] The reset input terminal of the SR latch is connected with the output terminal of the comparison circuit, the set input terminal of the SR latch is connected with the output terminal of the first detection circuit, the output terminal of the SR latch and the first input terminal of the AND gate are connected, the second input terminal of the AND gate is connected with the output terminal of the second detection circuit, the third input terminal of the AND gate is connected with the output terminal of the third detection circuit, the output terminal of the AND gate is connected with the control terminal of the third electronic switch tube and the control terminal of the fourth electronic switch tube respectively, the first terminal of the seventh resistor, the first terminal of the second electronic switch tube and the first terminal of the eighth resistor are connected and input a positive voltage, the second terminal of the seventh resistor, the control terminal of the second electronic switch tube and the first terminal of the third electronic switch tube are connected, the second terminal of the third electronic switch tube is grounded, the second terminal of the second electronic switch tube is connected with the control terminal of the switch circuit, the second terminal of the eighth resistor, the first terminal of the ninth resistor and the first terminal of the fourth electronic switch tube are connected, the second terminal of the ninth resistor is grounded, and the second terminal of the fourth electronic switch tube is connected with the enable terminal of the power management integrated circuit.

[0032] Optionally, the logic control circuit further comprises a tenth resistor, an eleventh resistor, a fifth capacitor and a Schmitt trigger.

[0033] The first end of the tenth resistor is connected with the output end of the AND gate, the second end of the tenth resistor, the first end of the fifth capacitor, the first end of the eleventh resistor and the input end of the Schmitt trigger are connected, the second end of the fifth capacitor and the second end of the eleventh resistor are grounded, and the output end of the Schmitt trigger is connected with the control end of the third electronic switch tube and the control end of the fourth electronic switch tube respectively.

[0034] The second aspect of the embodiment of the present application provides a display device, comprising a driving circuit of a display panel and the power supply output circuit.

[0035] Compared with the prior art, the power supply output circuit comprises a power supply circuit, a comparison circuit, a power output circuit, a first detection circuit, a second detection circuit and a logic control circuit, when in sleep mode, the comparison circuit stops outputting the first wake-up signal, the power output circuit stops outputting the starting voltage, the first detection circuit and the second detection circuit stop working, and the power consumption of the display device in sleep mode is reduced, and when the display device is woken up, the comparison circuit, the first detection circuit and the second detection circuit output the first wake-up signal, the second wake-up signal and the third wake-up signal respectively, the logic control circuit is controlled to output the first enable signal to the power management integrated circuit, and the power management integrated circuit is started, when low-voltage rebound of the power supply voltage or the power voltage occurs, the logic control circuit stops outputting the first enable signal, and the power management integrated circuit does not work, thereby preventing the circuit from being damaged and the picture from being abnormal due to low-voltage rebound, and improving the working safety of the circuit and the display effect. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 A structural schematic diagram of the power supply output circuit provided for the embodiment one of the present application is shown in the figure.

[0037] Figure 2 A circuit schematic diagram of the comparison circuit and the power output circuit provided for the embodiment one of the present application is shown in the figure.

[0038] Figure 3 A circuit schematic diagram of the first detection circuit provided for the embodiment one of the present application is shown in the figure.

[0039] Figure 4 A circuit schematic diagram of the second detection circuit provided for the embodiment one of the present application is shown in the figure.

[0040] Figure 5 A circuit schematic diagram of the logic control circuit provided for the embodiment one of the present application is shown in the figure.

[0041] Figure 6 A structural schematic diagram of the power supply output circuit provided for the embodiment two of the present application is shown in the figure.

[0042] Figure 7 The third detection circuit provided for the second embodiment of the present application;

[0043] Figure 8 The first circuit schematic diagram of the logic control circuit provided for the second embodiment of the present application;

[0044] Figure 9 The second circuit schematic diagram of the logic control circuit provided for the second embodiment of the present application;

[0045] Figure 10 The structural schematic diagram of the display device provided for the third embodiment of the present application.

[0046] In the drawings, various reference numerals are used throughout the drawings.

[0047] 100, power supply output circuit; 200, driving circuit of display panel; 210, power management integrated circuit; 220, gate driving circuit; 10, power supply circuit; 20, comparison circuit; 30, power supply output circuit; 40, first detection circuit; 50, second detection circuit; 60, logic control circuit; 70, switching circuit; 80, third detection circuit;

[0048] VCC, power supply voltage; VCC1, power supply voltage; VCC2, driving voltage; VA1, first wake-up signal; VA2, second wake-up signal; VA3, third wake-up signal; VA4, fourth wake-up signal; VDD, start-up voltage; EN, enable end; V0, positive voltage; Vref1, first reference voltage; Vref2, second reference voltage; Vref3, third reference voltage;

[0049] U1, first comparator; U2, second comparator; U3, non-inverting amplifier; U4, third comparator; U5, fourth comparator; U6, SR latch; U7, AND gate; U8, Schmitt trigger; R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; R5, fifth resistor; R6, sixth resistor; R7, seventh resistor; R8, eighth resistor; R9, ninth resistor; R10, tenth resistor; R11, eleventh resistor; C1, first capacitor; C2, second capacitor; C3, third capacitor; C4, fourth capacitor; C5, fifth capacitor; INV1, first inverter; INV2, second inverter; INV3, third inverter; INV4, fourth inverter; Q1, first electronic switch tube; Q2, second electronic switch tube; Q3, third electronic switch tube; Q4, fourth electronic switch tube; S, set input end; R, reset input end; Q, output end of SR latch. DETAILED DESCRIPTION

[0050] In order to make the technical problems to be solved by the present application, technical solutions and beneficial effects clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not intended to limit the present application.

[0051] The terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise explicitly and specifically limited.

[0052] Embodiment one

[0053] The first aspect of the embodiment of the present application proposes a power supply output circuit 100, which is used to provide a power supply voltage VCC1 and / or a driving voltage VCC2 for a driving circuit 200 of a display panel, and the driving circuit 200 of the display panel can include a corresponding power management integrated circuit 210, a panel driving circuit, etc.

[0054] During hibernation, the supply voltage VCC drops to a first supply voltage, and the driving circuit 200 of the display panel controls part of the load to switch to low power consumption or stop working. When waking up, during the process of the supply voltage VCC rising to a second supply voltage, the voltage of the corresponding load of the driving circuit 200 of the display panel reaches the threshold voltage for starting to work, the load switches from a low power consumption state to a high power consumption state, the load instantaneously increases, the input voltage of the driving circuit 200 of the display panel drops, that is, a low voltage rebound occurs, and the sudden jump in voltage will cause damage to the corresponding driving circuit and cause abnormal display of the display device.

[0055] In order to reduce the power consumption of the circuit and avoid the problem of low voltage rebound, in the embodiment, a power supply output circuit 100 is proposed, as shown in Figure 1 The power supply output circuit 100 includes:

[0056] The power supply circuit 10 is used to input the supply voltage VCC at the input end of the power supply circuit 10, and the first output end of the power supply circuit 10 is connected with the driving circuit 200 of the display panel. The power supply circuit 10 is used to convert the supply voltage VCC into the power supply voltage VCC1. When the display panel switches from a hibernation state to a wake-up state, the supply voltage VCC rises from a first supply voltage to a second supply voltage, and the power supply voltage VCC1 rises from a first power supply voltage to a second power supply voltage. The driving circuit 200 of the display panel at least includes a power management integrated circuit 210, and the power management integrated circuit 210 is used to start working when receiving the power supply voltage VCC1 and a first enable signal;

[0057] The comparison circuit 20 is connected with the input end of the power supply circuit 10, and the comparison circuit 20 is used for outputting a first wake-up signal VA1 when the power supply voltage VCC reaches a first reference voltage Vref1, the first reference voltage Vref1 is greater than the first power supply voltage and less than the second power supply voltage.

[0058] The power supply output circuit 30 is connected with the comparison circuit 20, and the power supply output circuit 30 is triggered to output a start voltage VDD by the first wake-up signal VA1.

[0059] The first detection circuit 40 is connected with the input end of the power supply circuit 10 and the power supply output circuit 30, and the first detection circuit 40 is used for outputting a second wake-up signal VA2 when the start voltage VDD is received and the power supply voltage VCC reaches the first reference voltage Vref1.

[0060] The second detection circuit 50 is connected with the first output end of the power supply circuit 10 and the power supply output circuit 30, and the second detection circuit 50 is used for outputting a third wake-up signal VA3 when the start voltage VDD is received and the power supply voltage VCC1 is greater than a second reference voltage Vref2, the second reference voltage Vref2 is greater than the first power supply voltage and less than the second power supply voltage.

[0061] The logic control circuit 60 is used for outputting a first enable signal when the first wake-up signal VA1, the second wake-up signal VA2 and the third wake-up signal VA3 are received at the same time.

[0062] In the embodiment, the driving circuit 200 of the display panel is used for providing corresponding control signals, clock signals, voltage signals and the like for the display panel, the display panel displays corresponding image information according to the received signals, the control signals can include row scanning signals, data signals and the like, the display panel realizes line-by-line scanning when the row scanning signals are received, and displays corresponding image information when the data signals are received during the row scanning.

[0063] The driving circuit 200 of the display panel at least includes a power management integrated circuit 210, the power management integrated circuit 210 includes a power input end, an enable end EN and at least one power output end, the power input end is used for connecting the power supply circuit 10 and obtaining the power supply voltage VCC1, the power output end of the power management integrated circuit 210 can be connected with corresponding loads, for example, the power output end of the power management integrated circuit 210 is respectively connected with a timing controller, a source driving circuit and the like in the driving circuit 200 of the display panel, the power management integrated circuit 210 is enabled to work when the first enable signal is received, and converts the received power supply voltage VCC1 into a working voltage required by the rear-end load, the source driving circuit is used for outputting data signals under the control of the timing controller, and the display panel displays corresponding image information under the driving of the data signals and the row scanning signals.

[0064] and stop enabling operation and turn off output when the enable terminal EN of the power management integrated circuit 210 does not receive the first enable signal.

[0065] The power supply circuit 10 obtains the supply voltage VCC through connection of the mainboard and realizes conversion work of the supply voltage VCC to the power supply voltage VCC1, which can be boost conversion or buck conversion, and can also be voltage stabilization conversion, etc. The supply voltage VCC and the power supply voltage VCC1 realize positive correlation change, the mainboard controls the display panel to switch to the sleep state or the wake-up state through the driving circuit 200 of the display panel, and realizes screen-off in the sleep state and screen lighting in the wake-up state.

[0066] In the sleep state, the mainboard reduces the size of the supply voltage VCC, that is, the supply voltage VCC is reduced to the first supply voltage, at this time, the power supply voltage VCC1 is correspondingly reduced to the first power supply voltage, the comparison circuit 20 compares the supply voltage VCC with the first reference voltage Vref1, at this time, the supply voltage VCC is less than the first reference voltage Vref1, the comparison circuit 20 cuts off the output of the first wake-up signal VA1, when the power supply output circuit 30 does not receive the first wake-up signal VA1, the power supply output circuit 30 is cut off, and the output of the start voltage VDD to the first detection circuit 40 and the second detection circuit 50 is cut off, the first detection circuit 40 and the second detection circuit 50 are used to detect the change of the supply voltage VCC and the power supply voltage VCC1 respectively, when the start signal is not received, the first detection circuit 40 and the second detection circuit 50 stop working, no second wake-up signal VA2 and third wake-up signal VA3 are output, and no additional power consumption is generated, that is, the power consumption of the display device in the sleep state is reduced.

[0067] At the same time, the logic control circuit 60 does not receive the first wake-up signal VA1, the second wake-up signal VA2 and the third wake-up signal VA3 output by the comparison circuit 20, the first detection circuit 40 and the second detection circuit 50, the logic control circuit 60 cuts off the output of the first enable signal or selects the output of the third enable signal with the opposite level of the first enable signal, the power management integrated circuit 210 stops enabling operation and turns off output when the first enable signal is not received, further reduces the circuit power consumption in the sleep state, and the load connected with the power management integrated circuit 210 does not receive the working voltage, the load does not work, and does not cause screen flicker.

[0068] When switching from the sleep state to the wake-up state, the main board controls the power supply voltage VCC to gradually rise, and correspondingly, the power supply voltage VCC1 gradually rises. When the power supply voltage VCC gradually rises to the first reference voltage Vref1, the comparison circuit 20 compares and outputs the first wake-up signal VA1. When the power supply output circuit 30 receives the first wake-up signal VA1, it triggers the output of the starting voltage VDD to the first detection circuit 40 and the second detection circuit 50, and the first detection circuit 40 and the second detection circuit 50 start to work. When the first detection circuit 40 detects that the power supply voltage VCC reaches the first reference voltage Vref1, the first detection circuit 40 outputs the second wake-up signal VA2. Correspondingly, when the second detection circuit 50 detects that the power supply voltage VCC1 reaches the second reference voltage Vref2, the second detection circuit 50 detects and outputs the third wake-up signal VA3. At this time, the logic control circuit 60 simultaneously receives the first wake-up signal VA1, the second wake-up signal VA2, and the third wake-up signal VA3. The logic control circuit 60 switches the output of the first enable signal. When the power management integrated circuit 210 receives the power supply voltage VCC1 greater than the second reference voltage Vref2 and receives the first enable signal, it starts to work, and converts the input power supply voltage VCC1 into a working voltage and outputs it to the rear-end load. When the corresponding working voltage of the rear-end load reaches the threshold voltage, the rear-end load starts to work and controls the display panel to display the corresponding image information.

[0069] In the wake-up process, when the load is switched from the low power consumption of the sleep state to the high power consumption of the wake-up state, causing the power supply voltage VCC and / or the power supply voltage VCC1 to have voltage rebound, when the first detection circuit 40 detects that the power supply voltage VCC is less than the first reference voltage Vref1 and / or the second detection circuit 50 detects that the power supply voltage VCC1 is less than the second reference voltage Vref2, the first detection circuit 40 stops outputting the second wake-up signal VA2 and / or the second detection circuit 50 stops outputting the third wake-up signal VA3. At this time, the logic control circuit 60 does not simultaneously receive the first wake-up signal VA1, the second wake-up signal VA2, and the third wake-up signal VA3. The logic control circuit 60 stops outputting the first enable signal or outputs the third enable signal which is opposite in level to the first enable signal. When the power management integrated circuit 210 does not receive the first enable signal, it stops enabling and working and turns off the output. The load connected to the power management integrated circuit 210 does not receive the working voltage, and the load does not work, which will not cause the screen to flicker. At the same time, the corresponding load and circuit will not receive the changing working voltage, and the corresponding load and circuit maintain the stopped working state, which will not cause damage to the circuit.

[0070] The power supply circuit 10 can be selected from corresponding boost circuits, buck circuits, voltage regulator circuits, etc., according to the conversion method. The first power supply voltage, the second reference voltage Vref2, and the second power supply voltage increase sequentially. The first power supply voltage can be 0V or other low voltages. The first power supply voltage is less than the threshold operating voltage of the power management integrated circuit 210. The second reference voltage Vref2 can be set to the threshold operating voltage of the power management integrated circuit 210 or greater than the threshold operating voltage of the power management integrated circuit 210. The second power supply voltage is greater than the threshold operating voltage of the power management integrated circuit 210. For example, if the threshold operating voltage is set to 2.5V, the first power supply voltage can be 1.8V, the second reference voltage Vref2 can be 3.0V, and the second power supply voltage can be 3.3V. The magnitude of each voltage can be set according to actual needs.

[0071] The comparator circuit 20, the first detection circuit 40, and the second detection circuit 50 can be selected with corresponding comparators and auxiliary components, and the logic control circuit 60 can be selected with corresponding logic gates, signal sources, switches, etc.

[0072] like Figure 2 As shown, in an optional embodiment, the comparison circuit 20 includes a first comparator U1, a first capacitor C1, a first resistor R1, and a second resistor R2;

[0073] The non-inverting input terminal of the first comparator U1, the first terminal of the first capacitor C1, the first terminal of the first resistor R1, and the input terminal of the power supply circuit 10 are connected. The inverting input terminal of the first comparator U1 is used to input the first reference voltage Vref1. The second terminal of the first capacitor C1 and the second terminal of the first resistor R1 are grounded. The output terminal of the first comparator U1 and the first terminal of the second resistor R2 are connected to form the output terminal of the comparator circuit 20. The power supply terminal of the first comparator U1 and the second terminal of the second resistor R2 are connected and used to input the positive voltage V0.

[0074] The power output circuit 30 includes a first inverter INV1 and a first electronic switch Q1;

[0075] The input terminal of the first inverter INV1 is connected to the output terminal of the comparator circuit 20, and the output terminal of the first inverter INV1 is connected to the control terminal of the first electronic switch Q1. The input terminal of the first electronic switch Q1 is used to input a positive voltage V0, and the output terminal of the first electronic switch Q1 constitutes the output terminal of the power output circuit 30.

[0076] like Figure 3 As shown, the first detection circuit 40 includes a second comparator U2, a non-inverting amplifier U3, a second inverter INV2, a third resistor R3, a fourth resistor R4, and a second capacitor C2.

[0077] The non-inverting input of the second comparator U2 is connected to the input of the power supply circuit 10. The inverting input of the second comparator U2 is used to input the first reference voltage Vref1. The power supply terminal of the second comparator U2 is connected to the output of the power supply output circuit 30. The output of the second comparator U2 is connected to the input of the non-inverting amplifier U3. The output of the non-inverting amplifier U3, the first terminal of the third resistor R3, the first terminal of the fourth resistor R4, the first terminal of the second capacitor C2, and the input of the second inverter INV2 are connected. The second terminals of the third resistor R3, the fourth resistor R4, and the second terminal of the second capacitor C2 are grounded. The output of the second inverter INV2 constitutes the output of the first detection circuit 40.

[0078] like Figure 4 As shown, the second detection circuit 50 includes a third comparator U4, a third capacitor C3, a fifth resistor R5, and a third inverter INV3;

[0079] The non-inverting input of the third comparator U4 is used to input the second reference voltage Vref2. The first terminal of the third capacitor C3, the first terminal of the fifth resistor R5, and the first output terminal of the power supply circuit 10 are connected. The second terminal of the third capacitor C3 is grounded. The second terminal of the fifth resistor R5 is connected to the inverting input of the third comparator U4. The power supply terminal of the third comparator U4 is connected to the output terminal of the power supply output circuit 30. The output terminal of the third comparator U4 is connected to the input terminal of the third inverter INV3. The output terminal of the third inverter INV3 constitutes the output terminal of the second detection circuit 50.

[0080] like Figure 5 As shown, the detection control circuit includes an SR latch U6, an AND gate U7, an eighth resistor R8, a ninth resistor R9, and a fourth electronic switch Q4.

[0081] The reset input terminal R of SR latch U6 is connected to the output terminal of comparator circuit 20. The set input terminal S of SR latch U6 is connected to the output terminal of first detection circuit 40. The output terminal Q of SR latch U6 is connected to the first input terminal of AND gate U7. The second input terminal of AND gate U7 is connected to the output terminal of second detection circuit 50. The output terminal of AND gate U7 is connected to the control terminal of fourth electronic switch Q4. The first terminal of eighth resistor R8 is connected to and inputs a positive voltage V0. The second terminal of eighth resistor R8, the first terminal of ninth resistor R9, and the first terminal of fourth electronic switch Q4 are connected. The second terminal of ninth resistor R9 is grounded. The second terminal of fourth electronic switch Q4 is connected to the enable terminal EN of power management integrated circuit 210.

[0082] In this embodiment, during sleep mode, the motherboard reduces the power supply voltage VCC to the first power supply voltage. At this time, the power supply voltage VCC1 correspondingly drops to the first power supply voltage. The first comparator U1 compares the power supply voltage VCC with the first reference voltage Vref1. At this time, the power supply voltage VCC is less than the first reference voltage Vref1, and the first comparator U1 outputs a low level. The low level is inverted by the first inverter INV1 and outputs a high level signal to the first electronic switch Q1. The first electronic switch Q1 is triggered to turn off and cuts off the output of positive voltage V0 to the second comparator U2 and the third comparator U4. When no positive voltage V0 is received, the second comparator U2 and the third comparator U4 do not work. The second inverter INV2 inverts and outputs a high level, and the second wake-up signal VA2 is output without a low level. The third inverter INV3 inverts and outputs a low level, and the third wake-up signal VA3 is output without a high level. The second comparator U2 and the third comparator U4 do not work, thus reducing the circuit power consumption in sleep mode.

[0083] Simultaneously, the reset input R of the SR latch U6 in the logic control circuit 60 is at a low level, the set input S is at a high level, the SR flip-flop outputs a low level, the second detection circuit 50 outputs a low level, the AND gate U7 outputs a low level, the fourth electronic switch Q4 is turned on, the power management integrated circuit 210 receives a high-level third enable signal, the power management integrated circuit 210 stops enabling and shuts down the output, further reducing the circuit power consumption in sleep mode, and the load connected to the power management integrated circuit 210 does not receive the working voltage, the load does not work, and there is no screen flicker.

[0084] When switching from sleep mode to wake-up mode, the motherboard control supply voltage VCC gradually increases, and correspondingly, the power supply voltage VCC1 gradually increases. When the power supply voltage VCC gradually rises to the first reference voltage Vref1, the first comparator U1 outputs a high-level first wake-up signal VA1, and the first inverter INV1 converts the output to a low-level signal to the first electronic switch Q1. The first electronic switch Q1 turns on and outputs a positive voltage V0 to the power supply terminals of the second comparator U2 and the third comparator U4. The second comparator U2 of the first detection circuit 40 and the third comparator U4 of the second detection circuit 50 start working. The second comparator U2 detects that the power supply voltage VCC has reached the first reference voltage Vref1, and outputs a high-level signal. This signal is then inverted by the second inverter INV2 to output a low-level second wake-up signal VA2. Correspondingly, the third comparator U4 of the second detection circuit 50 detects that the power supply voltage VCC1 has reached the second reference voltage Vref1. The reference voltage Vref2 is compared, and the third comparator U4 outputs a low level. This low level is then inverted by the third inverter INV3 to output a high level third wake-up signal VA3. At this time, the set input S of the SR latch U6 switches from high to low, and the reset input R switches from low to high. At this time, the output Q of the SR latch U6 switches from low to high. The AND gate U7 of the logic control circuit 60 receives two high levels simultaneously. The AND gate U7 outputs a high-level signal to the fourth electronic switch Q4. The fourth electronic switch Q4 is turned off, and the logic control circuit 60 switches to output a low-level first enable signal. The power management integrated circuit 210 starts working when it receives a power supply voltage VCC1 that is greater than the second reference voltage Vref2 and when it receives the first enable signal. It converts the input power supply voltage VCC1 into a working voltage and outputs it to the back-end load. The back-end load starts working when the corresponding working voltage reaches the threshold voltage and controls the display panel to display the corresponding image information.

[0085] During the wake-up process, when the load switches from a low-power sleep state to a high-power wake-up state, causing a voltage rebound in the supply voltage VCC and / or power supply voltage VCC1, the second comparator U2 of the first detection circuit 40 detects that the supply voltage VCC is less than the first reference voltage Vref1, and / or the third comparator U4 of the second detection circuit 50 detects that the power supply voltage VCC1 is less than the second reference voltage Vref2. At this time, the first detection circuit 40 cuts off the output of the low-level second wake-up signal VA2, and / or the second detection circuit 50 cuts off the output of the high-level third wake-up signal VA3. At this time, the AND gate U7 of the logic control circuit 60 does not simultaneously receive the first wake-up signal VA1, the second wake-up signal VA2, and the third wake-up signal VA3. The AND gate U7 outputs a low level to control the fourth electronic switch Q4 to conduct. When the power management integrated circuit 210 receives the high-level third enable signal, it stops enabling and shuts down its output. The load connected to the power management integrated circuit 210 does not receive the operating voltage, so the load does not work and will not cause screen flickering. Simultaneously, the corresponding load and circuit will not receive the changing operating voltage, and the corresponding load and circuit will remain in a stopped state, preventing circuit damage.

[0086] The first capacitor C1 and the first resistor R1 in the comparator circuit 20 constitute a filter circuit, which is used to filter out noise in the power supply voltage VCC, prevent noise input from causing the first comparator U1 to control the power output circuit 30 to output the start-up voltage VDD, and avoid the power output circuit 30 from outputting incorrectly.

[0087] The non-inverting amplifier U3 in the first detection circuit 40 is used to amplify the signal. The third resistor R3, the fourth resistor R4, and the second capacitor C2 constitute the first delay circuit to ensure that the signal output by the second comparator U2 is stable and to prevent false wake-up. The delay time is determined by the time constant, which is equal to the product of the capacitance value of the second capacitor C2 and the total resistance values ​​of the second resistor R2 and the third resistor R3.

[0088] The third capacitor C3 and the fifth resistor R5 in the second detection circuit 50 constitute a filter circuit, which is used to filter out noise from the power supply voltage VCC1 input to the power management integrated circuit 210, and prevent the power management integrated circuit 210 from starting up incorrectly.

[0089] The beneficial effects of this invention embodiment compared with the prior art are as follows: The power supply output circuit 100 described above is composed of a power supply circuit 10, a comparison circuit 20, a power output circuit 30, a first detection circuit 40, a second detection circuit 50, and a logic control circuit 60. In sleep mode, the comparison circuit 20 cuts off the output of the first wake-up signal VA1, the power output circuit 30 cuts off the output of the start-up voltage VDD, and the first detection circuit 40 and the second detection circuit 50 stop working, reducing the power consumption of the display device in sleep mode. At the same time, when the display device wakes up, the comparison circuit 20, the first detection circuit 40, and the second detection circuit 50 respectively output the first wake-up signal VA1, the second wake-up signal VA2, and the third wake-up signal VA3. The logic control circuit 60 is controlled to output the first enable signal to the power management integrated circuit 210, and the power management integrated circuit 210 starts. When a low voltage rebound occurs in the power supply voltage VCC or the power supply voltage VCC1, the logic control circuit 60 cuts off the output of the first enable signal, and the power management integrated circuit 210 does not work, thereby preventing circuit damage and screen abnormalities caused by low voltage rebound, and improving the circuit operation safety and display effect.

[0090] Example 2

[0091] Based on Example 1, such as Figure 6 As shown, the power management integrated circuit 210 is also used to stop operating when a third enable signal is received;

[0092] The driving circuit 200 of the display panel also includes a gate driving circuit 220;

[0093] The power supply circuit 10 also includes a second output terminal. The power supply circuit 10 is also used to convert the power supply voltage VCC into a driving voltage VCC2 and output it through the second output terminal. When the display panel switches from the sleep state to the wake-up state, the driving voltage VCC2 rises from the first driving voltage to the second driving voltage.

[0094] The power supply output circuit 100 also includes:

[0095] The switching circuit 70 is connected to the second output terminal of the power supply circuit 10 and the gate drive circuit 220 respectively. The switching circuit 70 is triggered to turn on by the second enable signal and triggered to turn off by the fourth enable signal.

[0096] The third detection circuit 80 is connected to the second output terminal of the power supply circuit 10 and the power output circuit 30. The third detection circuit 80 is used to output a fourth wake-up signal VA4 when the start-up voltage VDD is received and the drive voltage VCC2 is greater than the third reference voltage Vref3. The third reference voltage Vref3 is greater than the first drive voltage and less than the second drive voltage.

[0097] The logic control circuit 60 is used to output a first enable signal and a second enable signal when it simultaneously receives a first wake-up signal VA1, a second wake-up signal VA2, a third wake-up signal VA3 and a fourth wake-up signal VA4, otherwise it outputs a third enable signal and a fourth enable signal.

[0098] In this embodiment, the power management integrated circuit 210 is used to provide operating voltage for the timing controller and the source drive circuit. The gate drive circuit 220 is bound to the display panel and provides the row scan signal. When the load switches from the low power consumption of the sleep state to the high power consumption of the wake-up state, the gate drive circuit 220 may experience an increase in drive current due to the start-up of the display panel, and may also cause a drop in drive voltage VCC2, i.e., the drive voltage VCC2 experiences a voltage rebound.

[0099] To address this issue, this embodiment also includes a third detection circuit 80. The power supply terminal of the third detection circuit 80 is connected to the power output circuit 30, and the output terminal of the third detection circuit 80 is connected to the logic control circuit 60. The gate drive circuit 220 is connected to the power supply circuit 10 via a switch circuit 70. The switch circuit 70 is turned on or off according to the second or fourth enable signal output by the logic control circuit 60.

[0100] The power supply circuit 10 obtains the power supply voltage VCC through the motherboard and performs the conversion of the power supply voltage VCC to the power supply voltage VCC1 and the drive voltage VCC2. It can be a boost conversion, a buck conversion, or a voltage regulation conversion. The power supply voltage VCC1 changes in a positive correlation with the power supply voltage VCC, and the drive voltage VCC2 changes in a positive correlation with the power supply voltage VCC. The power management integrated circuit 210 and the gate drive circuit 220 transmit the power supply voltage VCC1 and the drive voltage VCC2 separately. The motherboard controls the display panel to switch to a sleep state or a wake-up state through the power management integrated circuit 210 and the gate drive circuit 220 of the display panel, and realizes the screen is off in the sleep state and the screen is lit in the wake-up state.

[0101] In sleep mode, the motherboard reduces the power supply voltage VCC to the first power supply voltage. At this time, the power supply voltage VCC1 drops to the first power supply voltage, and the drive voltage VCC2 drops to the first drive voltage. The comparator circuit 20 compares the power supply voltage VCC with the first reference voltage Vref1. At this time, the power supply voltage VCC is less than the first reference voltage Vref1, and the comparator circuit 20 cuts off the output of the first wake-up signal VA1. When the power output circuit 30 does not receive the first wake-up signal VA1, the power output circuit 30 is cut off and the startup voltage VDD is cut off to the first detection circuit 40, the second detection circuit 50, and the third detection circuit 80. When no startup signal is received, the first detection circuit 40, the second detection circuit 50, and the third detection circuit 80 stop working, and there is no output of the second wake-up signal VA2 and the fourth wake-up signal VA4, so no additional power consumption is generated, which reduces the power consumption of the display device in sleep mode.

[0102] Meanwhile, when the logic control circuit 60 does not receive the first wake-up signal VA1, the second wake-up signal VA2, the third wake-up signal VA3, and the fourth wake-up signal VA4, the logic control circuit 60 outputs a third enable signal to the power management integrated circuit 210 and a fourth enable signal to the switching circuit 70. When the power management integrated circuit 210 receives the third enable signal, it stops enabling and shuts down, further reducing the circuit power consumption in the sleep state. In addition, the load connected to the power management integrated circuit 210 does not receive the working voltage, so the load does not work and will not cause screen flickering. At the same time, the switching circuit 70 receives the fourth enable signal and is triggered to shut down. There is no driving voltage VCC2 output, and the gate drive circuit 220 stops working, that is, there is no horizontal scanning signal output to the display panel. The display panel will not start horizontal scanning, that is, the display panel will not display any image and will remain in the sleep state.

[0103] When switching from sleep mode to wake-up mode, the motherboard control supply voltage VCC gradually increases. Correspondingly, the power supply voltage VCC1 and drive voltage VCC2 gradually increase. When the power supply voltage VCC gradually rises to the first reference voltage Vref1, the comparator circuit 20 compares and outputs the first wake-up signal VA1. When the power output circuit 30 receives the first wake-up signal VA1, it triggers the output start-up voltage VDD to the first detection circuit 40, the second detection circuit 50, and the third detection circuit 80. The first detection circuit 40, the second detection circuit 50, and the third detection circuit 80 start working. The first detection circuit 40 detects that the power supply voltage VCC has reached the first reference voltage Vref1 and outputs the second wake-up signal VA2. Correspondingly, the second detection circuit 50 detects that the power supply voltage VCC1 has reached the second reference voltage Vref2 and outputs the third wake-up signal VA3. The third detection circuit 80 detects that the drive voltage VCC2 has reached the third reference voltage Vref2 and outputs the third wake-up signal VA3. When the reference voltage Vref3 is reached, the logic control circuit 60 simultaneously receives the first wake-up signal VA1, the second wake-up signal VA2, the third wake-up signal VA3, and the fourth wake-up signal VA4. The logic control circuit 60 switches the output of the first enable signal to the power management integrated circuit 210 and the output of the second enable signal to the switching circuit 70. The power management integrated circuit 210 starts working when it receives a power supply voltage VCC1 greater than the second reference voltage Vref2 and when it receives the first enable signal. It converts the input power supply voltage VCC1 into a working voltage and outputs it to the back-end load. When the switching circuit 70 receives the second enable signal, it is triggered to conduct and outputs a driving voltage VCC2 greater than the third reference voltage Vref3 to the gate driving circuit 220. The gate driving circuit 220 can output the row scanning signal normally. The back-end load starts working when the corresponding working voltage reaches the threshold voltage and works together with the gate driving circuit 220 to control the display panel to display the corresponding image information.

[0104] During the wake-up process, when the load switches from the low power consumption of the sleep state to the high power consumption of the wake-up state, causing a voltage rebound in one or both of the power supply voltage VCC1 and the drive voltage VCC2, the second detection circuit 50 detects that the power supply voltage VCC1 is less than the second reference voltage Vref2, and the second detection circuit 50 cuts off the output of the third wake-up signal VA3. The third detection circuit 80 detects that the drive voltage VCC2 is less than the third reference voltage Vref3, and the third detection circuit 80 cuts off the output of the fourth wake-up signal VA4. At this time, the logic control circuit 60 does not simultaneously receive the first wake-up signal VA1, the second wake-up signal VA2, the third wake-up signal VA3, and the fourth wake-up signal VA4. The logic control circuit 60 switches the output of the third enable signal and the fourth enable signal. When the power management integrated circuit 210 receives the third enable signal, it stops enabling and shuts off the output. When the switching circuit 70 receives the fourth enable signal, it triggers shutdown. The gate drive circuit 220 stops working, the display panel does not work, and there will be no screen flicker. At the same time, the corresponding load and the display panel will not receive the changing working voltage, and the corresponding load and the display panel will remain in a stopped working state, which will not cause damage to the thin-film transistors in the load or the display panel.

[0105] In this circuit, the first driving voltage, the second reference voltage Vref2, and the second driving voltage increase sequentially. The first driving voltage can be 0V or other low voltages. The first driving voltage is less than the threshold operating voltage of the power management integrated circuit 210. The third reference voltage Vref3 can be set to the threshold operating voltage of the gate driving circuit 220 or greater than the threshold operating voltage of the gate driving circuit 220. The second driving voltage is greater than the threshold operating voltage of the gate driving circuit 220. For example, if the threshold operating voltage of the gate driving circuit 220 is set to 1.5V, the first driving voltage can be 0V, the second reference voltage Vref2 can be 1.5V, and the second driving voltage can be 1.8V. The values ​​of each voltage can be set according to actual needs.

[0106] The switching circuit 70 can be selected with a switching device that has controlled on / off states, and the third detection circuit 80 can use a corresponding switching device. Correspondingly, the logic control circuit 60 can adjust its circuit structure according to the output mode of the enable signal.

[0107] In an alternative embodiment, such as Figure 7 As shown, the third detection circuit 80 includes a fourth comparator U5, a fourth capacitor C4, a sixth resistor R6, and a fourth inverter INV4;

[0108] The non-inverting input of the fourth comparator U5 is used to input the third reference voltage Vref3. The first terminal of the fourth capacitor C4, the first terminal of the sixth resistor R6, and the second output terminal of the power supply circuit 10 are connected. The second terminal of the fourth capacitor C4 is grounded. The second terminal of the sixth resistor R6 is connected to the inverting input of the fourth comparator U5. The power supply terminal of the fourth comparator U5 is connected to the output terminal of the power supply output circuit 30. The output terminal of the fourth comparator U5 is connected to the input terminal of the fourth inverter INV4. The output terminal of the fourth inverter INV4 constitutes the output terminal of the third detection circuit 80.

[0109] like Figure 8 As shown, the logic control circuit 60 includes an SR latch U6, an AND gate U7, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a second electronic switch Q2, a third electronic switch Q3, and a fourth electronic switch Q4.

[0110] The reset input R of SR latch U6 is connected to the output of comparator circuit 20; the set input S of SR latch U6 is connected to the output of first detection circuit 40; the output Q of SR latch U6 is connected to the first input of AND gate U7; the second input of AND gate U7 is connected to the output of second detection circuit 50; the third input of AND gate U7 is connected to the output of third detection circuit 80; and the output of AND gate U7 is connected to the control terminals of third electronic switch Q3 and fourth electronic switch Q4, respectively. The first terminal of seventh resistor R7 and the second electronic switch Q4 are connected to... The first terminal of resistor 2 is connected to the first terminal of the eighth resistor R8 and a positive voltage V0 is input. The second terminal of the seventh resistor R7, the control terminal of the second electronic switch Q2, and the first terminal of the third electronic switch Q3 are connected. The second terminal of the third electronic switch Q3 is grounded. The second terminal of the second electronic switch Q2 is connected to the control terminal of the switch circuit 70. The second terminal of the eighth resistor R8, the first terminal of the ninth resistor R9, and the first terminal of the fourth electronic switch Q4 are connected. The second terminal of the ninth resistor R9 is grounded. The second terminal of the fourth electronic switch Q4 is connected to the enable terminal EN of the power management integrated circuit 210.

[0111] In this embodiment, during sleep mode, the motherboard reduces the supply voltage VCC to the first supply voltage. At this time, the power supply voltage VCC1 drops to the first power supply voltage, and the drive voltage VCC2 drops to the first drive voltage. The first comparator U1 compares the supply voltage VCC with the first reference voltage Vref1. Since the supply voltage VCC is less than the first reference voltage Vref1, the first comparator U1 outputs a low level, cutting off the high-level first wake-up signal VA1. The low level signal is inverted by the first inverter INV1 and outputs a high-level signal to the first electronic switch Q1. When transistor Q1 is triggered to turn off, it cuts off the output positive voltage V0 to the second comparator U2 and the third comparator U4. When no positive voltage V0 is received, the second comparator U2, the third comparator U4 and the fourth comparator U5 do not work. The second inverter INV2 outputs a high level, and there is no low level second wake-up signal VA2 output. The third inverter INV3 outputs a low level, and there is no high level third wake-up signal VA3 output. The fourth inverter INV4 outputs a low level, and there is no high level fourth wake-up signal VA4 output. The second comparator U2, the third comparator U4 and the fourth comparator U5 do not work, reducing the circuit power consumption in the sleep state.

[0112] Simultaneously, the reset input R of the SR latch U6 in the logic control circuit 60 is low, the set input S is high, the SR flip-flop outputs a low level, the second detection circuit 50 and the third detection circuit 80 output a low level, the AND gate U7 outputs a low level, the third electronic switch Q3 is turned off, the control terminal of the second electronic switch Q2 is pulled up to a high potential, the second electronic switch Q2 is turned off, the fourth electronic switch Q4 is turned on, the power management integrated circuit 210 receives a high-level third enable signal, the power management integrated circuit 210 stops enabling and turns off its output, further reducing the circuit power consumption in the sleep state, and the load connected to the power management integrated circuit 210 does not receive the working voltage, the load does not work, and there is no screen flicker. At the same time, the switching circuit 70 receives a low-level fourth enable signal, the switching circuit 70 is turned off, there is no drive voltage VCC2 output, the gate drive circuit 220 stops working, that is, there is no horizontal scanning signal output to the display panel, the display panel will not start horizontal scanning, that is, the display panel will not display the screen, and the screen remains in a sleep state.

[0113] When switching from sleep mode to wake-up mode, the motherboard control power supply voltage VCC gradually increases, and correspondingly, the power supply voltage VCC1 gradually increases. When the power supply voltage VCC gradually increases to the first reference voltage Vref1, the first comparator U1 compares and outputs a high-level first wake-up signal VA1, and the first inverter INV1 converts and outputs a low-level signal to the first electronic switch Q1. The first electronic switch Q1 is turned on and outputs a positive voltage V0 to the power supply terminals of the second comparator U2, the third comparator U4, and the fourth comparator U5. The second comparator U2 of the first detection circuit 40, the third comparator U4 of the second detection circuit 50, and the fourth comparator U5 of the third detection circuit 80 start working.

[0114] The second comparator U2 detects that the supply voltage VCC reaches the first reference voltage Vref1, and outputs a high-level signal. This signal is then inverted by the second inverter INV2 to output a low-level wake-up signal VA2. Correspondingly, the third comparator U4 of the second detection circuit 50 detects that the supply voltage VCC1 reaches the second reference voltage Vref2, and outputs a low-level signal. This signal is then inverted by the third inverter INV3 to output a high-level third wake-up signal VA3. The fourth comparator U5 of the third detection circuit 80 detects that the supply voltage VCC1 reaches the third reference voltage Vref3, and outputs a low-level signal. This signal is then inverted by the fourth inverter INV4 to output a high-level fourth wake-up signal VA4. At this time, the set input S of the SR latch U6 switches from high to low, the reset input R switches from low to high, and the output Q of the SR latch U6 switches from low to high. The AND gate of the logic control circuit 60... U7 simultaneously receives three high-level signals. The AND gate U7 outputs a high-level signal to the third electronic switch Q3 and the fourth electronic switch Q4. The third electronic switch Q3 turns on and pulls down the control terminal of the second electronic switch Q2 to a low potential. The second electronic switch Q2 turns on, and the fourth electronic switch Q4 turns off. The logic control circuit 60 switches the output of a low-level first enable signal to the power management integrated circuit 210 and a high-level second enable signal to the switching circuit 70. The power management integrated circuit 210 starts working when it receives a power supply voltage VCC1 greater than the second reference voltage Vref2 and receives the first enable signal. The switching circuit 70 is triggered to turn on and transmits a driving voltage VCC2 greater than the third reference voltage Vref3 to the gate driving circuit 220. The gate driving circuit 220 can output the horizontal scanning signal normally. The back-end load starts working when the corresponding working voltage reaches the threshold voltage and works together with the gate driving circuit 220 to control the display panel to display the corresponding image information.

[0115] During the wake-up process, when the load switches from the low-power sleep state to the high-power wake-up state, causing a voltage bounce in one or both of the power supply voltage VCC1 and the drive voltage VCC2, the third comparator U4 detects that the power supply voltage VCC1 is less than the second reference voltage Vref2, and the second detection circuit 50 cuts off, outputting the third wake-up signal VA3. The fourth comparator U5 detects that the drive voltage VCC2 is less than the third reference voltage Vref3, and the third detection circuit 80 cuts off, outputting the fourth wake-up signal VA4. At this time, the AND gate U7 does not simultaneously receive the first wake-up signal VA1, the second wake-up signal VA2, and the third wake-up signal VA4. When the third and fourth wake-up signals VA4 are received, the AND gate U7 outputs a low level, the second electronic switch Q2 is turned off, and the fourth electronic switch Q4 is turned on, switching the output of the third and fourth enable signals. When the power management integrated circuit 210 receives the third enable signal, it stops enabling and turns off the output. When the switching circuit 70 receives the fourth enable signal, it is triggered to turn off. The gate drive circuit 220 stops working, the display panel does not work, and there will be no screen flicker. At the same time, the corresponding load and the display panel will not receive a changing working voltage. The corresponding load and the display panel remain in a stopped working state, which will not cause damage to the thin film transistors in the load or the display panel.

[0116] The fourth capacitor C4 and the sixth resistor R6 of the third detection circuit 80 constitute a filter circuit, which is used to filter out noise in the drive voltage VCC2.

[0117] Corresponding to the level of the above signal, the first electronic switch Q1, the second electronic switch Q2, the third electronic switch Q3 and the fourth electronic switch Q4 can be corresponding types of switching devices. In an optional embodiment, the first electronic switch Q1, the second electronic switch Q2 and the fourth electronic switch Q4 are P-channel field-effect transistors and the third electronic switch Q3 is an N-channel field-effect transistor.

[0118] In order to improve the signal stability of AND gate U7 and prevent the front-end detection circuit from misjudging and causing the logic control circuit 60 to output an incorrect enable signal, in an optional embodiment, such as Figure 9 As shown, the logic control circuit 60 also includes a tenth resistor R10, an eleventh resistor R11, a fifth capacitor C5, and a Schmitt trigger U8.

[0119] The first terminal of the tenth resistor R10 is connected to the output terminal of AND gate U7. The second terminal of the tenth resistor R10, the first terminal of the fifth capacitor C5, the first terminal of the eleventh resistor R11, and the input terminal of Schmitt trigger U8 are connected. The second terminal of the fifth capacitor C5 and the second terminal of the eleventh resistor R11 are grounded. The output terminal of Schmitt trigger U8 is connected to the control terminal of the third electronic switch Q3 and the control terminal of the fourth electronic switch Q4, respectively.

[0120] In this embodiment, the tenth resistor R10, the eleventh resistor R11, the fifth capacitor C5, and the Schmitt trigger U8 form the second delay circuit. The tenth resistor R10 is responsible for controlling the current flowing through the Schmitt trigger U8 to prevent damage to the Schmitt trigger U8. The eleventh resistor R11 and the fifth capacitor C5 form an RC delay circuit. During sleep mode, the eleventh resistor R11 discharges the fifth capacitor C5. When the AND gate U7 outputs a high-level signal, the second delay circuit receives the high-level signal and outputs a high-level signal after a delay for a period of time to prevent the front-end detection circuit from misjudging and outputting an abnormal wake-up signal. When the AND gate U7 continuously outputs a high-level signal for a preset period of time, the second delay circuit outputs a high-level signal and controls the corresponding fourth electronic switch Q4 to turn off and the second electronic switch Q2 to turn on, thereby enabling the power management integrated circuit 210 and powering on the gate drive circuit 220.

[0121] Example 3

[0122] A second aspect of the present invention provides a display device, such as... Figure 10 As shown, the display device includes a driving circuit 200 for the display panel and a power supply output circuit 100. The specific structure of the power supply output circuit 100 is as described in the above embodiments. Since this display device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be described in detail here. The power supply output circuit 100 is connected to the driving circuit 200 for the display panel.

[0123] In this embodiment, the driving circuit 200 of the display panel may include a power management integrated circuit 210 and a gate driving circuit 220. The power management integrated circuit 210 is used to provide operating voltage for the timing controller and the source driving circuit, and the gate driving circuit 220 is bonded to the display panel and provides a row scanning signal.

[0124] The power supply output circuit 100 is connected to the power supply terminal of the gate drive circuit 220. The power supply output circuit 100 is also connected to the power input terminal and the enable terminal EN of the power management integrated circuit 210. In sleep mode, the power supply output circuit 100 enables the power management integrated circuit 210 to stop working and cuts off the output drive voltage VCC2 to the gate drive circuit 220. The display panel does not work and the relevant loads switch to low power consumption.

[0125] In the wake-up state, the power supply output circuit 100 enables the power management integrated circuit 210 to work and outputs the power supply voltage VCC1 to the power management integrated circuit 210. At the same time, it outputs the drive voltage VCC2 to the gate drive circuit 220. The gate drive circuit 220 and the power management integrated circuit 210 work normally. The power management integrated circuit 210 converts the input power supply voltage VCC1 into the working voltage and outputs it to the back-end load. The gate drive circuit 220 can output the horizontal scanning signal normally. The back-end load starts working when the corresponding working voltage reaches the threshold voltage and works together with the gate drive circuit 220 to control the display panel to display the corresponding image information.

[0126] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A power supply output circuit, characterized in that, include: The power supply circuit has an input terminal for inputting a power supply voltage and a first output terminal connected to the driving circuit of the display panel. The power supply circuit is used to convert the power supply voltage into a power supply voltage. When the display panel switches from a sleep state to a wake-up state, the power supply voltage rises from a first power supply voltage to a second power supply voltage, and the power supply voltage rises from a first power supply voltage to a second power supply voltage. The driving circuit of the display panel includes at least a power management integrated circuit, which is used to start working when it receives the power supply voltage and a first enable signal. A comparator circuit is connected to the input terminal of the power supply circuit. The comparator circuit is used to output a first wake-up signal when the power supply voltage reaches a first reference voltage. The first reference voltage is greater than the first power supply voltage and less than the second power supply voltage. A power output circuit is connected to the comparison circuit, and the power output circuit is triggered by the first wake-up signal to output a startup voltage. The first detection circuit is connected to the input terminal of the power supply circuit and the power output circuit. The first detection circuit is used to output a second wake-up signal when the start-up voltage is received and the power supply voltage reaches the first reference voltage. The second detection circuit is connected to the first output terminal of the power supply circuit and the power output circuit. The second detection circuit is used to output a third wake-up signal when the start-up voltage is received and the power supply voltage is greater than the second reference voltage. The second reference voltage is greater than the first power supply voltage and less than the second power supply voltage. A logic control circuit is used to output the first enable signal when the first wake-up signal, the second wake-up signal and the third wake-up signal are received simultaneously.

2. The power supply output circuit as described in claim 1, characterized in that, The comparison circuit includes a first comparator, a first capacitor, a first resistor, and a second resistor; The non-inverting input terminal of the first comparator, the first terminal of the first capacitor, the first terminal of the first resistor, and the input terminal of the power supply circuit are connected. The inverting input terminal of the first comparator is used to input the first reference voltage. The second terminal of the first capacitor and the second terminal of the first resistor are grounded. The output terminal of the first comparator and the first terminal of the second resistor are connected to form the output terminal of the comparator circuit. The power supply terminal of the first comparator and the second terminal of the second resistor are connected and used to input a positive voltage.

3. The power supply output circuit as described in claim 1, characterized in that, The power output circuit includes a first inverter and a first electronic switch. The input terminal of the first inverter is connected to the output terminal of the comparator circuit, the output terminal of the first inverter is connected to the control terminal of the first electronic switch, the input terminal of the first electronic switch is used to input a positive voltage, and the output terminal of the first electronic switch constitutes the output terminal of the power output circuit.

4. The power supply output circuit as described in claim 1, characterized in that, The first detection circuit includes a second comparator, a non-inverting amplifier, a second inverter, a third resistor, a fourth resistor, and a second capacitor; The non-inverting input of the second comparator is connected to the input of the power supply circuit, the inverting input of the second comparator is used to input the first reference voltage, the power supply terminal of the second comparator is connected to the output of the power supply output circuit, the output of the second comparator is connected to the input of the non-inverting amplifier, the output of the non-inverting amplifier, the first end of the third resistor, the first end of the fourth resistor, the first end of the second capacitor and the input of the second inverter are connected, the second end of the third resistor, the second end of the fourth resistor and the second end of the second capacitor are grounded, and the output of the second inverter constitutes the output of the first detection circuit.

5. The power supply output circuit as described in claim 1, characterized in that, The second detection circuit includes a third comparator, a third capacitor, a fifth resistor, and a third inverter; The non-inverting input of the third comparator is used to input the second reference voltage. The first terminal of the third capacitor, the first terminal of the fifth resistor, and the first output terminal of the power supply circuit are connected. The second terminal of the third capacitor is grounded. The second terminal of the fifth resistor is connected to the inverting input of the third comparator. The power supply terminal of the third comparator is connected to the output terminal of the power supply output circuit. The output terminal of the third comparator is connected to the input terminal of the third inverter. The output terminal of the third inverter constitutes the output terminal of the second detection circuit.

6. The power supply output circuit as described in any one of claims 1 to 5, characterized in that, The power management integrated circuit is also used to stop working when a third enable signal is received; The driving circuit of the display panel also includes a gate driving circuit; The power supply circuit also includes a second output terminal. The power supply circuit is further used to convert the power supply voltage into a driving voltage and output it through the second output terminal. When the display panel switches from a sleep state to a wake-up state, the driving voltage rises from a first driving voltage to a second driving voltage. The power supply output circuit also includes: A switching circuit is connected to the second output terminal of the power supply circuit and the gate driving circuit respectively. The switching circuit is triggered to turn on by a second enable signal and triggered to turn off by a fourth enable signal. The third detection circuit is connected to the second output terminal of the power supply circuit and the power output circuit. The third detection circuit is used to output a fourth wake-up signal when the start-up voltage is received and the driving voltage is greater than the third reference voltage. The third reference voltage is greater than the first driving voltage and less than the second driving voltage. The logic control circuit is configured to output the first enable signal and the second enable signal when it simultaneously receives the first wake-up signal, the second wake-up signal, the third wake-up signal, and the fourth wake-up signal; otherwise, it outputs the third enable signal and the fourth enable signal.

7. The power supply output circuit as described in claim 6, characterized in that, The third detection circuit includes a fourth comparator, a fourth capacitor, a sixth resistor, and a fourth inverter; The non-inverting input of the fourth comparator is used to input the third reference voltage. The first terminal of the fourth capacitor, the first terminal of the sixth resistor, and the second output terminal of the power supply circuit are connected. The second terminal of the fourth capacitor is grounded. The second terminal of the sixth resistor is connected to the inverting input of the fourth comparator. The power supply terminal of the fourth comparator is connected to the output terminal of the power supply output circuit. The output terminal of the fourth comparator is connected to the input terminal of the fourth inverter. The output terminal of the fourth inverter constitutes the output terminal of the third detection circuit.

8. The power supply output circuit as described in claim 6, characterized in that, The logic control circuit includes an SR latch, an AND gate, a seventh resistor, an eighth resistor, a ninth resistor, a second electronic switch, a third electronic switch, and a fourth electronic switch. The reset input of the SR latch is connected to the output of the comparator circuit. The set input of the SR latch is connected to the output of the first detection circuit. The output of the SR latch is connected to the first input of the AND gate. The second input of the AND gate is connected to the output of the second detection circuit. The third input of the AND gate is connected to the output of the third detection circuit. The output of the AND gate is connected to the control terminals of the third and fourth electronic switches, respectively. The first terminal of the seventh resistor, the first terminal of the second electronic switch, and the first terminal of the eighth resistor are connected and a positive voltage is input. The second terminal of the seventh resistor, the control terminal of the second electronic switch, and the first terminal of the third electronic switch are connected. The second terminal of the third electronic switch is grounded. The second terminal of the second electronic switch is connected to the control terminal of the switching circuit. The second terminal of the eighth resistor, the first terminal of the ninth resistor, and the first terminal of the fourth electronic switch are connected. The second terminal of the ninth resistor is grounded. The second terminal of the fourth electronic switch is connected to the enable terminal of the power management integrated circuit.

9. The power supply output circuit as described in claim 8, characterized in that, The logic control circuit also includes a tenth resistor, an eleventh resistor, a fifth capacitor, and a Schmitt trigger; The first end of the tenth resistor is connected to the output of the AND gate. The second end of the tenth resistor, the first end of the fifth capacitor, the first end of the eleventh resistor, and the input of the Schmitt trigger are connected. The second end of the fifth capacitor and the second end of the eleventh resistor are grounded. The output of the Schmitt trigger is connected to the control terminals of the third electronic switch and the fourth electronic switch, respectively.

10. A display device, characterized in that, It includes a driving circuit for a display panel and a power supply output circuit as described in any one of claims 1 to 9, wherein the power supply output circuit is connected to the driving circuit for the display panel.

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