Asynchronous wake-up circuitry
By completely shutting down the clock source in sleep mode through an asynchronous wake-up circuit system, the problem of zero dynamic power consumption and wake-up latency that cannot be achieved in existing technologies is solved, and fast, low-power system wake-up is realized.
Patent Information
- Application Number
- CN202511608986.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-05
- Publication Date
- 2026-01-20
AI Technical Summary
Existing technologies cannot achieve zero dynamic power consumption in sleep mode and have long wake-up times.
An asynchronous wake-up circuit system is adopted, including analog and digital circuit sections. The asynchronous circuit completely shuts off the clock source when the system is in sleep mode and quickly restarts the clock when an external wake-up event occurs, ensuring a rapid switch to normal working mode.
It achieves zero dynamic power consumption in sleep mode and can quickly switch from sleep mode to normal working mode, solving the problems of dynamic power consumption and wake-up delay in traditional technologies.
Smart Images
Figure CN121367482A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates to the field of electronic circuits, and in particular to an asynchronous wake-up circuit system. BACKGROUND
[0002] In electronic systems, clock signals are the core of coordinating all digital logic modules to work synchronously, and the control mode directly determines the power consumption and performance of the system. To achieve the goal of low power consumption, the current mainstream technologies mainly include clock gating, power gating, dynamic voltage and frequency adjustment, and standby mode. However, these traditional schemes have obvious shortcomings due to their own principle limitations. Specifically, clock gating and standby mode cannot completely turn off the clock in deep sleep, resulting in residual dynamic power consumption of the system; the power gating technology takes a long time to recover when waking up, and is prone to losing the register state; and the dynamic voltage and frequency adjustment process is complex, and also cannot achieve zero dynamic power consumption in sleep. SUMMARY
[0003] The technical problem to be solved by the present disclosure is to overcome the defects that the existing technology cannot achieve zero dynamic power consumption in sleep state and takes a long time to wake up the system, and the purpose is to provide an asynchronous wake-up circuit system.
[0004] The present disclosure solves the above technical problems by the following technical solutions:
[0005] In a first aspect of the present disclosure, an asynchronous wake-up circuit system is provided, which is divided into an analog circuit part and a digital circuit part.
[0006] The analog circuit part includes an oscillator.
[0007] The digital circuit part includes a wake-up control module, a clock control module, and a system state machine.
[0008] The output end of the oscillator provides a clock signal to the clock control module, and the input end of the oscillator receives a power-down control signal output by the clock control module.
[0009] The first input end of the wake-up control module receives a wake-up signal, the output end of the wake-up control module is electrically connected to the input end of the system state machine, and the second input end of the wake-up control module receives the clock signal.
[0010] The first input end of the clock control module receives the wake-up signal, the second input end of the clock control module receives the clock signal, and the third input end of the clock control module receives a sleep mode signal output by the system state machine.
[0011] The mode output end of the system state machine is electrically connected with the third input end of the clock control module, the first input end of the system state machine is electrically connected with the output end of the wake-up control module, and the second input end of the system state machine receives the clock signal;
[0012] The clock control module is realized by an asynchronous circuit, and in response to the level inversion of the wake-up signal and the high level of the sleep mode signal, the clock control module outputs a low level power-off control signal;
[0013] In response to the low level of the sleep mode signal, the clock control module outputs a high level power-off control signal;
[0014] The oscillator outputs the clock signal in response to the low level power-off control signal output by the clock control module;
[0015] In response to the high level power-off control signal output by the clock control module, the oscillator has no signal output;
[0016] The wake-up control module is realized by an asynchronous circuit, and is used for receiving the wake-up signal and outputting a wake-up event without the clock signal;
[0017] The system state machine outputs the sleep mode signal in response to receiving an instruction of entering a sleep mode sent by an upper computer;
[0018] In response to receiving the wake-up event, the system state machine exits the sleep mode and enters a normal working mode.
[0019] Optionally, the digital circuit part further comprises an analog low-pass filter;
[0020] The input end of the analog low-pass filter receives an external wake-up signal, and the output end is electrically connected with the first input end of the wake-up control module and the first input end of the clock control module;
[0021] The analog low-pass filter filters glitches of the external wake-up signal and outputs the wake-up signal.
[0022] Optionally, the clock control module comprises a wake-up signal processing unit array, a sleep mode signal transmission unit, a logic combination unit and an oscillator enable control unit;
[0023] The wake-up signal processing unit array comprises a plurality of wake-up signal processing units with the same structure;
[0024] The wake-up signal processing unit is electrically connected with the logic combination unit;
[0025] The logic combination unit is electrically connected with the oscillator enable control unit;
[0026] The sleep mode signal transmission unit is electrically connected with the oscillator enable control unit;
[0027] The input end of each of the wake-up signal processing units respectively receives the wake-up signal and the sleep mode signal;
[0028] The input end of the sleep mode signal transmission unit receives the sleep mode signal and the clock signal, and outputs a high-level signal in response to a rising edge of the clock signal when the sleep mode signal is a high level;
[0029] The input end of the logic combination unit receives the output signal of the wake-up signal processing unit and an external reset signal;
[0030] The logic combination unit outputs a high-level signal in response to at least one of the output signal of the wake-up signal processing unit and the external reset signal being a low level;
[0031] The logic combination unit outputs a low-level signal in response to the output signal of the wake-up signal processing unit and the external reset signal both being high levels;
[0032] The input end of the oscillator enable control unit receives the output signal of the logic combination unit and the clock signal;
[0033] The power-down control signal output by the oscillator enable control unit is a low level in response to the output signal of the logic combination unit being a high level;
[0034] The power-down control signal output by the oscillator enable control unit is a high level in response to a falling edge of the clock signal and the output signal of the logic combination unit being a low level.
[0035] Optionally, the wake-up signal processing unit comprises:
[0036] a first rising edge flip-flop, a first falling edge flip-flop, and a first AND gate;
[0037] The second input end of the first rising edge flip-flop and the second input end of the first falling edge flip-flop receive the wake-up signal.
[0038] And / or,
[0039] The first input end of the first rising edge flip-flop and the first input end of the first falling edge flip-flop are grounded.
[0040] The output end of the first rising edge flip-flop is electrically connected with the input end of the first AND gate.
[0041] An output end of the first falling edge trigger is electrically connected with an input end of the first AND gate.
[0042] Optionally, the clock control module further comprises a first inverter, a third input end of the first rising edge trigger and the first falling edge trigger receives the sleep mode signal processed by the first inverter.
[0043] A first input end of the first rising edge trigger and the first falling edge trigger is a data input end.
[0044] A second input end of the first rising edge trigger and the first falling edge trigger is a clock input end.
[0045] A third input end of the first rising edge trigger and the first falling edge trigger is a set input end.
[0046] Optionally, the logic combination unit comprises:
[0047] a second AND gate and a first NAND gate.
[0048] An input end of the second AND gate is electrically connected with an output end of the wake-up signal processing unit.
[0049] An output end of the second AND gate is electrically connected with a first input end of the first NAND gate.
[0050] A second input end of the first NAND gate receives the external reset signal.
[0051] Optionally, the sleep mode signal transmission unit comprises:
[0052] a second rising edge trigger, a third AND gate, a second inverter and a third inverter.
[0053] A first input end of the second rising edge trigger receives the sleep mode signal.
[0054] A second input end of the second rising edge trigger receives the clock signal.
[0055] A third input end of the second rising edge trigger receives the external reset signal processed by the second inverter.
[0056] An output end of the second rising edge trigger is electrically connected with a second input end of the third AND gate through the third inverter.
[0057] A first input end of the third AND gate receives the sleep mode signal.
[0058] Optionally, the first input end of the second rising edge flip-flop is a data input end, the second input end of the second rising edge flip-flop is a clock input end, and the third input end of the second rising edge flip-flop is a reset input end.
[0059] Optionally, the oscillator enables the control unit to include a second falling edge flip-flop.
[0060] The output end of the sleep mode signal transmission unit is electrically connected to the first input end of the second falling edge flip-flop.
[0061] The output end of the logic combination unit is electrically connected to the third input end of the second falling edge flip-flop.
[0062] The second input end of the second falling edge flip-flop receives the clock signal.
[0063] Optionally, the first input end of the second falling edge flip-flop is a data input end, the second input end of the second falling edge flip-flop is a clock input end, and the third input end of the second falling edge flip-flop is a reset input end.
[0064] On the basis of common general knowledge in the art, the above-mentioned preferred conditions can be combined in any manner to obtain various preferred examples of the present disclosure.
[0065] The positive progress effect of the present disclosure is that:
[0066] The asynchronous wake-up circuit system provided by the present disclosure completely closes the clock source when the system is in sleep mode through the asynchronous circuit, thereby achieving zero dynamic power consumption. At the same time, when an external wake-up event occurs, the system can directly and quickly restart the clock through the asynchronous circuit, ensuring fast switching from the sleep mode to the normal working mode. Thus, the present disclosure effectively solves the dual problems of the traditional clock gating that cannot eliminate the dynamic power consumption in the sleep state and the power gating technology that has long wake-up delay. BRIEF DESCRIPTION OF DRAWINGS
[0067] Figure 1 FIG. 1 is a structural schematic diagram of an asynchronous wake-up circuit system according to Embodiment 1 of the present disclosure.
[0068] Figure 2 FIG. 1 is a structural schematic diagram of an asynchronous wake-up circuit system according to Embodiment 1 of the present disclosure.
[0069] Figure 3 FIG. 2 is a module schematic diagram of a clock control module according to Embodiment 2 of the present disclosure.
[0070] Figure 4 FIG. 2 is a structural schematic diagram of a clock control module according to Embodiment 2 of the present disclosure. DETAILED DESCRIPTION
[0071] The present disclosure is further illustrated by way of examples below, but is not limited to the scope of the examples.
[0072] The prefix words such as "first", "second" in the embodiments of the present disclosure are merely used to distinguish different description objects, and have no limiting effect on the position, order, priority, quantity or content of the described objects. The use of prefix words such as ordinal numbers in the embodiments of the present disclosure does not constitute a limitation on the described objects, and the description of the described objects should refer to the description in the context of the claims or embodiments, and should not constitute an unnecessary limitation because of the use of such prefix words. In addition, in the description of the embodiments, unless otherwise specified, the meaning of "a plurality of" is two or more than two.
[0073] Embodiment 1
[0074] As shown in Figure 1 The present embodiment provides an asynchronous wake-up circuit system 101, which is divided into an analog circuit part 102 and a digital circuit part 103;
[0075] The analog circuit part 102 includes an analog low-pass filter 104 and an oscillator 105;
[0076] The digital circuit part 103 includes a wake-up control module 106, a clock control module 107 and a system state machine 108;
[0077] The output end of the oscillator 105 provides a clock signal to the clock control module 107, and the input end of the oscillator 105 receives a power-down control signal output by the clock control module 107;
[0078] The first input end of the wake-up control module 106 receives a wake-up signal, the output end of the wake-up control module 106 is electrically connected with the input end of the system state machine 108, and the second input end of the wake-up control module 106 receives a clock signal;
[0079] The first input end of the clock control module 107 receives a wake-up signal, the second input end of the clock control module 107 receives a clock signal, and the third input end of the clock control module 107 receives a sleep mode signal output by the system state machine 108;
[0080] The mode output end of the system state machine 108 is electrically connected with the third input end of the clock control module 107, the first input end of the system state machine 108 is electrically connected with the output end of the wake-up control module 106, and the second input end of the system state machine 108 receives a clock signal;
[0081] The clock control module 107, realized by an asynchronous circuit, outputs a low-level power-down control signal in response to a level flip of the wake-up signal and a high level of the sleep mode signal;
[0082] The clock control module 107 outputs a high-level power-down control signal in response to a low level of the sleep mode signal;
[0083] The oscillator 105 outputs a clock signal in response to a low level of the power-down control signal output by the clock control module 107;
[0084] The oscillator 105 has no signal output in response to a high level of the power-down control signal output by the clock control module 107;
[0085] The wake-up control module 106, realized by an asynchronous circuit, is configured to receive a wake-up signal and output a wake-up event without a clock signal;
[0086] The system state machine 108 outputs a sleep mode signal in response to receiving an instruction to enter a sleep mode sent by an upper computer;
[0087] The system state machine 108 exits the sleep mode and enters a normal working mode in response to receiving a wake-up event;
[0088] An input end of the analog low-pass filter 104 receives an external wake-up signal, and an output end of the analog low-pass filter 104 is electrically connected to a first input end of the wake-up control module 106 and a first input end of the clock control module 107;
[0089] The analog low-pass filter 104 filters glitches of the external wake-up signal and outputs a wake-up signal.
[0090] The analog low-pass filter 104 in the analog circuit part 102 is responsible for receiving an external wake-up signal and filtering glitches on the signal, so as to ensure that the subsequent circuit will not produce a false action due to interference. The oscillator 105 is a clock source of the system, which decides whether to start oscillation according to the power-down control signal sent by the clock control module 107, so as to generate a working clock required by a digital system.
[0091] The wake-up control module 106 in the digital circuit part 103 is designed by an asynchronous digital circuit, which is responsible for edge detection on the filtered wake-up signal without a system clock, so as to accurately identify an effective wake-up event and generate a wake-up event signal. The clock control module 107 is the core of the present disclosure, which is designed asynchronously, directly controls the enablement of the oscillator 105, and is responsible for control logic such as clock division. The system state machine 108 is a control core of the circuit system, which is responsible for switching between a normal working mode and a sleep mode.
[0092] The signal connection and cooperation relationship between the modules are as follows:
[0093] The output of the analog low-pass filter 104 is connected to the input of the wake-up control module 106 and the clock control module 107, and provides a filtered wake-up signal for them. The output of the oscillator 105 is used as a clock signal for the wake-up control module 106, the clock control module 107 and the system state machine 108, or the output of the oscillator 105 is transmitted to the clock control module 107 and the system state machine 108 through the frequency division circuit of the clock control module 107 after being frequency-divided. Meanwhile, the clock control module 107 outputs a power-down control signal to the oscillator 105, when the signal is at low level, the oscillator 105 works normally, and when the signal is at high level, the oscillator 105 is turned off and stops outputting the clock.
[0094] The system state machine 108 outputs a sleep mode signal to the clock control module 107 to inform whether the system is in the sleep state. When the wake-up control module 106 detects a valid wake-up signal, it sends a wake-up event signal to the system state machine 108 to trigger the system to exit the sleep mode.
[0095] As shown in FIG. 1, Figure 2 a working principle diagram of the asynchronous wake-up circuit system 101 is provided. The asynchronous wake-up circuit system 101 is powered on and initialized to enter a normal working mode, at this time, the working power consumption of the system is high. Then, if the system receives an instruction of entering a low-power sleep mode sent by an upper computer, the system state machine 108 will jump to the sleep mode accordingly. If the instruction is not received, the system will continue to maintain in the normal working mode.
[0096] After entering the sleep mode, the wake-up control module 106 will first record the level state of the current external wake-up signal, and then the clock control module 107 will turn off the oscillator 105, and the digital clock will not flip. At this time, the power consumption of the oscillator 105 itself is reduced to zero, and the dynamic power consumption of the digital circuit 103 part is also reduced to zero due to the stop of the input clock, and the system as a whole enters a low-power sleep state.
[0097] When the system needs to be woken up again, if the level of the external input wake-up signal flips after being filtered, the oscillator 105 is enabled and the digital clock flips. If the level of the external input wake-up signal does not flip after being filtered, the system remains in the sleep mode.
[0098] The wake-up control module 106 filters and edge detects the wake-up signal, and generates a wake-up event when detecting a valid edge of the wake-up signal. Then the wake-up event is input into the system state machine 108, the system exits the sleep mode and wakes up quickly, at this time, the clock control module 107 also completes the reset, and prepares for the next time the system enters the sleep mode, and thus the system enters the normal working mode.
[0099] The asynchronous wake-up circuit system provided by the present disclosure completely closes the clock source when the system is in sleep state through the asynchronous circuit, thereby achieving zero dynamic power consumption. Meanwhile, when an external wake-up event occurs, the system can directly and quickly restart the clock through the asynchronous circuit, ensuring fast switching from the sleep mode to the normal working mode. Thus, the present disclosure effectively solves the dual problems of the traditional clock gating technology which cannot eliminate the dynamic power consumption in the sleep state and the power gating technology which has long wake-up delay.
[0100] Embodiment 2
[0101] This embodiment further limits the clock control module 107 based on Embodiment 1, as shown in the figure, the clock control module 107 includes: a wake-up signal processing unit array 10, a sleep mode signal transmission unit 20, a logic combination unit 30, and an oscillator enable control unit 40. Figure 3
[0102] The wake-up signal processing unit array 10 is composed of multiple wake-up signal processing units with the same structure, and each unit respectively receives an external wake-up signal and a sleep mode signal sent by the system state machine 108. When any one of the multiple wake-up signals has a level inversion and the sleep mode signal is at a high level (i.e., the system is in a sleep state) at this time, the corresponding wake-up signal processing unit will output a low-level signal; and if the sleep mode signal is at a low level (the system is in a working state), the wake-up signal processing unit will output a high-level signal regardless of the wake-up signal.
[0103] The sleep mode signal transmission unit 20 receives the sleep mode signal and the clock signal, and its output will be converted to a high level at the rising edge of the clock signal.
[0104] The logic combination unit 30 simultaneously receives the output signals of all wake-up signal processing units and an external reset signal. As long as any one of these input signals is at a low level, the logic combination unit 30 outputs a high level; only when all input signals are at a high level, the logic combination unit 30 outputs a low level.
[0105] The final oscillator enable control unit 40 receives the output of the logic combination unit 30 and the system clock signal, and outputs a power-down control signal. Once the output of the logic combination unit 30 is at a high level, the oscillator enable control unit 40 immediately outputs a low level, thereby quickly turning on the oscillator 105; and when the output of the logic combination unit 30 is at a low level, it will output a high level at the falling edge of the clock signal, thereby turning off the oscillator 105, at this time the dynamic power consumption of the digital circuit part 103 is zero, and the system works in a low-power mode.
[0106] Through the coordinated work of the above units, the clock control module 107 achieves a rapid response to the asynchronous wake-up signal in sleep mode and can automatically reset after waking up, preparing for the next sleep and wake-up cycle of the system.
[0107] In one alternative implementation, such as Figure 4 As shown, each wake-up signal processing unit in the wake-up signal processing unit array 10 includes:
[0108] First rising edge D flip-flop ( Figure 4 The diagram shows RD1), the first falling-edge D flip-flop (...). Figure 4 The diagram shows FD1 and the first AND gate ( ). Figure 4 AND1 is shown in the middle.
[0109] Among them, the second input terminal of the D flip-flop on the first rising edge ( Figure 4 The clock input (clk) of RD1 is shown in the diagram, which receives the wake-up signal; the first input of the D flip-flop on the first rising edge ( Figure 4 The diagram shows the data input terminal D of RD1 and the first input terminal (D) of the first falling edge D flip-flop. Figure 4 The diagram shows that the data input terminal D of FD1 is grounded;
[0110] The third input terminal of the D flip-flop on the first rising edge ( Figure 4 The diagram shows the set input (Set) of RD1 and the third input of the first falling edge D flip-flop (…). Figure 4 The image shows the set input terminal (Set) of FD1 receiving data after passing through the first inverter (…). Figure 4 The image shows the sleep mode signal processed by INV1;
[0111] The outputs of the first rising edge D flip-flop and the first falling edge D flip-flop are both electrically connected to the input of the first AND gate.
[0112] The logic combination unit 30 includes:
[0113] Second AND gate ( Figure 4 The diagram shows AND2 and the first NAND gate ( Figure 4 NAND1 is shown in the image.
[0114] The input terminal of the second AND gate is electrically connected to the output terminal of the wake-up signal processing unit;
[0115] The output of the second AND gate is electrically connected to the first input of the first NAND gate, and the external reset signal is electrically connected to the second input of the first NAND gate.
[0116] The sleep mode signal transmission unit 20 includes:
[0117] Second rising edge D flip-flop (Figure 4 a third AND gate (AND3) is shown in RD2), a second inverter (INV2), and a third inverter (INV3). Figure 4 a third AND gate (AND3) is shown in RD2), a second inverter (INV2), and a third inverter (INV3). Figure 4 a third AND gate (AND3) is shown in RD2), a second inverter (INV2), and a third inverter (INV3). Figure 4 a third AND gate (AND3) is shown in RD2), a second inverter (INV2), and a third inverter (INV3).
[0118] The first input end (D) of the second rising edge D flip-flop is electrically connected with the data input end D of RD2. Figure 4 The first input end (D) of the second rising edge D flip-flop is electrically connected with the data input end D of RD2.
[0119] The second input end (clk) of the second rising edge D flip-flop is electrically connected with the clock input end clk of RD2. Figure 4 The second input end (clk) of the second rising edge D flip-flop is electrically connected with the clock input end clk of RD2.
[0120] The third input end (Reset) of the second rising edge D flip-flop is electrically connected with the reset input end Reset of RD2. Figure 4 The third input end (Reset) of the second rising edge D flip-flop is electrically connected with the reset input end Reset of RD2.
[0121] The output end of the second rising edge D flip-flop is electrically connected with the second input end of the third AND gate through the third inverter; the first input end of the third AND gate receives the sleep mode signal.
[0122] The oscillator enable control unit 40 comprises a second falling edge flip-flop:
[0123] The output end of the sleep mode signal transmission unit 20 is electrically connected with the first input end (D) of the second falling edge flip-flop (FD2). Figure 4 The output end of the sleep mode signal transmission unit 20 is electrically connected with the first input end (D) of the second falling edge flip-flop (FD2). Figure 4 The output end of the sleep mode signal transmission unit 20 is electrically connected with the first input end (D) of the second falling edge flip-flop (FD2).
[0124] The third input end (Reset) of the second falling edge flip-flop is electrically connected with the reset input end Reset of FD2. Figure 4 The third input end (Reset) of the second falling edge flip-flop is electrically connected with the reset input end Reset of FD2.
[0125] The second input end (clk) of the second falling edge flip-flop receives the clock signal. Figure 4 Figure 4 The second input end (clk) of the second falling edge flip-flop receives the clock signal.
[0126] The asynchronous wake-up circuit system 101 is powered on and initialized to enter a normal working mode. If the system receives an instruction of entering a low-power sleep mode sent by an upper computer, the system state machine 108 will jump to the sleep mode accordingly. After the system enters the sleep mode, the sleep mode signal is transmitted to the clock control module. The sleep mode signal transmission unit 20 transmits a high-level signal to the oscillator enable control unit 40. At the moment of the clock falling edge, the oscillator enable control unit 40 outputs a high-level signal to the oscillator 105. At this time, the oscillator 105 module is closed and no clock output is generated. At this time, the dynamic power consumption of the whole system is zero.
[0127] When the host computer wants to wake up the system, it only needs to flip the level of the external wake-up signal. At this time, the first rising edge D flip-flop or the first falling edge D flip-flop of the wake-up signal processing unit transmits the data input end signal of the D flip-flop to the output end. Since the data input end signal is grounded, the wake-up signal processing unit outputs a low-level signal, which is then transmitted to the input end of the logic combination unit 30, and outputs a high-level signal to the reset input end of the oscillator enable control unit 40. At this time, the oscillator enable control unit 40 outputs a low-level signal to the oscillator 105, and the oscillator 105 works normally to provide a clock signal to the digital circuit part 103.
[0128] After waking up the system, the clock control module 107 also needs to be reset to prepare for the next time the system enters the sleep mode. When it needs to be reset, the external reset signal is low, which is directly transmitted to the input end of the logic combination unit 30. The logic combination unit 30 outputs a high-level signal to the reset input end of the oscillator enable control unit 40. At this time, the oscillator enable control unit 40 outputs a low-level signal to the oscillator 105, and the oscillator 105 works normally. The entire asynchronous wake-up circuit system 101 enters the normal working mode.
[0129] Through the combination of flip-flops and logic gates, the clock control module 107 can reliably judge and quickly respond in various system states. The system has extremely low power consumption in the sleep state, and the response to the external wake-up signal is sensitive and stable. The entire wake-up process is orderly and controllable, preventing false wake-up and system startup disorder, and greatly improving the reliability and stability of low-power devices.
[0130] Although the specific embodiments of the present disclosure are described above, those skilled in the art should understand that this is only an example. The protection scope of the present disclosure is defined by the appended claims. Those skilled in the art can make various changes or modifications to these embodiments without departing from the principles and essence of the present disclosure. These changes and modifications all fall within the protection scope of the present disclosure.
Claims
1. Asynchronous wake-up circuitry, characterized by, The asynchronous wake-up circuit system is divided into an analog circuit part and a digital circuit part; The analog circuit part comprises an oscillator; The digital circuit part comprises a wake-up control module, a clock control module and a system state machine; An output end of the oscillator provides a clock signal to the clock control module, and an input end of the oscillator receives a power-off control signal output by the clock control module; A first input end of the wake-up control module receives a wake-up signal, an output end of the wake-up control module is electrically connected to an input end of the system state machine, and a second input end of the wake-up control module receives the clock signal; A first input end of the clock control module receives the wake-up signal, a second input end of the clock control module receives the clock signal, and a third input end of the clock control module receives a sleep mode signal output by the system state machine; A mode output end of the system state machine is electrically connected to the third input end of the clock control module, a first input end of the system state machine is electrically connected to the output end of the wake-up control module, and a second input end of the system state machine receives the clock signal; The clock control module is implemented by an asynchronous circuit, and in response to a level inversion of the wake-up signal and the sleep mode signal being high, the clock control module outputs a low-level power-off control signal; In response to the sleep mode signal being low, the clock control module outputs a high-level power-off control signal; The oscillator outputs the clock signal in response to the power-off control signal output by the clock control module being low; In response to the power-off control signal output by the clock control module being high, the oscillator outputs no signal; The wake-up control module is implemented by an asynchronous circuit, and is configured to receive the wake-up signal and output a wake-up event without the clock signal; The system state machine outputs the sleep mode signal in response to receiving an instruction of entering a sleep mode sent by an upper computer; In response to receiving the wake-up event, the system state machine exits the sleep mode and enters a normal working mode.
2. The asynchronous wake-up circuitry of claim 1, wherein, The digital circuit part further comprises an analog low-pass filter; An input end of the analog low-pass filter receives an external wake-up signal, and an output end of the analog low-pass filter is electrically connected to a first input end of the wake-up control module and a first input end of the clock control module; The analog low-pass filter filters glitches of the external wake-up signal and outputs the wake-up signal.
3. Asynchronous wake-up circuitry as claimed in claim 2, characterized in that, The clock control module comprises a wake-up signal processing unit array, a sleep mode signal transmission unit, a logic combination unit and an oscillator enable control unit; The wake-up signal processing unit array comprises a plurality of wake-up signal processing units with the same structure; The wake-up signal processing unit is electrically connected to the logic combination unit; The logic combination unit is electrically connected to the oscillator enable control unit; The sleep mode signal transmission unit is electrically connected to the oscillator enable control unit; An input end of each wake-up signal processing unit receives the wake-up signal and the sleep mode signal respectively. The input end of the sleep mode signal transmission unit receives the sleep mode signal and the clock signal, and outputs a high level signal in response to the rising edge of the clock signal when the sleep mode signal is at a high level; The input end of the logic combination unit receives the output signal of the wake-up signal processing unit and an external reset signal; The logic combination unit outputs a high level signal in response to at least one of the output signal of the wake-up signal processing unit and the external reset signal being at a low level; The logic combination unit outputs a low level signal in response to the output signal of the wake-up signal processing unit and the external reset signal both being at a high level; The input end of the oscillator enable control unit receives the output signal of the logic combination unit and the clock signal; The power-down control signal output by the oscillator enable control unit is at a low level in response to the output signal of the logic combination unit being at a high level; The power-down control signal output by the oscillator enable control unit is at a high level in response to the falling edge of the clock signal and the output signal of the logic combination unit being at a low level.
4. The asynchronous wake-up circuitry of claim 3, wherein, The wake-up signal processing unit comprises: a first rising edge flip-flop, a first falling edge flip-flop, and a first AND gate; wherein the second input end of the first rising edge flip-flop and the second input end of the first falling edge flip-flop receive the wake-up signal; and / or, the first input end of the first rising edge flip-flop and the first input end of the first falling edge flip-flop are grounded; the output end of the first rising edge flip-flop is electrically connected with the input end of the first AND gate; the output end of the first falling edge flip-flop is electrically connected with the input end of the first AND gate.
5. Asynchronous wake-up circuitry as claimed in claim 4, characterized in that, The clock control module further comprises a first inverter, and the third input end of the first rising edge flip-flop and the first falling edge flip-flop receives the sleep mode signal processed by the first inverter; the first input end of the first rising edge flip-flop and the first falling edge flip-flop is a data input end; the second input end of the first rising edge flip-flop and the first falling edge flip-flop is a clock input end; the third input end of the first rising edge flip-flop and the first falling edge flip-flop is a set input end.
6. The asynchronous wake-up circuitry of claim 5, wherein, The logic combination unit comprises: a second AND gate and a first NAND gate; wherein the input end of the second AND gate is electrically connected with the output end of the wake-up signal processing unit; the output end of the second AND gate is electrically connected with the first input end of the first NAND gate; the second input end of the first NAND gate receives the external reset signal.
7. The asynchronous wake-up circuitry of claim 6, wherein, The sleep mode signal transmission unit comprises: a second rising edge flip-flop, a third AND gate, a second inverter, and a third inverter; wherein the first input end of the second rising edge flip-flop receives the sleep mode signal; the second input end of the second rising edge flip-flop receives the clock signal; the third input end of the second rising edge flip-flop receives the external reset signal processed by the second inverter; the output end of the second rising edge flip-flop is electrically connected with the second input end of the third AND gate through the third inverter; A first input terminal of the third AND gate receives the sleep mode signal.
8. The asynchronous wake-up circuitry of claim 7, wherein, A first input terminal of the second rising edge flip-flop is a data input terminal, a second input terminal of the second rising edge flip-flop is a clock input terminal, and a third input terminal of the second rising edge flip-flop is a reset input terminal.
9. The asynchronous wake-up circuitry of claim 8, wherein, The oscillator enable control unit comprises a second falling edge flip-flop: An output terminal of the sleep mode signal transmission unit is electrically connected to a first input terminal of the second falling edge flip-flop. An output terminal of the logic combination unit is electrically connected to a third input terminal of the second falling edge flip-flop. A second input terminal of the second falling edge flip-flop receives the clock signal.
10. The asynchronous wake-up circuitry of claim 9, wherein, A first input terminal of the second falling edge flip-flop is a data input terminal, a second input terminal of the second falling edge flip-flop is a clock input terminal, and a third input terminal of the second falling edge flip-flop is a reset input terminal.