Direct digital synthesis method and system based on mixed fraction proportion

Abstract

The invention discloses a direct digital synthesis method and system based on a mixed fraction proportion. The method comprises the following steps: determining an integer frequency control word, a numerator frequency control word and a denominator frequency control word based on a target frequency, a sampling frequency and a bit width of a phase accumulator; performing a fractional phase accumulation operation based on the sampling frequency, the molecular frequency control word, and the phase accumulator to generate a carry signal; performing integer phase carry and accumulation operation in parallel with the fractional phase accumulation operation according to the sampling frequency, the integer frequency control word and the phase accumulator to obtain an integer phase value; and acquiring a waveform digital amplitude corresponding to the integer phase value, and performing signal conversion according to the waveform digital amplitude to obtain an amplitude signal corresponding to the target frequency so as to improve the precision of the frequency synthesis signal.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a direct digital synthesis method and system based on mixed fraction ratio. BACKGROUND

[0002] In modern mixed signal processing system, it is inevitable to need signals with multiple frequencies, wherein different frequency signals can be used as reference of signal processing link in analog circuit; when signals with frequencies are used as clock signal in digital circuit, they are used for synchronization between digital circuits and sampling timing of ADC / DAC. Therefore, signal generator with high quality and controllable target frequency becomes necessary component in modern mixed signal processing system.

[0003] For frequency signals requiring accurate phase or frequency synchronization, PLL (Phase Locked Loop) or DDS (Direct Digital Synthesis System) components are generally used to generate signals with the same source clock. In order to improve the integration of the system, in the case of resource permission, the programmable logic of FPGA (Field Programmable Gate Array) can be used to realize the DDS function, and the external DAC (Digital Analog Converter) can be used to realize the reference signal generation function. However, the problem of the above method for generating signals with target frequency is that if the ratio of target frequency to sampling frequency cannot be expressed as a finite decimal number (such as 1 / 6, 1 / 7, etc.) in binary, an error will be generated between the frequency of the generated signal and the target frequency; at the same time, if the ratio of target frequency to sampling frequency can be expressed as a finite decimal number in binary, but the bit length is too long, the DDS will need a very long phase accumulator bit width to accommodate the corresponding decimal part, resulting in larger resource occupation and smaller timing margin. SUMMARY

[0004] In order to solve the above technical problems, the present application discloses a direct digital synthesis method and system based on mixed fraction ratio, which is used to improve the frequency accuracy of digital synthesis.

[0005] In order to achieve the above purpose, the present application discloses a direct digital synthesis method based on mixed fraction ratio, comprising: determining a frequency control word based on target frequency, sampling frequency and bit width of phase accumulator, and splitting the frequency control word into integer frequency control word, numerator frequency control word and denominator frequency control word; performing fraction phase accumulation operation based on the sampling frequency, the numerator frequency control word and the phase accumulator to generate a carry signal; wherein the fraction phase accumulation operation comprises obtaining the accumulation result of the numerator frequency control word according to the phase accumulator, so as to generate the carry signal according to the accumulation result and the denominator frequency control word; According to the sampling frequency, the integer frequency control word and the phase accumulator, an integer phase accumulation operation is performed in parallel with the fractional phase accumulation operation, to obtain an integer phase value; wherein the integer phase accumulation operation comprises obtaining an accumulation result of the integer frequency control word according to the phase accumulator and the carry signal, to obtain an integer phase value; A waveform digital amplitude value corresponding to the integer phase value is obtained, to perform signal conversion according to the waveform digital amplitude value, to obtain an amplitude signal corresponding to the target frequency.

[0006] The direct digital synthesis method based on mixed fractional ratio disclosed in the application splits the frequency control word into an integer part, a numerator part and a denominator part, performs the fractional phase accumulation and the integer phase accumulation operation in parallel, and dynamically adjusts the integer accumulation process by using the carry signal generated by the fractional accumulation, so as to accurately generate the target frequency signal, and effectively avoids the error caused by the frequency ratio non-finite binary fraction in the traditional direct digital synthesis and the resource occupation problem caused by the long bit width phase accumulator. Specifically, the frequency control word is determined and split, so that the target frequency can be accurately expressed as an integer part and a fractional ratio, which adapts to any frequency ratio and avoids the dependence on the long bit width phase accumulator; the fractional phase accumulation operation feature is realized by accumulating the numerator frequency control word and generating the carry signal when the denominator is reached, which realizes the accurate accumulation of the fractional phase, and the carry signal accurately reflects the overflow state of the fractional part, providing a basis for the adjustment of the integer part; the integer phase accumulation operation feature is that the integer phase value can respond to the overflow of the fractional part in real time by performing the plus one operation according to the carry signal in the integer accumulation, so as to accumulate the accurate total phase value; the waveform is generated based on the accurate integer phase value, to ensure the accuracy of the output signal frequency. These features cooperate with each other: the split of the frequency control word enables the fractional ratio to be processed independently, the fractional accumulation operation generates the carry signal as a bridge, the integer accumulation operation dynamically corrects the phase by using the carry signal, the parallel execution of the two operations ensures the synchronism, and finally the phase without accumulation error is output, which solves the problems of frequency error and resource occupation.

[0007] As a preferred example, the frequency control word is determined based on the target frequency, the sampling frequency and the bit width of the phase accumulator, and the frequency control word is split into an integer frequency control word, a numerator frequency control word and a denominator frequency control word, comprising: The total number of phases of the phase accumulator in a full-scale period is determined according to the bit width of the phase accumulator; The product of the target frequency and the total number of phases is obtained, to obtain the frequency control word by dividing the product by the sampling frequency; The integer frequency control word is obtained by performing the integer operation on the frequency control word, and the remainder of the frequency control word is obtained, to take the remainder as a frequency error component; divide the frequency error component by the sampling frequency to obtain an original fractional frequency control word; wherein the original fractional frequency control word is a ratio of an original numerator frequency control word and an original denominator frequency control word; obtain a greatest common divisor of the original numerator frequency control word and the original denominator frequency control word to obtain a numerator frequency control word and a denominator frequency control word according to the greatest common divisor.

[0008] The above scheme determines the total number of full-scale phases according to the bit width of the phase accumulator, which establishes the hardware basis of the phase resolution and ensures that the subsequent calculation is accurately matched with the actual system capability. Then, the product of the target frequency and the total number of phases is obtained and divided by the sampling frequency to determine the frequency control word, and then the frequency control word is rounded to separate the integer part and extract the frequency error component. The parallel processing of integer and fractional phase accumulation provides a clear boundary, allowing the non-integer frequency component to be processed independently. Further, the frequency error component is divided by the sampling frequency to form an original fractional frequency control word. Finally, the greatest common divisor of the original numerator and denominator is obtained and the fraction is simplified accordingly, so that the bit width required by the fractional phase accumulator is greatly reduced, thereby reducing the hardware resource occupation without sacrificing the frequency accuracy, improving the timing stability of the system, and making the fractional phase accumulation operation more efficient and suitable for resource-limited FPGA implementation environment.

[0009] As a preferred example, the fractional phase accumulation operation is performed based on the sampling frequency, the numerator frequency control word and the phase accumulator to generate a carry signal, including: determining the sampling period of the numerator frequency control word and the integer frequency control word according to the sampling frequency; for any one of the sampling periods, inputting the numerator frequency control word into the fractional phase accumulator to add the numerator frequency control word to the current fractional phase value stored in the fractional phase accumulator to obtain a temporary sum; when the temporary sum is greater than or equal to the denominator frequency control word, controlling the fractional phase accumulator to generate a carry signal and obtain the difference between the temporary sum and the denominator frequency control word, and taking the difference as the current fractional phase value stored in the fractional phase accumulator.

[0010] The above scheme determines the sampling period as the timing reference based on the sampling frequency, which ensures that the fractional phase accumulation operation is strictly synchronized with the system clock, avoiding phase accumulation deviation caused by timing misalignment, thereby laying a timing foundation for accurate processing of the fractional part. In any sampling period, the numerator frequency control word is input into the fractional phase accumulator and added to the current fractional phase value to obtain a temporary sum. The numerator frequency control word represents the numerator component of the fractional ratio, and the fractional phase is gradually increased through continuous accumulation. The special feature is that the numerator frequency control word directly drives the phase increment calculation, avoiding resource waste caused by excessive binary decimal digits in traditional methods, while retaining the complete information of the fractional part. When the temporary sum is greater than or equal to the denominator frequency control word, a carry signal is generated and the current fractional phase value is updated by the difference value. This mechanism triggers the carry by dynamically comparing the temporary sum with the threshold (i.e., the denominator of the fractional frequency control word), ensuring that the carry signal is accurately generated only when the fractional phase accumulation reaches an integer unit. The difference value as the new current value operation completely retains the fractional remainder, preventing phase overflow and maintaining phase continuity, thereby significantly improving the accuracy and stability of non-integer ratio frequency synthesis.

[0011] As a preferred example, the fractional phase accumulation operation is performed based on the sampling frequency, the numerator frequency control word, and the phase accumulator to generate a carry signal, including: For any one of the sampling periods, when the temporary sum is less than the denominator frequency control word, the temporary sum is saved as the current fractional phase value saved by the fractional phase accumulator.

[0012] The above scheme accurately handles the boundary conditions in fractional phase accumulation, ensuring the continuity and integrity of the fractional accumulation process. Specifically, for each sampling period, when the temporary sum is less than the denominator frequency control word, the temporary sum is directly used as the new current fractional phase value. This operation retains the accumulation state of the fractional part, avoiding incorrect resetting or loss of the phase value under non-carry conditions. This real-time updating mechanism based on the temporary sum effectively maintains the continuous accumulation of the fractional phase, providing a reliable foundation for accurate generation of the carry signal, thereby eliminating frequency errors caused by incomplete fractional processing and improving the output accuracy of the direct digital synthesis system under complex frequency ratios.

[0013] As a preferred example, the integer phase accumulation operation is performed in parallel with the fractional phase accumulation operation based on the sampling frequency, the integer frequency control word, and the phase accumulator to obtain an integer phase value, including: For any one of the sampling periods, the integer frequency control word is input into the integer phase accumulator, so that the integer frequency control word is added to the current integer phase value saved in the integer phase accumulator to obtain a temporary integer phase value; when the carry signal is received, controlling the integer phase accumulator to perform a plus one operation on the temporary integer phase value to obtain a real-time integer phase value output by the integer phase accumulator in the sampling period and taking the real-time integer phase value as a current integer phase value saved in the integer phase accumulator.

[0014] The above scheme effectively solves the accumulated error problem of the integer phase value when the fraction carries by designing a parallel execution mechanism of the integer phase accumulation operation and the fraction phase accumulation operation and introducing an immediate correction strategy triggered by the carry signal, thereby ensuring the accuracy of the target frequency generation. Specifically, the integer phase accumulation operation is performed in parallel according to the sampling frequency, the integer frequency control word and the phase accumulator, which avoids the timing deviation that may be caused by sequential execution by synchronously processing the phase accumulation of the integer and fraction parts. When the carry signal is received, the integer phase accumulator is controlled to perform a plus one operation on the temporary integer phase value to obtain a real-time integer phase value output by the integer phase accumulator in the sampling period and take the real-time integer phase value as a current integer phase value saved in the integer phase accumulator, which immediately corrects the temporary value according to the existence of the carry signal, compensates for the phase increment accumulated by the fraction part when the threshold is reached by directly responding to the carry event of the fraction phase accumulation, thereby eliminating the loss of the integer phase value caused by the carry delay, and finally ensuring the integrity of the phase accumulation and the frequency accuracy.

[0015] As a preferred example, the integer phase accumulation operation is performed in parallel with the fraction phase accumulation operation according to the sampling frequency, the integer frequency control word and the phase accumulator to obtain an integer phase value, comprising: For any one of the sampling periods: when the carry signal is received, controlling the integer phase accumulator to perform a plus one operation on the temporary integer phase value to obtain a real-time integer phase value output by the integer phase accumulator in the sampling period and taking the real-time integer phase value as a current integer phase value saved in the integer phase accumulator.

[0016] The above scheme ensures the integrity and accuracy of the phase accumulation process by clearly defining the behavior of the integer phase accumulator under the condition of no carry signal, thereby effectively avoiding the introduction of phase errors. For any sampling period, the operation covers all possible sampling times, ensuring that the system can process phase updates in time within each period, maintaining real-time performance. When no carry signal is received, it indicates that the fractional phase accumulation has not reached the overflow threshold, so the integer part does not need to be additionally added by one. At this time, the temporary integer phase value is directly output as the real-time integer phase value, which can accurately reflect the accumulation result of the integer frequency control word and the current integer phase value, avoiding the phase offset caused by the wrong addition of one. At the same time, the temporary integer phase value is taken as the current integer phase value saved in the integer phase accumulator. This updating mechanism ensures that the current state is correctly passed to the next period, providing an accurate initial value for subsequent accumulation, preventing the accumulation of incorrect phase values. Overall, this scheme dynamically adjusts the integer phase processing logic by closely relying on the state of the carry signal, achieving seamless collaboration between integer and fractional phase accumulation, and fundamentally solving the problem of missing phase updates in the no-carry scenario, ensuring the accurate generation of the target frequency signal.

[0017] As a preferred example, the waveform digital amplitude corresponding to the integer phase value is obtained, and signal conversion is performed according to the waveform digital amplitude to obtain an amplitude signal corresponding to the target frequency, including: obtaining a phase value high bit and a phase value low bit of the integer phase value, and querying a preset waveform lookup table according to the phase value high bit to obtain a basic waveform digital amplitude corresponding to the integer phase value; performing interpolation calculation on the basic waveform digital amplitude according to the phase value low bit to obtain the waveform digital amplitude corresponding to the integer phase value; performing digital-to-analog conversion on the waveform digital amplitude to obtain an analog signal, and filtering the analog signal to obtain an amplitude signal corresponding to the target frequency.

[0018] The above scheme effectively alleviates the influence of phase quantization error on waveform quality by fine processing the internal structure of the integer phase value. Specifically, each integer phase value is decomposed into a phase value high bit and a phase value low bit. This design fully utilizes the high bit value as the stability of the main phase index, while the low bit value captures the subtle changes in the phase, providing a key basis for subsequent interpolation. According to the phase value high bit, the waveform lookup table is queried to obtain the basic waveform digital amplitude, avoiding the problem of excessive size of the lookup table caused by directly using the complete phase value, which not only reduces the hardware resource consumption, but also ensures the fast acquisition of the basic amplitude. And according to the phase value low bit, the basic waveform digital amplitude is interpolated, which smooths the amplitude transition between adjacent phase points through a linear interpolation mechanism, significantly suppressing the stair effect caused by the discontinuity of phase stepping, thereby reducing harmonic distortion. Finally, the digital-to-analog conversion and filtering are performed on the waveform numerical amplitude, which not only converts the digital signal into an analog form, but also eliminates high-frequency noise and image components in the conversion process through filtering, finally outputting a high-fidelity amplitude signal.

[0019] As a preferred example, the obtaining of the waveform digital amplitude corresponding to the integer phase value to perform signal conversion according to the waveform digital amplitude to obtain an amplitude signal corresponding to the target frequency further includes: obtaining a zero-order hold model of the digital-to-analog conversion operation to determine an inverse sinc target frequency response function according to the zero-order hold model and a sampling frequency; compensating the amplitude of each waveform digital amplitude according to the inverse sinc target frequency response function to perform a digital-to-analog conversion operation on the waveform digital amplitude after amplitude compensation to obtain the analog signal.

[0020] The above scheme introduces an amplitude compensation mechanism to specifically solve the frequency response attenuation problem caused by the zero-order hold effect in the digital-to-analog conversion link, thereby improving the amplitude accuracy of the output waveform. Specifically, the zero-order hold model of the digital-to-analog conversion operation is obtained, which accurately captures the inherent characteristics of the digital-to-analog converter in maintaining constant output between sampling points, which is the physical root cause of the sinc function attenuation; the inverse sinc target frequency response function is determined according to the zero-order hold model and the sampling frequency, which accurately deduces the inverse sinc function in combination with the sampling frequency parameter, which is specifically used to offset the sinc attenuation effect to ensure the flattening of the frequency response within the target frequency range; the amplitude of each waveform digital amplitude is compensated according to the inverse sinc target frequency response function, which pre-processes the amplitude in the digital domain by applying the inverse sinc function to dynamically adjust the amplitude, thereby pre-compensating the amplitude loss that will inevitably occur in the subsequent digital-to-analog conversion; the digital-to-analog conversion operation is performed on the waveform digital amplitude after amplitude compensation to obtain the analog signal, which effectively offsets the zero-order hold effect in the conversion process after compensation, and the amplitude of the finally output analog signal is closer to the ideal value, significantly reducing the amplitude distortion.

[0021] As a preferred example, before determining the frequency control word based on the target frequency, the sampling frequency and the bit width of the phase accumulator, and splitting the frequency control word into the integer frequency control word, the numerator frequency control word and the denominator frequency control word, the method comprises: obtaining a resolution ratio of the sampling frequency and a preset sampling resolution, to determine an actual integer bit width of the integer phase accumulator according to the ratio; determining an original denominator frequency control word of the frequency control word according to the target frequency, the sampling frequency and the actual integer bit width; determining an actual fractional bit width of the fractional phase accumulator according to the original denominator frequency control word.

[0022] The above scheme dynamically optimizes the bit width structure of the phase accumulator, significantly reduces the hardware resource demand while ensuring the frequency synthesis accuracy. First, the resolution ratio of the sampling frequency and the preset sampling resolution is obtained to determine the ideal integer bit width of the integer phase accumulator according to the ratio, which ensures that the bit width can match the frequency resolution required by the system, avoids introducing quantization error due to insufficient bit width, and provides a reference for subsequent optimization. Then, the ideal integer bit width is reduced by one based on the integer phase accumulation operation to obtain the actual integer bit width. This one-bit reduction operation takes into account the boundary characteristics of the integer phase accumulation in actual hardware implementation, and by reducing one bit, it not only preserves the key accuracy but also avoids redundant resource occupation, effectively alleviating the contradiction between the number of registers and the timing margin in FPGA. Then, the original denominator frequency control word of the frequency control word is determined according to the target frequency, the sampling frequency and the actual integer bit width, which accurately calculates the denominator part using the adjusted bit width, so that the fractional phase accumulation can more accurately handle the non-integer ratio relationship, thereby suppressing the frequency drift caused by mismatched bit width. Finally, the actual fractional bit width of the fractional phase accumulator is determined according to the original denominator frequency control word, which dynamically adapts the bit number demand of the fractional part, only allocates the minimum bit width required to represent the denominator, avoids the resource waste in the fixed bit width scheme, and improves the realizability of the system in the resource-limited environment.

[0023] On the other hand, the application discloses a direct digital synthesis system based on a mixed fractional ratio, comprising a control word splitting module, a fractional phase accumulation module, an integer phase accumulation module and a waveform conversion module. The control word splitting module is used to determine the frequency control word based on the target frequency, the sampling frequency and the bit width of the phase accumulator, and split the frequency control word into the integer frequency control word, the numerator frequency control word and the denominator frequency control word. The fractional phase accumulation module is configured to perform a fractional phase accumulation operation based on the sampling frequency, the numerator frequency control word and the phase accumulator to generate a carry signal; wherein the fractional phase accumulation operation comprises obtaining an accumulation result of the numerator frequency control word according to the phase accumulator to generate the carry signal according to the accumulation result and the denominator frequency control word; The integer phase accumulation module is configured to perform an integer phase accumulation operation according to the sampling frequency, the integer frequency control word and the phase accumulator in parallel with the fractional phase accumulation operation to obtain an integer phase value; wherein the integer phase accumulation operation comprises obtaining an accumulation result of the integer frequency control word according to the phase accumulator and the carry signal to obtain the integer phase value; The waveform conversion module is configured to obtain a waveform digital amplitude corresponding to the integer phase value to perform signal conversion according to the waveform digital amplitude to obtain an amplitude signal corresponding to the target frequency.

[0024] The direct digital synthesis system based on the mixed fractional ratio disclosed in the application can accurately generate a target frequency signal by splitting a frequency control word into an integer, a numerator and a denominator, performing fractional phase accumulation and integer phase accumulation operations in parallel, and dynamically adjusting the integer accumulation process by using the carry signal generated by fractional accumulation, thereby effectively avoiding the error caused by the non-finite binary fraction of the frequency ratio in the traditional direct digital synthesis and the resource occupation problem caused by the long bit width phase accumulator. Specifically, the frequency control word is determined and split to make the target frequency accurately represented as an integer part and a fractional ratio, which is suitable for any frequency ratio and avoids the dependence on the long bit width phase accumulator; the fractional phase accumulation operation feature realizes the accurate accumulation of the fractional phase by repeatedly accumulating the numerator frequency control word and generating the carry signal when the denominator is reached, the carry signal accurately reflects the overflow state of the fractional part and provides a basis for the adjustment of the integer part; the integer phase accumulation operation feature performs the add-one operation according to the carry signal in the integer accumulation, so that the integer phase value can respond to the overflow of the fractional part in real time, thereby accumulating an accurate total phase value; the waveform is generated based on the accurate integer phase value to ensure the accuracy of the frequency of the output signal. These features cooperate with each other: the split frequency control word makes the fractional ratio independently handled, the carry signal generated by the fractional accumulation operation serves as a bridge, the integer accumulation operation dynamically corrects the phase by using the carry signal, the parallel execution of the two operations ensures the synchronicity, and finally the waveform without cumulative error is output, which solves the problems of frequency error and resource occupation. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the present application, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description only represent some of the embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0026] Figure 1 is a flowchart of a direct digital synthesis method based on a hybrid fractional ratio provided by an embodiment of the present application; Figure 2 is a structural diagram of a direct digital synthesis system based on a hybrid fractional ratio provided by an embodiment of the present application; Figure 3 is a structural diagram of a direct digital synthesis device based on a hybrid fractional ratio provided by another embodiment of the present application; Figure 4 is a flowchart of a direct digital synthesis method based on a hybrid fractional ratio provided by another embodiment of the present application. DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments only represent some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative effort fall within the scope of protection of the present application.

[0028] Referring to Figure 1 To solve the technical problem that the target frequency corresponding frequency signal cannot be accurately generated and a large phase resource is needed for signal generation in the prior art, the present embodiment discloses a direct digital synthesis method based on a hybrid fractional ratio, comprising: Step 101: determining a frequency control word based on a target frequency, a sampling frequency and a bit width of a phase accumulator, and splitting the frequency control word into an integer frequency control word, a numerator frequency control word and a denominator frequency control word.

[0029] In the present embodiment, this step mainly comprises: first, obtaining a resolution ratio of the sampling frequency and a preset sampling resolution, to determine an actual integer bit width of an integer phase accumulator according to the ratio; determining an original denominator frequency control word of the frequency control word according to the target frequency, the sampling frequency and the actual integer bit width; determining an actual fractional bit width of a fractional phase accumulator according to the original denominator frequency control word.

[0030] Secondly, a total number of phases of the phase accumulator in a full-scale period is determined according to a bit width of the phase accumulator; a product of a target frequency and the total number of phases is obtained to determine a frequency control word according to a ratio of the product to a sampling frequency; an integer frequency control word is obtained by rounding the frequency control word; and a frequency error component of the product divided by the sampling frequency is obtained; the frequency error component is divided by the sampling frequency to obtain an original fractional frequency control word; wherein the original fractional frequency control word is a ratio of an original numerator frequency control word to an original denominator frequency control word; a greatest common divisor of the original numerator frequency control word and the original denominator frequency control word is obtained to obtain a numerator frequency control word and a denominator frequency control word according to the greatest common divisor.

[0031] Step 102: performing a fractional phase accumulation operation based on the sampling frequency, the numerator frequency control word and the phase accumulator to generate a carry signal; wherein the fractional phase accumulation operation comprises obtaining an accumulation result of the numerator frequency control word according to the phase accumulator to generate the carry signal according to the accumulation result and the denominator frequency control word.

[0032] In the embodiment, the step mainly comprises: determining sampling periods of the numerator frequency control word and the integer frequency control word according to the sampling frequency; for any one of the sampling periods, inputting the numerator frequency control word into a fractional phase accumulator to add the numerator frequency control word to a current fractional phase value stored in the fractional phase accumulator to obtain a temporary sum; when the temporary sum is greater than or equal to the denominator frequency control word, controlling the fractional phase accumulator to generate a carry signal and obtain a difference between the temporary sum and the denominator frequency control word, and taking the difference as the current fractional phase value stored in the fractional phase accumulator.

[0033] For any one of the sampling periods, when the temporary sum is less than the denominator frequency control word, taking the temporary sum as the current fractional phase value stored in the fractional phase accumulator.

[0034] Step 103: performing an integer phase accumulation operation in parallel with the fractional phase accumulation operation according to the sampling frequency, the integer frequency control word and the phase accumulator to obtain an integer phase value; wherein the integer phase accumulation operation comprises obtaining an accumulation result of the integer frequency control word according to the phase accumulator and the carry signal to obtain the integer phase value.

[0035] In the embodiment, the step mainly includes: for any one of the sampling periods, inputting the integer frequency control word into the integer phase accumulator to add the integer frequency control word and a current integer phase value stored in the integer phase accumulator to obtain a temporary integer phase value; when the carry signal is received, controlling the integer phase accumulator to perform an add-one operation on the temporary integer phase value to obtain a real-time integer phase value output by the integer phase accumulator in the sampling period and taking the real-time integer phase value as the current integer phase value stored in the integer phase accumulator.

[0036] For any one of the sampling periods: when the carry signal is not received, controlling the integer phase accumulator to output the temporary integer phase value as the real-time integer phase value and taking the temporary integer phase value as the current integer phase value stored in the integer phase accumulator.

[0037] Step 104: obtaining a waveform digital amplitude corresponding to the integer phase value to perform signal conversion according to the waveform digital amplitude to obtain an amplitude signal corresponding to the target frequency.

[0038] In the embodiment, the step mainly includes: obtaining a phase value high bit and a phase value low bit of the integer phase value to query a preset waveform lookup table according to the phase value high bit to obtain a basic waveform digital amplitude corresponding to the integer phase value; performing interpolation calculation on the basic waveform digital amplitude according to the phase value low bit to obtain a waveform digital amplitude corresponding to the integer phase value; performing digital-to-analog conversion on the waveform digital amplitude to obtain an analog signal, and filtering the analog signal to obtain an amplitude signal corresponding to the target frequency.

[0039] In the embodiment, a zero-order hold model of the digital-to-analog conversion is obtained to determine a inverse-sine target frequency response function according to the zero-order hold model and a sampling frequency; and each waveform digital amplitude is amplitude-compensated according to the inverse-sine target frequency response function to perform digital-to-analog conversion on the waveform digital amplitude after amplitude compensation to obtain the analog signal.

[0040] On the other hand, with reference to Figure 2 The embodiment further discloses a direct digital synthesis system based on mixed fractional ratios, which comprises a control word splitting module 201, a fractional phase accumulation module 202, an integer phase accumulation module 203, and a waveform conversion module 204.

[0041] The control word splitting module 201 is configured to determine a frequency control word based on a target frequency, a sampling frequency, and a bit width of a phase accumulator, and split the frequency control word into an integer frequency control word, a numerator frequency control word, and a denominator frequency control word.

[0042] The fractional phase accumulation module 202 is configured to perform a fractional phase accumulation operation based on the sampling frequency, the numerator frequency control word and the phase accumulator, to generate a carry signal; wherein the fractional phase accumulation operation comprises obtaining an accumulation result of the numerator frequency control word according to the phase accumulator, to generate the carry signal according to the accumulation result and the denominator frequency control word.

[0043] The integer phase accumulation module 203 is configured to perform an integer phase accumulation operation according to the sampling frequency, the integer frequency control word and the phase accumulator, in parallel with the fractional phase accumulation operation, to obtain an integer phase value; wherein the integer phase accumulation operation comprises obtaining an accumulation result of the integer frequency control word according to the phase accumulator and the carry signal, to obtain the integer phase value.

[0044] The waveform conversion module 204 is configured to obtain a waveform digital amplitude value corresponding to the integer phase value, to perform signal conversion according to the waveform digital amplitude value, to obtain an amplitude signal corresponding to the target frequency.

[0045] Embodiment two The embodiment further provides a direct digital synthesis method based on a hybrid fractional ratio, specifically, referring to Figure 3 , first, according to the DDS, i.e. according to the digital synthesis logic of the direct digital synthesizer, a fractional phase accumulator of a control word of a fractional part in a frequency control word and an integer phase accumulator of an integer part are constructed respectively, to continuously generate an integer phase sequence corresponding to a target frequency, which is formed by a plurality of integer phase values sequentially ordered according to time, through data interaction of the fractional phase accumulator and the integer phase accumulator, and then generate a frequency signal of the target frequency according to an amplitude signal corresponding to each of the integer phase values in the integer phase sequence.

[0046] Specifically, referring to Figure 3 , the direct digital synthesizer constructed based on the internal logic of the DDS comprises a fractional phase accumulator, an integer phase accumulator, a selector, a comparator, a phase interpolator, an inverse Sinc filter, a digital-to-analog converter and an analog reconstruction filter; wherein the fractional phase accumulator comprises a fractional register, a fractional adder and a fractional subtractor; the integer phase accumulator comprises an integer register and an integer adder.

[0047] Referring to Figure 3The output terminals of the fractional adder and the fractional subtractor are respectively connected in signal mode with the input terminals of the selector; the output terminal of the fractional register is connected in signal mode with the input terminal of the comparator; the first output terminal of the comparator is connected in signal mode with the input terminal of the selector; the second output terminal of the comparator is connected in signal mode with the input terminal of the integer adder; the output terminal of the integer adder is connected in signal mode with the input terminal of the integer register; the output terminal of the integer register is connected in signal mode with the input terminal of the integer adder and the input terminal of the phase interpolator; the output terminal of the selector is connected in signal mode with the input terminal of the fractional register; the output terminal of the phase interpolator is connected in signal mode with the input terminal of the inverse Sinc filter; the output terminal of the inverse Sinc filter is connected in signal mode with the input terminal of the digital-to-analog converter; the output terminal of the digital-to-analog converter is connected in signal mode with the input terminal of the analog reconstruction filter; and the analog reconstruction filter is configured to output a frequency signal corresponding to the target frequency.

[0048] Referring to Figure 4 The hybrid fractional ratio-based direct digital synthesizer provided in the embodiment is used to implement the hybrid fractional ratio-based direct digital synthesis method. Figure 3 The flowchart of the hybrid fractional ratio-based direct digital synthesis method performed by the direct digital synthesizer shown in FIG. 1 mainly includes steps 401 to 404. Step 401: Determine the bit width of the integer phase accumulator and the bit width of the fractional phase accumulator based on the target frequency, the sampling frequency and the preset sampling resolution.

[0049] In the embodiment, the process of determining the bit width of the phase accumulator includes two parallel steps of determining the integer phase accumulator bit width and determining the fractional phase accumulator bit width, wherein the process of determining the integer phase bit width of the integer phase accumulator is as follows. Determine the minimum output frequency required by the digital synthesis or the frequency resolution required, calculate the minimum value range that the integer phase accumulator needs to accommodate according to the ratio of the frequency of the sampling clock (i.e., the sampling frequency) and the frequency resolution, and then determine the ideal integer bit width of the integer phase accumulator according to the minimum value range; then, perform a minus one operation on the ideal integer bit width based on the preset integer phase accumulation operation to obtain the actual integer bit width of the integer phase accumulator. Specifically, in an embodiment of the embodiment, the bit width selection manner of the phase accumulator is related to the sampling frequency Fs, the accuracy requirement of the output frequency Fo, the proportional relationship between the output frequency Fo and Fs, and the number of available logic resources. The value that can be represented by the fractional phase accumulator must be greater than the calculated denominator value of the fractional frequency control word; and the value that can be represented by the integer phase accumulator must be greater than the value of the sampling frequency divided by the minimum output frequency.

[0050] For the integer phase bit width selection of the integer phase accumulator, in the case that Fs = 100MHz (megahertz) is required and the frequency resolution Fr < 2kHz (kilohertz) is required, the determination process of the integer phase bit width is as follows: Fs / Fr = 50000; - 1>Fs / Fr; According to the above determination process, the integer phase bit width needs to be selected as 16 binary bits (2 16 - 1 =65535)as the ideal integer bit width of the integer phase accumulator. It needs to be noted that in order to make the target frequency processed by the phase accumulator be able to change between 0 and Fs / 2, that is, 0 Fo 0.5Fs, the bit width of the integer frequency control word is actual integer bit width -1 (binary), that is, if the actual integer bit width is 16 binary bits, the bit width of the integer frequency control word should be 15 binary bits.

[0051] Secondly, for the bit width selection of the fractional phase accumulator, according to the target frequency (Fo), the sampling frequency (Fs) and the determined integer phase accumulator bit width (Pac_N), the fractional frequency control word is calculated, and the fractional frequency control word is reduced to the simplest fractional form to obtain the original denominator frequency control word. The fractional phase accumulator needs to be able to accommodate the original denominator frequency control word, and the calculation formula of the actual fractional bit width of the fractional phase accumulator is as follows: In the case that Fs = 100MHz and Fo = 3 + 1 / 3MHz, the reduced fractional frequency control word value is 8 / 15, and the value that the fractional phase accumulator can represent must be greater than the denominator of the fractional frequency control word, that is, -1>15 needs to be true, so 5 binary bits can be selected as the actual fractional bit width of the fractional phase accumulator; wherein the represents the actual fractional bit width of the fractional phase accumulator.

[0052] In another embodiment of the present embodiment, in the case that Fs = 100MHz, Pac_N = 16bits (binary bits), and Fo = 22.5792MHz, Fcw = 22.5792 * 2 16 / 100 = 14797 + 504512 / 1000000; K = GCD(504512, 1000000) = 64; Fcw = 14797 + (504512 / 64) / (1000000 / 64) = 14797 + 7883 / 15625 (reduction). Then - 1>15625 needs to be true, so 14 binary bits (214 -1 = 16383, 16383>15625) as the actual fractional bit width of the fractional phase accumulator. Wherein, the Fcw represents the frequency control word, and the K represents the greatest common divisor of the numerator and the denominator.

[0053] Step 402: determining a frequency control word based on the target frequency, the sampling frequency and the bit width, and splitting the frequency control word into an integer frequency control word, a numerator frequency control word and a denominator frequency control word.

[0054] In this embodiment, the step mainly includes: first, determining the total number of phases of the phase accumulator in a full-scale period according to the bit width of the phase accumulator, obtaining the product of the target frequency and the total number of phases, and determining the frequency control word according to the ratio of the product to the sampling frequency. Wherein, the frequency control word is calculated as follows: Fcw = (Fo * ) / Fs Wherein, the Fcw represents the frequency control word; the Fo represents the target frequency; the Fs represents the sampling frequency of the sampling clock; and the Pac_N represents the actual integer bit width of the integer phase accumulator.

[0055] Secondly, performing an integer operation on the frequency control word to obtain an integer frequency control word, obtaining the frequency error component of the product divided by the sampling frequency, and making the frequency error component at the sampling frequency to obtain an original fractional frequency control word, obtaining the greatest common divisor of the original numerator frequency control word and the original denominator frequency control word, and obtaining the numerator frequency control word and the denominator frequency control word according to the greatest common divisor. Specifically, the process of obtaining the numerator frequency control word and the denominator frequency control word is as follows: Fcw_i = (Fo * ) / Fs; Fcw_r = ((Fo * ) MOD Fs) / Fs Wherein, Fcw_i is the integer frequency control word, Fcw_r is the fractional frequency control word, Pac_N is the integer part phase accumulator bit width, and Pac_R is the fractional phase accumulator bit width; MOD represents the remainder operation, which converts Fcw into a fractional form by taking the remainder; and GCD represents the greatest common divisor operator, which is used to reduce the fractional part.

[0056] In one embodiment of the present embodiment, the example calculation of the integer frequency control word, the numerator frequency control word and the denominator frequency control word is as follows: Fs = 100 MHz; Fo = 3 + 1 / 3 MHz (Ro = 1 / 30); it is required that Fr < 2 kHz; Pac_N = 16 bits; if an integer DDS is used, the frequency resolution is: Fr = 100M / 65536 = 1525.87 Hz; Fcw = 2184.5333 (decimal truncation, rounding) => 2185; Therefore, the actual output frequency is: Fo_r = Fcw / Fr * Fs = 3.334 MHz; It can be seen that the output frequency error is 0.0007 MHz, and the error is 213 ppm, which is unacceptable in a high-precision scenario. Under the same conditions, keep Pac_N = 16 bits; Fcw_i = 2184 (integer part of the above formula); Fcw_r = ((10 / 3 * 65536) MOD 100) / 100 = 160 / 300; K = GCD(160, 300) = 20; reduce Fcw_r: Fcw_r = (160 / 20) / (300 / 20) = 8 / 15.

[0057] Fill Fcw_i, Fcw_r into the integer part of the frequency control word and the fractional part of the frequency control word of the DDS, and the required frequency of the mixed fractional ratio DDS output can be controlled.

[0058] It can be seen that the output frequency error is 0.0007 MHz, and the error is 213 ppm, which is unacceptable in a high-precision scenario. Under the same conditions, keep Pac_N = 16 bits; Fcw_i = 2184 (integer part of the above formula); Fcw_r = ((10 / 3 * 65536) MOD 100) / 100 = 160 / 300; K = GCD(160, 300) = 20; reduce Fcw_r: Fcw_r = (160 / 20) / (300 / 20) = 8 / 15. Pac_N *Fs = 3 + 1 / 3 MHz. It can be seen that the output frequency error is theoretically 0, and it can fully meet the needs with high-precision Fs.

[0059] Since Fs is generally a relatively large value, directly as the denominator of the fractional part is too large, it requires large bit width registers, adders and multipliers and other resources, which is difficult to realize on a hardware circuit. In order to save resources and power consumption, the fractional part can be selected to be relatively small bit width. Therefore, let K = GCD(Fcw_r numerator, Fcw_r denominator), where K is the greatest common divisor of the numerator and the denominator. Divide the numerator and the denominator by K to reduce the Fcw_r fraction to an acceptable range; GCD can be solved by using factorization, short division or trial division method in actual implementation.

[0060] It should be noted that the parameter values provided in the above embodiments are only examples. The parameters Fs, Fo, Fr, etc. can be substituted into the calculation of the relevant control word values and the bit widths of the accumulators on the data path according to actual requirements. In order to accurately represent the calculated fraction, the bit width of the fraction frequency control word (numerator, denominator) needs to be equal to the fraction phase accumulator bit width calculated above.

[0061] The bit widths of the integer and fraction phase accumulators affect the frequency resolution and the range of fractions that can be represented by the DDS. Therefore, the process of obtaining the frequency control word provided in this embodiment can be adjusted according to user requirements in terms of logic design. Because of the reconfigurable nature of the FPGA, the use of this design can greatly reduce the occupation of the FPGA logic resources when a fixed frequency point is output. For ASIC, the selection of the relevant bit width needs to consider the generality. A larger bit width can be selected under the condition of cost tolerance, which can adapt to a wider adjustment range and represent more complex fractions.

[0062] Step 403: inputting the integer frequency control word into the integer phase accumulator, inputting the numerator frequency control word into the fraction phase accumulator, inputting the denominator frequency control word into the fraction phase accumulator and the comparator respectively, and inputting the sampling frequency of the sampling clock into the integer phase accumulator and the fraction phase accumulator respectively, so that the fraction phase accumulator performs a fraction phase accumulation operation and the integer phase accumulator performs an integer phase accumulation operation, to obtain an integer phase value corresponding to each sampling period.

[0063] In this embodiment, this step is mainly to determine the sampling period according to the sampling frequency of the sampling clock.

[0064] In each same sampling period, the fraction phase accumulator adds the current fraction phase value saved by itself and the input numerator frequency control word, that is, performs an A+B operation as shown in Figure 3 . Wherein, A represents the current fraction phase value, and B represents the numerator frequency control word. The integer phase accumulator adds the current integer phase value saved by itself and the input integer frequency control word, that is, performs a D+E+F operation as shown in Figure 3 . Wherein, F represents the current integer phase value, and F represents the integer frequency control word. It should be noted that, under the condition of resource permission, the sum of the addition output by the fraction phase accumulator can be further scaled by base 2 and added to a longer phase accumulator, so as to obtain a more accurate phase output value through the longer phase accumulator.

[0065] For any one of the sampling period, when the fraction phase accumulator output plus the numerator frequency control word to the comparator and the selector of the sum, and in the comparator determines that the sum is greater than or equal to the denominator frequency control word, namely if A+B C, then the comparator considers that the fraction phase accumulator overflow, at this time the comparator immediately sends a carry signal E to the integer phase accumulator, the size of the carry signal E is the 1LSB of the integer phase accumulator, while the comparator sends a signal to the selector, the selector according to the signal sent by the comparator to obtain the difference between the sum and the denominator frequency control word, and sends the difference to the fraction phase register, so that the current fraction phase value saved in the fraction phase register is updated to the difference.

[0066] When the judge determines that the sum is less than the denominator frequency control word, then the judge sends a signal to the selector, the selector sends the sum to the fraction phase register, so that the current fraction phase value saved in the fraction phase register is updated to the sum.

[0067] It should be noted that the carry signal generated by the judge is a pulse signal, and the effective width is one Fs period; For any one of the sampling period, when the integer phase accumulator receives the carry signal generated by the fraction phase accumulator, it performs a 1 operation (1LSB). In this way, the carry period of the integer phase accumulator is the overflow period of the fraction phase accumulator in the frequency control word. It also realizes the mixed fraction ratio phase accumulator.

[0068] In any one of the sampling period, the action of the integer phase accumulator except carry out in parallel with the fraction phase accumulator; that is, in a sampling period, the fraction phase accumulator executes the above addition and overflow judgment / overflow processing, while the integer phase accumulator adds the integer frequency control word and receives the carry signal generated by the fraction phase accumulator at the same time.

[0069] Specifically, the integer frequency control word is input to an integer phase accumulator, so as to add the integer frequency control word to a current integer phase value stored in the integer phase accumulator, to obtain a temporary integer phase value; when the carry signal is received, the integer phase accumulator is controlled to add one to the temporary integer phase value, to obtain a real-time integer phase value output by the integer phase accumulator in the sampling period and take the real-time integer phase value as the current integer phase value stored in the integer phase accumulator; and when the carry signal is not received, the integer phase accumulator is controlled to output the temporary integer phase value as the real-time integer phase value and take the temporary integer phase value as the current integer phase value stored in the integer phase accumulator.

[0070] The 0 value and the maximum value of the bit width of the integer phase accumulator are mapped to the interval [0, 2π], and according to the phase accumulation and carry process, the integer phase accumulator continuously accumulates the phase, that is, from 0 to its maximum value, the phase output to the waveform lookup table changes from [0, 2π], the waveform lookup table outputs the waveform amplitude, to output a complete waveform period. Then the integer phase accumulator will overflow, that is, the accumulator output changes from the maximum value to the maximum value-2 累加器位宽 and then the next waveform output period starts.

[0071] Step 404: input each of the integer phase values to the phase interpolator, to obtain the amplitude signal corresponding to each sampling period of the target frequency through the phase interpolator, the inverse sine filter, the digital-to-analog converter and the analog reconstruction filter.

[0072] In this embodiment, this step mainly includes: inputting each of the integer phase values output by the integer phase accumulator to the phase interpolator with a waveform lookup table; for any one of the integer phase values, according to the high bit of the phase value and the low bit of the phase value of the integer phase value, obtaining the basic waveform digital amplitude corresponding to the integer phase value; and according to the low bit of the phase value, interpolating the basic waveform digital amplitude to obtain the waveform digital amplitude corresponding to the integer phase value. For a sine waveform, the waveform lookup table can use a 1 / 4 sine lookup table, and then implement the sign change.

[0073] For the case of limited lookup table accuracy, the mantissa before the integer phase accumulator is truncated and the two adjacent sine amplitudes output by the lookup table are expanded and interpolated using Taylor series, to achieve the purpose of improving the output accuracy and reducing the output THD. Since the Taylor expansion of the sine and cosine functions is as shown in the following formula: Sin x = Σ k=0 (-1)k (2k+1) / (2k+1)! = x – x3 / 3! + x 5 / 5! – x 7 / 7! Cos x = Σ k=0 (-1)k 2k / (2k)! = 1 – x 2 / 2! + x 4 / 4! – x 6 / 6! Then, in each sampling period, the phase increment introduced by the phase interpolator is relatively small, and according to the Taylor expansion of the sine function as above, the simplest Taylor series expansion interpolation can use the small angle approximation, that is, only the first term of the series is taken, that is, sin x ≈ x; cos x ≈ 1.

[0074] The truncated mantissa is linearly interpolated into the amplitude value output by the waveform lookup table, so as to reduce the phase error of the output. Specifically, the integer phase value output by the integer phase accumulator (only the integer part can be used, or the decimal part can be scaled to the size of 1 / 2 LSB of the integer part through a multiplier, and then added to the integer part as the complete phase accumulator. Regardless of which way, there is actually a rounding error, but the error brought by the Taylor expansion is relatively low), the address of the waveform table is input into the waveform lookup table according to the index of the waveform table, wherein the address is the high bit of the phase value of each integer phase value, and Pac_rem is the truncated mantissa (that is, the phase error); if the bit width of the integer phase accumulator is 16 bits, the index length is 12 bits, and Pac_rem = 16-12 = 4; then Laddr = Pac[15:4] takes the high 12 bits of the integer phase value; Pac_rem = Pac_rem[3:0] takes the low 4 bits of the integer phase value; according to the sum-difference product formula, sin(x+y) = sin(x)cos(y) + cos(x)sin(y); x is substituted into the normalized form of Laddr (that is, x = 2π*Laddr / 2 12 ), y is substituted into the normalized form of Pac_rem (y = 2π*Pac_rem / 2 16 ), since y is relatively small, only the first term of the Taylor series can be taken in the implementation (if more terms are added to reduce the output spectrum spur), that is, sin(x+y) = sin(x)*1 + cos(x)*y, wherein sin(x) and cos(x) are obtained by looking up the sine lookup table through Laddr, and the sine and cosine amplitude values obtained are added after being multiplied by the result obtained by the Taylor expansion through the multiplier. In this example implementation, it is 1 and y, and more terms can be selected according to the demand to improve the output accuracy. Wherein, the Laddr is the index of the waveform lookup table; In addition, in order to simplify the calculation, in the case where the required output precision is high and the number of required terms is large, a plurality of lookup tables can be used to output the values of corresponding terms (such as the x 3 / 3! x 5 / 5!…) when calculating the Taylor expansion value of the sine function of Pac_rem (i.e. the value of y), thereby reducing the performance overhead of the calculation of the Taylor expansion. Preferably, dithering can also be added to the phase and amplitude values, further reducing the output spur (phase noise, quantization noise).

[0075] When the waveform digital amplitude output by the phase interpolator is input into the anti-sinc filter, the zero-order hold characteristic of the DAC is compensated by the anti-sinc filter, which has a frequency response characteristic that is exactly opposite to the frequency response characteristic of the zero-order hold, so as to compensate for the roll-off caused by the zero-order hold characteristic of the DAC. The anti-sinc filter is preferably implemented by a digital filter, which can be a FIR filter or an IIR filter. The appropriate digital filter structure, order and coefficient can be selected according to the requirements of frequency response flatness, resource consumption and the like to achieve the function; when the requirement is not high, an analog filter can also be used to achieve the function. Preferably, as shown in Figure 3 After the integer phase value H output by the integer phase accumulator is input into the waveform lookup table, the phase control word G input from the outside can also be received to adjust the H through the phase control word G. Specifically, the bit width of the phase control word value G is the same as that of the integer phase accumulator, and is used to dynamically adjust the output phase, so that the phase of the output frequency can be moved according to the user's demand, and the phase modulation function is realized.

[0076] Finally, the waveform digital amplitude is converted into an analog signal through the DAC and the reconstruction filter, and the output is an amplitude signal corresponding to the target frequency.

[0077] The direct digital synthesis method based on the mixed fractional ratio disclosed in the embodiment changes the phase counter and the frequency control word from an integer to an integer / fractional ratio, so that the rounding error of the output frequency when fractional frequency division is required can be eliminated through the mixed fractional ratio; at the same time, the number of logic gates is reduced, and the resource occupation is reduced. Then, in the case where the resources allow, the fractional part also participates in the phase interpolation calculation, so that the output phase does not exist periodic modulation, and the output phase noise and spur components are reduced. Finally, the amplitude can use Taylor series expansion interpolation, and the output amplitude precision is higher, and the output spectrum spur components are reduced in the case of low resource usage.

[0078] The above-described specific embodiments further illustrate the purpose, technical solutions and beneficial effects of the present application. It should be understood that the above-described specific embodiments are merely examples of the present application and are not intended to limit the protection scope of the present application. It is particularly pointed out that any modification, equivalent replacement, improvement, etc. made by those skilled in the art within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method of direct digital synthesis based on hybrid fractional- ratio, characterized in that, The method comprises: determining a frequency control word based on a target frequency, a sampling frequency and a bit width of a phase accumulator, and splitting the frequency control word into an integer frequency control word, a numerator frequency control word and a denominator frequency control word; performing a fractional phase accumulation operation based on the sampling frequency, the numerator frequency control word and the phase accumulator to generate a carry signal; wherein the fractional phase accumulation operation comprises obtaining an accumulation result of the numerator frequency control word according to the phase accumulator, and generating the carry signal according to the accumulation result and the denominator frequency control word; performing an integer phase accumulation operation according to the sampling frequency, the integer frequency control word and the phase accumulator in parallel with the fractional phase accumulation operation to obtain an integer phase value; wherein the integer phase accumulation operation comprises obtaining an accumulation result of the integer frequency control word according to the phase accumulator and the carry signal to obtain the integer phase value; obtaining a waveform digital amplitude corresponding to the integer phase value to perform signal conversion according to the waveform digital amplitude to obtain an amplitude signal corresponding to the target frequency.

2. The hybrid fractional ratio-based direct digital synthesis method of claim 1, wherein, The method of determining a frequency control word based on a target frequency, a sampling frequency and a bit width of a phase accumulator, and splitting the frequency control word into an integer frequency control word, a numerator frequency control word and a denominator frequency control word comprises: determining a total number of phases of the phase accumulator in a full-scale period according to the bit width of the phase accumulator; obtaining a product of the target frequency and the total number of phases to obtain a frequency control word by dividing the product by the sampling frequency; performing an integer operation on the frequency control word to obtain an integer frequency control word, and obtaining a remainder of the frequency control word to take the remainder as a frequency error component; dividing the frequency error component by the sampling frequency to obtain an original fractional frequency control word; wherein the original fractional frequency control word is a ratio of an original numerator frequency control word to an original denominator frequency control word; obtaining a greatest common divisor of the original numerator frequency control word and the original denominator frequency control word to obtain a numerator frequency control word and a denominator frequency control word according to the greatest common divisor.

3. The hybrid fractional ratio-based direct digital synthesis method of claim 1, wherein, The method of performing a fractional phase accumulation operation based on the sampling frequency, the numerator frequency control word and the phase accumulator to generate a carry signal comprises: determining a sampling period of the numerator frequency control word and the integer frequency control word according to the sampling frequency; for any one of the sampling periods, inputting the numerator frequency control word into a fractional phase accumulator to add the numerator frequency control word to a current fractional phase value saved in the fractional phase accumulator to obtain a temporary sum; when the temporary sum is greater than or equal to the denominator frequency control word, controlling the fractional phase accumulator to generate a carry signal and obtain a difference between the temporary sum and the denominator frequency control word, and taking the difference as the current fractional phase value saved in the fractional phase accumulator.

4. The hybrid-fractional-band-based direct digital synthesis method of claim 3, wherein, The method of performing a fractional phase accumulation operation based on the sampling frequency, the numerator frequency control word and the phase accumulator to generate a carry signal comprises: For any one of the sampling periods, when the temporary sum is less than the denominator frequency control word, the temporary sum is taken as the current fractional phase value saved by the fractional phase accumulator.

5. The hybrid fractional-n based direct digital synthesis method of claim 3, wherein, The integer phase accumulation operation is performed in parallel with the fractional phase accumulation operation according to the sampling frequency, the integer frequency control word and the phase accumulator, to obtain an integer phase value, comprising: For any one of the sampling periods, the integer frequency control word is input into an integer phase accumulator, so that the integer frequency control word is added to a current integer phase value saved in the integer phase accumulator, to obtain a temporary integer phase value; When the carry signal is received, the integer phase accumulator is controlled to perform a plus one operation on the temporary integer phase value, to obtain a real-time integer phase value output by the integer phase accumulator in the sampling period and take the real-time integer phase value as the current integer phase value saved in the integer phase accumulator.

6. The hybrid-fractional-band-based direct digital synthesis method of claim 5, wherein, The integer phase accumulation operation is performed in parallel with the fractional phase accumulation operation according to the sampling frequency, the integer frequency control word and the phase accumulator, to obtain an integer phase value, comprising: For any one of the sampling periods: When the carry signal is not received, the integer phase accumulator is controlled to output the temporary integer phase value as the real-time integer phase value and take the temporary integer phase value as the current integer phase value saved in the integer phase accumulator.

7. The hybrid fractional-n based direct digital synthesis method of claim 1, wherein, The waveform digital amplitude value corresponding to the integer phase value is obtained, and signal conversion is performed according to the waveform digital amplitude value, to obtain an amplitude signal corresponding to the target frequency, comprising: The phase value high bit and the phase value low bit of the integer phase value are obtained, a preset waveform lookup table is queried according to the phase value high bit, to obtain a basic waveform digital amplitude value corresponding to the integer phase value; The basic waveform digital amplitude value is subjected to interpolation calculation according to the phase value low bit, to obtain the waveform digital amplitude value corresponding to the integer phase value; The waveform digital amplitude value is subjected to digital-to-analog conversion operation, to obtain an analog signal, and the analog signal is filtered, to obtain the amplitude signal corresponding to the target frequency.

8. The hybrid-fractional-spur-based direct digital synthesis method of claim 7, wherein, The waveform digital amplitude value corresponding to the integer phase value is obtained, and signal conversion is performed according to the waveform digital amplitude value, to obtain an amplitude signal corresponding to the target frequency, further comprising: A zero-order hold model of the digital-to-analog conversion operation is obtained, to determine an inverse zinger target frequency response function according to the zero-order hold model and the sampling frequency; The waveform digital amplitude value is subjected to amplitude compensation according to the inverse zinger target frequency response function, and the waveform digital amplitude value subjected to amplitude compensation is subjected to digital-to-analog conversion operation, to obtain the analog signal.

9. The hybrid fractional-n based direct digital synthesis method of claim 1, wherein, Before the frequency control word is determined based on the target frequency, the sampling frequency and the bit width of the phase accumulator, and the frequency control word is split into the integer frequency control word, the numerator frequency control word and the denominator frequency control word, comprising: A resolution ratio of the sampling frequency and a preset sampling resolution is obtained, to determine an actual integer bit width of the integer phase accumulator according to the ratio; determining an original denominator frequency control word of the frequency control word according to the target frequency, the sampling frequency and the actual integer bit width; determining an actual fractional bit width of a fractional phase accumulator according to the original denominator frequency control word.

10. A direct digital synthesis system based on mixed fraction ratios, characterized in that, comprising a control word splitting module, a fractional phase accumulation module, an integer phase accumulation module and a waveform conversion module; the control word splitting module is configured to determine a frequency control word based on a target frequency, a sampling frequency and a bit width of a phase accumulator, and split the frequency control word into an integer frequency control word, a numerator frequency control word and a denominator frequency control word; the fractional phase accumulation module is configured to perform a fractional phase accumulation operation based on the sampling frequency, the numerator frequency control word and the phase accumulator to generate a carry signal; wherein the fractional phase accumulation operation comprises obtaining an accumulation result of the numerator frequency control word according to the phase accumulator, to generate the carry signal according to the accumulation result and the denominator frequency control word; the integer phase accumulation module is configured to perform an integer phase accumulation operation according to the sampling frequency, the integer frequency control word and the phase accumulator in parallel with the fractional phase accumulation operation, to obtain an integer phase value; wherein the integer phase accumulation operation comprises obtaining an accumulation result of the integer frequency control word according to the phase accumulator and the carry signal, to obtain an integer phase value; the waveform conversion module is configured to obtain a waveform digital amplitude corresponding to the integer phase value, to perform signal conversion according to the waveform digital amplitude, to obtain an amplitude signal corresponding to the target frequency.

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