Hybrid fractional ratio based direct digital synthesis method and system

Abstract

The application discloses a direct digital synthesis method and system based on a mixed fractional ratio, and the method comprises the following steps: determining an integer frequency control word, a numerator frequency control word and a denominator frequency control word based on a target frequency, a sampling frequency and a bit width of a phase accumulator; performing a fractional phase accumulation operation based on the sampling frequency, the numerator frequency control word and the phase accumulator to generate a carry signal; performing an integer phase carry and accumulation operation in parallel with the fractional phase accumulation operation according to the sampling frequency, the integer frequency control word and the phase accumulator to obtain an integer phase value; and obtaining a waveform digital amplitude value corresponding to the integer phase value to perform signal conversion according to the waveform digital amplitude value to obtain an amplitude signal corresponding to the target frequency, so that the accuracy of a frequency synthesis signal is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a direct digital synthesis method and system based on a mixed fraction ratio. Background Technology

[0002] Modern mixed-signal processing systems inevitably require signals of multiple frequencies. Different frequency signals serve as references for signal processing in analog circuits; when used as clock signals in digital circuits, they facilitate synchronization between digital circuits and timing sampling for ADCs / DACs. Therefore, signal generators that produce high-quality, controllable signals with a target frequency are essential components of modern mixed-signal processing systems.

[0003] For frequency signals requiring precise phase or frequency synchronization, components such as PLLs (Phase-Locked Loops) or DDSs (Direct Digital Synthesizers) are typically used to generate signals via a shared clock source. To improve system integration, systems using FPGAs (Field-Programmable Gate Arrays) can implement DDS functionality using the FPGA's programmable logic, provided resources allow, and connect an external DAC (Digital-to-Analog Converter) to generate the reference signal. However, the above methods for generating signals at the target frequency have a problem: if the ratio of the target frequency to the sampling frequency cannot be represented as a finite decimal in binary (e.g., 1 / 6, 1 / 7), an error will occur between the frequency of the generated signal and the target frequency; conversely, if the ratio of the target frequency to the sampling frequency can be represented as a finite decimal in binary, but the number of bits is too long, the DDS will need a very long phase accumulator bit width to accommodate the corresponding decimal part, leading to increased resource consumption and reduced timing margin. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention discloses a direct digital synthesis method and system based on a mixed fraction ratio, which is used to improve the frequency accuracy of digital synthesis.

[0005] To achieve the above objectives, the present invention discloses a direct digital synthesis method based on a mixed fraction ratio, comprising:

[0006] The frequency control word is determined based on the target frequency, sampling frequency, and bit width of the phase accumulator, and the frequency control word is then split into an integer frequency control word, a numerator frequency control word, and a denominator frequency control word.

[0007] A fractional phase accumulation operation is performed based on the sampling frequency, the numerator frequency control word, and the phase accumulator to generate a carry signal; wherein, the fractional phase accumulation operation includes obtaining the accumulation result of the numerator frequency control word according to the phase accumulator, and generating the carry signal according to the accumulation result and the denominator frequency control word;

[0008] Based on the sampling frequency, the integer frequency control word, and the phase accumulator, an integer phase accumulation operation is performed in parallel with the fractional phase accumulation operation to obtain an integer phase value; wherein, the integer phase accumulation operation includes obtaining the accumulation result of the integer frequency control word based on the phase accumulator and the carry signal to obtain the integer phase value;

[0009] The digital amplitude of the waveform corresponding to the integer phase value is obtained, and signal conversion is performed based on the digital amplitude of the waveform to obtain the amplitude signal corresponding to the target frequency.

[0010] This invention discloses a direct digital synthesis method based on a hybrid fractional ratio. By splitting the frequency control word into integer, numerator, and denominator parts, and performing fractional and integer phase accumulation operations in parallel, the method dynamically adjusts the integer accumulation process using the carry signal generated by fractional accumulation. This accurately generates the target frequency signal, effectively avoiding errors caused by non-finite binary fractional frequency ratios and resource consumption issues associated with long-bit-width phase accumulators in traditional direct digital synthesis. Specifically, determining and splitting the frequency control word allows the target frequency to be accurately represented as an integer part and a fractional ratio, adapting to any frequency ratio and avoiding dependence on long-bit-width phase accumulators. The fractional phase accumulation operation accumulates the numerator frequency control word and generates a carry signal when the denominator is reached, achieving accurate accumulation of the fractional phase. The carry signal accurately reflects the overflow state of the fractional part, providing a basis for adjusting the integer part. The parallel execution of the integer phase accumulation operation increments the integer phase value based on the carry signal, ensuring that the integer phase value responds in real time to the overflow of the fractional part, thus accumulating a precise total phase value. A waveform is generated based on the precise integer phase value, ensuring accurate output signal frequency. These features work together: splitting the frequency control word allows the fractional ratio to be processed independently; the fractional accumulation operation generates a carry signal as a bridge; the integer accumulation operation uses the carry signal to dynamically correct the phase; the two are executed in parallel to ensure synchronization; and the final output is a phase without accumulated error, thus solving the problems of frequency error and resource consumption.

[0011] As a preferred example, the step of determining the frequency control word based on the target frequency, sampling frequency, and bit width of the phase accumulator, and splitting the frequency control word into an integer frequency control word, a numerator frequency control word, and a denominator frequency control word, includes:

[0012] The total number of phases of the phase accumulator within the full-scale period is determined based on the bit width of the phase accumulator.

[0013] Obtain the product of the target frequency and the total number of phases, and divide the product by the sampling frequency to obtain the frequency control word;

[0014] The frequency control word is rounded down to obtain an integer frequency control word, and the remainder of the frequency control word is obtained, so as to use the remainder as a frequency error component;

[0015] Divide the frequency error component by the sampling frequency to obtain the original fractional frequency control word; wherein the original fractional frequency control word is the ratio of the original numerator frequency control word to the original denominator frequency control word;

[0016] Obtain the greatest common divisor of the original numerator frequency control word and the original denominator frequency control word, and then obtain the numerator frequency control word and the denominator frequency control word based on the greatest common divisor.

[0017] The above scheme determines the total number of full-scale phases based on the bit width of the phase accumulator, establishing the hardware foundation for phase resolution and ensuring that subsequent calculations accurately match the capabilities of the actual system. Next, the product of the target frequency and the total number of phases is obtained and divided by the sampling frequency to determine the frequency control word. Then, the frequency control word is rounded to separate the integer part and extract the frequency error component, providing a clear boundary for the parallel processing of integer and fractional phase accumulation, allowing non-integer frequency components to be processed independently. Further, the frequency error component is divided by the sampling frequency to form the original fractional frequency control word. Finally, the greatest common divisor of the original numerator and denominator is obtained and the fraction is simplified accordingly, significantly reducing the bit width required for the fractional phase accumulator. This reduces hardware resource consumption without sacrificing frequency accuracy, while improving system timing stability, making the fractional phase accumulation operation more efficient and adaptable to resource-constrained FPGA implementation environments.

[0018] As a preferred example, the step of performing a fractional phase accumulation operation based on the sampling frequency, the molecular frequency control word, and the phase accumulator to generate a carry signal includes:

[0019] The sampling periods of the molecular frequency control word and the integer frequency control word are determined based on the sampling frequency.

[0020] For any given sampling period, the molecular frequency control word is input to the fractional phase accumulator so that the molecular frequency control word is added to the current fractional phase value stored in the fractional phase accumulator to obtain a temporary sum;

[0021] When the temporary sum is greater than or equal to the denominator frequency control word, the fractional phase accumulator is controlled to generate a carry signal and obtain the difference between the temporary sum and the denominator frequency control word, so that the difference is used as the current fractional phase value stored in the fractional phase accumulator.

[0022] The above scheme uses the sampling frequency as a timing reference to determine the sampling period. This ensures that the fractional phase accumulation operation is strictly synchronized with the system clock, avoiding phase accumulation deviations caused by timing misalignments, thus laying a timing foundation for the accurate processing of the fractional part. Within any sampling period, the numerator frequency control word is input into the fractional phase accumulator and added to the current fractional phase value to obtain a temporary sum. The numerator frequency control word represents the numerator component of the fractional proportion. Through continuous accumulation, the fractional phase is progressively increased. Its special feature is that the numerator frequency control word directly drives the phase increment calculation, avoiding the resource waste caused by excessively long binary decimal places in traditional methods, while preserving the complete information of the fractional part. When the temporary sum is greater than or equal to the denominator frequency control word, a carry signal is generated and the current fractional phase value is updated with the difference. This mechanism triggers the carry by dynamically comparing the temporary sum with the threshold (i.e., the denominator of the fractional frequency control word), ensuring that the carry signal is generated precisely only when the fractional phase accumulation reaches an integer unit. The operation of the difference as the new current value fully preserves the fractional margin, preventing phase overflow and maintaining phase continuity, thereby significantly improving the accuracy and stability of non-integer proportional frequency synthesis.

[0023] As a preferred example, the step of performing a fractional phase accumulation operation based on the sampling frequency, the molecular frequency control word, and the phase accumulator to generate a carry signal includes:

[0024] For any given sampling period, when the temporary sum is less than the denominator frequency control word, the temporary sum is stored as the current fractional phase value in the fractional phase accumulator.

[0025] The above scheme ensures the continuity and integrity of the fractional phase accumulation process by accurately handling boundary conditions. Specifically, for each sampling period, when the temporary sum is less than the denominator frequency control word, the temporary sum is directly used as the new current fractional phase value. This operation preserves the accumulated state of the fractional part, avoiding erroneous reset or loss of phase values ​​under conditions without carry. This real-time update mechanism based on the temporary sum effectively maintains the continuous accumulation of the fractional phase, providing a reliable foundation for the accurate generation of carry signals, thereby eliminating frequency errors caused by incomplete fractional processing and improving the output accuracy of the direct digital synthesis system under complex frequency ratios.

[0026] As a preferred example, the step of performing an integer phase accumulation operation in parallel with the fractional phase accumulation operation, based on the sampling frequency, the integer frequency control word, and the phase accumulator, to obtain an integer phase value, includes:

[0027] For any given sampling period, the integer frequency control word is input to the integer phase accumulator so that the integer frequency control word is added to the current integer phase value stored in the integer phase accumulator to obtain a temporary integer phase value;

[0028] When the carry signal is received, the integer phase accumulator is controlled to increment the temporary integer phase value by one to obtain the real-time integer phase value output by the integer phase accumulator in the sampling period, and the real-time integer phase value is used as the current integer phase value stored in the integer phase accumulator.

[0029] The above scheme effectively solves the problem of accumulated error in integer phase values ​​during fractional carry by designing a parallel execution mechanism for integer and fractional phase accumulation operations and introducing an instant correction strategy triggered by carry signals, thereby ensuring the accuracy of target frequency generation. Specifically, the integer phase accumulation operation is executed in parallel according to the sampling frequency, integer frequency control word, and phase accumulator. This feature avoids timing deviations that may occur during sequential execution by synchronously processing the phase accumulation of the integer and fractional parts. When a carry signal is received, the integer phase accumulator is controlled to increment the temporary integer phase value by one to obtain the real-time integer phase value output by the integer phase accumulator in that sampling period. This real-time integer phase value is then stored in the integer phase accumulator as the current integer phase value. This feature provides instant correction of the temporary value based on the presence of the carry signal. By directly responding to the carry event of fractional phase accumulation, it compensates for the phase increment when the fractional part accumulates to the threshold, thereby eliminating the loss of integer phase values ​​due to carry delay and ultimately ensuring the integrity of phase accumulation and frequency accuracy.

[0030] As a preferred example, the step of performing an integer phase accumulation operation in parallel with the fractional phase accumulation operation to obtain an integer phase value, based on the sampling frequency, the integer frequency control word, and the phase accumulator, includes:

[0031] For any of the aforementioned sampling periods:

[0032] When no carry signal is received, the integer phase accumulator is controlled to output the temporary integer phase value as the real-time integer phase value and the temporary integer phase value is used as the current integer phase value stored in the integer phase accumulator.

[0033] The above scheme ensures the integrity and accuracy of the phase accumulation process by explicitly defining the behavior of the integer phase accumulator under conditions without carry signals, thus effectively avoiding the introduction of phase errors. For any sampling period, this operation covers all possible sampling moments, ensuring that the system can process phase updates in a timely manner in each period, maintaining real-time performance. When no carry signal is received, it indicates that the fractional phase accumulation has not reached the overflow threshold, so the integer part does not need to be incremented by one. At this time, the temporary integer phase value is directly output as the real-time integer phase value, which can accurately reflect the accumulation result of the integer frequency control word and the current integer phase value, avoiding phase offset caused by incorrect incrementing. At the same time, the temporary integer phase value is used as the current integer phase value stored in the integer phase accumulator. This update mechanism ensures that the current state is correctly passed to the next period, providing an accurate initial value for subsequent accumulation and preventing the erroneous accumulation of phase values. Overall, this scheme achieves seamless coordination between integer and fractional phase accumulation by dynamically adjusting the integer phase processing logic closely relying on the state of the carry signal, fundamentally solving the problem of missing phase updates in scenarios without carry, and ensuring the accurate generation of the target frequency signal.

[0034] As a preferred example, the step of obtaining the waveform digital amplitude corresponding to the integer phase value, and performing signal conversion based on the waveform digital amplitude to obtain the amplitude signal corresponding to the target frequency, includes:

[0035] Obtain the high-order and low-order phase bits of the integer phase value, and query a preset waveform lookup table based on the high-order phase bit to obtain the digital amplitude of the basic waveform corresponding to the integer phase value;

[0036] The digital amplitude of the basic waveform is interpolated based on the low-order bits of the phase value to obtain the digital amplitude of the waveform corresponding to the integer phase value.

[0037] The digital amplitude of the waveform is converted from digital to analog to obtain an analog signal, and the analog signal is filtered to obtain the amplitude signal corresponding to the target frequency.

[0038] The above scheme effectively mitigates the impact of phase quantization errors on waveform quality by refining the internal structure of integer phase values. Specifically, each integer phase value is decomposed into high-order and low-order phase values. This design fully utilizes the stability of the high-order value as the main phase index, while using the low-order value to capture subtle phase changes, providing crucial information for subsequent interpolation. The digital amplitude of the basic waveform is obtained by querying the waveform lookup table based on the high-order phase value, avoiding the problem of an excessively large lookup table caused by directly using the complete phase value. This reduces hardware resource consumption and ensures rapid acquisition of the basic amplitude. Interpolation calculation of the digital amplitude of the basic waveform is performed based on the low-order phase value. The linear interpolation mechanism smooths the amplitude transition between adjacent phase points, significantly suppressing the step effect caused by discontinuous phase steps, thereby reducing harmonic distortion. Finally, digital-to-analog conversion and filtering are performed on the waveform's numerical amplitude. This not only converts the digital signal into analog form but also eliminates high-frequency noise and image components during the conversion process, ultimately outputting a high-fidelity amplitude signal.

[0039] As a preferred example, the step of obtaining the waveform digital amplitude corresponding to the integer phase value, and performing signal conversion based on the waveform digital amplitude to obtain the amplitude signal corresponding to the target frequency, further includes:

[0040] Obtain the zero-order hold model of the digital-to-analog conversion operation, and determine the inverse Singer target frequency response function based on the zero-order hold model and the sampling frequency;

[0041] Amplitude compensation is performed on each digital amplitude of the waveform according to the inverse Singer target frequency response function, and then a digital-to-analog conversion operation is performed on the amplitude-compensated digital amplitude of the waveform to obtain the analog signal.

[0042] The above scheme improves the amplitude accuracy of the output waveform by introducing an amplitude compensation mechanism to specifically address the frequency response attenuation problem caused by the zero-order hold effect in the digital-to-analog conversion (D / A conversion) stage. Specifically, it involves: obtaining the zero-order hold model of the D / A conversion operation, accurately capturing the inherent characteristic of the D / A converter maintaining a constant output between sampling points (the physical root cause of Singer function attenuation); determining the inverse Singer target frequency response function based on the zero-order hold model and sampling frequency, precisely deriving the inverse Singer function using the sampling frequency parameter (specifically designed to counteract the Singer attenuation effect and ensure a flat frequency response within the target frequency range); performing amplitude compensation on the digital amplitude of each waveform based on the inverse Singer target frequency response function (preprocessing the amplitude in the digital domain by dynamically adjusting the amplitude using the inverse Singer function to pre-compensate for the amplitude loss that inevitably occurs during subsequent D / A conversion); and performing a D / A conversion on the amplitude-compensated digital amplitude of the waveform to obtain an analog signal. This step effectively counteracts the zero-order hold effect during the conversion process, resulting in an analog signal amplitude closer to the ideal value and significantly reducing amplitude distortion.

[0043] As a preferred example, before determining the frequency control word based on the target frequency, sampling frequency, and bit width of the phase accumulator, and before splitting the frequency control word into an integer frequency control word, a numerator frequency control word, and a denominator frequency control word, the process includes:

[0044] Obtain the resolution ratio between the sampling frequency and the preset sampling resolution, and determine the actual integer bit width of the integer phase accumulator based on the ratio;

[0045] The original denominator frequency control word of the frequency control word is determined based on the target frequency, the sampling frequency, and the actual integer bit width;

[0046] The actual fractional bit width of the fractional phase accumulator is determined based on the original denominator frequency control word.

[0047] The above scheme significantly reduces hardware resource requirements while maintaining frequency synthesis accuracy by dynamically optimizing the phase accumulator bit width structure. First, the resolution ratio of the sampling frequency to the preset sampling resolution is obtained to determine the ideal integer bit width of the integer phase accumulator. This ensures that the bit width matches the required frequency resolution of the system, avoiding quantization errors caused by insufficient bit width and providing a benchmark for subsequent optimization. Next, the ideal integer bit width is subtracted by one based on the integer phase accumulation operation to obtain the actual integer bit width. This subtraction operation considers the boundary characteristics of integer phase accumulation in actual hardware implementation. By reducing one bit, critical accuracy is preserved while avoiding redundant resource occupation, effectively alleviating the contradiction between the number of registers and timing margin in the FPGA. Then, the original denominator frequency control word is determined based on the target frequency, sampling frequency, and actual integer bit width. This uses the adjusted bit width to accurately calculate the denominator, enabling fractional phase accumulation to more accurately handle non-integer proportional relationships, thereby suppressing frequency drift caused by bit width mismatch. Finally, the actual fractional bit width of the fractional phase accumulator is determined based on the original denominator frequency control word. This dynamically adapts to the bit requirement of the fractional part, allocating only the minimum bit width required to represent the denominator, avoiding resource waste in fixed bit width schemes, and improving the feasibility of the system in resource-constrained environments.

[0048] On the other hand, the present invention discloses a direct digital synthesis system based on a mixed fractional ratio, including a control word splitting module, a fractional phase accumulation module, an integer phase accumulation module, and a waveform conversion module;

[0049] The control word splitting module is used to determine the frequency control word based on the target frequency, sampling frequency and the bit width of the phase accumulator, and split the frequency control word into an integer frequency control word, a numerator frequency control word and a denominator frequency control word.

[0050] The fractional phase accumulation module is used to perform a fractional phase accumulation operation based on the sampling frequency, the numerator frequency control word, and the phase accumulator to generate a carry signal; wherein, the fractional phase accumulation operation includes obtaining the accumulation result of the numerator frequency control word according to the phase accumulator, and generating the carry signal according to the accumulation result and the denominator frequency control word;

[0051] The integer phase accumulation module is used to perform an integer phase accumulation operation in parallel with the fractional phase accumulation operation according to the sampling frequency, the integer frequency control word, and the phase accumulator to obtain an integer phase value; wherein, the integer phase accumulation operation includes obtaining the accumulation result of the integer frequency control word according to the phase accumulator and the carry signal to obtain the integer phase value;

[0052] The waveform conversion module is used to obtain the waveform digital amplitude corresponding to the integer phase value, and to perform signal conversion based on the waveform digital amplitude to obtain the amplitude signal corresponding to the target frequency.

[0053] This invention discloses a direct digital synthesis system based on a hybrid fractional ratio. By splitting the frequency control word into integer, numerator, and denominator parts, and performing fractional and integer phase accumulation operations in parallel, the system dynamically adjusts the integer accumulation process using the carry signal generated by fractional accumulation. This accurately generates the target frequency signal, effectively avoiding errors caused by non-finite binary fractional frequency ratios and resource consumption issues associated with long-bit-width phase accumulators in traditional direct digital synthesis. Specifically, determining and splitting the frequency control word allows the target frequency to be accurately represented as an integer part and a fractional ratio, adapting to any frequency ratio and avoiding dependence on long-bit-width phase accumulators. The fractional phase accumulation operation repeatedly accumulates the numerator frequency control word and generates a carry signal when the denominator is reached, achieving accurate accumulation of the fractional phase. The carry signal accurately reflects the overflow state of the fractional part, providing a basis for adjusting the integer part. The parallel execution of the integer phase accumulation operation increments the integer phase value based on the carry signal, ensuring that the integer phase value responds in real time to the overflow of the fractional part, thus accumulating a precise total phase value. A waveform is generated based on the precise integer phase value, ensuring accurate output signal frequency. These features work together: splitting the frequency control word allows the fractional ratio to be processed independently; the fractional accumulation operation generates a carry signal as a bridge; the integer accumulation operation uses the carry signal to dynamically correct the phase; the two are executed in parallel to ensure synchronization; and the final output is a waveform without accumulated error, which together solves the problems of frequency error and resource consumption. Attached Figure Description

[0054] To more clearly illustrate the technical solution of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0055] Figure 1 This is a flowchart illustrating a direct digital synthesis method based on a mixed fraction ratio provided in an embodiment of the present invention.

[0056] Figure 2 This is a schematic diagram of the structure of a direct digital synthesis system based on a mixed fraction ratio provided in an embodiment of the present invention;

[0057] Figure 3 This is a schematic diagram of the structure of a direct digital synthesis device based on a mixing fraction ratio provided in another embodiment of the present invention;

[0058] Figure 4This is a flowchart illustrating a direct digital synthesis method based on a mixed fraction ratio, provided in another embodiment of the present invention. Detailed Implementation

[0059] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0060] Reference Figure 1 To address the technical problem in existing technologies that cannot accurately generate frequency signals corresponding to target frequencies and require significant phase resources for signal generation, this embodiment discloses a direct digital synthesis method based on a mixed fractional ratio, including:

[0061] Step 101: Determine the frequency control word based on the target frequency, sampling frequency, and bit width of the phase accumulator, and split the frequency control word into an integer frequency control word, a numerator frequency control word, and a denominator frequency control word.

[0062] In this embodiment, the steps mainly include: first, obtaining the resolution ratio between the sampling frequency and the preset sampling resolution, so as to determine the actual integer bit width of the integer phase accumulator based on the ratio; determining the original denominator frequency control word of the frequency control word based on the target frequency, the sampling frequency and the actual integer bit width; and determining the actual fractional bit width of the fractional phase accumulator based on the original denominator frequency control word.

[0063] Next, the total number of phases of the phase accumulator within the full-scale period is determined based on the bit width of the phase accumulator; the product of the target frequency and the total number of phases is obtained, and the frequency control word is determined based on the ratio of the product to the sampling frequency; the frequency control word is rounded to obtain an integer frequency control word, and the frequency error component of the product divided by the sampling frequency is obtained; the frequency error component is divided by the sampling frequency to obtain the original fractional frequency control word; wherein, the original fractional frequency control word is the ratio of the original numerator frequency control word to the original denominator frequency control word; the greatest common divisor of the original numerator frequency control word and the original denominator frequency control word is obtained, and the numerator frequency control word and the denominator frequency control word are obtained based on the greatest common divisor.

[0064] Step 102: Perform a fractional phase accumulation operation based on the sampling frequency, the numerator frequency control word, and the phase accumulator to generate a carry signal; wherein, the fractional phase accumulation operation includes obtaining the accumulation result of the numerator frequency control word according to the phase accumulator, and generating the carry signal according to the accumulation result and the denominator frequency control word.

[0065] In this embodiment, the step mainly includes: determining the sampling period of the numerator frequency control word and the integer frequency control word according to the sampling frequency; for any sampling period, inputting the numerator frequency control word to the fractional phase accumulator, so that the numerator frequency control word is added to the current fractional phase value stored in the fractional phase accumulator to obtain a temporary sum; when the temporary sum is greater than or equal to the denominator frequency control word, controlling the fractional phase accumulator to generate a carry signal and obtain the difference between the temporary sum and the denominator frequency control word, so as to use the difference as the current fractional phase value stored in the fractional phase accumulator.

[0066] For any given sampling period, when the temporary sum is less than the denominator frequency control word, the temporary sum is stored as the current fractional phase value in the fractional phase accumulator.

[0067] Step 103: Based on the sampling frequency, the integer frequency control word, and the phase accumulator, perform an integer phase accumulation operation in parallel with the fractional phase accumulation operation to obtain an integer phase value; wherein, the integer phase accumulation operation includes obtaining the accumulation result of the integer frequency control word based on the phase accumulator and the carry signal to obtain the integer phase value.

[0068] In this embodiment, the step mainly includes: for any sampling period, inputting the integer frequency control word to the integer phase accumulator, so that the integer frequency control word is added to the current integer phase value stored in the integer phase accumulator to obtain a temporary integer phase value; when the carry signal is received, controlling the integer phase accumulator to increment the temporary integer phase value by one to obtain the real-time integer phase value output by the integer phase accumulator in the sampling period, and using the real-time integer phase value as the current integer phase value stored in the integer phase accumulator.

[0069] For any of the sampling periods: when no carry signal is received, the integer phase accumulator is controlled to output the temporary integer phase value as the real-time integer phase value and the temporary integer phase value is used as the current integer phase value stored in the integer phase accumulator.

[0070] Step 104: Obtain the digital amplitude of the waveform corresponding to the integer phase value, and perform signal conversion based on the digital amplitude of the waveform to obtain the amplitude signal corresponding to the target frequency.

[0071] In this embodiment, the step mainly includes: obtaining the high-order and low-order phase bits of the integer phase value, querying a preset waveform lookup table based on the high-order phase bit to obtain the basic waveform digital amplitude corresponding to the integer phase value; performing interpolation calculation on the basic waveform digital amplitude based on the low-order phase bit to obtain the waveform digital amplitude corresponding to the integer phase value; performing digital-to-analog conversion on the waveform digital amplitude to obtain an analog signal, and filtering the analog signal to obtain the amplitude signal corresponding to the target frequency.

[0072] Specifically, the zero-order hold model of the digital-to-analog conversion operation is obtained, and the inverse singer target frequency response function is determined based on the zero-order hold model and the sampling frequency; amplitude compensation is performed on each digital amplitude of the waveform based on the inverse singer target frequency response function, and the digital-to-analog conversion operation is performed on the amplitude-compensated digital amplitude of the waveform to obtain the analog signal.

[0073] On the other hand, refer to Figure 2 This embodiment also discloses a direct digital synthesis system based on a mixed fractional ratio, including a control word splitting module 201, a fractional phase accumulation module 202, an integer phase accumulation module 203, and a waveform conversion module 204.

[0074] The control word splitting module 201 is used to determine the frequency control word based on the target frequency, sampling frequency and the bit width of the phase accumulator, and split the frequency control word into an integer frequency control word, a numerator frequency control word and a denominator frequency control word.

[0075] The fractional phase accumulation module 202 is used to perform a fractional phase accumulation operation based on the sampling frequency, the numerator frequency control word, and the phase accumulator to generate a carry signal; wherein, the fractional phase accumulation operation includes obtaining the accumulation result of the numerator frequency control word according to the phase accumulator, so as to generate the carry signal according to the accumulation result and the denominator frequency control word.

[0076] The integer phase accumulation module 203 is used to perform an integer phase accumulation operation in parallel with the fractional phase accumulation operation according to the sampling frequency, the integer frequency control word and the phase accumulator, to obtain an integer phase value; wherein, the integer phase accumulation operation includes obtaining the accumulation result of the integer frequency control word according to the phase accumulator and the carry signal to obtain the integer phase value.

[0077] The waveform conversion module 204 is used to obtain the waveform digital amplitude corresponding to the integer phase value, and to perform signal conversion based on the waveform digital amplitude to obtain the amplitude signal corresponding to the target frequency.

[0078] Example 2

[0079] This embodiment further provides a direct digital synthesis method based on a mixed fraction ratio, specifically, referring to... Figure 3 First, based on the DDS (Direct Digital Synthesizer), i.e., the digital synthesis logic of the direct digital synthesizer, a fractional phase accumulator for the fractional part of the frequency control word and an integer phase accumulator for the integer part are constructed respectively. Through the data interaction between the fractional phase accumulator and the integer phase accumulator, an integer phase sequence corresponding to the target frequency is continuously generated, which is formed by multiple integer phase values ​​ordered sequentially according to time. Then, based on the amplitude signal corresponding to each integer phase value in the integer phase sequence, the frequency signal of the target frequency is generated.

[0080] Specifically, refer to Figure 3 The direct digital synthesizer constructed based on the internal logic of the DDS includes a fractional phase accumulator, an integer phase accumulator, a selector, a comparator, a phase interpolator, an inverse singer filter, a digital-to-analog converter, and an analog reconstruction filter; wherein, the fractional phase accumulator includes a fractional register, a fractional adder, and a fractional subtractor; and the integer phase accumulator includes an integer register and an integer adder.

[0081] Reference Figure 3 The outputs of the fractional adder and the fractional subtractor are respectively connected to the input signals of the selector; the output of the fractional register is connected to the input signal of the comparator; the first output of the comparator is connected to the input signal of the selector; the second output of the comparator is connected to the input signal of the integer adder; the output of the integer adder is connected to the input signal of the integer register; the output of the integer register is connected to the input signals of the integer adder and the phase interpolator; the output of the selector is connected to the input signal of the fractional register; the output of the phase interpolator is connected to the input signal of the inverse singer filter; the output of the inverse singer filter is connected to the input signal of the digital-to-analog converter; the output of the digital-to-analog converter is connected to the input signal of the analog reconstruction filter; the analog reconstruction filter is used to output the frequency signal corresponding to the target frequency.

[0082] Reference Figure 4 The embodiment provided is based on Figure 3The flowchart shown illustrates a direct digital synthesizer performing a direct digital synthesis method based on a mixing fraction ratio, mainly including steps 401 to 404, wherein the steps are as follows:

[0083] Step 401: Determine the bit width of the integer phase accumulator and the bit width of the fractional phase accumulator based on the target frequency, sampling frequency and preset sampling resolution.

[0084] In this embodiment, the main step is as follows: the process of determining the bit width of the phase accumulator includes two parallel steps: determining the bit width of the integer phase accumulator and determining the bit width of the fractional phase accumulator. The process of determining the integer phase bit width of the integer phase accumulator is as follows:

[0085] The minimum output frequency or frequency resolution required for digital synthesis is determined. The minimum numerical range that the integer phase accumulator needs to accommodate is calculated based on the sampling clock frequency, i.e., the ratio of the sampling frequency to the frequency resolution. Then, the ideal integer bit width of the integer phase accumulator is determined based on the minimum numerical range. Next, the ideal integer bit width is decremented by one based on a preset integer phase accumulation operation to obtain the actual integer bit width of the integer phase accumulator.

[0086] Specifically, in this first embodiment, the bit width selection method of the phase accumulator is related to the sampling frequency Fs, the accuracy requirements of the output frequency Fo, the ratio of the output frequency Fo to Fs, and the amount of available logic resources. Specifically, the value that the fractional phase accumulator can represent must be greater than the denominator of the calculated fractional frequency control word; while the value that the integer phase accumulator can represent must be greater than the value of the sampling frequency divided by the lowest output frequency.

[0087] Regarding the selection of the integer phase bit width for the integer phase accumulator, when Fs = 100MHz (megahertz) and the frequency resolution Fr < 2kHz (kilohertz) is required, the process for determining the integer phase bit width is as follows:

[0088] Fs / Fr = 50000; - 1>Fs / Fr;

[0089] Based on the above determination process, it can be seen that the integer phase bit width needs to be selected as 16 binary bits (2... 16 – 1 = 65535) is the ideal integer bit width for an integer phase accumulator. It should be noted that in order for the target frequency processed by the phase accumulator to vary between 0 and Fs / 2, that is, 0... Fo 0.5Fs, the bit width of the integer frequency control word is the actual integer bit width - 1 (binary). That is, if the actual integer bit width is 16 binary bits, then the bit width of the integer frequency control word should be 15 binary bits.

[0090] Secondly, regarding the selection of the bit width of the fractional phase accumulator, based on the target frequency (Fo), sampling frequency (Fs), and the determined integer phase accumulator bit width (Pac_N), the fractional frequency control word is calculated, and this fractional frequency control word is then reduced to its simplest fractional form to obtain the original denominator frequency control word. The fractional phase accumulator needs to be able to accommodate the original denominator frequency control word; therefore, the formula for calculating the actual fractional bit width of the fractional phase accumulator is as follows:

[0091] With Fs = 100MHz and Fo = 3 + 1 / 3MHz, the fractional frequency control word value after simplification is 8 / 15. Therefore, the value that the fractional phase accumulator can represent must be greater than the denominator of the fractional frequency control word, i.e. -1>15 needs to be true, therefore 5 binary bits can be selected as the actual fractional bit width of the fractional phase accumulator; wherein, the This represents the actual fractional bit width of the fractional phase accumulator.

[0092] In another embodiment of this example, with Fs = 100MHz, Pac_N = 16 bits (binary bits), and Fo = 22.5792MHz, Fcw = 22.5792 * 2 16 / 100 = 14797 + 504512 / 1000000; K = GCD(504512,1000000) = 64; Fcw = 14797 + (504512 / 64) / (1000000 / 64) = 14797 + 7883 / 15625 (simplify the fraction). Therefore... – 1>15625 needs to be true, therefore 14 binary bits can be selected (2 14 –1 = 16383, 16383>15625) is used as the actual fractional bit width of the fractional phase accumulator. Here, Fcw represents the frequency control word, and K represents the greatest common divisor of the numerator and denominator.

[0093] Step 402: Determine the frequency control word based on the target frequency, the sampling frequency, and the bit width, and split the frequency control word into an integer frequency control word, a numerator frequency control word, and a denominator frequency control word.

[0094] In this embodiment, the main steps are as follows: First, determine the total number of phases of the phase accumulator within its full-scale period based on the bit width of the phase accumulator; obtain the product of the target frequency and the total number of phases; and determine the frequency control word based on the ratio of the product to the sampling frequency. The frequency control word is calculated as follows:

[0095] Fcw = (Fo * ) / Fs

[0096] Wherein, Fcw represents the frequency control word; Fo represents the target frequency; Fs represents the sampling frequency of the sampling clock; and Pac_N represents the actual integer bit width of the integer phase accumulator.

[0097] Next, the frequency control word is rounded down to obtain an integer frequency control word, and the frequency error component of the product divided by the sampling frequency is obtained. The frequency error component is then placed at the sampling frequency to obtain the original fractional frequency control word. The greatest common divisor (GCD) of the original numerator and denominator frequency control words is obtained, and the numerator and denominator frequency control words are derived based on the GCD. Specifically, the process of obtaining the numerator and denominator frequency control words is as follows:

[0098] Fcw_i = (Fo * ) / Fs;

[0099] Fcw_r = ((Fo * MOD Fs) / Fs

[0100] Where Fcw_i is the integer frequency control word, Fcw_r is the fractional frequency control word, Pac_N is the bit width of the integer part phase accumulator, and Pac_R is the bit width of the fractional phase accumulator; MOD represents the modulo operator, which uses the remainder to convert Fcw into a mixed number form; GCD represents the greatest common divisor operator, which is used to simplify the fractional part.

[0101] In this embodiment, the integer frequency control word, numerator frequency control word, and denominator frequency control word are calculated as follows: Fs = 100MHz; Fo = 3 + 1 / 3MHz (Ro = 1 / 30); Fr < 2kHz is required; Pac_N = 16 bits; if an integer DDS is used, the frequency resolution is: Fr = 100M / 65536 = 1525.87 Hz; Fcw = 2184.5333 (decimal truncation, rounding) => 2185;

[0102] The actual output frequency is: Fo_r = Fcw / Fr * Fs = 3.334 MHz;

[0103] It can be seen that the output frequency error is 0.0007MHz, which is 213ppm, and is unacceptable in high-precision scenarios. Under the same conditions, keep Pac_N = 16 bits; Fcw_i = 2184 (continued from the integer part of the above formula); Fcw_r = ((10 / 3 * 65536) MOD 100) / 100 = 160 / 300; K=GCD(160,300) = 20; reduce Fcw_r by fraction: Fcw_r = (160 / 20) / (300 / 20) = 8 / 15.

[0104] By filling Fcw_i and Fcw_r into the integer part and fractional part of the frequency control word of the DDS, the required frequency of the DDS output with a mixed fractional ratio can be controlled.

[0105] Verification of the accuracy of the aforementioned frequency control word shows that Fo = (Fcw_i + Fcw_r) / 2 Pac_N *Fs = 3 + 1 / 3 MHz. It can be seen that the output frequency error is theoretically 0, and with the high precision of Fs, it can fully meet the requirements.

[0106] Since Fs is generally a relatively large value, directly using it as the denominator of the fractional part would be too large, requiring large-width registers, adders, and multipliers, which is difficult to implement in hardware circuits. To save resources and power consumption, a relatively smaller bit width can be chosen for the fractional part. Therefore, let K = GCD(Fcw_r numerator, Fcw_r denominator), where K is the greatest common divisor of the numerator and denominator. Dividing both the numerator and denominator by K reduces the fraction Fcw_r to an acceptable range. In practical implementation, GCD can be solved using factorization, short division, or trial division.

[0107] It should be noted that the parameter values ​​provided in the above embodiments are only examples. Parameters such as Fs, Fo, and Fr can be substituted into the calculation of the relevant control word values ​​and the bit width of each accumulator on the data path according to actual needs. At the same time, in order to represent the calculated fraction without error, the bit width of the fractional frequency control word (numerator and denominator) needs to be equal to the bit width of the fractional phase accumulator calculated above.

[0108] The bit width of the integer and fractional part phase accumulator affects the frequency resolution and the range of fractions that can be represented by the DDS. Therefore, in this embodiment, the frequency control word acquisition process allows the relevant bit width to be selected and adjusted during logic design according to user needs. Due to the reconfigurable nature of FPGA, using this design to output a fixed frequency point can greatly reduce the occupation of FPGA logic resources. For ASIC, the selection of the relevant bit width needs to consider versatility. If cost allows, a larger bit width can be selected to accommodate a wider adjustment range and represent more complex fractions.

[0109] Step 403: Input the integer frequency control word into the integer phase accumulator, input the numerator frequency control word into the fractional phase accumulator, input the denominator frequency control word into the fractional phase accumulator and the comparator respectively, and input the sampling frequency of the sampling clock into the integer phase accumulator and the fractional phase accumulator respectively, so that the fractional phase accumulator performs a fractional phase accumulation operation and the integer phase accumulator performs an integer phase accumulation operation to obtain the integer phase value corresponding to each sampling period.

[0110] In this embodiment, the main step is to determine the sampling period based on the sampling frequency of the sampling clock.

[0111] Within each identical sampling period, the fractional phase accumulator adds its stored current fractional phase value to the input molecular frequency control word, i.e., Figure 3 As shown, the A+B operation is performed. Here, A represents the current fractional phase value, and B represents the numerator frequency control word. The integer phase accumulator adds its stored current integer phase value to the input integer frequency control word, i.e., as shown... Figure 3 As shown, the D+E+F operation is performed. Here, F represents the current integer phase value, and F represents the integer frequency control word. It should be noted that, if resources permit, the sum of the outputs from the fractional phase accumulator can be scaled by radix-2 and then added to a longer phase accumulator to obtain a more accurate phase output value.

[0112] For any given sampling period, when the fractional phase accumulator output is summed with the numerator frequency control word and input into the comparator and the selector, and the comparator determines that the sum is greater than or equal to the denominator frequency control word, i.e., if A + B When C occurs, the comparator considers that the fractional phase accumulator has overflowed. At this time, the comparator immediately sends a carry signal E to the integer phase accumulator. The carry signal E is 1 LSB of the integer phase accumulator. At the same time, the comparator sends a signal to the selector. The selector obtains the difference between the sum and the denominator frequency control word according to the signal sent by the comparator, and sends the difference to the fractional phase register so that the current fractional phase value stored in the fractional phase register is updated to the difference.

[0113] When the judge determines that the sum is less than the denominator frequency control word, the judge sends a signal to the selector, and the selector sends the sum to the fractional phase register so that the current fractional phase value stored in the fractional phase register is updated to the sum.

[0114] It should be noted that the carry signal generated by the judgment device is a pulse signal with an effective width of one Fs cycle;

[0115] For any given sampling period, when the integer phase accumulator receives the carry signal from the fractional phase accumulator, it performs an increment operation (1 LSB). Thus, the carry period of the integer phase accumulator is the overflow period of the fractional phase accumulator in the frequency control word. This achieves a hybrid fractional phase accumulator.

[0116] Within any of the sampling periods, the integer phase accumulator operates in parallel with the fractional phase accumulator, except for the carry operation; that is, within a sampling period, while the fractional phase accumulator performs the above addition and overflow judgment / overflow processing, the integer phase accumulator simultaneously accumulates the integer frequency control word and receives the carry signal generated by the fractional phase accumulator.

[0117] Specifically, the integer frequency control word is input to the integer phase accumulator, causing the integer frequency control word to be added to the current integer phase value stored in the integer phase accumulator to obtain a temporary integer phase value. When the carry signal is received, the integer phase accumulator is controlled to increment the temporary integer phase value by one to obtain the real-time integer phase value output by the integer phase accumulator in the sampling period, and this real-time integer phase value is used as the current integer phase value stored in the integer phase accumulator. When the carry signal is not received, the integer phase accumulator is controlled to output the temporary integer phase value as the real-time integer phase value, and this temporary integer phase value is used as the current integer phase value stored in the integer phase accumulator.

[0118] The 0 and maximum values ​​of the integer phase accumulator are mapped to the interval [0, 2π]. Based on the phase accumulation and carry process, the integer phase accumulator continuously accumulates the phase, that is, it increments from 0 to its maximum value. During this process, the phase output to the waveform lookup table changes from [0, 2π]. The waveform lookup table outputs the waveform amplitude to complete one waveform cycle. Afterward, the integer phase accumulator overflows, meaning the accumulator output changes from the maximum value to the maximum value minus 2. 累加器位宽 Then the next waveform output cycle begins.

[0119] Step 404: Input each of the integer phase values ​​into the phase interpolator to obtain the amplitude signal corresponding to the target frequency in each sampling period through the phase interpolator, the inverse singer filter, the digital-to-analog converter, and the analog reconstruction filter.

[0120] In this embodiment, the main steps are as follows: Each integer phase value output by the integer phase accumulator is input into a phase interpolator with a waveform lookup table. For any integer phase value, the digital amplitude of the underlying waveform corresponding to the integer phase value is obtained based on the high-order and low-order phase bits. Interpolation calculation is then performed on the digital amplitude of the underlying waveform based on the low-order phase bits to obtain the digital amplitude of the waveform corresponding to the integer phase value. For a sine wave, a 1 / 4 sine lookup table can be used, with a sign change applied.

[0121] When the accuracy of the lookup table is limited, the mantissa before truncation of the integer phase accumulator and the two nearest sine amplitudes output by the lookup table can be used for Taylor series expansion and interpolation to improve output accuracy and reduce output THD. The Taylor expansion of the sine and cosine functions is shown below:

[0122] Sin x = Σ k=0 (-1)k (2k+1) / (2k+1)! = x – x 3 / 3! + x 5 / 5! – x 7 / 7!

[0123] Cos x = Σ k=0 (-1)k 2k / (2k)! = 1 – x 2 / 2! + x 4 / 4! – x 6 / 6!

[0124] Therefore, the phase increment introduced by the phase interpolator in each sampling period is relatively small. According to the Taylor expansion of the sine function above, the simplest Taylor series expansion interpolation can use the small angle approximation method, that is, only the first term in the series is taken, i.e.: Sinx ≈ x; Cosx ≈ 1.

[0125] By using the truncated mantissa as a linear interpolation of the error into the amplitude value output by the waveform lookup table, the phase error of the output can be reduced. The specific implementation is as follows: The integer phase value output by the integer phase accumulator (only the integer part can be used, or the numerator of the fractional part can be scaled to 1 / 2 LSB size of the integer part by a multiplier and then added to the integer part to be used as a complete phase accumulator. In either way, there is actually a rounding error, but it is lower than the error caused by Taylor expansion), according to the index of the waveform table, the input address of the waveform lookup table is the high bit of the phase value of each integer phase value, where Pac_rem is the truncated mantissa (i.e., phase error); if the bit width of the integer phase accumulator is 16 bits and the index length is 12 bits, Pac_rem = 16 – 12 = 4; then Ladr = Pac[15:4] takes the high 12 bits of the integer phase value; Pac_rem = Pac_rem[3:0] takes the low 4 bits of the integer phase value; according to the sum-to-product formula, Sin(x+y) = sin(x)cos(y) + cos(x)sin(y); Substitute x into Ladder's normalized form (i.e., x = 2π*Laddr / 2) 12 Substitute y into the normalized form of Pac_rem (y = 2π*Pac_rem / 2) 16 Since y is relatively small, only the first term of the Taylor series can be taken in the implementation (the number of terms can be increased to further reduce output spectral spurious signals), that is: Sin(x+y) = sin(x) * 1 + cos(x) * y, where sin(x) and cos(x) are obtained from the sine lookup table through Ladr, and the obtained sine and cosine amplitudes are multiplied by the Taylor expansion by a multiplier and then added together. In this example implementation, they are 1 and y, and more terms can be selected as needed to improve the accuracy of the output. Wherein, Ladr is the index of the waveform lookup table;

[0126] Furthermore, for the sake of simplified calculation, when high output precision and a large number of terms are required, multiple lookup tables can be used to output the corresponding terms (such as x for the sinx function) when calculating the Taylor expansion of the sine and cosine functions with respect to Pac_rem (i.e., the y-value). 3 / 3! x 5The value of / 5!…) can be adjusted to reduce the performance overhead of calculating the Taylor expansion. Preferably, dithering can also be added to the phase and amplitude values ​​to further reduce output spurious noise (phase noise, quantization noise).

[0127] After the phase interpolator outputs the digital amplitude of the waveform, the digital amplitude is input into the inverse sinc filter to compensate for the zero-order hold characteristic of the DAC. The inverse sinc filter is characterized by its output frequency response being exactly opposite to the zero-order hold frequency response, thus compensating for the roll-off caused by the DAC's zero-order hold characteristic. For implementation, a digital filter is recommended; either an FIR filter or an IIR filter can be used. The appropriate digital filter structure, order, and coefficients can be selected based on requirements such as frequency response flatness and resource consumption. Analog filters can also be used when requirements are not high. Preferably, as shown... Figure 3 As shown, after the integer phase accumulator outputs an integer phase value H and before inputting the integer phase value H into the waveform lookup table, it can also receive an externally input phase control word G to adjust H through the phase control word G. Specifically, the bit width of the phase control word G is the same as the bit width of the integer phase accumulator, and it is used to dynamically adjust the output phase, so that the phase of the output frequency can be moved according to the user's needs, realizing the phase modulation function.

[0128] Finally, the digital amplitude of the waveform is transformed into an analog signal through a DAC and a reconstruction filter, and the output is the amplitude signal corresponding to the target frequency.

[0129] The direct digital synthesis method based on a hybrid fractional ratio disclosed in this embodiment changes the phase counter and frequency control word from integers to a hybrid integer / fractional ratio. This hybrid fractional ratio eliminates rounding errors in the output frequency when fractional division is required, while also reducing the number of logic gates and resource consumption. Next, when resources permit, the fractional part also participates in phase interpolation calculations to ensure that the output phase is free from periodic modulation, reducing output phase noise and spurious components. Finally, the amplitude can be interpolated using Taylor series expansion, resulting in higher output amplitude accuracy and reducing output spectral spurious components under low resource usage.

[0130] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A method of direct digital synthesis based on hybrid fractional- ratio, characterized in that, The method comprises: determining a frequency control word based on a target frequency, a sampling frequency and a bit width of a phase accumulator, and splitting the frequency control word into an integer frequency control word, a numerator frequency control word and a denominator frequency control word; performing a fractional phase accumulation operation based on the sampling frequency, the numerator frequency control word and the phase accumulator to generate a carry signal; wherein the fractional phase accumulation operation comprises obtaining an accumulation result of the numerator frequency control word according to the phase accumulator, and generating the carry signal according to the accumulation result and the denominator frequency control word; performing an integer phase accumulation operation according to the sampling frequency, the integer frequency control word and the phase accumulator in parallel with the fractional phase accumulation operation to obtain an integer phase value; wherein the integer phase accumulation operation comprises obtaining an accumulation result of the integer frequency control word according to the phase accumulator and the carry signal to obtain an integer phase value; obtaining a waveform digital amplitude corresponding to the integer phase value to perform signal conversion according to the waveform digital amplitude to obtain an amplitude signal corresponding to the target frequency; wherein the determining of the frequency control word based on the target frequency, the sampling frequency and the bit width of the phase accumulator, and the splitting of the frequency control word into the integer frequency control word, the numerator frequency control word and the denominator frequency control word comprise: determining a total number of phases of the phase accumulator in a full-scale period according to a bit width of the phase accumulator; obtaining a product of the target frequency and the total number of phases, and dividing the product by the sampling frequency to obtain a frequency control word; performing an integer operation on the frequency control word to obtain an integer frequency control word, and obtaining a remainder of the frequency control word to take the remainder as a frequency error component; dividing the frequency error component by the sampling frequency to obtain an original fractional frequency control word; wherein the original fractional frequency control word is a ratio of an original numerator frequency control word to an original denominator frequency control word; obtaining a greatest common divisor of the original numerator frequency control word and the original denominator frequency control word to obtain a numerator frequency control word and a denominator frequency control word according to the greatest common divisor.

2. The hybrid fractional ratio-based direct digital synthesis method of claim 1, wherein, the performing of the fractional phase accumulation operation based on the sampling frequency, the numerator frequency control word and the phase accumulator to generate the carry signal comprises: determining a sampling period of the numerator frequency control word and the integer frequency control word according to the sampling frequency; for any one of the sampling periods, inputting the numerator frequency control word into a fractional phase accumulator to add the numerator frequency control word to a current fractional phase value saved in the fractional phase accumulator to obtain a temporary sum; when the temporary sum is greater than or equal to the denominator frequency control word, controlling the fractional phase accumulator to generate a carry signal and obtain a difference between the temporary sum and the denominator frequency control word, and taking the difference as the current fractional phase value saved in the fractional phase accumulator.

3. The hybrid fractional ratio-based direct digital synthesis method of claim 2, wherein, the performing of the fractional phase accumulation operation based on the sampling frequency, the numerator frequency control word and the phase accumulator to generate the carry signal comprises: For any one of the sampling periods, when the temporary sum is less than the denominator frequency control word, the temporary sum is taken as the current fractional phase value saved by the fractional phase accumulator.

4. The hybrid fractional ratio-based direct digital synthesis method of claim 2, wherein, The integer phase accumulation operation is performed in parallel with the fractional phase accumulation operation according to the sampling frequency, the integer frequency control word and the phase accumulator, to obtain an integer phase value, comprising: For any one of the sampling periods, the integer frequency control word is input into an integer phase accumulator, so that the integer frequency control word is added to a current integer phase value saved in the integer phase accumulator, to obtain a temporary integer phase value; When the carry signal is received, the integer phase accumulator is controlled to perform a plus one operation on the temporary integer phase value, to obtain a real-time integer phase value output by the integer phase accumulator in the sampling period and take the real-time integer phase value as the current integer phase value saved in the integer phase accumulator.

5. The hybrid-fractional-band-based direct digital synthesis method of claim 4, wherein, The integer phase accumulation operation is performed in parallel with the fractional phase accumulation operation according to the sampling frequency, the integer frequency control word and the phase accumulator, to obtain an integer phase value, comprising: For any one of the sampling periods: When the carry signal is not received, the integer phase accumulator is controlled to output the temporary integer phase value as the real-time integer phase value and take the temporary integer phase value as the current integer phase value saved in the integer phase accumulator.

6. The hybrid fractional-n based direct digital synthesis method of claim 1, wherein, The waveform digital amplitude value corresponding to the integer phase value is obtained, and signal conversion is performed according to the waveform digital amplitude value, to obtain an amplitude signal corresponding to the target frequency, comprising: The phase value high bit and the phase value low bit of the integer phase value are obtained, a preset waveform lookup table is queried according to the phase value high bit, to obtain a basic waveform digital amplitude value corresponding to the integer phase value; The basic waveform digital amplitude value is subjected to interpolation calculation according to the phase value low bit, to obtain the waveform digital amplitude value corresponding to the integer phase value; The waveform digital amplitude value is subjected to digital-to-analog conversion operation, to obtain an analog signal, and the analog signal is filtered, to obtain the amplitude signal corresponding to the target frequency.

7. The hybrid-fractional-band-based direct digital synthesis method of claim 6, wherein, The waveform digital amplitude value corresponding to the integer phase value is obtained, and signal conversion is performed according to the waveform digital amplitude value, to obtain an amplitude signal corresponding to the target frequency, further comprising: A zero-order hold model of the digital-to-analog conversion operation is obtained, to determine a inverse-sine target frequency response function according to the zero-order hold model and the sampling frequency; The waveform digital amplitude value is subjected to amplitude compensation according to the inverse-sine target frequency response function, and the waveform digital amplitude value subjected to the amplitude compensation is subjected to digital-to-analog conversion operation, to obtain the amplitude signal.

8. The hybrid fractional-n based direct digital synthesis method of claim 1, wherein, Before the frequency control word is determined based on the target frequency, the sampling frequency and the bit width of the phase accumulator, and the frequency control word is split into the integer frequency control word, the numerator frequency control word and the denominator frequency control word, comprising: A resolution ratio of the sampling frequency and a preset sampling resolution is obtained, to determine an actual integer bit width of the integer phase accumulator according to the ratio; determine an original denominator frequency control word of the frequency control word according to the target frequency, the sampling frequency and the actual integer bit width; determine an actual fractional bit width of a fractional phase accumulator according to the original denominator frequency control word.

9. A direct digital synthesis system based on mixed fraction ratios, characterized in that, comprise a control word splitting module, a fractional phase accumulation module, an integer phase accumulation module and a waveform conversion module; the control word splitting module is configured to determine a frequency control word based on a target frequency, a sampling frequency and a bit width of a phase accumulator, and split the frequency control word into an integer frequency control word, a numerator frequency control word and a denominator frequency control word; wherein the bit width of the phase accumulator is used to determine a total number of phases of the phase accumulator in a full-scale period; a product of the target frequency and the total number of phases is obtained to divide the product by the sampling frequency to obtain the frequency control word; an integer frequency control word is obtained by rounding the frequency control word, and a remainder of the frequency control word is obtained to take the remainder as a frequency error component; the frequency error component is divided by the sampling frequency to obtain an original fractional frequency control word; wherein the original fractional frequency control word is a ratio of an original numerator frequency control word and an original denominator frequency control word; a greatest common divisor of the original numerator frequency control word and the original denominator frequency control word is obtained to obtain the numerator frequency control word and the denominator frequency control word according to the greatest common divisor; the fractional phase accumulation module is configured to perform a fractional phase accumulation operation based on the sampling frequency, the numerator frequency control word and the phase accumulator to generate a carry signal; wherein the fractional phase accumulation operation comprises obtaining an accumulation result of the numerator frequency control word according to the phase accumulator to generate the carry signal according to the accumulation result and the denominator frequency control word; the integer phase accumulation module is configured to perform an integer phase accumulation operation according to the sampling frequency, the integer frequency control word and the phase accumulator in parallel with the fractional phase accumulation operation to obtain an integer phase value; wherein the integer phase accumulation operation comprises obtaining an accumulation result of the integer frequency control word according to the phase accumulator and the carry signal to obtain the integer phase value; the waveform conversion module is configured to obtain a waveform digital amplitude corresponding to the integer phase value to perform signal conversion according to the waveform digital amplitude to obtain an amplitude signal corresponding to the target frequency.

Images