Multi-domain precise clock synchronization method on train

Abstract

The invention provides a multi-domain precise clock synchronization method on a train, which comprises the following steps: designing a biplane annular networking topology, and establishing a train operation network; in the initial running stage of a train, a multi-domain precise clock synchronization protocol gPTP is executed, a logic isolation virtual local area network is divided according to a full-independent multi-synchronization-domain architecture, gPTP instance synchronization parameters are configured, and a synchronization protocol is started; in each synchronization domain, all nodes periodically broadcast Announce messages to transmit clock information, and decide a master clock (MC) according to the BMCA; periodically calculating link propagation time delay among all the synchronization ports; according to the clock synchronization spanning tree, starting from the master clock, using Sync and FollowUp message periods to transmit the time of the master clock, and synchronizing the slave clock step by step; the gPTP instance in the multiple domains calculates an offset value according to Sync and FollowUp messages and inputs the offset value into a detection component, and the detection component calculates and corrects the offset value and checks fault master clock information; and inputting the offset value into a correction component, aggregating the offset value into a corrected offset value, inputting the corrected offset value into an action component, and updating a local gPTP clock according to the corrected offset value to complete clock synchronization.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of clock synchronization, in particular, and more particularly to a multi-domain precise clock synchronization method on a train. BACKGROUND

[0002] With the continuous development of train technology, the Train Communication Network (TCN) plays a crucial role in train operation. TCN is used to transmit key data during train operation, including Process Data (PD), Message Data (MD), and monitoring data. Accurate transmission of these data is essential for the safe operation and efficient management of trains. The traditional TCN architecture is mainly based on the IEC 61375 standard, which is jointly developed by the International Electrotechnical Commission (IEC) and the International Union of Railways (UIC), and specifies the basic architecture of TCN backbone network and marshalling network.

[0003] Currently, the train communication network mainly uses Wire Train Bus (WTB) and Multifunction Vehicle Bus (MVB) for data transmission. Although WTB and MVB meet the needs of train communication to some extent, with the increasing intelligence of trains, the number of intelligent devices, sensors and controllers is increasing, leading to a significant increase in data traffic. This makes the traditional dedicated bus network face problems such as insufficient bandwidth, high maintenance cost and poor scalability. In addition, in order to meet the transmission requirements of large-bandwidth multimedia traffic, backbone networks and marshalling networks also gradually adopt switching Ethernet technology. However, these technologies have obvious shortcomings in clock synchronization, and it is difficult to meet the requirements of high-precision clock synchronization.

[0004] In the prior art, the clock synchronization of the train communication network mainly relies on the IEEE 1588 Precise Time Protocol (PTP). Although PTP improves the accuracy of clock synchronization to some extent, its synchronization accuracy and reliability are still insufficient to meet the requirements of intelligent railway systems for high precision and high reliability. In particular, in the case of train marshalling, re-marshalling and link failure, the clock synchronization scheme of a single synchronization domain cannot guarantee the stability and reliability of clock synchronization. In addition, the existing clock synchronization method has the problems of low synchronization accuracy, large error, and difficulty in integrating device operation and maintenance data, which seriously affects the real-time performance and intelligent operation and maintenance capability of the train control system. Therefore, designing a multi-domain precise clock synchronization method suitable for train communication network to improve the accuracy and reliability of clock synchronization has become a technical problem to be solved at present. SUMMARY

[0005] According to the technical problems proposed above, a multi-domain accurate clock synchronization method on a train is provided. The application solves the problems of low clock synchronization accuracy, poor reliability, difficulty in adapting to train reorganization and link failure in the traditional train communication network by designing a double-plane ring networking topology and a full-independent multi-clock synchronization domain architecture, combining an improved gPTP protocol and a synchronization algorithm, realizing high-precision and high-reliability clock synchronization, and meeting the strict requirements of the intelligent railway system on clock synchronization.

[0006] The technical means adopted by the application are as follows: A multi-domain accurate clock synchronization method on a train, comprising: S1, designing a double-plane ring networking topology and building a train operation network; S2, in the initial operation stage of the train, executing a multi-domain accurate clock synchronization protocol gPTP based on the built train operation network, dividing a logical isolation VLAN according to a full-independent multi-synchronization domain architecture, configuring gPTP instance synchronization parameters in each domain, and starting the synchronization protocol; S3, in each synchronization domain, all nodes periodically broadcast Announce messages to transfer clock information, and decide a master clock MC according to BMCA; S4, the link propagation delay is periodically calculated through Pdelay_Req, Pdelay_Resp and Pdelay_Resp_Follow_Up messages between all synchronization ports, so as to ensure the accuracy of clock synchronization; S5, a clock synchronization spanning tree is generated, and the master clock time is periodically transferred using Sync and Follow_Up messages from the master clock, and the slave clock is synchronized step by step; S6, the gPTP instance in the multi-domain calculates an offset value according to the Sync and Follow_Up messages, and inputs the calculated offset value into a detection component, the detection component calculates a corrected offset value and checks the fault master clock information; S7, the offset value in the multi-domain is input into a correction component, and the correction component aggregates the offset value into a corrected offset value and inputs the corrected offset value into an action component; S8, the action component updates the local gPTP clock according to the corrected offset value, and completes the clock synchronization.

[0007] Further, step S1 comprises: S11, determining the ring double-plane structure of the backbone network and the marshalling network, wherein the upper nodes and the lower nodes of the ring of the backbone network belong to two planes A and B, and the nodes of the marshalling network directly connected with the backbone network are in the same plane, and the main architecture of the network is constructed based on this; S12, for each marshalling network, it is designed as a ring topology belonging to two planes, and one marshalling network is deployed in one closed carriage, and the network structure is further refined to meet the communication needs of devices in different carriages; S13, the terminal devices in the train are divided into single-homed terminals and dual-homed terminals, wherein the single-homed terminals have only one network interface exposed to the network, and the dual-homed terminals need two ports to be connected to the switching devices of the A and B planes respectively, and the network interfaces are reasonably allocated according to the types of the terminal devices, so that all devices can access the built double-plane ring network, and a network foundation is provided for subsequent clock synchronization operations.

[0008] Further, step S2 comprises: S21, in the initial running stage of the train, all nodes participating in the TSN network and traffic configuration are initialized to ensure that each node supports the multi-domain gPTP protocol and function; S22, according to the all-independent multi-synchronization domain architecture, the network is logically isolated using virtual local area network (VLAN) technology; each gPTP instance runs in a different VLAN, and the clock device listens to and processes gPTP packets in multiple VLANs through the same physical interface; for example, Domain 0-3 of the backbone network uses VLAN 100, VLAN 200, VLAN 300, and VLAN 400 respectively, so as to ensure that the packets between different synchronization domains do not interfere with each other; S23, configure synchronization parameters for the gPTP instance in each VLAN, including clock accuracy, clock priority, and clock category; the configuration of these parameters will directly affect the accuracy and reliability of clock synchronization, and ensure that the clock synchronization within each synchronization domain can be carried out according to the predetermined rules; S24, start the multi-domain precise clock synchronization protocol gPTP, so that each node starts the clock synchronization operation according to the configured parameters and protocol rules, including broadcasting Announce packets, calculating link propagation delay, and transmitting master clock time, so as to realize multi-domain clock synchronization of the entire train network.

[0009] Further, step S3 comprises: S31, all nodes in each synchronization domain generate Announce packets according to a predetermined period. The Announce packet is a key message in the clock synchronization protocol, which is used to transmit the attribute information of the clock, including priority1, clockClass, clockAccuracy, offsetScaledLogVariance, priority2, and clockIdentity; S32, each node broadcasts the generated Announce packet in the synchronization domain to which it belongs, so that other nodes in the synchronization domain receive the packet and obtain the clock information of the sending node; the broadcasting process ensures that the clock information can be propagated in the entire synchronization domain, providing a basis for subsequent master clock election; S33, each node in the synchronization domain receives the Announce packet from other nodes and parses the clock attribute information in the packet; the receiving process is the corresponding operation of broadcasting, ensuring that each node can obtain the clock information of all other nodes in the synchronization domain, providing complete data support for subsequent master clock election; S34, each node executes the Best Master Clock Algorithm (BMCA) according to the clock attribute information in the received Announce packet, and elects a master clock (MC) by comparing the attribute information carried in the Announce packet according to the Best Master Clock Algorithm. The master clock is the reference for clock synchronization in the synchronization domain, and all other nodes (slave clocks) will synchronize their clocks according to the time information of the master clock. The election of the master clock ensures that there is a unified time reference in the synchronization domain, providing a key reference for subsequent clock synchronization operations; Further, step S4 comprises: S41, each synchronization port periodically sends a Pdelay_Req (delay request) packet to the opposite port to request the opposite port to measure and return the link propagation delay; the sending of this packet marks the start of the link propagation delay measurement process, providing a trigger signal for subsequent delay calculation; S42, after receiving the Pdelay_Req packet, the opposite port records the exact time point of receiving the packet; the recording of this time point is one of the key data for calculating the link propagation delay, which reflects the time from the sending end to the receiving end of the packet.

[0010] S43, after recording the receiving time, the opposite port immediately sends a Pdelay_Resp (delay response) packet to the sending port, which carries the time information recorded by the opposite port when receiving the Pdelay_Req packet; the sending of this packet is to pass the receiving time information back to the sending port, so that the sending port can calculate the link propagation delay; S44, after receiving the Pdelay_Resp packet, the sending port calculates the link propagation delay according to the time of sending the Pdelay_Req packet and the receiving time carried in the received Pdelay_Resp packet; S45, after sending the Pdelay_Resp packet, the opposite end port sends a Pdelay_Resp_Follow_Up packet to further improve the accuracy of the time delay measurement. The packet carries the accurate time information when the opposite end port sends the Pdelay_Resp packet. The sending of this packet is to provide more accurate time synchronization information to help the sending port more accurately calculate the link propagation delay; S46, after receiving the Pdelay_Resp_Follow_Up packet, the sending port corrects the previously calculated link propagation delay according to the time information carried in the packet. The corrected delay value will be more accurate and can better reflect the actual propagation characteristics of the link, thereby providing more accurate delay compensation data for clock synchronization; S47, repeat the above process to periodically calculate the link propagation delay to ensure the accuracy of clock synchronization.

[0011] Further, step S5 includes: S51, in each synchronization domain, determine the clock synchronization spanning tree according to the network topology and clock synchronization requirements. The spanning tree defines the synchronization path from the master clock to each slave clock, ensuring that each slave clock can receive time synchronization information from the master clock. The construction of the spanning tree is based on the physical connection and logical relationship between nodes to ensure the efficiency and reliability of clock synchronization; S52, the master clock (MC) port sends a Sync packet at a predetermined period. The Sync packet carries the accurate timestamp of the master clock, which is used to notify the slave clock (SC) of the current time of the master clock. The master clock port records the sending timestamp when sending the Sync packet, which is the basis for subsequent clock synchronization calculation; S53, after receiving the Sync packet from the master clock, the slave clock port records the accurate time of receiving the packet. The slave clock port needs to record the receiving time to calculate the link propagation delay from the master clock to the slave clock. This step is a key link in clock synchronization, ensuring that the slave clock can accurately obtain the time information of the master clock; S54, after sending the Sync packet, the master clock port sends a Follow_Up packet. The Follow_Up packet carries the accurate timestamp (preciseOriginTimestamp) of the master clock sending the Sync packet and the accumulated correction time (correctionField) from receiving the previous hop Sync packet to sending the current Sync packet. The Follow_Up packet provides a correction value to help the slave clock more accurately calculate the clock offset; S55, after receiving the Follow_Up message from the clock port, using the preciseOriginTimestamp and correctionField carried in the Follow_Up message, combining the time of receiving the Sync message recorded by itself, calculating the clock offset value; S56, adjusting the local clock time according to the offset value calculated by the slave clock; S57, repeating the above process, each slave clock periodically receives the time information of the master clock, and adjusts the local clock according to the latest offset value, to ensure that all clocks in the whole synchronization domain always maintain high-precision synchronization state.

[0012] Further, step S6 includes: S61, each gPTP instance in the multi-domain receives the Sync message and the Follow_Up message from the master clock; wherein the Sync message carries the precise time stamp of the master clock, and the Follow_Up message carries the precise time stamp (preciseOriginTimestamp) and the accumulated correction time (correctionField) of the master clock when sending the Sync message; S62, each gPTP instance calculates the preliminary offset value according to the received Sync message and Follow_Up message; S63, input the calculated preliminary offset value into the detection component, and the detection component is used to further analyze and process the preliminary offset value to ensure its accuracy and reliability. The detection component verifies the received preliminary offset value to check whether there is an anomaly or error; S64, if the detection component finds that the preliminary offset value is abnormal, the preliminary offset value will be corrected according to the preset algorithm; S65, in the process of verifying and correcting the offset value, the detection component will also check whether there is a sign of faulty master clock, if it is found that the offset value of a certain master clock is continuously abnormal or exceeds the reasonable range, the detection component will record and report the fault information; S66, after the verification and correction of the detection component, the final offset value is obtained.

[0013] Further, step S7 includes: S71, collecting the calculated offset values from the gPTP instances of each synchronization domain, which reflect the time deviation between the slave clock and the master clock in each synchronization domain; S72, input the collected multi-domain offset value into the correction component, the correction component performs aggregation operation by using algorithms including election method, weighted average algorithm, least square method and Kalman filter to obtain an aggregated offset value; S73, the correction component generates a final correction offset value according to the aggregated offset value, and inputs the generated correction offset value into the action component.

[0014] Further, step S8 comprises: S81, the action component receives the correction offset value from the correction component, and according to the aggregated offset value, uses a clock convergence algorithm including an empty servo algorithm, a linear regression adaptive algorithm and a PI servo algorithm to obtain a correction offset value; S82, the local gPTP clock is corrected by using the correction offset value, so that the local clock is kept synchronized with the master clock; S83, the local clock records the adjusted state, including the adjustment time and adjustment amount information; S84, the action component verifies whether the updated local clock is synchronized with the master clock, if there is a deviation, the adjustment process is repeated until the verification result shows that the local clock is synchronized with the master clock, and the clock synchronization operation is completed.

[0015] Compared with the prior art, the present application has the following advantages: 1. The double-plane ring network topology designed in the present application ensures network bandwidth and resource utilization, and takes into account the reliability and deterministic communication requirements of the TSN standard. The ring backbone network reduces the synchronization difficulty of the synchronization domain of the backbone network, and each synchronization domain has clear boundaries and strong scalability.

[0016] 2. The all-independent multi-clock synchronization domain architecture designed in the present application adopts double-master clock hot standby redundancy and double-synchronization spanning tree method to ensure the accuracy and stability of clock synchronization under most network fault conditions.

[0017] 3. The synchronization component architecture designed in the present application describes in detail the execution logic and function of the detection component, the correction component and the action component, and the modular design improves the maintainability, reusability and system reliability of the architecture.

[0018] 4. The present application is designed for train communication system, and its network topology, domain division design and protocol layer synchronization architecture are also applicable to other industrial network fields to realize high-reliable clock synchronization, which is helpful to promote the research and landing of TSN standard in a larger range. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings described below are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0020] Figure 1 The method flowchart of the present application.

[0021] Figure 2 The train new double-plane ring network topology schematic diagram provided by the embodiment of the present application.

[0022] Figure 3 The full independent multi-clock synchronization domain schematic diagram provided by the embodiment of the present application.

[0023] Figure 4 The multi-domain synchronization message processing component architecture schematic diagram provided by the embodiment of the present application. DETAILED DESCRIPTION

[0024] In order to make the person skilled in the art better understand the present application scheme, the following will combine the drawings in the embodiments of the present application, and the technical solutions in the embodiments of the present application will be described clearly and completely. Obviously, the described embodiments are only some embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should be within the scope of the present application.

[0025] It should be noted that the terms "include" and "have" and any variations thereof in the specification and claims of the present application and the above-mentioned drawings are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device containing a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0026] As shown in Figure 1 The present application provides a multi-domain precise clock synchronization method on a train, comprising: S1, designing a double-plane ring network topology and building a train operation network; S2, in the initial operation stage of the train, performing a multi-domain precise clock synchronization protocol gPTP based on the built train operation network, dividing a logical isolation VLAN according to a full independent multi-synchronization domain architecture, configuring gPTP instance synchronization parameters in each domain, and starting the synchronization protocol; S3, in each synchronization domain, all nodes periodically broadcast Announce messages to deliver clock information, and determine the master clock MC according to BMCA; S4, all synchronization ports periodically calculate link propagation delay through Pdelay_Req, Pdelay_Resp, and Pdelay_Resp_Follow_Up messages to ensure the accuracy of clock synchronization; S5, according to the clock synchronization spanning tree, the master clock time is periodically transmitted using Sync and Follow_Up messages from the master clock, and the slave clock is synchronized step by step; S6, the gPTP instance in the multi-domain calculates the offset value according to the Sync and Follow_Up messages, and inputs the calculated offset value into the detection component, which calculates the corrected offset value and checks the fault master clock information; S7, input the offset value in the multi-domain into the correction component, which aggregates into a corrected offset value and inputs into the action component; S8, the action component updates the local gPTP clock according to the corrected offset value, and completes the clock synchronization.

[0027] In specific implementation, as a preferred embodiment of the present application, step S1 comprises: S11, determine the ring double-plane structure of the backbone network and the marshalling network, wherein the upper and lower nodes of the ring of the backbone network belong to two planes A and B, and the nodes of the marshalling network directly connected to the backbone network belong to the same plane, and the main architecture of the network is constructed on this basis; S12, for each marshalling network, design it as a ring topology belonging to two planes, and deploy one marshalling network in one closed carriage, further refine the network structure to meet the communication needs of devices in different carriages; S13, divide the terminal devices in the train into single-homed terminal and dual-homed terminal, wherein the single-homed terminal has only one network interface exposed to the network, and the dual-homed terminal needs two ports to be connected to the switching devices of the two planes A and B, and the network interfaces are reasonably allocated according to the type of terminal device to ensure that all devices can access the double-plane ring network built, and provide network basis for subsequent clock synchronization operation.

[0028] In this embodiment, a network topology meeting the requirements of train multi-domain clock synchronization and deterministic transmission capability is designed, including all traffic of process data, message data, monitoring data, flow data, and best-effort data running in the time-sensitive train communication network, such as Figure 2As shown, designed as a two-stage ring double-plane topology, the first stage topology carries the backbone network traffic, the upper nodes ETBN1-1~ETBNm-1 and the lower nodes ETBN1-2~ETBNm-2 of the ring belong to two planes A and B, and the marshalling network nodes directly connected with the backbone network belong to the same plane, the second stage topology carries the marshalling network traffic, generally one marshalling network is deployed in one closed carriage, also designed as a ring topology belonging to two planes, for the terminal devices in the train, there are two types, one is a single-attached terminal, only one network interface is exposed to the network, the other is a double-attached terminal, the device needs two ports to be connected with the switching devices of two planes A and B, for the two types of terminals, the TSN protocols that can be implemented are different, and the deterministic capabilities implemented accordingly are different. Next, the advantages of the design of the topology are discussed, as follows: The physical length of the train is large, in order to ensure the data transmission quality and reliability, the Ethernet cable should not be too long, therefore, the backbone network between the head and tail carriages is generally linear, IEC 61375-2-5 recommends using a link aggregation protocol to increase network bandwidth, and using a bypass function to solve node failure problems, the selection of the marshalling network is not strictly limited, linear, ring, and ladder can all be used as the topology of the marshalling network, which is a design compatible with worse cases, which can ensure the reachability of the traffic when node or link failure occurs, however, when running TSN protocols with higher requirements for determinism, the original advantages become disadvantages, the forwarding window of the scheduled key traffic in TSN on the switching node is accurately calculated, assuming that the switching device A fails and the bypass function is enabled, the switching device queuing delay, processing delay, and transmission delay required for the traffic originally forwarded through A change, and when reaching the next hop, may be out of order with other data packets of the same priority, causing the original calculated gating list to not correspond to the out-of-order data packets one by one, thereby causing network determinism to fail, therefore, the bypass function in TSN should be discarded. To ensure that the bandwidth on the backbone network does not decrease, redundant standby ETB nodes can be placed on another plane, data on the train can be transmitted through two planes, based on the same idea, the marshalling network is also designed as a double-plane ring network, for the communication between double-attached train terminal devices, the following ideas are used to ensure reliable determinism: 1) When centralized scheduling, a scheduling scheme is calculated for all traffic to balance the load to two planes, when failure occurs, real-time incremental scheduling is started, the reason for using incremental scheduling is to reduce the impact on normal running traffic, and to re-plan the traffic through the failed link to another plane link. The advantage of this scheme is that the centralized scheduling before initial operation is relatively low in difficulty, and the network resource occupation of the scheduled flow is small, the disadvantage is that an effective real-time scheduling scheme needs to be designed, and the scheduling switching delay of the failed link flow is large.

[0029] 2) In the network scheduling stage before the initial operation of the train, the main and backup link scheduling schemes are prepared. If node or link failure occurs during the operation of the main scheduling link, the backup scheduling link is switched. Compared with scheme 1, the centralized scheduling difficulty of this scheme is higher, but the advantage is that the switching delay of the failed link traffic is lower.

[0030] 3) If the terminal device has the IEEE 802.1CB reliable frame replication and elimination capability, zero switching delay can be achieved on the basis of scheme 2, and the receiver of the service communication can not perceive the influence caused by the network failure. This scheme can maximize the reliability of data transmission, but it requires the CB protocol capability of the terminal device.

[0031] The above schemes provide two communication links for all service traffic, which can handle single node and single link failures outside the communication terminal. For data traffic transmitted on the marshalling network, timely communication can be restored only when both paths through the two planes of the marshalling network fail, which does not affect the transmission of other traffic on the marshalling network. Similarly, for traffic transmitted on the backbone network, timely communication can be restored only when both main and backup backbone network paths fail.

[0032] In specific implementation, as a preferred embodiment of the present application, step S2 comprises: S21, in the initial operation stage of the train, all nodes participating in the TSN network and traffic configuration are initialized to ensure that each node supports the multi-domain gPTP protocol and function; S22, according to the full independent multi-synchronization domain architecture, the network is logically isolated using virtual local area network (VLAN) technology; each gPTP instance runs in a different VLAN, and the clock device simultaneously listens to and processes gPTP packets in multiple VLANs through the same physical interface; for example, Domain 0-3 of the backbone network uses VLAN 100, VLAN 200, VLAN 300, and VLAN 400, respectively, to ensure that packets between different synchronization domains do not interfere with each other; S23, configure synchronization parameters for the gPTP instance in each VLAN, including clock accuracy, clock priority, and clock category; the configuration of these parameters will directly affect the accuracy and reliability of clock synchronization, ensuring that the clock synchronization within each synchronization domain can be performed according to the predetermined rules; S24, start the multi-domain precise clock synchronization protocol gPTP, so that each node starts clock synchronization operation according to the configured parameters and protocol rules, including broadcasting Announce packets, calculating link propagation delay, and transferring master clock time, thereby realizing multi-domain clock synchronization of the entire train network.

[0033] In this embodiment, in order to provide high-reliable precise clock synchronization, a full independent multi-clock synchronization domain scheme is designed based on the double-plane ring network design, as shown in the figure. Figure 3 The backbone network has a global master clock (GMC) GMC_0 and GMC_1 at the head and tail respectively, wherein GMC_1 is a hot standby clock of GMC_0, and synchronizes the local clock to GMC_0 in normal operation, GMC_0 and GMC_1 are MCs of the spanning tree in two directions respectively, each node on the backbone network is in three synchronization domains, namely domain0 and domain1 of GMC_0 as MC, and domain2 or domain3 of GMC_1 as MC, since the spanning tree when GMC_1 is the master clock does not contain GMC_0, therefore other nodes can only receive GMC_1 synchronization messages in one direction, and a gPTP instance is created in each synchronization domain. Since the double-plane backbone network is also a ring topology, clock synchronization on the backbone network can avoid the design difficulty and synchronization overhead caused by cross-consist network synchronization. The backbone network synchronization fails only when both GMCs fail at the same time; the clock of a node cannot be synchronized only when all links from the node to the two GMCs are not available.

[0034] For each consist network, the clocks on two backbone network nodes connected to the consist network are selected as consist master clocks (CMC) CMC_0 and CMC_1, CMC_0 and CMC_1 are MCs of the spanning tree in two directions respectively, each node on the consist network is in four synchronization domains, namely domain4i and domain4i+1 of CMC_0 as MC, and domain4i+2 and domain4i+3 of CMC_1 as MC, wherein i=1, 2,..., n, n is the number of consist networks, and a gPTP instance is created in each synchronization domain. For the backbone network nodes connected to the consist network, GMC_0 and GMC_1 are master clocks of six synchronization domains, GMC_1 is a slave clock of two synchronization domains, and the remaining clocks are master clocks of four synchronization domains on the consist network and slave clocks of three synchronization domains on the backbone network. Single-homed terminal devices connected to the consist network are slave clocks of four synchronization domains, and dual-homed devices connected to the consist network are slave clocks of four synchronization domains, but will receive twice synchronization messages with the same sequence number from each synchronization domain, and the gPTP instance needs to filter the synchronization information with duplicate sequence numbers before calculating the offset. The multi-domain clock synchronization scheme has the following advantages: 1) The distribution of GMC and CMC reduces the synchronization level of each node to the MC, and when designing the detection and correction component algorithm, the weight of the synchronization message of the sub-domain with less level to the MC can be increased, thereby improving the clock synchronization accuracy.

[0035] 2) The backbone network and each marshalling network have independent synchronization domain designs, and when small-scale topology changes or train re-marshalling occur, the interference between the synchronization domains is minimized.

[0036] 3) Each node other than the GMC is located in at least 4 synchronization domains, which can avoid most multi-node and multi-link failure conditions.

[0037] Two GMCs are configured in the entire train communication network, and the nodes on the other backbone network nodes are synchronized in 4 domains. If one of the GMCs has jitter, drift, jump, or other faults, the clock accuracy decreases, but as the master clock, it still sends synchronization messages to other nodes. The clock node will receive correct synchronization messages on two domains and incorrect synchronization messages on two domains. The stateless detection and correction algorithm cannot determine the source of the incorrect messages. This is the Byzantine General problem in the distributed consistency scenario. It can be proved that to correctly identify m faulty clocks, at least 2m+1 correct clock information is required. Therefore, at most one faulty MC is allowed in the 4 MCs. The synchronization domains on the backbone network and each marshalling network obviously have this problem. The problem brought by deploying 4 MCs is that the domain structure is more complex, the device cost is high, and the network size may not be sufficient to elect 4 MCs. Another idea is to optimize the synchronization detection component algorithm. By memorizing the historical synchronization state, a filtering algorithm can be designed to predict the correct synchronization time range, discard incorrect messages, and report fault information to ensure synchronization stability while providing monitoring and alarm functions.

[0038] In specific implementation, as a preferred embodiment of the present application, step S3 comprises: S31, all nodes in each synchronization domain generate Announce messages according to a preset period. The Announce message is a key message in the clock synchronization protocol, which is used to transmit the attribute information of the clock, including priority1, clockClass, clockAccuracy, offsetScaledLogVariance, priority2, and clockIdentity. S32, each node broadcasts the generated Announce message in the synchronization domain to which the node belongs, so that other nodes in the synchronization domain receive the message and obtain the clock information of the sending node; the broadcasting process ensures that the clock information can be transmitted in the entire synchronization domain, providing a basis for subsequent master clock election; S33, each node in the synchronization domain receives the Announce message from other nodes and parses the clock attribute information in the message; the receiving process is the corresponding operation of broadcasting, which ensures that each node can obtain the clock information of all other nodes in the synchronization domain, providing complete data support for subsequent master clock election; S34, each node executes a best master clock algorithm (BMCA) according to clock attribute information in the received Announce packet, and elects a master clock (MC) according to the best master clock algorithm by sequentially comparing attribute information carried in the Announce packet. The master clock is a reference for clock synchronization in a synchronization domain, and all other nodes (slave clocks) will perform clock synchronization according to time information of the master clock. The election of the master clock ensures that there is a unified time reference in the synchronization domain, and provides a key reference for subsequent clock synchronization operations; In a specific implementation, as a preferred embodiment of the application, step S4 includes: S41, each synchronization port periodically sends a Pdelay_Req (delay request) packet to the opposite port to request the opposite port to measure and return a link propagation delay; the sending of the packet marks the start of the link propagation delay measurement process, and provides a trigger signal for subsequent delay calculation; S42, after the opposite port receives the Pdelay_Req packet, the opposite port records an accurate time point of receiving the packet; the recording of the time point is one of the key data for calculating the link propagation delay, and reflects the time from the sending end to the receiving end of the packet.

[0039] S43, after the opposite port records the receiving time, the opposite port immediately sends a Pdelay_Resp (delay response) packet to the sending port, and the packet carries time information recorded by the opposite port when receiving the Pdelay_Req packet; the sending of the packet is to transmit the receiving time information back to the sending port, so that the sending port can calculate the link propagation delay; S44, after the sending port receives the Pdelay_Resp packet, the sending port calculates the link propagation delay according to the time of sending the Pdelay_Req packet and the receiving time of the opposite end carried in the received Pdelay_Resp packet; this calculation step is the core of the whole link propagation delay measurement, and the one-way propagation delay of the link is calculated through accurate time difference calculation; S45, after the opposite port sends the Pdelay_Resp packet, in order to further improve the accuracy of the delay measurement, the opposite port can send a Pdelay_Resp_Follow_Up packet, which carries accurate time information of the opposite port when sending the Pdelay_Resp packet; the sending of the packet is to provide more accurate time synchronization information to help the sending port more accurately calculate the link propagation delay; S46, after the sending port receives the Pdelay_Resp_Follow_Up message, the link propagation delay calculated before is corrected according to the time information carried in the message; the corrected time delay value is more accurate and can better reflect the actual propagation characteristics of the link, thereby providing more accurate time delay compensation data for clock synchronization; S47, the above process is repeated to periodically calculate the link propagation delay, so as to ensure the accuracy of clock synchronization.

[0040] In a specific implementation, as a preferred embodiment of the application, step S5 comprises: S51, in each synchronization domain, a clock synchronization spanning tree is determined according to the network topology structure and clock synchronization requirements; the spanning tree defines the synchronization path from the master clock to each slave clock, and ensures that each slave clock can receive time synchronization information from the master clock. The construction of the spanning tree is based on the physical connection and logical relationship between nodes, and ensures the efficiency and reliability of clock synchronization; S52, the master clock (MC) port sends a Sync message at a preset period, and the Sync message carries the accurate time stamp of the master clock, which is used to notify the slave clock (SC) of the current time of the master clock; the master clock port records the sending time stamp when sending the Sync message, and this time stamp is the basis for subsequent clock synchronization calculation; S53, after the slave clock port receives the Sync message from the master clock, the accurate time of receiving the message is recorded; the slave clock port needs to record the receiving time in order to calculate the link propagation delay from the master clock to the slave clock. This step is a key link of clock synchronization, and ensures that the slave clock can accurately obtain the time information of the master clock; S54, after the master clock port sends the Sync message, a Follow_Up message is sent, and the Follow_Up message carries the accurate time stamp (preciseOriginTimestamp) of the master clock when sending the Sync message, and the accumulated correction time (correctionField) from receiving the previous hop Sync message to sending the current Sync message; the Follow_Up message provides a correction value to help the slave clock more accurately calculate the clock offset; S55, after the slave clock port receives the Follow_Up message, the preciseOriginTimestamp and correctionField carried in the Follow_Up message are used to calculate the clock offset value in combination with the time of receiving the Sync message recorded by the slave clock itself; S56, the slave clock adjusts the time of the local clock according to the calculated offset value; S57, repeat the above process, each slave clock periodically receives the time information of the master clock, and adjusts the local clock according to the latest offset value, to ensure that all clocks in the entire synchronization domain always maintain high-precision synchronization state.

[0041] In a specific implementation, as a preferred embodiment of the present application, step S6 comprises: S61, each gPTP instance in the multi-domain receives the Sync message and Follow_Up message from the master clock; wherein the Sync message carries the precise timestamp of the master clock, and the Follow_Up message carries the precise OriginTimestamp of the master clock when sending the Sync message and the cumulative correction time (correctionField); S62, each gPTP instance calculates a preliminary offset value according to the received Sync message and Follow_Up message; S63, input the calculated preliminary offset value into the detection component, and the detection component is used to further analyze and process the preliminary offset value to ensure its accuracy and reliability. The detection component verifies the received preliminary offset value to check whether there is an anomaly or error; the verification process includes but is not limited to: checking whether the offset value is within a reasonable range, checking whether the trend of the offset value is consistent with the expectation, and checking the consistency of the offset value with historical data; S64, if the detection component finds that the preliminary offset value is abnormal, the preliminary offset value will be corrected according to a preset algorithm; the correction algorithm can be based on various factors, such as: statistical information of historical offset values, current network state, estimated value of link propagation delay, and preset threshold and fault tolerance range; S65, in the process of verifying and correcting the offset value, the detection component will also check whether there is a sign of a faulty master clock, if it is found that the offset value of a certain master clock is continuously abnormal or exceeds a reasonable range, the detection component will record and report fault information for further diagnosis and processing; S66, after verification and correction by the detection component, the final offset value is obtained. This corrected offset value will be passed to the subsequent correction component for further clock synchronization processing.

[0042] In a specific implementation, as a preferred embodiment of the present application, step S7 comprises: S71, collect the calculated offset values from the gPTP instances in each synchronization domain, which reflect the time deviation between the clocks in each synchronization domain and the master clock; the offset values of each synchronization domain are calculated independently, so there may be some differences.

[0043] S72, input the collected multi-domain offset values into the correction component, and the correction component performs aggregation operation using algorithms including election method, weighted average algorithm, least square method, Kalman filter to obtain an aggregated offset value; S73, the correction component generates a final correction offset value according to the aggregated offset value, and inputs the generated correction offset value into the action component.

[0044] In specific implementation, as a preferred embodiment of the present application, step S8 includes: S81, the action component receives the correction offset value from the correction component, and according to the aggregated offset value, uses the clock convergence algorithm including the empty servo algorithm, the linear regression adaptive algorithm and the PI servo algorithm to obtain the correction offset value; S82, using the correction offset value to correct the local gPTP clock, so that the local clock keeps synchronized with the master clock; S83, the local clock records the adjusted state, including the adjustment time and the adjustment amount information; S84, the action component verifies whether the updated local clock keeps synchronized with the master clock, if there is deviation, the adjustment process is repeated until the verification result shows that the local clock keeps synchronized with the master clock, then the clock synchronization operation is completed.

[0045] In this embodiment, the design of the function structure diagram of the gPTP component on the receiving side of the synchronization message of the multi-domain clock synchronization on the train is as follows: Figure 4The Sync message and the Follow_Up message (two-step method) pass through the gPTP instance on the domain to calculate the offset, and the historical aggregated offset value is combined through a fault-tolerant filter, which can select mean filtering, weighted mean filtering, Kalman filtering, etc. The fault detection component judges whether to report fault data according to the filtering result, and according to all the fault data reported by the slave clock, an algorithm can also be designed to quickly locate the network fault position. The correction component receives the offset value left by the detection component, and can design an election method, a weighted average algorithm, a least square method, a Kalman filter, etc. to perform aggregation operation to obtain an aggregated offset value. The aggregated offset value is input into the action component, and the action component executes a clock convergence algorithm such as an empty servo algorithm, a linear regression adaptive algorithm, a proportional-integral (PI) servo algorithm, etc. to obtain a correction offset value to synchronize the local clock. The local clock will record the sending and receiving time of the synchronization message on the network card, which is used to calculate the offset value in the gPTP instance.

[0046] Embodiment In Figure 3 Taking the double-plane ring network topology as shown in the figure as an example, the device runs the IEEE 802.1AS protocol after power-on, and the specific execution steps are as follows: Step 1, without physical port isolation, use virtual local area network (VLAN) for logical isolation. Each gPTP instance runs in a different VLAN, and the slave clock device can simultaneously listen to and process gPTP messages in multiple VLANs through the same physical interface. One division result is as follows: Domain 0-3 on the backbone network uses VLAN 100, VLAN 200, VLAN 300, and VLAN 400, respectively.

[0047] Step 2, since there is a ring network in the physical network, in order to avoid ring storm, multiple spanning tree protocol (MSTP) can be executed to segment the multi-domain network, or the clock synchronization domain ring can be directly disconnected through static VLAN configuration.

[0048] Step 3, the gPTP instance in each synchronization domain periodically broadcasts an Announce message, which carries the attribute information of the elected master clock, including: 1) priority1; 2) clockClass; 3) clockAccuracy; 4) offsetScaledLogVariance; 5) priority2; 6) clockIdentity. The best master clock election algorithm (BMCA) is executed on each gPTP instance, and the above attributes are compared in turn to elect a master clock MC. For example,Figure 3 Domain 0 elects the master clock node as ETBN1-1. Meanwhile, the synchronization spanning tree is calculated to determine the role of each port in the synchronization domain, including Master, Slave, and Passive. For example, the synchronization spanning tree on Domain 0 of the backbone network ECN 0 is: ETBN1-1 (MC) → ETBN2-1 → ETBN2-2 → ETBN1-2 The synchronization spanning tree on Domain 4 of the marshalling network ECN 0 is:

[0049] Step 4: Measure link propagation delay using point-to-point delay mechanism. Considering the possibility of network failure re-convergence during synchronization, for each gPTP instance port, regardless of the port role as Master, Slave, or Passive, the propagation delay time of the link needs to be recorded. The point-to-point measurement of link propagation delay is calculated by one end Port-1 actively sending Pdelay_Req messages periodically, and recording the sending time , the opposite end Port-2 receives the Pdelay_Req message and records the receiving time , since both ends use local clock timing, in order to avoid the error caused by frequency offset, Port-2 needs to return Pdelay_Resp message as soon as possible, and Pdelay_Resp_Follow_Up message carrying the sending time of Pdelay_Resp message, Port-1 records the receiving time of Pdelay_Resp , parses in Pdelay_Resp_Follow_Up, according to , , , , , The average link delay can be calculated as:

[0050] The above is a two-step calculation method, when the gPTP port hardware supports direct insertion of sending timestamp, one-step calculation method can be used, that is, to carry and in Pdelay_Resp message at the same time. The gPTP instances on the same port in different clock domains calculate the link propagation delay respectively.

[0051] Step 5, Sync and Follow_Up messages are used to transmit synchronization information in IEEE 802.1AS (one-step method only needs Sync message), which requires all clocks in the synchronization domain to be frequency-synchronized, in two-step method, Master Port sends Sync message, Slave Port records the time stamp of receiving Sync , Master Port continues to send Follow_Up message, which carries preciseOriginTimestamp representing MC synchronization time and correctionField representing accumulated correction time from receiving the last hop Sync message to sending this Sync message, Slave Port receives Follow_Up, and since all clocks are frequency-synchronized, it can calculate the single-instance synchronization correction phase difference as:

[0052] Step 6, if gPTP exists as a slave clock in different clock synchronization domains, multiple offset values will be calculated in step 5, according to Figure 4 , next, it is necessary to perform fault-tolerant filtering on each offset value, and Kalman filtering is used as an example to illustrate the filtering process. It mainly includes two steps of prediction and update. Assuming that the master-slave clock deviation offset changes smoothly over time, the state variable can be assumed as , the state transition matrix is , the observation matrix represents only observing the offset value, the initial state , the initial error covariance matrix . The prediction stage is based on the state transition matrix and the previous state to predict the current offset, the state prediction equation is , the error covariance prediction equation is , where is the covariance matrix of process noise, which describes possible process noise such as network transmission jitter and clock hardware oscillator instability. In the update stage, the predicted value is corrected by combining the current actual offset value, first calculate the Kalman gain which weighs the importance of the predicted value and the measured value: If the uncertainty of the prediction is small or if the measurement noise is large, the Kalman gain will reduce the trust in the measured value, the smaller the prediction value is, the greater the influence of the prediction value. The state update formula is: , where represents the current offset measurement value, Residual error between the measured value and the predicted value, the formula represents the update of the state after the residual error is corrected by the Kalman gain, and the error covariance matrix is updated: The offset in the observed updated state is taken as the input of the correction component aggregation algorithm. During the filtering process, a detection residual error threshold can be set, and if the residual error , it indicates that the measured value may be abnormal, and the master clock is judged to be invalid, which is reported to the centralized TSN controller by the fault detection component.

[0053] Step 7, the correction component receives the valid update offset value of the multiple synchronization domains, and designs an aggregation algorithm. Referring to the foregoing, the election method, weighted average algorithm, least square method, and Kalman filter can be used. Taking the election method as an example, a unique legal offset value can be elected according to the synchronization domain level of the node, the arrival time, and the master clock accuracy. The weighted average algorithm can determine the weight of each synchronization domain arrival offset and then calculate the aggregated offset by comprehensive average.

[0054] Step 8, the action component receives the aggregated offset processed by the correction component, and can select the null servo algorithm, linear regression adaptive algorithm, and PI servo algorithm to finally correct the local clock. Generally, the null servo is used, and the clock phase is directly modified according to the aggregated offset.

[0055] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for multi-domain precise clock synchronization on a train, characterized in that, Comprise: S1, design double plane annular networking topology, and build train operation network; S2, in the initial operation stage of the train, based on the train operation network built, execute multi-domain accurate clock synchronization protocol gPTP, according to the logical isolation virtual local area network division of full independent multi-synchronization domain architecture, configure gPTP instance synchronization parameters in each domain, and start the synchronization protocol; S3, in each synchronization domain, all nodes periodically broadcast Announce message to transfer clock information, and decide master clock MC according to BMCA; S4, the link propagation delay is periodically calculated between all synchronization ports through Pdelay_Req, Pdelay_Resp and Pdelay_Resp_Follow_Up messages, to ensure the accuracy of clock synchronization; S5, according to the clock synchronization spanning tree, the master clock time is periodically transmitted from the master clock using Sync and Follow_Up messages, and the slave clock is synchronized step by step; S6, the gPTP instance in the multi-domain calculates the offset value according to the Sync and Follow_Up messages, and inputs the calculated offset value into the detection component, which calculates the corrected offset value and checks the fault master clock information; S7, input the offset value in the multi-domain into the correction component, and input the aggregated correction offset value into the action component; S8, the action component updates the local gPTP clock according to the correction offset value, and completes the clock synchronization.

2. The method of claim 1, wherein, Step S1, comprising: S11, determine the annular double plane structure of the backbone network and the marshalling network, wherein the upper and lower nodes of the annular backbone network belong to A and B two planes, and the nodes of the marshalling network directly connected with the backbone network are the same plane, and the main architecture of the network is constructed based on this; S12, for each marshalling network, design it as an annular topology belonging to two planes, and one marshalling network is deployed in a closed carriage, and the network structure is further refined to meet the communication needs of the devices in different carriages; S13, the terminal devices in the train are divided into single-attached terminal and double-attached terminal, wherein the single-attached terminal has only one network interface exposed to the network, and the double-attached terminal needs two ports to be connected with the switching devices of A and B two planes, and the network interfaces are reasonably allocated according to the types of terminal devices, to ensure that all devices can access the built double plane annular network, and provide network basis for subsequent clock synchronization operation.

3. The method of claim 1, wherein, Step S2, comprising: S21, in the initial operation stage of the train, initialize all nodes participating in TSN network and traffic configuration, to ensure that each node supports multi-domain gPTP protocol and function; S22, according to the full independent multi-synchronization domain architecture, logically isolate the network using virtual local area network technology; each gPTP instance runs in a different virtual local area network, and the slave clock device listens to and processes gPTP messages in multiple virtual local area networks through the same physical interface; S23, configure synchronization parameters for gPTP instances in each VLAN, including clock accuracy, clock priority and clock category; S24, start the multi-domain precise clock synchronization protocol gPTP, so that each node starts clock synchronization operation according to the configured parameters and protocol rules, including broadcasting Announce message, calculating link propagation delay, and delivering master clock time, so as to realize multi-domain clock synchronization of the entire train network.

4. The method of claim 1, wherein, Step S3 comprises: S31, all nodes in each synchronization domain generate Announce messages according to a preset period. The Announce message is a key message in the clock synchronization protocol, and is used to deliver clock attribute information; S32, each node broadcasts the generated Announce message in the synchronization domain to which the node belongs; S33, each node in the synchronization domain receives the Announce message from other nodes and parses the clock attribute information in the message; S34, each node executes a best master clock election algorithm according to the clock attribute information in the received Announce message, and elects a master clock by comparing the attribute information carried in the Announce message according to the best master clock election algorithm.

5. The method of claim 1, wherein, Step S4 comprises: S41, each synchronization port periodically sends a Pdelay_Req message to the opposite port to request the opposite port to measure and return the link propagation delay; S42, after the opposite port receives the Pdelay_Req message, the opposite port records the accurate time point of receiving the message; S43, after the opposite port records the receiving time, the opposite port immediately sends a Pdelay_Resp message to the sending port, and the Pdelay_Resp message carries the time information recorded by the opposite port when receiving the Pdelay_Req message; S44, after the sending port receives the Pdelay_Resp message, the sending port calculates the link propagation delay according to the time when the sending port sends the Pdelay_Req message and the receiving time carried in the received Pdelay_Resp message; S45, after the opposite port sends the Pdelay_Resp message, the opposite port sends a Pdelay_Resp_Follow_Up message, and the Pdelay_Resp_Follow_Up message carries the accurate time information of the opposite port when sending the Pdelay_Resp message; S46, after the sending port receives the Pdelay_Resp_Follow_Up message, the sending port corrects the previously calculated link propagation delay according to the time information carried in the Pdelay_Resp_Follow_Up message; S47, repeat the above process to periodically calculate the link propagation delay to ensure the accuracy of clock synchronization.

6. The method of claim 1, wherein, Step S5 comprises: S51, in each synchronization domain, determine a clock synchronization spanning tree according to the network topology structure and clock synchronization requirements; S52, the master clock port sends a Sync message according to a preset period, and the Sync message carries the accurate timestamp of the master clock, which is used to notify the current time of the slave clock and the master clock; S53, after the slave clock port receives the Sync message from the master clock, the slave clock port records the accurate time of receiving the message; S54, after sending the Sync message, the master clock port sends a Follow_Up message, which carries the accurate timestamp of the Sync message sent by the master clock and the accumulated correction time elapsed since the last Sync message from the master clock was received to the current Sync message being sent; S55, after receiving the Follow_Up message, the slave clock port uses the accurate timestamp and the accumulated correction time carried in the Follow_Up message, and combines the time of receiving the Sync message recorded by itself, to calculate the clock offset value; S56, the slave clock adjusts the local clock time according to the calculated offset value; S57, repeat the above process, each slave clock periodically receives the time information of the master clock, and adjusts the local clock according to the latest offset value, to ensure that all clocks in the entire synchronization domain always maintain high-precision synchronization state.

7. The method of claim 1, wherein, Step S6 includes: S61, each gPTP instance in the multi-domain receives the Sync message and the Follow_Up message from the master clock; wherein the Sync message carries the accurate timestamp of the master clock, and the Follow_Up message carries the accurate timestamp of the Sync message sent by the master clock and the accumulated correction time; S62, each gPTP instance calculates a preliminary offset value according to the received Sync message and Follow_Up message; S63, input the calculated preliminary offset value into the detection component, and the detection component verifies the received preliminary offset value to check whether there is an anomaly or error; S64, if the detection component finds that the preliminary offset value is abnormal, the preliminary offset value will be corrected according to the preset algorithm; S65, in the process of verifying and correcting the offset value, the detection component will also check whether there is a sign of a faulty master clock, and if it finds that the offset value of a certain master clock is continuously abnormal or exceeds a reasonable range, the detection component will record and report the fault information; S66, after verification and correction by the detection component, the final offset value is obtained.

8. The method of claim 1, wherein, Step S7 includes: S71, collect the calculated offset values from the gPTP instances of each synchronization domain, which reflect the time deviation between the slave clock and the master clock in each synchronization domain; S72, input the collected multi-domain offset values into the correction component, and the correction component performs aggregation operation using algorithms including election method, weighted average algorithm, least squares method, and Kalman filter to obtain an aggregated offset value; S73, the correction component generates a final correction offset value according to the aggregated offset value, and inputs the generated correction offset value into the action component.

9. The method of claim 1, wherein, Step S8 includes: S81, the action component receives the correction offset value from the correction component, and according to the aggregated offset value, uses the execution clock convergence algorithm including the empty servo algorithm, the linear regression adaptive algorithm, and the PI servo algorithm to obtain the correction offset value; S82, correct the local gPTP clock using the correction offset value, so that the local clock is synchronized with the master clock; S83, the local clock records the adjusted state, including the adjustment time and adjustment amount information; S84, the action component verifies whether the updated local clock is synchronized with the master clock. If there is a deviation, the adjustment process is repeated until the verification result shows that the local clock is synchronized with the master clock, and the clock synchronization operation is completed.

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