Cache processing method and device

Abstract

The invention provides a cache processing method. A first device receives a first data stream including a first packet and a second packet. And the first device caches the first message in the on-chip cache and caches the second message in the memory module. The first device is connected with the memory module through a universal network interface, and the universal network interface can be an Ethernet interface, or a UEC interface, or a UB interface. And the first device schedules the first message in the on-chip cache and the second message in the memory module so as to send the first message and the second message. The first device and the memory module are connected through the universal network interface, so that a new communication protocol for interaction between the first communication device and the memory module does not need to be additionally developed, and adaptive modification can be carried out on the basis of the communication protocol supported by the universal network interface. Moreover, the capacity of the memory module can be flexibly configured according to a specific network scene, so as to meet the networking requirements of different network scenes.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication, and in particular to a cache processing method and device. BACKGROUND

[0002] In a communication network, in order to avoid packet loss caused by traffic congestion, a certain scale of memory can be integrated in a forwarding chip of a network device. When traffic congestion occurs, the memory is used to cache traffic.

[0003] However, the current way of integrating memory in the forwarding chip cannot meet the needs in some scenarios. For example, in a scenario where multiple clients access the same server, the network device receives traffic from different clients through multiple ingress interfaces, and the traffic received through the multiple ingress interfaces is sent to the server through the same egress interface. In this scenario, if the memory capacity integrated in the forwarding chip of the network device is not enough, packet loss will occur.

[0004] Therefore, there is an urgent need for a solution to solve the above problems. SUMMARY

[0005] The present application provides a cache processing method, which can effectively avoid packet loss caused by traffic congestion.

[0006] In a first aspect, the present application provides a cache processing method, which can be applied to a first device. The first device includes an on-chip cache, and the first device is also connected to a memory module through a general network interface. In the present application, the general network interface can be an Ethernet interface, or a UEC (Ultra Ethernet Consortium) interface, or a UB (Unified Bus) interface. The first device can receive a first data stream, which includes a first packet and a second packet. After receiving the first data stream, the first device can cache the first packet in the on-chip cache and cache the second packet in the memory module. Further, the first device can schedule the first packet in the on-chip cache and the second packet in the memory module to send the first packet and the second packet, thereby realizing the forwarding of the first packet and the second packet. In the present application, the first device and the memory module are connected through a general network interface, so there is no need to develop a new communication protocol for the interaction between the first communication device and the memory module. Instead, the communication protocol supported by the general network interface can be modified adaptively. Moreover, the capacity of the memory module can be flexibly configured according to specific network scenarios to meet the networking needs of different network scenarios. For example, in a scenario with high cache requirements, a memory module with a larger capacity can be configured, so that the first device can cache more packets to avoid packet loss caused by traffic congestion.

[0007] In a possible implementation, after receiving the first data stream, the first device can cache the first data stream by using a first queue corresponding to the first data stream. The first queue is also a queue used for forwarding the first data stream, that is, a queue that needs to be scheduled when the first data stream is forwarded. In this application, the first queue can be implemented by using an on-chip cache of the first device and a memory module connected to the first device. Specifically, the first queue can include a first subqueue and a second subqueue, the first subqueue being a queue in the on-chip cache, and the second subqueue being a queue in the memory module.

[0008] In a possible implementation, the first device caches the second packet in the memory module connected to the first device. In a specific implementation, the first device can send a packet caching instruction to the memory module through the general network interface, where the packet caching instruction is used to instruct the memory module to cache the second packet, and the packet caching instruction includes the first indication information and the second packet. The first indication information indicates that the memory module performs a packet caching operation. Correspondingly, after receiving the packet caching instruction, the memory module parses the first indication information and the second packet, and then performs a packet caching operation on the second packet to cache the second packet in the memory module.

[0009] In a possible implementation, the first indication information includes a first operation type and an identifier of the second packet, the operation corresponding to the first operation type is a packet caching operation, and the first indication information indicates that the memory module performs the packet caching operation based on the identifier of the second packet. Correspondingly, after receiving the packet caching instruction, the memory module can parse the first indication information and obtain the identifier of the second packet. Further, the memory module can determine a cache space for caching the second packet from cache spaces available to the memory module, and cache the second packet by using the determined cache space.

[0010] In a possible implementation, the first indication information includes a first operation type and a first address, the operation corresponding to the first operation type is a packet caching operation, and the first indication information indicates that the memory module performs the packet caching operation based on the first address. Correspondingly, after receiving the packet caching instruction, the memory module can parse the first indication information and obtain the first address. Further, the memory module can cache the second packet by using the first address.

[0011] In a possible implementation, the first device schedules the first packet in the on-chip cache and the second packet in the memory module to be sent, and in a specific implementation, the first device can read the first packet from the on-chip cache, and send a packet reading instruction to the memory module through the general network interface, where the packet reading instruction is used to instruct the memory module to read the second packet, and the packet reading instruction includes second indication information, where the second indication information indicates that the memory module performs a packet reading operation. Further, the first device can receive a feedback message sent by the memory module through the general network interface, and the feedback message includes the second packet. The first device can parse the second packet from the feedback message, and further send the first packet and the second packet.

[0012] In a possible implementation, the feedback message can include the foregoing packet reading instruction in addition to the second packet, for example, the second packet is added after the packet reading instruction to obtain the feedback message, so that the first device determines that the feedback message is a feedback message for the packet reading instruction, and extracts the second packet from the feedback message.

[0013] In a possible implementation, the second indication information includes a second operation type and an identifier of the second packet, the operation corresponding to the second operation type is a packet reading operation, and the second indication information indicates that the memory module performs the packet reading operation based on the identifier of the second packet. Correspondingly, after receiving the packet reading instruction, the memory module can parse the second indication information and obtain the identifier of the second packet. Further, the memory module can use the identifier of the second packet as an index to query a correspondence between the identifier of the second packet and a cache space used to cache the second packet that is stored in advance, to determine the cache space used to cache the second packet, and read the second packet from the determined cache space.

[0014] In a possible implementation, the second indication information includes a second operation type and a second address, the operation corresponding to the second operation type is a packet reading operation, and the second indication information indicates that the memory module performs the packet reading operation based on the second address. Correspondingly, after receiving the packet reading instruction, the memory module can parse the second indication information and obtain the second address. Further, the memory module can use the second address to read the second packet.

[0015] In a possible implementation, to prevent the first data stream from being out of order, the first device can send the first packet and the second packet in the order in which the first packet and the second packet are received.

[0016] In a possible implementation, when scheduling the queue, the first device can need to discard part or all of the messages in the queue. As a specific example, if the first device determines that the third message needs to be discarded, and the third message is buffered in the memory module when the message is enqueued for scheduling, the first device sends a message release instruction to the memory module through the general network interface, the message release instruction is used to instruct the memory module to release the third message buffered in the memory module, and the message release instruction includes third indication information, the third indication information indicates that the memory module performs a message release operation. Correspondingly, after the memory module receives the message release instruction, the third indication information is parsed, and the third message is released from the memory module. Wherein, releasing the third message from the memory module can also be understood as releasing the cache space in the memory module for buffering the third message.

[0017] In a possible implementation, the third indication information includes a third operation type and an identifier of the third message, the operation corresponding to the third operation type is a message release operation, and the third indication information indicates that the memory module performs the message release operation based on the identifier of the third message. Correspondingly, after the memory module receives the message release instruction, the third indication information can be parsed, and the identifier of the third message is obtained. Further, the memory module can query the correspondence between the identifier of the third message and the cache space for buffering the third message based on the identifier of the third message as an index, to determine the cache space for buffering the third message, and release the determined cache space.

[0018] In a possible implementation, the third indication information includes a third operation type and a third address, the operation corresponding to the third operation type is a message release operation, and the third indication information indicates that the memory module performs the message release operation based on the third address. Correspondingly, after the memory module receives the message release instruction, the third indication information can be parsed, and the third address is obtained. Further, the memory module can release the third address.

[0019] In a possible implementation, considering that if the amount of data received by the first device is large, the on-chip cache of the first device and the capacity of the memory module are insufficient to buffer the received traffic, the first device will also discard part of the traffic, thereby causing message packet loss. In order to effectively avoid message packet loss due to traffic congestion, the first device can send backpressure indication information to an upstream device of the first device to instruct the upstream device to reduce the bandwidth of sending traffic to the first device, when the usage rate of the on-chip cache is greater than or equal to a first preset threshold, and the usage rate of the memory module is greater than or equal to a second preset threshold.

[0020] In a possible implementation, the memory module can be an HBM module, so as to avoid packet loss due to traffic congestion and guarantee packet forwarding efficiency.

[0021] In a possible implementation, the first device and the memory module can belong to the same network device. For example, the first device is a forwarding chip in the network device, and the memory module is another chip in the network device.

[0022] In a possible implementation, the first device and the memory module belong to two different devices. For example, the first device is a forwarding chip in the network device, that is, the first device belongs to the network device, and the memory module can belong to another storage device.

[0023] In a second aspect, the present application provides a cache processing device applied to a first device, the device comprising a receiving unit, a processing unit and a sending unit. The receiving unit is configured to receive a first data stream, the first data stream comprising first packets and second packets. The processing unit is configured to cache the first packets in an on-chip cache of the first device and cache the second packets in a memory module connected to the first device. The first device is connected to the memory module through a general network interface, and the general network interface comprises an Ethernet interface, or a UEC (Unified Ethernet Consortium) interface, or a UB (Unified Bus) interface. The processing unit is further configured to schedule the first packets in the on-chip cache and the second packets in the memory module, so that the sending unit sends the first packets and the second packets.

[0024] In a possible implementation, the first queue is a queue for forwarding the first data stream, the first queue comprising a first subqueue and a second subqueue, the first subqueue being a queue in the on-chip cache for caching the first packets, and the second subqueue being a queue in the memory module for caching the second packets.

[0025] In a possible implementation, the processing unit is configured to send a packet caching instruction to the memory module through the general network interface, the packet caching instruction being used to instruct the memory module to cache the second packets, the packet caching instruction comprising first indication information and the second packets, and the first indication information being used to instruct the memory module to perform a packet caching operation.

[0026] In a possible implementation, the first indication information comprises a first operation type and an identifier of the second packet, the operation corresponding to the first operation type is a packet caching operation, and the first indication information indicates that the memory module performs the packet caching operation based on the identifier of the second packet.

[0027] In a possible implementation, the first indication information comprises a first operation type and a first address, the operation corresponding to the first operation type is a packet caching operation, and the first indication information indicates that the memory module performs the packet caching operation based on the first address.

[0028] In a possible implementation, the processing unit is configured to: read the first packet from the on-chip cache; use a sending unit included in the apparatus to send, to the memory module through the general-purpose network interface, a packet reading instruction, the packet reading instruction being used to instruct the memory module to read the second packet, the packet reading instruction comprising second indication information, the second indication information indicating that the memory module performs a packet reading operation; and use the receiving unit to receive, through the general-purpose network interface, a feedback message sent by the memory module, the feedback message comprising the second packet.

[0029] In a possible implementation, the feedback message further comprises the packet reading instruction.

[0030] In a possible implementation, the second indication information comprises a second operation type and an identifier of the second packet, the operation corresponding to the second operation type is a packet reading operation, and the second indication information indicates that the memory module performs the packet reading operation based on the identifier of the second packet.

[0031] In a possible implementation, the second indication information comprises a second operation type and a second address, the operation corresponding to the second operation type is a packet reading operation, and the second indication information indicates that the memory module performs the packet reading operation based on the second address.

[0032] In a possible implementation, the sending unit is configured to: send the first packet and the second packet in the order in which the first packet and the second packet are received.

[0033] In a possible implementation, the sending unit included in the apparatus is further configured to: send, to the memory module through the general-purpose network interface, a packet releasing instruction, the packet releasing instruction being used to instruct the memory module to release a third packet cached in the memory module, the packet releasing instruction comprising third indication information, the third indication information indicating that the memory module performs a packet releasing operation.

[0034] In a possible implementation, the third indication information includes a third operation type and an identifier of the third packet, the operation corresponding to the third operation type is a packet release operation, and the third indication information indicates that the memory module performs the packet release operation based on the identifier of the third packet.

[0035] In a possible implementation, the third indication information includes a third operation type and a third address, the operation corresponding to the third operation type is a packet release operation, and the third indication information indicates that the memory module performs the packet release operation based on the third address.

[0036] In a possible implementation, the sending unit of the device is further configured to send back pressure indication information to an upstream device of the first device to instruct the upstream device to reduce a bandwidth of sending traffic to the first device, when the usage rate of the on-chip cache is greater than or equal to a first preset threshold and the usage rate of the memory module is greater than or equal to a second preset threshold.

[0037] In a possible implementation, the memory module includes a high bandwidth memory (HBM) module.

[0038] In a possible implementation, the first device and the memory module belong to a same network device.

[0039] In a possible implementation, the first device and the memory module belong to two different devices.

[0040] In a third aspect, an embodiment of the present application provides a device, including: a processor and a memory; the memory is used to store instructions or a computer program; and the processor is used to execute the instructions or the computer program, and execute the method in the above first aspect and any one of the above first aspect.

[0041] In a fourth aspect, an embodiment of the present application provides a computer readable storage medium, including instructions or a computer program, when the instructions or the computer program are executed on a computer, the computer is caused to execute the method in the above first aspect and any one of the above first aspect.

[0042] In a fifth aspect, an embodiment of the present application provides a computer program product including instructions or a computer program, when the instructions or the computer program are executed on a computer, the computer is caused to execute the method in the above first aspect and any one of the above first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the accompanying drawings in the following description only represent some embodiments of the present application, and for those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0044] Figure 1a A structural schematic diagram of a forwarding chip is shown;

[0045] Figure 1b A structural schematic diagram of another forwarding chip is shown;

[0046] Figure 2 A structural schematic diagram of a cache system provided by the embodiments of the present application is shown;

[0047] Figure 3 A flow schematic diagram of a cache processing method provided by the embodiments of the present application is shown;

[0048] Figure 4a A structural schematic diagram of a message cache instruction provided by the embodiments of the present application is shown;

[0049] Figure 4b A structural schematic diagram of another message cache instruction provided by the embodiments of the present application is shown;

[0050] Figure 4c A structural schematic diagram of a message reading instruction provided by the embodiments of the present application is shown;

[0051] Figure 4d A structural schematic diagram of another message reading instruction provided by the embodiments of the present application is shown;

[0052] Figure 4e A process schematic diagram of message forwarding provided by the embodiments of the present application is shown;

[0053] Figure 4f A structural schematic diagram of a message release instruction provided by the embodiments of the present application is shown;

[0054] Figure 4g A structural schematic diagram of another message release instruction provided by the embodiments of the present application is shown;

[0055] Figure 5a A schematic diagram of an exemplary application scenario provided by the embodiments of the present application is shown;

[0056] Figure 5b A schematic diagram of another exemplary application scenario provided by the embodiments of the present application is shown;

[0057] Figure 6This is a schematic diagram of the structure of a cache processing device provided in an embodiment of this application;

[0058] Figure 7 This is a schematic diagram of the structure of a device provided in an embodiment of this application. Detailed Implementation

[0059] This application provides a caching method that can effectively avoid packet loss due to traffic congestion.

[0060] To avoid packet loss due to traffic congestion, network devices can integrate a certain amount of memory into their forwarding chips. (See reference...) Figure 1a To understand, Figure 1a A schematic diagram of a forwarding chip is shown. Figure 1a As shown, the core die of the forwarding chip houses a packet processor (PP) and two static random-access memories (SRAMs), which can also be referred to as the on-chip cache of the forwarding chip. The forwarding chip can cache packets in these on-chip caches. The PP is used to process the packets; the packet processing operations performed by the PP are not detailed here. Furthermore, although... Figure 1a Although not shown in the diagram, the core die may include other modules, such as a traffic management (TM) module or a swap buffer (SWB) module. Furthermore, the amount of SRAM included on the core die is not limited to... Figure 1a As shown in the two examples, the number of SRAMs included on the core die can also be one or other numbers.

[0061] However, SRAM is expensive and has low capacity density. Therefore, limited by the process limits of die size, the maximum capacity of SRAM deployed on the core die can only reach about 1 gigabyte (GB), which cannot support higher cache sizes. Consequently, in scenarios with high cache requirements, the cache capacity available for caching packets in the forwarding chip is insufficient, leading to packet loss due to traffic congestion.

[0062] Furthermore, since SRAM is directly deployed inside the forwarding chip, and the chip area and cache specifications are fixed and cannot be changed after chip production, it is impossible to adaptively configure the cache specifications based on different network scenarios. In other words, Figure 1a The forwarding chip shown is not suitable for different network scenarios.

[0063] See Figure 1b ,Figure 1b A schematic diagram of another type of forwarding chip is shown. (Example) Figure 1b As shown, the forwarding chip includes a core die and an HBM die; in other words, the core die and the HBM die are packaged together to form a complete forwarding chip. The core die has a PP and SRM module deployed on it, and also a TM module or SWB module. The HBM die has an HBM deployed on it. The forwarding chip can use the SRAM on the core die and the HBM on the HBM die to buffer packets. Specifically, when the forwarding chip receives a packet, it first buffers the packet in the SRAM; if the SRAM is full, it buffers the packet in the HBM. Because the HBM has a large capacity, when the forwarding chip is... Figure 1b With the structure shown, in scenarios with high caching requirements, the forwarding chip has sufficient capacity to cache packets, thereby avoiding packet loss due to traffic congestion.

[0064] However, in Figure 1b In this architecture, the core die and the HBM die are interconnected via a serializer-deserializer (SerDes), while the TM module and the HBM require a dedicated physical layer (PHY) for interconnection. Therefore, an additional dedicated PHY needs to be designed between the TM module and the HBM, resulting in high development costs.

[0065] Furthermore, once the forwarding chip specifications are determined, its internal structure cannot be changed, and it is impossible to adaptively configure the cache specifications based on different network scenarios. In other words, Figure 1b The forwarding chip shown is also not applicable to different network scenarios.

[0066] In view of this, embodiments of this application provide a caching method. Using the solution of this application, in scenarios with high caching demand, the forwarding chip has sufficient capacity to cache packets, thereby avoiding packet loss due to traffic congestion. Moreover, there is no need to design a dedicated protocol for interaction between the forwarding chip and other caching devices, resulting in low development costs. Furthermore, caching specifications can be adaptively configured based on different network scenarios. In other words, using the solution provided by embodiments of this application, the same forwarding chip can be applied to different network scenarios.

[0067] Next, the solutions provided by the embodiments of this application will be described in conjunction with the accompanying drawings.

[0068] In this embodiment, the forwarding chip includes an on-chip cache, and is also connected to a memory module via a general network interface. (See reference...) Figure 2 To understand, Figure 2 This is a schematic diagram of the structure of a caching system provided in an embodiment of this application. Figure 2In this paper, an HBM module is used as an example to illustrate the concept. However, the memory module in this application is not limited to an HBM module; it can also be other types of memory modules, such as double data rate synchronous dynamic random access memory (DDR SDRAM). DDR SDRAM can also be abbreviated as DDR.

[0069] like Figure 2 As shown, the caching system includes a forwarding chip and an HBM module.

[0070] The forwarding chip includes a core die and input / output (IO) dies. The IO dies provide a general-purpose network interface. In this application, the general-purpose network interface is a concept relative to a dedicated network interface. Unlike a dedicated network interface, which is specifically designed to connect to a particular device (e.g., a chip), a general-purpose network interface can be used to connect to various devices. For example, it can be used to connect to other chips or other devices (e.g., network devices). The general-purpose network interface can be, for example, an Ethernet interface, a UEC interface, or a UB interface. The forwarding chip can connect to the HBM module through this general-purpose network interface. Regarding the core die, please refer to the description of the core die above; it will not be repeated here.

[0071] Ethernet and UEC interfaces will not be discussed in detail here. Regarding the UB interface, it's important to note that it's an improvement upon the traditional Ethernet interface in terms of the physical, data link, and transport layers, enabling it to offer higher transmission rates compared to traditional Ethernet interfaces. The UB interface can be used in high-bandwidth artificial intelligence (AI) networks or high-bandwidth computing networks.

[0072] The HBM module includes an adaptation (ADP) module and at least one HBM. For ease of understanding, Figure 2 Three HBMs are shown; however, in practical applications, the number of storage modules included in a memory module is not limited to this. Figure 2 The three modules are shown. The HBM is used to buffer packets, and the ADP module is used to control and / or manage the HBM. The ADP module also interacts with the forwarding chip through the aforementioned general network interface. Controlling the HBM, as mentioned here, could include controlling the HBM to perform operations such as packet reading and packet storage. Managing the HBM, as mentioned here, could include managing the HBM's address.

[0073] In one example, the forwarding chip and the memory module can belong to the same network device. The physical distance between the forwarding chip and the memory module can be a few meters. In another example, the forwarding chip and the memory module can belong to two different devices; for example, the forwarding chip belongs to the network device, and the memory module belongs to another device that supports a large cache. In this scenario, the physical distance between the forwarding chip and the memory module can be flexibly deployed, ranging from a few meters to hundreds of meters. In one example, if the forwarding chip and the memory module belong to two different devices, the memory module could also be another storage device capable of providing a large cache.

[0074] The network devices mentioned in the embodiments of this application include, but are not limited to, routers, switches, and other devices.

[0075] Next, combined Figure 3 This paper introduces the caching method provided in this application. Figure 3 This is a flowchart illustrating a caching method provided in this application. Figure 3 The method shown can be applied to a first device, which may be, for example, a... Figure 2 The forwarding chip shown. Figure 3 The method shown includes the following steps S101-S103.

[0076] S101: The first device receives a first data stream, the first data stream including a first message and a second message.

[0077] In this embodiment, the first device can receive a first data stream sent by an upstream device. The first data stream may include multiple messages, at least including a first message and a second message. The upstream device mentioned herein may be a network device, a user terminal, or a server; this embodiment does not specifically limit its scope.

[0078] S102: The first device caches the first message in the on-chip cache of the first device and caches the second message in the memory module connected to the first device. The first device is connected to the memory module through a general network interface, which includes an Ethernet interface, a UEC interface, or a UB interface.

[0079] After receiving the first data stream, the first device can perform an enqueue operation on the first data stream. Enqueueing the first data stream can be understood as using a first queue corresponding to the first data stream to cache it. Here, caching can be understood as temporary storage. In this embodiment, the first queue can be implemented through an on-chip cache of the first device and a memory module connected to the first device. Specifically, the first queue may include a first sub-queue and a second sub-queue, where the first sub-queue is a queue in the on-chip cache and the second sub-queue is a queue in the memory module.

[0080] After receiving the first data stream, the first device prioritizes using a first sub-queue to cache the packets in the first data stream. If the on-chip cache capacity is insufficient, it continues to use a second sub-queue to cache other packets in the first data stream that have not yet been cached. In a specific example, when the first device receives the first packet from the first data stream, the on-chip cache capacity is sufficient, so the first device can cache the first packet in the on-chip cache. As a specific example, the first device can cache the first packet in the aforementioned first sub-queue. When the first device receives the second packet from the first data stream, the on-chip cache capacity is insufficient, so the first device can cache the second packet in the memory module. As a specific example, the first device can cache the second packet in the aforementioned second sub-queue. This application embodiment does not specifically limit the order in which the first device receives the first packet and the second packet. The order in which the first device receives the first packet and the second packet can be: receiving the first packet first and then receiving the second packet, or the order in which the first device receives the first packet and the second packet can be: receiving the second packet first and then receiving the first packet.

[0081] In one example, the first device can send a message caching instruction to the memory module via the aforementioned general network interface. This instruction instructs the memory module to cache the second message, thereby caching the second message in the memory module. In this application, the message caching instruction includes first indication information and a second message. The first indication information instructs the memory module to perform a message caching operation. Accordingly, after receiving the message caching instruction, the memory module parses the first indication information and the second message, and then performs a message caching operation on the second message to cache it in the memory module.

[0082] In one example, the first device can add an interaction command header to the general network protocol corresponding to the aforementioned general network interface, and use this interaction command header to carry the aforementioned first indication information. The aforementioned second message is then carried after the interaction command header. In other words, the aforementioned message buffering instruction may include an interaction command header carrying the first indication information, and a second message carried in a field located after the interaction command header.

[0083] In a specific example, if the address of the memory module is managed by the memory module itself, for example, the address of the memory module is managed by the ADP module of the memory module, then the first indication information may include the first operation type and the identifier of the second message, wherein the operation corresponding to the first operation type is a message caching operation.

[0084] See also Figure 4a To understand, Figure 4a This is a schematic diagram illustrating the structure of a message caching instruction provided in an embodiment of this application. For example...Figure 4a As shown, the message caching instruction includes: an operation type field, a message identifier (pac_id) field, and a payload field. Wherein:

[0085] The Operation Type field carries the first operation type. For example, a value of 0 in the Operation Type field indicates that the field carries the first operation type. The Message Identifier field carries the identifier of the second message, and the Payload field carries the second message.

[0086] In this scenario, the first instruction information can instruct the memory module to perform a message caching operation based on the identifier of the second message. Accordingly, after receiving the message caching instruction, the memory module can parse the first instruction information and obtain the identifier of the second message. Further, the memory module can determine a cache space for caching the second message from its available cache space and use the determined cache space to cache the second message. In addition, the memory module also stores the correspondence between the identifier of the second message and the cache space used to cache the second message, so that during the message reading phase, the cache space used to cache the second message can be determined based on the identifier of the second message, thereby reading the second message from the cache space used to cache the second message.

[0087] In this application, the correspondence between the identifier of the second message and the cache space used to cache the second message can be, for example, the correspondence between the identifier of the second message and the address linked list corresponding to the cache space used to cache the second message.

[0088] In yet another specific example, if the address of the memory module is managed by a first device, the first indication information may include a first operation type and a first address, where the first operation type corresponds to a message buffering operation. See also... Figure 4b To understand, Figure 4b This is a schematic diagram illustrating the structure of another message caching instruction provided in an embodiment of this application. For example... Figure 4b As shown, the packet caching instruction includes: an operation type field, a packet address (pac_addr) field, and a payload field. Wherein:

[0089] The operation type field carries the first operation type. For example, a value of 0 in the operation type field indicates that the operation type field carries the first operation type. The address field carries the aforementioned first address, and the payload field carries the second message.

[0090] In this scenario, the first instruction information can instruct the memory module to perform a packet caching operation based on the first address. Accordingly, after receiving the packet caching instruction, the memory module can parse the first instruction information and obtain the first address. Further, the memory module can use the first address to cache the second packet. The first address mentioned here can be a starting address or an address list. When the first address is a starting address, the memory module can, for example, start caching the second packet from that starting address; when the first address is an address list, the memory module can cache the second packet in the address space indicated by the address list.

[0091] In addition, the first device can also store the correspondence between the identifier of the second message and the first address, so that in the subsequent message reading stage, the first address can be determined based on the identifier of the second message, so that the second message can be read from the memory module using the first address.

[0092] S103: The first device schedules the first message in the on-chip cache and the second message in the memory module to send the first message and the second message.

[0093] After the first device performs an enqueue operation on the first data stream, it can schedule the first queue according to a queue scheduling policy to continue forwarding the first data stream to downstream devices. In this application, when scheduling the first queue, the first packet in the on-chip buffer and the second packet in the memory module can be scheduled to send the first packet and the second packet to the downstream device. In a scenario where the first queue includes a first sub-queue and a second sub-queue, the first device can schedule the first packet in the first sub-queue and the second packet in the second sub-queue to send the first packet and the second packet to the downstream device.

[0094] The downstream devices mentioned in this application include, but are not limited to, downstream network equipment, user terminals, or servers.

[0095] In a specific example, the first device may read a first message from the on-chip cache and a second message from the memory module, and further send the first message and the second message to a downstream device.

[0096] Next, the specific implementation of the first device reading the second message from the memory module will be explained.

[0097] In one example, the first device can send a message read instruction to the memory module via the aforementioned general network interface. This message read instruction instructs the memory module to read the second message from the memory module. In this application, the message read instruction includes second indication information, which instructs the memory module to perform the message read operation. Accordingly, after receiving the message read instruction, the memory module parses the second indication information, reads the second message from the memory module, and sends a feedback message carrying the second message to the first device. In a specific example, the feedback message may include the aforementioned message read instruction in addition to the second message. For example, the second message can be appended after the message read instruction to obtain the feedback message, so that the first device can determine that the feedback message is in response to the message read instruction and extract the second message from the feedback message.

[0098] In one example, the first device can add an interactive command header to the general network protocol corresponding to the aforementioned general network interface, and use the interactive command header to carry the aforementioned second instruction information.

[0099] In a specific example, if the address of the memory module is managed by the memory module itself, for example, the address of the memory module is managed by the ADP module of the memory module, then the second indication information may include the second operation type and the identifier of the second message, wherein the operation corresponding to the second operation type is a message reading operation.

[0100] See also Figure 4c To understand, Figure 4c This is a schematic diagram illustrating the structure of a message reading instruction provided in an embodiment of this application. For example... Figure 4c As shown, the message reading instruction includes: an operation type field and a message identifier field. Wherein:

[0101] The Operation Type field is used to carry a second operation type. For example, a value of 1 in the Operation Type field indicates that the field carries a second operation type. The Message Identifier field is used to carry an identifier for the second message.

[0102] In this scenario, the second instruction information can instruct the memory module to perform a message reading operation based on the identifier of the second message. Accordingly, after receiving the message reading instruction, the memory module can parse the second instruction information and obtain the identifier of the second message. Further, the memory module can use the identifier of the second message as an index to query the pre-stored correspondence between the identifier of the second message and the cache space used to cache the second message, thereby determining the cache space used to cache the second message, and reading the second message from the determined cache space.

[0103] In another specific example, if the address of the memory module is managed by the first device, the second indication information may include a second operation type and a second address. For example, the first device may use the identifier of the second message as an index to query the pre-stored correspondence between the identifier of the second message and the address in the memory module used to cache the second message, and determine the second address in the memory module used to cache the second message. As described above, the first device pre-stores the correspondence between the identifier of the second message and the first address; therefore, the second address mentioned here may be the aforementioned first address. The operation corresponding to this second operation type is a message reading operation. See also... Figure 4d To understand, Figure 4d This is a schematic diagram illustrating the structure of another message reading instruction provided in an embodiment of this application. For example... Figure 4d As shown, the message reading instruction includes: an operation type field and a message address field. Wherein:

[0104] The operation type field is used to carry a second operation type. For example, a value of 1 in the operation type field indicates that the operation type field carries a second operation type. The address field is used to carry the aforementioned second address.

[0105] In this scenario, the second instruction information can instruct the memory module to perform a message reading operation based on the second address. Accordingly, after receiving the message reading instruction, the memory module can parse the second instruction information and obtain the second address. Furthermore, the memory module can use the second address to read the second message.

[0106] In one example, if the downstream device has the capability to correct out-of-order data flow, the first device can send the first and second packets to the downstream device according to the order in which they are read. Generally, the first device reads packets from the on-chip cache faster than from the memory module. Therefore, the first device reads the first packet first, then the second packet, and thus can send the first packet to the downstream device before sending the second packet.

[0107] In another example, to avoid out-of-order delivery of the first data stream, the first device can send the first and second messages in the order they were received. Assume the first device receives the first and second messages in the following order: first the second message, then the first message. Then, even if the first device reads the first message from the on-chip cache first, it cannot immediately send the first message to the downstream device. Instead, it waits until it reads the second message from the memory module, then sends the second message to the downstream device first, followed by the first message. This ensures that the order in which the first device sends the first and second messages to the downstream device matches the order in which it receives the first and second messages from the upstream device, thus preventing out-of-order delivery of the first data stream. (See reference...) Figure 4e To understand, Figure 4e This is a schematic diagram illustrating a message forwarding process provided in an embodiment of this application.

[0108] like Figure 4e As shown:

[0109] Step ①: The forwarding chip receives the packets with sequence numbers 1, 2, 3, and 4 in sequence. All four packets belong to the first data stream.

[0110] Step ②: When the TM module or SWB module of the forwarding chip performs enqueue scheduling, if the on-chip buffer is insufficient when receiving messages with sequence numbers 1 and 2, then the messages with sequence numbers 1 and 2 are buffered in the memory module. If the on-chip buffer is sufficient when receiving messages with sequence numbers 3 and 4, then the messages with sequence numbers 3 and 4 are buffered in the on-chip buffer. Messages with sequence numbers 1 and 2 can correspond to the aforementioned second message, and messages with sequence numbers 3 and 4 can correspond to the aforementioned first message.

[0111] Step 3: When the forwarding chip performs dequeue scheduling, it first reads the packets with sequence numbers 1 and 2 from the memory module. However, reading the packets with sequence numbers 1 and 2 from the memory module requires a certain delay. At this time, although the packets with sequence numbers 3 and 4 in the on-chip buffer can be sent directly, they still have to wait for the packets with sequence numbers 1 and 2 to be sent first.

[0112] Step 4: After queuing the packets with sequence numbers 1, 2, 3, and 4 in order, the forwarding chip sends them to the downstream device in sequence. Here, "queuing in order" refers to queuing the packets according to the order in which the forwarding chip receives them.

[0113] In one example, when scheduling a queue, the first device may need to discard some or all of the packets in the queue. As a specific example, if the first device determines that a third packet needs to be discarded, and the third packet was cached in the memory module during packet enqueue scheduling, the first device can notify the memory module to release the cached third packet. Releasing the cached third packet in the memory module can also be understood as releasing the cache space in the memory module that cached the third packet, so that the released cache space can be used to cache other packets subsequently. In one example, the third packet may belong to the aforementioned first data stream. In this scenario, the third packet may, for example, be cached in a second sub-queue in the memory module. In yet another example, the third packet may also belong to a second data stream different from the first data stream; this embodiment of the application does not specifically limit this.

[0114] As an example, the first device can send a message release command to the memory module via the aforementioned general network interface. This message release command instructs the memory module to release the third message. In this application, the message release command includes third indication information, which instructs the memory module to perform a message release operation. Accordingly, after receiving the message release command, the memory module parses the third indication information and then releases the third message from the memory module.

[0115] In one example, the first device can add an interactive command header to the general network protocol corresponding to the aforementioned general network interface, and use the interactive command header to carry the aforementioned third instruction information.

[0116] In a specific example, if the address of the memory module is managed by the memory module itself, for example, the address of the memory module is managed by the ADP module of the memory module, then the third indication information may include the third operation type and the identifier of the third message, and the operation corresponding to the third operation type is a message release operation.

[0117] See also Figure 4f To understand, Figure 4f This is a schematic diagram illustrating the structure of a message release instruction provided in an embodiment of this application. For example... Figure 4f As shown, the message release instruction includes: an operation type field and a message identifier field. Wherein:

[0118] The Operation Type field is used to carry a third operation type. For example, a value of 2 in the Operation Type field indicates that the Operation Type field carries a third operation type. The Message Identifier field is used to carry an identifier for a third message.

[0119] In this scenario, the third indication information can instruct the memory module to perform a message release operation based on the identifier of the third message. Accordingly, after receiving the message release instruction, the memory module can parse the third indication information and obtain the identifier of the third message. Further, the memory module can use the identifier of the third message as an index to query the correspondence between pre-stored identifiers of third messages and cache space used to cache third messages, thereby determining the cache space used to cache the third message and releasing the determined cache space.

[0120] In another specific example, if the address of the memory module is managed by the first device, the third indication information may include a third operation type and a third address. For example, the first device may use the identifier of the third message as an index to query the correspondence between the pre-stored identifier of the third message and the address in the memory module used to cache the third message, and determine the third address in the memory module used to cache the third message. The operation corresponding to this third operation type is a message release operation. See also... Figure 4g To understand, Figure 4g This is a schematic diagram illustrating the structure of another message release instruction provided in an embodiment of this application. For example... Figure 4g As shown, the message release instruction includes: an operation type field and a message address field. Wherein:

[0121] The operation type field is used to carry a third operation type. For example, a value of 2 in the operation type field indicates that the operation type field carries a third operation type. The address field is used to carry the aforementioned third address.

[0122] In this scenario, the third instruction information can instruct the memory module to perform a message release operation based on the third address. Accordingly, after receiving the message release instruction, the memory module can parse the third instruction information and obtain the third address. Further, the memory module can release the third address. In one example, the third address may include the starting address and the storage length. In another example, the third address may be an address linked list; no specific limitation is made here.

[0123] In one example, if the first device receives a large amount of data, and the capacity of its on-chip cache and memory module is insufficient to buffer the received traffic, the first device will still discard some traffic, resulting in packet loss. To effectively avoid packet loss due to traffic congestion, the first device can also combine the utilization rate of the on-chip cache and the utilization rate of the memory module to determine the probability of discarding some traffic. In a specific example, if both the utilization rate of the on-chip cache and the utilization rate of the memory module are high—for example, if the utilization rate of the on-chip cache is greater than or equal to a first preset threshold and the utilization rate of the memory module is greater than or equal to a second preset threshold—it means that if the upstream device continues to send traffic to the first device at the current bandwidth, the first device is very likely to discard some traffic due to insufficient cache. Therefore, in this embodiment, when the utilization rate of the on-chip cache is greater than or equal to the first preset threshold and the utilization rate of the memory module is greater than or equal to the second preset threshold, the first device sends backpressure indication information to its upstream device to instruct the upstream device to reduce the bandwidth of the traffic sent to the first device. This reduces the traffic received by the first device, thereby effectively avoiding packet loss due to traffic congestion. This application does not specifically limit the content or format of the back pressure indication information.

[0124] This application does not specifically limit the first preset threshold and the second preset threshold. The first preset threshold and the second preset threshold can be set according to actual conditions. The first preset threshold and the second preset threshold can be the same or different. For example, the first preset threshold and the second preset threshold can both be 90%. Or, the first preset threshold can be 90% and the second preset threshold can be 95%.

[0125] As can be seen from the above description, in this application, the first device and the memory module are connected by a general network interface. Therefore, there is no need to develop a new communication protocol for interaction between the first communication device and the memory module. Adaptive modifications can be made to the communication protocol supported by the general network interface (for example, adding the aforementioned interaction command header).

[0126] Furthermore, the capacity of the memory module can be flexibly configured according to specific network scenarios to meet the networking requirements of different scenarios. For example, in scenarios with large caching requirements, a larger capacity memory module can be configured, enabling the first device to cache more packets and avoid packet loss due to traffic congestion. In other words, using the solution provided in this application embodiment, the same forwarding chip can be applied to different network scenarios.

[0127] Next, we will introduce two possible application scenarios of the embodiments of this application.

[0128] SeeFigure 5a , Figure 5a This is a schematic diagram illustrating an exemplary application scenario provided in an embodiment of this application.

[0129] Figure 5a A schematic diagram of a switch board is shown. The switch board can be a box-type board or a frame-type board. This application embodiment does not make specific limitations. Figure 5a The switch board shown can be used in data center networks. There are two network scenarios within a data center: a data center network (DCN) for interconnecting data centers within the same data center, and a data center interconnect (DCI) network for interconnecting data centers with other data centers.

[0130] In DCN, the switching equipment is required to provide high bandwidth and low latency. Traffic congestion and suddenness are not the main issues, and the requirements for device buffering are secondary.

[0131] In DCI networks, switches are required to have large bandwidth, strong congestion management and control capabilities, and strong absorption capacity for burst traffic.

[0132] Given the similarities and differences in services between the two scenarios mentioned above, a high-bandwidth forwarding chip can be designed that can be used in both DCN and DCI switches. Combining the solution provided in this application's embodiments, the bandwidth and buffer size requirements of different scenarios can be accommodated within the switch by deciding whether to deploy an HBM module or by appropriately configuring the specifications of the HBM module.

[0133] For example, such as Figure 5a As shown, the forwarding chip adopts a multi-chip encapsulation method. Figure 5a The illustration shows four I / O chips providing general network interfaces and one core chip providing packet forwarding. The bandwidth provided by the I / O chips is not specifically limited in this embodiment. For details regarding the contents of the core chip, please refer to the preceding section. Figures 1a to 2 The relevant descriptions will not be repeated here.

[0134] The forwarding chip connects to the HBM module via a general-purpose network interface provided by a specific I / O chip. For information on the structure of the HBM module, please refer to the previous section. Figure 2 The relevant descriptions in the description will not be repeated here.

[0135] If the switch board is used in a DCN (Distributed Network Network), the HBM module specifications can be lower, meaning the HBM module capacity can be set smaller. If the switch board is used in a DCI (Distributed Compatibility Network) network, the HBM module specifications can be higher, meaning the HBM module capacity can be set larger. Using this solution, the same forwarding chip can be used in both DCN and DCI networks, connecting HBM modules of different specifications to meet the buffering requirements of different scenarios. In one example, if... Figure 5a If the switch board shown is used in a DCI network, then the HBM specification can be configured to 100GB. In this scenario, the switch board can provide a buffer absorption capability at the level of hundreds of milliseconds.

[0136] See Figure 5b , Figure 5b This is a schematic diagram illustrating another exemplary application scenario provided in the embodiments of this application.

[0137] Figure 5b The application scenarios shown are Figure 5a The difference in the application scenarios shown is that, in Figure 5b In this scenario, the HBM module is not deployed inside the switch board, but in other devices independent of the switch board. The physical distance between the HBM module and the switch board can range from a few meters to hundreds of meters.

[0138] In addition, Figure 5b In the scenario shown, if the HBM module is deployed in a device independent of the switch board, then the HBM module can interface with one or more switch boards. That is, multiple switch boards can cache data into the HBM module. For ease of understanding, in... Figure 5b The diagram shows the HBM module connecting to one or two switch boards. In practical applications, the number of switch boards connected to the HBM module is not limited to two.

[0139] Based on the caching method provided in the above embodiments, this application also provides a caching device for executing the caching method provided in the above method embodiments.

[0140] See Figure 6 The figure is a schematic diagram of the structure of a cache processing device provided in an embodiment of this application.

[0141] Figure 6 The cache processing device 600 shown can be applied to the first device to execute the cache processing method executed by the first device provided in the above method embodiments.

[0142] The device 600 includes: a receiving unit 601, a processing unit 602, and a sending unit 603.

[0143] The receiving unit 601 is used to receive a first data stream, the first data stream including a first message and a second message.

[0144] The processing unit 602 is configured to cache the first message in the on-chip cache of the first device and cache the second message in the memory module connected to the first device. The first device is connected to the memory module through a general network interface, which includes an Ethernet interface, or a Super Ethernet Alliance (UEC) interface, or a Unified Bus (UB) interface.

[0145] The processing unit 602 is further configured to schedule the first message in the on-chip cache and the second message in the memory module so that the sending unit 603 can send the first message and the second message.

[0146] In one possible implementation, the first queue is a queue for forwarding the first data stream, and the first queue includes a first sub-queue and a second sub-queue. The first sub-queue is a queue in the on-chip cache used to cache the first message, and the second sub-queue is a queue in the memory module used to cache the second message.

[0147] In one possible implementation, the processing unit 602 is configured to: send a message caching instruction to the memory module through the general network interface, the message caching instruction being used to instruct the memory module to cache the second message, the message caching instruction including first indication information and the second message, the first indication information instructing the memory module to perform a message caching operation.

[0148] In one possible implementation, the first indication information includes a first operation type and an identifier of the second message, wherein the operation corresponding to the first operation type is a message caching operation, and the first indication information instructs the memory module to perform a message caching operation based on the identifier of the second message.

[0149] In one possible implementation, the first indication information includes a first operation type and a first address, the operation corresponding to the first operation type is a message caching operation, and the first indication information instructs the memory module to perform a message caching operation based on the first address.

[0150] In one possible implementation, the processing unit 602 is configured to: read the first message from the on-chip cache; send a message read instruction to the memory module via the general network interface using the sending unit 603 included in the device, the message read instruction instructing the memory module to read the second message, the message read instruction including second indication information, the second indication information instructing the memory module to perform a message read operation; and receive a feedback message sent by the memory module via the general network interface using the receiving unit 601, the feedback message including the second message.

[0151] In one possible implementation, the feedback message may also include the message reading instruction.

[0152] In one possible implementation, the second indication information includes a second operation type and an identifier of the second message. The operation corresponding to the second operation type is a message reading operation. The second indication information instructs the memory module to perform a message reading operation based on the identifier of the second message.

[0153] In one possible implementation, the second indication information includes a second operation type and a second address, the operation corresponding to the second operation type is a message reading operation, and the second indication information instructs the memory module to perform a message reading operation based on the second address.

[0154] In one possible implementation, the sending unit 603 is configured to: send the first message and the second message in the order in which the first message and the second message are received.

[0155] In one possible implementation, the sending unit 603 of the device is further configured to: send a message release instruction to the memory module through the general network interface, the message release instruction being used to instruct the memory module to release a third message cached in the memory module, the message release instruction including third indication information, the third indication information instructing the memory module to perform a message release operation.

[0156] In one possible implementation, the third indication information includes a third operation type and an identifier of the third message, wherein the operation corresponding to the third operation type is a message release operation, and the third indication information instructs the memory module to perform a message release operation based on the identifier of the third message.

[0157] In one possible implementation, the third indication information includes a third operation type and a third address, the operation corresponding to the third operation type is a message release operation, and the third indication information instructs the memory module to perform a message release operation based on the third address.

[0158] In one possible implementation, the sending unit 603 of the device is further configured to: send backpressure indication information to an upstream device of the first device when the utilization rate of the on-chip cache is greater than or equal to a first preset threshold and the utilization rate of the memory module is greater than or equal to a second preset threshold, so as to instruct the upstream device to reduce the bandwidth of the traffic sent to the first device.

[0159] In one possible implementation, the memory module includes a high-bandwidth memory (HBM) module.

[0160] In one possible implementation, the first device and the memory module belong to the same network device.

[0161] In one possible implementation, the first device and the memory module belong to two different devices.

[0162] Please see Figure 7 As shown, device 700 includes: processor 710, communication interface 720, and memory 730. The number of processors 710 in device 700 can be one or more. Figure 7 Taking a processor as an example, in this embodiment, the processor 710, communication interface 720, and memory 730 can be connected via a bus system or other means. Figure 7 Taking the connection between China and Israel via the 740 bus system as an example.

[0163] The processor 710 may be a central processing unit (CPU), an NP, or a combination of a CPU and an NP. The processor 710 may further include a hardware chip. The hardware chip may be an ASIC, a programmable logic device (PLD), or a combination thereof. The PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0164] The memory 730 may include volatile memory, such as random-access memory (RAM); the memory 730 may also include non-volatile memory, such as flash memory, hard disk drive (HDD), or solid-state drive (SSD); the memory 730 may also include a combination of the above types of memory.

[0165] Optionally, the memory 730 stores an operating system and programs, executable modules, or data structures, or subsets thereof, or extended sets thereof. The programs may include various operation instructions for implementing various operations. The operating system may include various system programs for implementing various basic services and handling hardware-based tasks. The processor 710 can read the programs from the memory 730 to implement the methods provided in the embodiments of this application.

[0166] The bus system 740 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus system 740 can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 7 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0167] This application provides a computer-readable storage medium, including instructions or a computer program, which, when run on a computer, causes the computer to perform the methods described in the above method embodiments.

[0168] This application provides a computer program product containing instructions or computer programs, which, when run on a computer, causes the computer to perform the methods described in the above method embodiments.

[0169] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0170] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0171] In the embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical business division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0172] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0173] Furthermore, the various business units in the embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software business unit.

[0174] If the integrated unit is implemented as a software business unit and sold or used as a separate product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0175] Those skilled in the art will recognize that, in one or more of the examples above, the services described in this invention can be implemented using hardware, software, firmware, or any combination thereof. When implemented in software, these services can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transmission of computer programs from one place to another. Storage media can be any available medium accessible to general-purpose or special-purpose computers.

[0176] The above specific embodiments further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above are merely specific embodiments of the present invention.

[0177] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A caching method, characterized in that, Applied to a first device, the method includes: The first device receives a first data stream, which includes a first message and a second message; The first device caches the first message in the on-chip cache of the first device and caches the second message in the memory module connected to the first device. The first device is connected to the memory module through a general network interface, which includes: an Ethernet interface, or a Super Ethernet Alliance (UEC) interface, or a Unified Bus (UB) interface. The first device schedules the first message in the on-chip cache and the second message in the memory module to send the first message and the second message.

2. The method according to claim 1, characterized in that, The first queue is a queue used to forward the first data stream. The first queue includes a first sub-queue and a second sub-queue. The first sub-queue is a queue in the on-chip cache used to cache the first message, and the second sub-queue is a queue in the memory module used to cache the second message.

3. The method according to claim 2, characterized in that, The first device caches the second message in a memory module connected to the first device, including: The first device sends a message caching instruction to the memory module through the general network interface. The message caching instruction is used to instruct the memory module to cache the second message. The message caching instruction includes first indication information and the second message. The first indication information instructs the memory module to perform a message caching operation.

4. The method according to claim 3, characterized in that, The first indication information includes a first operation type and an identifier of the second message. The operation corresponding to the first operation type is a message caching operation. The first indication information instructs the memory module to perform a message caching operation based on the identifier of the second message.

5. The method according to claim 3, characterized in that, The first indication information includes a first operation type and a first address. The operation corresponding to the first operation type is a message caching operation. The first indication information instructs the memory module to perform a message caching operation based on the first address.

6. The method according to any one of claims 1-5, characterized in that, The first device schedules the first message in the on-chip cache and the second message in the memory module to send the first message and the second message, including: The first device reads the first message from the on-chip buffer; The first device sends a message read instruction to the memory module through the general network interface. The message read instruction is used to instruct the memory module to read the second message. The message read instruction includes second indication information, which instructs the memory module to perform a message read operation. The first device receives a feedback message sent by the memory module through the general network interface, the feedback message including the second message; The first device sends the first message and the second message.

7. The method according to claim 6, characterized in that, The feedback message also includes the message reading instruction.

8. The method according to claim 6 or 7, characterized in that, The second indication information includes a second operation type and an identifier of the second message. The operation corresponding to the second operation type is a message reading operation. The second indication information instructs the memory module to perform a message reading operation based on the identifier of the second message.

9. The method according to claim 6 or 7, characterized in that, The second indication information includes a second operation type and a second address. The operation corresponding to the second operation type is a message reading operation. The second indication information instructs the memory module to perform a message reading operation based on the second address.

10. The method according to any one of claims 6-9, characterized in that, The first device sends the first message and the second message, including: The first device sends the first message and the second message in the order in which it receives the first message and the second message.

11. The method according to any one of claims 1-10, characterized in that, The method further includes: The first device sends a message release instruction to the memory module through the general network interface. The message release instruction is used to instruct the memory module to release the third message cached in the memory module. The message release instruction includes third indication information, which instructs the memory module to perform a message release operation.

12. The method according to claim 11, characterized in that, The third indication information includes a third operation type and the identifier of the third message. The operation corresponding to the third operation type is a message release operation. The third indication information instructs the memory module to perform a message release operation based on the identifier of the third message.

13. The method according to claim 11, characterized in that, The third indication information includes a third operation type and a third address. The operation corresponding to the third operation type is a message release operation. The third indication information instructs the memory module to perform a message release operation based on the third address.

14. The method according to any one of claims 1-13, characterized in that, The method further includes: When the utilization rate of the on-chip cache is greater than or equal to a first preset threshold and the utilization rate of the memory module is greater than or equal to a second preset threshold, the first device sends back pressure indication information to the upstream device to instruct the upstream device to reduce the bandwidth of the traffic sent to the first device.

15. The method according to any one of claims 1-14, characterized in that, The memory module includes: High-bandwidth memory HBM module.

16. The method according to any one of claims 1-15, characterized in that, The first device and the memory module belong to the same network device.

17. The method according to any one of claims 1-15, characterized in that, The first device and the memory module are two different devices.

18. A cache processing apparatus, characterized in that, The first device is applied to the following: the device includes a receiving unit, a processing unit, and a transmitting unit. The receiving unit is used to receive a first data stream, the first data stream including a first message and a second message; The processing unit is configured to cache the first message in the on-chip cache of the first device and cache the second message in the memory module connected to the first device, wherein the first device is connected to the memory module through a general network interface, the general network interface including: an Ethernet interface, or a Super Ethernet Alliance (UEC) interface, or a Unified Bus (UB) interface; The processing unit is further configured to schedule the first message in the on-chip cache and the second message in the memory module so that the sending unit can send the first message and the second message.

19. A device, characterized in that, include: Processor and memory; The memory is used to store instructions or computer programs; The processor is configured to execute the instructions or computer program to perform the method described in any one of claims 1-17.

20. A computer-readable storage medium, characterized in that, This includes instructions or computer programs that, when run on a computer, cause the computer to perform the method described in any one of claims 1-17.

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