Laminated cell, preparation method thereof and photovoltaic module

Abstract

The invention relates to a laminated cell, a preparation method thereof and a photovoltaic module. The laminated cell comprises a bottom cell, a top cell and a composite layer arranged between the bottom cell and the top cell, wherein the bottom cell comprises a silicon substrate, one side, facing the top cell, of the silicon substrate is provided with a first suede structure, the first suede structure comprises a plurality of first rounded pyramid structures, the suede size of each first rounded pyramid structure is 1 [mu] m-3. 5 [mu] m, and the rounded radius of the tower top and the tower bottom is 5 nm-300 nm; the top cell includes a perovskite absorption layer. The laminated cell has improved photoelectric conversion efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of batteries, in particular to a laminated battery and a preparation method thereof, and a photovoltaic module. BACKGROUND

[0002] The increase of global non-renewable energy consumption and environmental and climate problems promote extensive research on sustainable energy. Among them, solar energy is the largest renewable energy. Since it has been proved that the conversion of solar energy into electrical energy is one of the effective methods for storing and using renewable energy, photovoltaic power generation has made great progress. Perovskite solar cells are a kind of solar cells with short development time but fast efficiency improvement. The efficiency of the formal single-junction perovskite solar cell in the laboratory has reached 26.1%, and the theoretical efficiency of the perovskite / silicon-based double-junction laminated battery based on perovskite is more than 45%. The highest efficiency of the world record has reached 33.9%. High efficiency makes it have broad commercial application prospects. However, the texturing structure of the bottom cell currently used in the laminated battery does not match the perovskite cell, resulting in that the battery efficiency still needs to be improved. SUMMARY

[0003] Based on this, some embodiments of the present application provide a laminated battery with improved photoelectric conversion efficiency.

[0004] In addition, some other embodiments of the present application also provide a preparation method of a laminated battery and a photovoltaic module.

[0005] A laminated battery comprises a bottom cell, a top cell and a composite layer arranged between the bottom cell and the top cell.

[0006] The bottom cell comprises a silicon substrate, and a side of the silicon substrate facing the top cell has a first texturing structure comprising a plurality of first rounded pyramid structures, each of the first rounded pyramid structures has a texturing size of 1 μm to 3.5 μm, and a rounded radius of a top and a bottom of each of the first rounded pyramid structures is 5 nm to 300 nm.

[0007] The top cell comprises a perovskite absorption layer.

[0008] In some embodiments, the rounded radius of the top and the bottom of each of the first rounded pyramid structures is 8 nm to 20 nm.

[0009] And / or, a spacing between two adjacent first rounded pyramid structures is 1.5 μm to 3.5 μm.

[0010] In some embodiments, the second side of the silicon substrate away from the top cell has a second texturing structure comprising a plurality of second rounded pyramid structures, each of the second rounded pyramid structures has a texturing size of 1 μm to 3.5 μm, and a rounded radius of 5 nm to 300 nm at the top and the bottom of the pyramid.

[0011] In some embodiments, the second side of the silicon substrate away from the top cell has a second texturing structure comprising a plurality of second rounded pyramid structures, a rounded radius of the top of the second rounded pyramid structure is smaller than a rounded radius of the top of the first rounded pyramid structure, and a rounded radius of the bottom of the second rounded pyramid structure is smaller than a rounded radius of the bottom of the first rounded pyramid structure.

[0012] Optionally, the rounded radius of the top and the bottom of the second rounded pyramid structure is less than or equal to 2 nm.

[0013] In some embodiments, the bottom cell is a heterojunction cell.

[0014] In some embodiments, one or more of the following conditions is satisfied:

[0015] (1) the material of the composite layer comprises one or both of indium tin oxide and indium zinc oxide;

[0016] (2) the thickness of the composite layer is 20 nm to 30 nm;

[0017] (3) the band gap of the perovskite absorption layer is 1.63 eV to 1.75 eV;

[0018] (4) the material of the perovskite absorption layer comprises ABX3, the A-site cation comprises one or more of cesium ion, formamidinium ion and methylammonium ion, the B-site cation comprises lead ion, and the X-site ion comprises iodine ion; optionally, the X-site ion further comprises one or more of chlorine ion and bromine ion;

[0019] (5) the thickness of the perovskite absorption layer is 600 nm to 1200 nm.

[0020] In some embodiments, the top cell comprises, in sequence on the composite layer, a first carrier transport layer, a perovskite absorption layer, a second carrier transport layer and a first transparent electrode layer, one of the first carrier transport layer and the second carrier transport layer is a hole transport layer, and the other is an electron transport layer.

[0021] The stacked cell further comprises a first electrode and a second electrode, the first electrode forms an ohmic contact with the first transparent electrode layer, and the second electrode forms an ohmic contact with the bottom cell.

[0022] In some embodiments, one or more of the following conditions are met:

[0023] (1) a hole modification layer is further provided between the hole transport layer and the perovskite absorption layer, and a material of the hole modification layer comprises a single-molecule self-assembly material; optionally, the material of the hole modification layer comprises one or both of 2PACz and 4PACz;

[0024] (2) a passivation layer is further provided between the electron transport layer and the perovskite absorption layer; optionally, a material of the passivation layer comprises LiF;

[0025] (3) a buffer layer is further provided between the second carrier transport layer and the transparent electrode layer; optionally, a material of the buffer layer comprises SnO2;

[0026] (4) an anti-reflection layer is further provided on a side of the first transparent electrode layer away from the second carrier transport layer; optionally, a material of the anti-reflection layer comprises one or both of MgF2 and LiF.

[0027] A preparation method of a stacked cell, comprising the following steps:

[0028] obtaining a bottom cell, the bottom cell comprising a silicon substrate, a first surface of the silicon substrate having a first textured structure, the first textured structure comprising a plurality of first rounded pyramid structures, each of the first rounded pyramid structures having a texture size of 1 μm to 3.5 μm and a rounded corner radius of 5 nm to 300 nm at a top and a bottom of the pyramid;

[0029] stacking a composite layer and a top cell on the first surface of the silicon substrate in sequence, the top cell comprising a perovskite absorption layer, to obtain a stacked cell.

[0030] In some embodiments, the bottom cell is obtained by a method comprising the following preparation steps:

[0031] performing a first texturing treatment on the first surface of the silicon substrate to form a plurality of first pyramid structures, each of the first pyramid structures comprising a top and a bottom, and a flat portion between the bottoms of two adjacent first pyramid structures, the flat portion having a width of 50 nm to 400 nm, and each of the first pyramid structures having a texture size of 1 μm to 3.5 μm;

[0032] performing a first chemical polishing treatment on the first surface after the first texturing treatment to form the first textured structure on the first surface of the silicon substrate;

[0033] Optionally, the first texturing treatment has a time period of 350s to 390s, and the first chemical polishing treatment has a time period of 135s to 175s.

[0034] In some embodiments, the method for preparing the bottom cell further comprises:

[0035] performing a second texturing treatment on a second surface of the silicon substrate opposite to the first surface, the second texturing treatment having a time period increased by 3% to 12% compared to the first texturing treatment;

[0036] performing a second chemical polishing treatment on the second surface after the second texturing treatment, the second chemical polishing treatment having a time period decreased by 5% to 20% compared to the first chemical polishing treatment, and forming a second texturing structure on the second surface;

[0037] Optionally, the second texturing structure comprises a plurality of second rounded pyramid structures, a rounded top of the second rounded pyramid structure has a rounded radius smaller than a rounded top of the first rounded pyramid structure, and a rounded bottom of the second rounded pyramid structure has a rounded radius smaller than a rounded bottom of the first rounded pyramid structure.

[0038] Optionally, the rounded top and the rounded bottom of the second rounded pyramid structure have a rounded radius of less than or equal to 2nm.

[0039] In some embodiments, the method for preparing the perovskite absorption layer comprises:

[0040] preparing a skeleton layer;

[0041] spinning a cation solution on the skeleton layer and annealing to prepare the perovskite absorption layer;

[0042] In the step of spinning the cation solution, the spinning speed is 2500rpm to 6000rpm; optionally, the spinning speed is 2500rpm to 5500rpm.

[0043] Optionally, the material of the skeleton layer comprises lead iodide and cesium halide.

[0044] Optionally, the solute in the cation solution comprises one or more of FAI, FABr, FACl, MAI, MABr and MACl.

[0045] In some embodiments, the step of laminating the composite layer on the first surface of the silicon substrate and the top cell comprises:

[0046] laminating the composite layer on the first surface;

[0047] stacking a first carrier transport layer, a perovskite absorption layer, a second carrier transport layer and a first transparent electrode layer on the composite layer in sequence to prepare a top cell; one of the first carrier transport layer and the second carrier transport layer is a hole transport layer, and the other is an electron transport layer;

[0048] Optionally, a hole modification layer is further arranged between the hole transport layer and the perovskite absorption layer, and a preparation step of the hole modification layer comprises:

[0049] obtaining a self-assembled monomolecular material solution;

[0050] spin-coating the self-assembled monomolecular material solution on the hole transport layer, annealing to prepare the hole modification layer;

[0051] In the step of spin-coating the self-assembled monomolecular material solution on the hole transport layer, the spin-coating speed is 2500 rpm-5000 rpm; optionally, the spin-coating speed is 2500 rpm-4500 rpm.

[0052] A photovoltaic module comprising a solar cell and a packaging structure, the solar cell being the above-mentioned stacked cell or the stacked cell prepared by the above-mentioned preparation method, and the packaging structure being used for packaging the solar cell.

[0053] The present application researches and finds that in the traditional texture structure of the bottom cell, the top of the pyramid is too sharp, which leads to high recombination loss on the structured interface, reduces the open circuit voltage (Voc), and in addition, affects the shape retention of the perovskite layer when the perovskite absorption layer is prepared, thereby leading to low battery efficiency, and even causing delamination of the perovskite absorption layer and other problems. Based on this, the stacked cell of some embodiments of the present application optimizes the texture structure of the bottom cell, the texture size is 1 μm-3.5 μm, a larger pyramid texture is used, the prepared perovskite is more likely to have better shape retention, and the larger pyramid texture size cooperates with the larger fillet radius to improve the uniformity of the top cell of each film layer without increasing the reflectivity and losing Jsc, the top of the pyramid is smooth, and forms a better ohmic contact with the electrode. At the same time, the top and bottom of the pyramid have a larger fillet radius, which is beneficial to reducing the interface recombination loss and improving the open circuit voltage, thereby improving the battery efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0054] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0055] Figure 1A structural schematic diagram of a stacked battery for some embodiments of the present application;

[0056] Figure 2 Another structural schematic diagram of a stacked battery for some embodiments of the present application;

[0057] Figure 3 A process flow schematic diagram of a preparation method of a stacked battery for some embodiments of the present application;

[0058] Figure 4 A schematic diagram of a first texturing treatment and a first chemical polishing treatment for some embodiments of the present application.

[0059] BRIEF DESCRIPTION OF DRAWINGS Figure 1 In the figure, the stacked battery 100, the bottom battery 110, the composite layer 120, the top battery 130, the silicon substrate 111, the amorphous silicon layer 112, the second transparent electrode layer 113, the hole transport layer 131, the hole modification layer 132, the perovskite absorption layer 133, the passivation layer 134, the electron transport layer 135, the buffer layer 136, the first transparent electrode layer 137 and the anti-reflection layer 138, the first electrode 140 and the second electrode 150;

[0060] Figure 2 In the figure, the stacked battery 200, the bottom battery 210, the composite layer 220, the top battery 230, the silicon substrate 211, the amorphous silicon layer 212, the second transparent electrode layer 213, the hole transport layer 231, the hole modification layer 232, the perovskite absorption layer 233, the passivation layer 234, the electron transport layer 235, the buffer layer 236, the first transparent electrode layer 237, the anti-reflection layer 238, the first electrode 240 and the second electrode 250. DETAILED DESCRIPTION

[0061] In order to facilitate the understanding of the present application, the present application will be described more fully below in conjunction with specific embodiments. The preferred embodiments of the present application are given in the detailed description. However, the present application can be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the application to those skilled in the art.

[0062] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0063] Unless otherwise indicated or contradictory, the terms or phrases used in the present application have the following meanings: Unless otherwise indicated or contradictory, the terms or phrases used in the present application have the following meanings:

[0064] In the present application, "first", "second" are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can be explicitly or implicitly included at least one of the features.

[0065] In the description of the present application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise specifically limited.

[0066] In the present application, "one or more" refers to any one, any two or any two or more of the listed items. Among them, "multiple" refers to any two or more.

[0067] In the present application, the percentage concentration involved, unless otherwise specified, refers to the final concentration. The final concentration refers to the proportion of the added component in the system after adding the component.

[0068] In the present application, "further", "more further", "in particular", "for example", "such as", "example", "for example" are used for the purpose of description, indicating that the technical solutions before and after are related in terms of coverage, but should not be understood as a limitation of the previous technical solution, nor should it be understood as a limitation of the scope of protection herein. In this article, unless otherwise stated, A (such as B) means that B is one non-limiting example of A, and it can be understood that A is not limited to B.

[0069] In the present application, "optionally", "optional", "optional" means optional, that is, selected from "have" or "no" two parallel solutions. If there are multiple "optional" in a technical solution, unless otherwise specified, and there is no contradiction or mutual restriction, each "optional" is independent. In the present application, "optionally contains", "optionally contains" and the like, means "contains or does not contain". "Optional component X" means that component X exists or does not exist, or means that it contains or does not contain the component X.

[0070] When a numerical range is disclosed in the present application, the above range is considered to be continuous, and includes the minimum value and the maximum value of the range, and every value between such minimum value and maximum value. Further, when the range refers to an integer, every integer between the minimum value and the maximum value of the range is included. In addition, when multiple ranges are provided to describe characteristics or properties, the ranges can be combined. In other words, unless otherwise specified, all ranges disclosed in the present application should be understood to include any and all sub-ranges incorporated therein.

[0071] In the present application, the technical features described in an open manner include closed technical solutions consisting of listed features, and also include open technical solutions containing listed features.

[0072] The terms "comprising" and "having" and any variations thereof in the embodiments of the present application are intended to cover a non-exclusive inclusion. For example, a process, method, system, product or device that includes a list of steps or units is not limited to the listed steps or units, but can optionally further include steps or units not listed, or can optionally further include other steps or components inherent to such processes, methods, products or devices.

[0073] In the present application, referring to "embodiments" means that the specific features, structures or characteristics described in connection with the embodiments can be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily all refer to the same embodiment, nor is it necessarily a separate or alternative embodiment in the exclusion of other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described in the present application can be combined with other embodiments.

[0074] In the flowchart of the present application, although each step is displayed in sequence according to the direction of the arrow, these steps are not necessarily performed in the order indicated by the arrow, unless otherwise specified herein. The execution of these steps is not strictly limited in sequence, and they can be executed in other orders. Moreover, at least part of the steps in the figure can include multiple sub-steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times. The execution sequence is not necessarily sequential, but can be alternately or alternately executed with at least part of other steps or other sub-steps or stages.

[0075] The traditional HJT bottom cell's textured structure does not completely match the perovskite stacked cell. The present application researches and finds that the top of the pyramid and the tip of the pyramid of the traditional HJT bottom cell are still too sharp, and the perovskite top cell, especially the hole modification layer and the perovskite layer, needs a more smooth textured structure. If the top of the pyramid and the bottom of the pyramid are too sharp, it will cause high recombination loss on the structured interface, reduce Voc, and also affect the shape retention of the perovskite layer, thereby leading to low device efficiency, and even causing problems such as perovskite delamination. Based on this, the present application provides a stacked cell and a preparation method thereof.

[0076] Specifically, in a first aspect, the present application provides a stacked cell, comprising: a bottom cell, a top cell, and a composite layer arranged between the bottom cell and the top cell;

[0077] The bottom cell comprises a silicon substrate, and the side of the silicon substrate facing the top cell has a first textured structure, and the first textured structure comprises a plurality of first rounded pyramid structures, the textured size of each first rounded pyramid structure is 1 μm-3.5 μm, and the rounded radius of the top and the bottom is 5 nm-300 nm.

[0078] The top cell comprises a perovskite absorption layer.

[0079] The stack cell of some embodiments of the present application optimizes the texture structure of the bottom cell, the texture size is 1-3.5 μm, a larger pyramid texture is used, the prepared perovskite is more likely to have better shape retention, and the larger pyramid texture size cooperates with the larger round corner radius to improve the uniformity of the top cell of each film layer without increasing the reflectivity and losing Jsc, the tower top is smooth, and the electrode forms a better ohmic contact, at the same time, the tower top and the tower bottom have a larger round corner radius, which is beneficial to reducing the interface recombination loss and improving the open circuit voltage, thereby improving the cell efficiency. In the present application, the round cornered pyramid refers to the pyramid after the round corner processing, so that the cross section of the tower top and the tower bottom of the pyramid is arc-shaped.

[0080] Exemplarily, the round corner radius of the tower top and the tower bottom of each first round cornered pyramid structure can be but is not limited to 5 nm, 6 nm, 8 nm, 10 nm, 20 nm, 30 nm, 50 nm, 60 nm, 80 nm, 100 nm, 150 nm, 200 nm, 300 nm or a range formed by any two of these values. If the round corner radius of the tower top and the tower bottom of the first round cornered pyramid structure is too small, for example, less than 5 nm, it does not completely match the perovskite top cell, and the cell efficiency is low. If the round corner radius of the tower top and the tower bottom of the first round cornered pyramid structure is too large, for example, greater than 300 nm, the light trapping effect of the texture is weakened, the cell reflection is increased, the Jsc of the stack cell is seriously decreased, and the PCE is reduced.

[0081] In some embodiments, the round corner radius of the tower top and the tower bottom of the first round cornered pyramid structure is 8-20 nm.

[0082] In some embodiments, the round corner radius of the tower top of the first round cornered pyramid structure is the same as the round corner radius of the tower bottom.

[0083] Exemplarily, the texture size of the first round cornered pyramid structure can be but is not limited to 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm or a range formed by any two of these values. If the texture size of the first round cornered pyramid structure is less than 1 μm, it is not conducive to the shape retention of the subsequent perovskite absorption layer, and after the round corner processing, the reflectivity is slightly increased, which is not conducive to the improvement of the cell efficiency. If the texture size of the first round cornered pyramid structure is greater than 3.5 μm, the larger the texture size, the thicker the thickness of the perovskite absorption layer of the top cell needs to completely cover the pyramid, and if the pyramid is too thin, the tower top is easy to leak out, which leads to electric leakage and reduces the device efficiency.

[0084] In the present application, the texture size refers to the height of the pyramid structure. For example, the texture size of the first round cornered pyramid structure refers to the height of the first round cornered pyramid structure.

[0085] In some embodiments, the distance between two adjacent first rounded pyramid structures is 1.5 μm to 3.5 μm. It can be understood that the first rounded pyramid structures are unevenly distributed, and the distance between two adjacent first rounded pyramid structures refers to the distance between the top of the two adjacent rounded pyramid structures.

[0086] In some embodiments, the side of the silicon substrate away from the top cell has a second texturing structure, and the second texturing structure includes a plurality of second rounded pyramid structures, each second rounded pyramid structure has a texturing size of 1 μm to 3.5 μm, and the rounded radius of the top and the bottom is 5 nm to 300 nm. With the above arrangement, the front and back of the silicon substrate can be simultaneously subjected to texturing and polishing treatment to obtain a texturing structure, which is conducive to simplifying the process and improving the production efficiency.

[0087] In other embodiments, the side of the silicon substrate away from the top cell has a second texturing structure, and the second texturing structure includes a plurality of second rounded pyramid structures, the rounded radius of the top of the second rounded pyramid structure is smaller than the rounded radius of the top of the first rounded pyramid structure, and the rounded radius of the bottom of the second rounded pyramid structure is smaller than the rounded radius of the bottom of the first rounded pyramid structure.

[0088] Specifically, the rounded radius of the top and the bottom of the second rounded pyramid structure is less than or equal to 2 nm.

[0089] In some embodiments, the bottom cell is a heterojunction cell. The heterojunction (HJT) solar cell has the advantages of high efficiency, low temperature coefficient and negligible performance degradation, and the process is mature, which is suitable for being used as a bottom cell of a stacked cell. The present application finds that for a heterojunction cell, a smaller rounded corner and a slower pyramid are conducive to the deposition of amorphous silicon film, while a perovskite stacked cell needs a more moderate pyramid with a larger rounded corner to promote the uniform reaction of the skeleton layer and the halide and promote uniform film formation. Therefore, by making the opposite two sides of the bottom cell have different texturing structures, the perovskite top cell can be better matched, the deposition of amorphous silicon film is facilitated, and the cell efficiency is further improved.

[0090] In some embodiments, the bottom cell further includes an amorphous silicon layer disposed on the side of the silicon substrate away from the top cell. Further, the bottom cell further includes a second transparent electrode layer disposed on the side of the amorphous silicon layer away from the silicon substrate.

[0091] In some embodiments, the material of the composite layer includes one or both of indium tin oxide (ITO) and indium zinc oxide (IZO). It can be understood that the material of the composite layer is not limited to the above two, but can also be other materials commonly used in the art, as long as it has high mobility and high transmittance.

[0092] In some embodiments, the thickness of the composite layer is 20-30 nm.

[0093] In some embodiments, the material of the perovskite absorption layer includes ABX3. Wherein, the A-site cation includes one or more of Cs + , FA + and MA + , the B-site ion includes lead ion, and the X-site ion includes iodine ion. Optionally, the X-site ion further includes one or both of bromine ion and chlorine ion. In a conventional stacked cell, when the perovskite layer is prepared, the PbI2 at the bottom of the tower is prone to local insufficient reaction, and the conductive capacity of PbI2 is poor. Excessive PbI2 will affect the interface contact and hinder the charge transport. In some embodiments of the present application, by optimizing the texture structure of the bottom cell, the reaction of PbI2 at the bottom of the tower is facilitated, the interface contact performance is improved, the charge transport is facilitated, and the cell efficiency is further improved.

[0094] In some embodiments, the perovskite absorption layer is prepared by first preparing a skeleton layer, then coating a cation solution and annealing.

[0095] In some embodiments, the thickness of the perovskite absorption layer is 600-1200 nm.

[0096] In some embodiments, the band gap of the perovskite absorption layer is 1.63-1.75 eV.

[0097] In some embodiments, the top cell includes, in sequence from top to bottom, a first carrier transport layer, a perovskite absorption layer, a second carrier transport layer and a first transparent electrode layer, one of the first carrier transport layer and the second carrier transport layer is a hole transport layer, and the other is an electron transport layer.

[0098] The stacked cell further includes a first electrode and a second electrode, the first electrode forms ohmic contact with the first transparent electrode layer, and the second electrode forms ohmic contact with the bottom cell.

[0099] In some embodiments, the material of the hole transport layer includes one or more of inorganic hole transport material and organic hole transport material. Specifically, the hole transport material includes one or both of nickel oxide (NiO x ) and Spiro-TTB. It can be understood that the above only gives two more specific hole transport materials, but is not limited thereto, and other hole transport materials with high mobility can also be used as the material of the hole transport layer of the present application.

[0100] In some embodiments, the thickness of the hole transport layer is 20-30 nm.

[0101] In some embodiments, a hole modification layer is further provided between the hole transport layer and the perovskite absorption layer. The material of the hole modification layer includes a single-molecule self-assembly material. Specifically, the material of the hole modification layer includes one or more of 2PACz and 4PACz. By providing the hole modification layer, it is beneficial to passivate the interface defects between the hole transport layer and the perovskite absorption layer.

[0102] In some embodiments, the hole modification layer is a single-molecule layer.

[0103] In some embodiments, the material of the electron transport layer includes C 60 .

[0104] In some embodiments, the thickness of the electron transport layer is 15 nm to 20 nm.

[0105] In some embodiments, a passivation layer is further provided between the perovskite absorption layer and the electron transport layer. Specifically, the material of the passivation layer includes LiF. In some embodiments, the thickness of the passivation layer is 1 nm to 3 nm. Alternatively, the thickness of the passivation layer is 1 nm. By providing the passivation layer, it is beneficial to passivate the interface defects between the electron transport layer and the perovskite absorption layer.

[0106] In some embodiments, the material of the transparent electrode layer includes one or both of ITO and IZO. Specifically, the thickness of the transparent electrode layer is 80 nm to 120 nm.

[0107] In some embodiments, a buffer layer is further provided between the second carrier transport layer and the transparent electrode layer. Specifically, the material of the buffer layer includes tin dioxide (SnO2). In some of the embodiments, the thickness of the buffer layer is 20 nm to 30 nm.

[0108] In some embodiments, the first electrode is a metal electrode. Specifically, the material of the first electrode includes one or more of silver (Ag), copper (Cu) and aluminum (Al). Specifically, the thickness of the first electrode is 150 nm to 300 nm.

[0109] In some embodiments, the second electrode is a metal electrode. Specifically, the material of the second electrode includes one or more of silver (Ag), copper (Cu) and aluminum (Al). Specifically, the thickness of the second electrode is 150 nm to 300 nm.

[0110] In some embodiments, an anti-reflection layer is further provided on the side of the transparent electrode layer away from the second carrier transport layer. Specifically, the material of the anti-reflection layer includes one or both of MgF2 and LiF. Specifically, the thickness of the anti-reflection layer is 100 nm to 120 nm.

[0111] In some embodiments, the texture structure of the side surface of the silicon substrate facing the top cell is the same as the texture structure of the side of the silicon substrate facing away from the top cell, please refer to Figure 1 The laminated cell 100 includes a bottom cell 110, a composite layer 120, and a top cell 130. The bottom cell 110 includes a silicon substrate 111, and the first texture structure of the side of the silicon substrate 111 facing the top cell 130 is the same as the second texture structure of the side of the silicon substrate 111 facing away from the top cell 130. The side of the silicon substrate 111 facing away from the top cell 130 is further provided with an amorphous silicon layer 112 and a second transparent electrode layer 113. The top cell 130 includes a hole transport layer 131, a hole modification layer 132, a perovskite absorption layer 133, a passivation layer 134, an electron transport layer 135, a buffer layer 136, a first transparent electrode layer 137, and an anti-reflection layer 138, which are sequentially stacked on the composite layer 120. The laminated cell 100 further includes a first electrode 140 and a second electrode 150. The first electrode 140 forms an ohmic contact with the first transparent electrode layer 137 in the top cell 130, and the second electrode 150 forms an ohmic contact with the second transparent electrode layer 113 in the bottom cell 110.

[0112] In other embodiments, the texture structure of the side surface of the silicon substrate facing the top cell is different from the texture structure of the side of the silicon substrate facing away from the top cell, please refer to Figure 2 The laminated cell 200 includes a bottom cell 210, a composite layer 220, and a top cell 230. The bottom cell 210 includes a silicon substrate 211, and the first texture structure of the side of the silicon substrate 211 facing the top cell 230 is different from the second texture structure of the side of the silicon substrate 211 facing away from the top cell 230. The side of the silicon substrate 211 facing away from the top cell 230 is further provided with an amorphous silicon layer 212 and a second transparent electrode layer 213. The top cell 230 includes a hole transport layer 231, a hole modification layer 232, a perovskite absorption layer 233, a passivation layer 234, an electron transport layer 235, a buffer layer 236, a first transparent electrode layer 237, and an anti-reflection layer 238, which are sequentially stacked on the composite layer 220. The laminated cell 200 further includes a first electrode 240 and a second electrode 250. The first electrode 240 forms an ohmic contact with the first transparent electrode layer 237 in the top cell 230, and the second electrode 250 forms an ohmic contact with the second transparent electrode layer 213 in the bottom cell 210.

[0113] In a second aspect, the present application provides a preparation method of a laminated cell, please refer to Figure 3 The preparation method includes the following steps:

[0114] Step S110: obtaining a bottom cell, the bottom cell includes a silicon substrate, and a first surface of the silicon substrate has a first texture structure, the first texture structure includes a plurality of first rounded pyramid structures, the texture size of each first rounded pyramid structure is 1 μm-3.5 μm, and the corner radius of the top and the bottom is 5 nm-300 nm.

[0115] Step S120: A composite layer and a top cell are sequentially stacked on the first surface of a silicon substrate. The top cell includes a perovskite absorber layer to prepare a stacked cell.

[0116] In some embodiments, the bottom battery is obtained by a method comprising the following preparation steps:

[0117] The first surface of the silicon substrate is subjected to a first texturing process to form multiple first pyramid structures. Each first pyramid structure includes a top and a bottom. There is a flat part between the bottoms of two adjacent first pyramid structures. The width of the flat part is 50nm~400nm. The textured surface size of each first pyramid structure is 1μm~3.5μm.

[0118] The first surface after the first texturing process is subjected to a first chemical polishing process to form a first texturing structure on the first surface of the silicon substrate.

[0119] In some embodiments, the first texturing process takes 350s to 390s, and the first chemical polishing process takes 135s to 175s.

[0120] This application's research found that if complete etching is followed by polishing during texturing, the base of the pyramid becomes over-polished, increasing reflectivity. In tandem solar cells, the pyramid tops and apexes remain too sharp. The hole modification layer and perovskite layer, in particular, require a smoother textured surface. However, the overly sharp pyramid tops and bottoms lead to high recombination losses at the structured interface, reducing Voc and affecting the shape retention of the perovskite layer, resulting in low device efficiency and even perovskite delamination. Based on this, some embodiments of this application optimize the texturing and polishing processes, such as... Figure 4 As shown, compared to traditional HJT texturing, by shortening the time of the first texturing process, during texturing, <100> Incomplete etching of the directional crystal planes, particularly at the base of the pyramid, followed by extended polishing time and a longer rounding process at the top and bottom of the pyramid, results in a first textured structure with smoother top and bottom surfaces. Specifically, the first textured structure is a pyramid structure with large rounded corners, a texture size of 1μm~3.5μm, and rounded corner radii of 5nm~300nm at the top and bottom. This first textured structure improves the uniform coverage of each film layer in the top cell with almost no increase in reflectivity or loss of Jsc, and the smooth top of the pyramid forms a better ohmic contact with the electrode. Furthermore, using a larger pyramid texture size in tandem solar cells makes it easier to achieve better conformal preservation of the perovskite absorber layer.

[0121] In some embodiments, the temperature of the first texturing process is 82°C to 88°C.

[0122] The texturing agent used in the first texturing process can be commonly used in the art. Specifically, the first texturing agent used in the first texturing process includes water, an alkaline agent, and a first additive. In one example, the mass ratio of water, the alkaline agent, and the first additive in the first texturing agent is 98.3:1:0.7. The alkaline agent can be, but is not limited to, potassium hydroxide. The first additive can be Hangzhou Jingyan JY-106S.

[0123] The polishing agent used in the first chemical polishing process can be an acidic polishing agent commonly used in the art. Specifically, the first polishing agent includes water, HF, HCl, and a second additive. In one example, the mass ratio of water, HF, HCl, and the second additive in the first polishing agent is 95:3.2:1.2:0.6. The second additive can be Xiaochen Guo ST04.

[0124] In some embodiments, the pH of the polishing agent used in the first chemical polishing process is 2-4.

[0125] In some embodiments, before the first texturing process, the method further includes the steps of pre-cleaning, rinsing, damage removal, and rinsing, which are sequentially performed.

[0126] In some embodiments, after the first texturing process and before the first chemical polishing process, the method further includes the steps of rinsing, post-cleaning, and rinsing, which are sequentially performed.

[0127] In some embodiments, after the first chemical polishing process, the method further includes the steps of rinsing, post-cleaning, rinsing, pickling, rinsing, slow pulling, and drying, which are sequentially performed.

[0128] Each of the above steps can be commonly used in the art, and will not be described here.

[0129] In one embodiment, each process step is shown in Table 1. In Table 1, DI represents deionized water, ADD1 represents the first additive, and ADD2 represents the second additive.

[0130] Table 1

[0131]

[0132] In some embodiments, the method for preparing the base cell further includes:

[0133] performing a second texturing process on a second surface of the silicon substrate opposite to the first surface, the time of the second texturing process being increased by 3%-12% compared to the time of the first texturing process;

[0134] performing a second chemical polishing process on the second surface after the second texturing process, the time of the second chemical polishing process being reduced by 5%-20% compared to the time of the first chemical polishing process, and forming a second textured structure on the second surface.

[0135] In some embodiments, the second texturing structure comprises a plurality of second rounded pyramid structures, a rounding radius of a top of the second rounded pyramid structure is smaller than a rounding radius of a top of the first rounded pyramid structure, and a rounding radius of a bottom of the second rounded pyramid structure is smaller than a rounding radius of a bottom of the first rounded pyramid structure.

[0136] Specifically, the rounding radius of the top and the bottom of the second rounded pyramid structure is less than or equal to 2 nm.

[0137] For a heterojunction cell, a smaller rounding and a slower pyramid top are conducive to amorphous silicon film deposition, while a perovskite tandem cell needs a more moderate, larger rounding pyramid to promote uniform reaction of the halide and the skeleton layer, and promote uniform film formation. Based on this, some embodiments of the present application perform different texturing and polishing processes on the two surfaces of the silicon substrate of the bottom cell, so that the first surface has a pyramid texturing structure with a large rounding topography, and the second surface has a pyramid texturing structure with a small rounding topography, so that the perovskite top cell can be better matched, and amorphous silicon film deposition is facilitated, further improving device efficiency.

[0138] In other embodiments, the side of the silicon substrate facing away from the top cell has a second texturing structure, the second texturing structure comprises a plurality of second rounded pyramid structures, each of the second rounded pyramid structures has a texturing size of 1-3.5 μm, and a rounding radius of the top and the bottom is 5-300 nm, and the preparation method of the bottom cell comprises the same steps of the second texturing process and the first texturing process, and the same steps of the second chemical polishing process and the first chemical polishing process. At this time, the first surface and the second surface of the silicon substrate can be simultaneously subjected to the texturing process and the chemical polishing process, which is conducive to simplifying the process and improving production efficiency.

[0139] In some embodiments, the composite layer is prepared by magnetron sputtering (PVD), and the material of the composite layer comprises one or both of indium tin oxide (ITO) and indium zinc oxide (IZO), and the thickness is 20-30 nm.

[0140] In some embodiments, the preparation steps of the perovskite absorption layer comprise:

[0141] Preparation of a skeleton layer;

[0142] Spinning a cation solution on the skeleton layer, and annealing to prepare a perovskite absorption layer.

[0143] In some embodiments, the material of the skeleton layer includes lead iodide (PbI2) and cesium halide (CsX). Specifically, the skeleton layer is obtained by co-evaporating lead iodide and cesium halide by a double-source co-evaporation process. Specifically, the ratio of the evaporation rates of lead iodide and cesium halide is (5-13):1. Alternatively, the ratio of the evaporation rates of lead iodide and cesium halide is (6-10):1.

[0144] In one example, the cesium halide is cesium bromide (CsBr).

[0145] In one example, the evaporation rate error during the evaporation process should be less than 5%, and the film thickness uniformity should be less than 5%.

[0146] In some embodiments, the thickness of the skeleton layer is 350-400 nm.

[0147] In some embodiments, the solute in the cation solution includes one or more of FAI, FABr, FACl, MAI, MABr, and MACl. The solvent in the cation solution includes one or both of anhydrous ethanol and isopropyl alcohol.

[0148] In some embodiments, the cation solution includes a mixed solution of FAI, MABr, and MACl. Specifically, the concentration of FAI is 0.3-0.6 mol / L, the concentration of MABr is 0.1-0.2 mol / L, and the concentration of MACl is 0.05-0.15 mol / L.

[0149] In other embodiments, the cation solution includes a mixed solution of FABr, MAI, and MACl. Specifically, the concentration of FABr is 0.3-0.6 mol / L, the concentration of MAI is 0.1-0.2 mol / L, and the concentration of MACl is 0.05-0.15 mol / L.

[0150] In some embodiments, in the step of spin-coating the cation solution, the spin-coating speed is 2500-6000 rpm. Further, the spin-coating speed is 2500-5500 rpm. The conventional spin-coating speed of the cation solution is 3000-6000 rpm, while in some embodiments of the present application, the spin-coating speed of the cation solution is optimized to be 2500-5500 rpm, which is beneficial for the cooperation with the texturing structure of the bottom cell, and further improves the shape integrity of the perovskite absorption layer. In addition, the large round corner texturing structure is more conducive to the nucleation and uniform growth of perovskite than the conventional HJT bottom cell or the micro-round corner texturing structure, which further improves the performance of the cell. Further, the spin-coating speed of the cation solution is 3000-4000 rpm.

[0151] In some embodiments, the spin-coating time for the step of coating the cation solution onto the framework layer is 20 s to 40 s. Optionally, the spin-coating time for the step of coating the cation solution onto the framework layer is 30 s.

[0152] In one example, during the step of coating the cation solution onto the framework layer, the ambient humidity was less than 10% and the ambient temperature was 25°C.

[0153] In some embodiments, during the preparation of the perovskite absorber layer, the annealing temperature is 100°C to 150°C, and the time is 15 min to 30 min. Further, during the annealing step, the humidity is 5% to 40%. Through annealing, the bottom-deposited cations and spin-coated cations react with the co-evaporated framework layer to crystallize and form the perovskite absorber layer.

[0154] Specifically, the thickness of the perovskite absorber layer is 600 nm to 1200 nm, and the band gap is 1.63 eV to 1.75 eV.

[0155] In some embodiments, the step of stacking a composite layer and a top cell on a first surface of a silicon substrate includes:

[0156] A composite layer is stacked on the first surface;

[0157] A top cell is fabricated by sequentially stacking a first carrier transport layer, a perovskite absorber layer, a second carrier transport layer, and a first transparent electrode layer on a composite layer; one of the first carrier transport layer and the second carrier transport layer is a hole transport layer, and the other is an electron transport layer.

[0158] In some embodiments, the hole transport layer is prepared using a PVD process. The hole transport layer is made of an inorganic material, such as nickel oxide (NiO). x Alternatively, the hole transport layer can be made of organic materials, such as Spiro-TTB. Specifically, the thickness of the hole transport layer is 20nm~30nm.

[0159] In some embodiments, a hole modification layer is further provided between the hole transport layer and the perovskite absorber layer. Specifically, the preparation steps of the hole modification layer include:

[0160] Obtain a self-assembled monomolecular material solution;

[0161] A hole-modified layer was prepared by spin-coating a self-assembled monomolecule material solution onto a hole transport layer and annealing it.

[0162] In the step of spin-coating a self-assembled monomolecular material solution onto the hole transport layer, the spin-coating speed is 2500 rpm to 5000 rpm. Optionally, the spin-coating speed is 2500 rpm to 4500 rpm.

[0163] The spin coating speed of the conventional hole modification solution is 3000 rpm-5000 rpm. By optimizing the spin coating speed of 2500 rpm-4500 rpm in the preparation process of the hole modification layer, the uniformity of the hole modification layer is greatly improved, which is beneficial to the cooperation with the textured structure of the bottom cell. The large round corner textured structure is more conducive to covering a more uniform hole modification layer than the conventional HJT bottom cell or the micro round corner textured structure, so that the cell performance is further improved.

[0164] In some embodiments, the preparation step of the hole modification layer includes: preparing a self-assembled monomolecular material solution with a concentration of 0.8-1 mg / mL, under the condition of a rotation speed of 2500 rpm-4500 rpm, and then annealing at 80-120°C for 10-15 min to prepare the hole modification layer. Further, the spin coating speed of the self-assembled monomolecular material solution is 2500 rpm-3500 rpm.

[0165] In some embodiments, the material of the electron transport layer includes C 60 The electron transport layer is prepared by evaporation. Specifically, the evaporation rate is 0.2 Å / s-0.3 Å / s. Specifically, the thickness of the electron transport layer is 15 nm-20 nm.

[0166] In some embodiments, a passivation layer is further provided between the electron transport layer and the perovskite absorption layer. Specifically, the material of the passivation layer includes LiF, and the passivation layer is prepared by a vacuum deposition process. Specifically, the evaporation rate is 0.1 Å / s- Å / s. Specifically, the thickness of the passivation layer is 1 nm-3 nm.

[0167] In some embodiments, the first transparent electrode layer is prepared by magnetron sputtering (PVD). Specifically, the material of the first transparent electrode layer includes one or both of indium tin oxide (ITO) and indium zinc oxide (IZO), and the thickness is 20-30 nm.

[0168] In some embodiments, a buffer layer is further provided between the first transparent electrode layer and the second carrier transport layer. Specifically, the material of the buffer layer includes tin dioxide (SnO2), and the thickness is 20 nm-30 nm. In some embodiments, the buffer layer is prepared by an atomic deposition process (ALD).

[0169] In some embodiments, the material of the anti-reflection layer includes one or more of MgF2 and LiF, and the thickness is 100 nm-120 nm. In one example, the refractive index n value of the anti-reflection layer is about 1.4. Specifically, the anti-reflection layer is prepared by an evaporation process. In one example, the evaporation rate is 0.5 Å / s-2 Å / s.

[0170] In some embodiments, the stacked cell further comprises a first electrode and a second electrode, the first electrode forms ohmic contact with the first transparent electrode layer, and the second electrode forms ohmic contact with the bottom cell.

[0171] In some embodiments, the first electrode is prepared by evaporation. The first electrode is a patterned metal electrode. Specifically, the material of the first electrode comprises one or more of silver (Ag), copper (Cu) and aluminum (Al), and has a thickness of 150 nm to 300 nm and an evaporation rate of 2 Å / s to 4 Å / s.

[0172] In some embodiments, the second electrode is prepared by evaporation. Specifically, the back electrode is evaporated on the side of the bottom cell away from the top cell. The second electrode is a patterned metal electrode. Specifically, the material of the second electrode comprises one or more of silver (Ag), copper (Cu) and aluminum (Al), and has a thickness of 150 nm to 300 nm and an evaporation rate of 2 Å / s to 4 Å / s.

[0173] A third aspect of the present application provides a photovoltaic module comprising the stacked cell and the encapsulation structure as described above, and the encapsulation structure is used for encapsulating the stacked cell. The photovoltaic module is used for converting received light energy into electrical energy and transmitting to an external load.

[0174] Specifically, the encapsulation structure comprises an encapsulation adhesive film and a cover plate.

[0175] In one embodiment, the photovoltaic module comprises at least one cell string, an encapsulation adhesive film and a cover plate. The cell string is connected by a plurality of stacked cells; the encapsulation adhesive film is used to cover the surface of the cell string; and the cover plate is used to cover the surface of the encapsulation adhesive film away from the cell string.

[0176] In order to make the purpose and advantages of the present application more clear, the stacked cell and its effects of the present application are further described in detail in combination with specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application. The following embodiments do not include other components except for inevitable impurities, unless otherwise specified. In the embodiments, the drugs and instruments are selected according to the conventional selection in the art, unless otherwise specified. The experimental methods in the embodiments are implemented according to the conventional conditions, such as the conditions described in the literature or books or the methods recommended by the manufacturers.

[0177] Embodiment 1

[0178] The present embodiment provides a stacked cell, which has the structure as shown in Figure 1As shown, from bottom to top are HJT bottom cell 110 with both N and P faces being large round corners, composite layer 120 and top cell 130, wherein bottom cell 110 includes silicon substrate 111, the first textured surface structure on the side of silicon substrate 111 facing top cell 130 is the same as the second textured surface structure on the side of silicon substrate 111 facing away from top cell 130. On the side of silicon substrate 111 facing away from top cell 130, there is further provided amorphous silicon layer 112 and second transparent electrode layer 113. Top cell 130 includes, in order, hole transport layer 131, hole modification layer 132, perovskite absorption layer 133, passivation layer 134, electron transport layer 135, buffer layer 136, first transparent electrode layer 137 and anti-reflection layer 138 stacked on composite layer 120. First electrode 140 of stacked cell 100 forms ohmic contact with first transparent electrode layer 137, and second electrode 150 forms ohmic contact with second transparent electrode layer 113.

[0179] The preparation method of the stacked cell of the present embodiment includes the following steps:

[0180] (1) Texturing is performed on both the N and P faces of the silicon substrate, followed by chemical polishing, to form round-cornered pyramids on both the N and P faces of the silicon substrate. The specific texturing and polishing process is shown in Table 2 below. The resulting textured surface size is 3 μm, and the round corner radius of the top and bottom of the tower is 8 nm.

[0181] (2) Forming intrinsic amorphous silicon layer and doped amorphous silicon layer on the P face of the textured silicon substrate to obtain HJT bottom cell.

[0182] (3) Preparing a patterned composite layer on the HJT bottom cell using magnetron sputtering (PVD), and the material of the composite layer is indium tin oxide (ITO) with a thickness of 25 nm.

[0183] (4) Preparing a hole transport layer on the composite layer by PVD process, and the material of the hole transport layer is nickel oxide (NiOx) with a thickness of 25 nm.

[0184] (5) Preparing a hole modification layer on the hole transport layer using spin coating process, and the hole modification layer is a monomolecular layer, the material is 2PACz, the concentration is 0.9 mg / mL, the rotation speed is 4000 rpm, the annealing temperature is 100℃, and the annealing time is 12 min.

[0185] (6) Preparing a skeleton layer on the hole transport layer using double-source co-evaporation process to evaporate PbI2 and CsBr, and the thickness of the skeleton layer is 380 nm, the evaporation rate ratio of PbI2 and CsBr is 8:1, the evaporation rate error during evaporation should be less than 5%, and the film thickness uniformity is less than 5%.

[0186] (7) The cation solution is spin-coated on the skeleton layer by a spin coating process, the cation solution is a mixed solution of FAI, MABr and MACI, and the solvent is anhydrous ethanol. The concentration of FAI is 0.45 mol / L, the concentration of MABr is 0.15 mol / L, and the concentration of MACI is 0.1 mol / L. The spin coating speed is 5000 rpm, the spin coating time is 30 s, the spin coating environment humidity is less than 10%, and the temperature is 25°C. After spin coating, annealing is performed under the condition that the humidity is 5% to 40%, the annealing temperature is 125°C, and the annealing time is 20 min. During the annealing process, the cations deposited at the bottom and the spin-coated cations react with the co-evaporated skeleton layer to form a perovskite light-absorbing layer, the thickness is 900 nm, and the band gap is 1.7 eV.

[0187] (8) A passivation layer is prepared on the perovskite light-absorbing layer by a vacuum deposition process, the passivation layer material is LiF, the thickness is 1 nm, and the evaporation rate is 0.1 Å / s.

[0188] (9) An electron transport layer is evaporated on the passivation layer, the electron transport layer material is C 60 , the thickness is 18 nm, and the evaporation rate is 0.25 Å / s.

[0189] (10) A buffer layer is prepared on the electron transport layer by an atomic deposition process (ALD), the buffer layer material is tin dioxide (SnO2), and the thickness is 25 nm.

[0190] (11) A patterned first transparent electrode layer is prepared on the buffer layer by a magnetron sputtering (PVD) process, the first transparent electrode layer material is ITO, and the thickness is 100 nm.

[0191] (12) A first electrode is evaporated on the first transparent electrode layer, the first electrode is a patterned metal electrode, the material is silver (Ag), the thickness is 200 nm, and the evaporation rate is 3 Å / s.

[0192] (13) After the above steps, a second electrode is evaporated on the P surface of the HJT bottom cell, the second electrode is similar to the first electrode, the material is silver (Ag), the thickness is 200 nm, and the evaporation rate is 3 Å / s.

[0193] (14) A anti-reflection layer is prepared on the first electrode of step (12) by an evaporation process, the material is MgF2, the thickness is 110 nm, the evaporation rate is 1 Å / s, and the refractive index n value is about 1.4.

[0194] Table 2 Texturing and polishing process of Example 1

[0195]

[0196] Example 2

[0197] The present embodiment provides a laminated battery, the battery structure and the preparation process are similar to the laminated battery of embodiment 1, the difference is that in the preparation of the laminated battery, the spin coating speed of the solution in the preparation process of the hole modification layer in step (5) and the spin coating speed of the cation solution in step (7) are different. In this embodiment, the spin coating speed of the solution in the preparation process of the hole modification layer is 3000 rpm, and the spin coating speed of the cation is 3500 rpm. The remaining steps are consistent with embodiment 1, and will not be repeated here.

[0198] Embodiment 3

[0199] The present embodiment provides a laminated battery, the battery structure and the preparation process are similar to the laminated battery of embodiment 2, the difference is that the N face and the P face of the HJT bottom cell prepared in this embodiment have different textured structures, as shown in Figure 2 The N face of the bottom cell of the present embodiment is textured and polished by the same process as embodiment 2, and the P face is textured and polished by the same process as comparative example 1. The pyramid textured structure of the N face of the bottom cell of the present embodiment has a size of 3 μm, and the round corner radius of the top and bottom of the pyramid is 8 nm; the pyramid textured structure of the P face has a size of 3 μm, and the round corner radius of the top and bottom of the pyramid is 1.9 nm. The remaining steps are consistent with embodiment 2.

[0200] Comparative Example 1

[0201] Comparative Example 1 provides a solar cell, the device structure and preparation steps are similar to those of embodiment 1, the difference is that the N face and the P face of the bottom cell use the conventional HJT textured structure, the texturing time in the texturing process is 400 s, the temperature is controlled at 85±3℃, the chemical polishing time is 130 s, and the pH value of the solution is controlled at 2~4, and the remaining steps and process parameters are consistent with those of embodiment 1.

[0202] Comparative Example 2

[0203] Comparative Example 2 provides a solar cell, the device structure and preparation steps are similar to those of embodiment 1, the difference is that the pyramid textured structure of the N face and the P face of the bottom cell has a size of 4 μm, and the round corner radius of the top and bottom of the pyramid is 308 nm. Specifically, in the texturing process, the texturing time is reduced to 310 s, the polishing time is increased to 210 s, and the mass ratio of water, alkaline reagent and first additive is 98.3:1:0.5.

[0204] The textured structure of the bottom cell of the above-mentioned embodiment 1, comparative example 1 and comparative example 2 is tested, and the results are shown in Table 3. The textured structure of the bottom cell of embodiment 2 is the same as that of embodiment 1, the N face textured structure of the bottom cell of embodiment 3 is the same as that of embodiment 1, and the P face textured structure is the same as that of comparative example 1, which will not be repeated here.

[0205] Table 3 Comparison of cell parameters after texturing treatment of HJT bottom cell with different morphologies

[0206]

[0207] The performance of the stacked batteries of each of the above examples and the comparative example was tested, and the results are shown in Table 4 below.

[0208] Table 4 Performance of stacked batteries of each of the examples and the comparative example

[0209]

[0210] As can be seen from the comparison between Example 1 and Comparative Example 1, by optimizing the structure of the bottom cell rough surface, the efficiency of the stacked battery is improved.

[0211] As can be seen from the comparison between Example 1 and Example 2, by reducing the spin coating speed to match the large round corner rough surface structure, the uniform coverage of the hole modification layer and the shape retention of the perovskite absorption layer are further improved, the PbI2 residue in the pyramid valley is reduced, and thus the battery efficiency is further improved.

[0212] As can be seen from the comparison between Example 2 and Example 3, the deposition of amorphous silicon layer on the P surface can be realized without a more smooth pyramid, while the large round corner rough surface is required for the deposition of perovskite top cell on the N surface. The use of different rough surface structures on the N surface and the P surface can improve the deposition quality of the top cell while the reflectivity of the bottom cell is not affected, thereby improving the battery efficiency.

[0213] The technical features of the above-described examples can be combined in any manner. In order to make the description concise, all possible combinations of the technical features in the above-described examples are not described, however, as long as the combinations of the technical features do not contradict each other, they should be considered as within the scope of the present disclosure.

[0214] The above-described examples only express several embodiments of the present application, facilitate specific and detailed understanding of the technical solutions of the present application, but should not be understood as limiting the scope of the patent protection. It should be noted that for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of the present application. It should be understood that the technical solutions obtained by those skilled in the art through logical analysis, reasoning or limited experiments on the basis of the technical solutions provided in the present application are within the scope of the appended claims of the present application. Therefore, the scope of protection of the present patent should be based on the contents of the appended claims, and the description and drawings can be used to explain the contents of the claims.

Claims

1. A stacked battery, characterized by comprising: The bottom cell, the top cell and the composite layer arranged between the bottom cell and the top cell are included; The bottom cell includes a silicon substrate, and a side of the silicon substrate facing the top cell has a first textured structure including a plurality of first rounded pyramid structures, each of the first rounded pyramid structures has a textured size of 1-3.5 μm, and a rounded radius of a top and a bottom of each of the first rounded pyramid structures is 5-300 nm; The top cell includes a perovskite absorption layer.

2. The stacked battery of claim 1, wherein, The rounded radius of the top and the bottom of each of the first rounded pyramid structures is 8-20 nm. And / or, a distance between two adjacent first rounded pyramid structures is 1.5-3.5 μm.

3. The stacked cell according to claim 1 or 2, characterized by A side of the silicon substrate away from the top cell has a second textured structure including a plurality of second rounded pyramid structures, each of the second rounded pyramid structures has a textured size of 1-3.5 μm, and a rounded radius of a top and a bottom of each of the second rounded pyramid structures is 5-300 nm.

4. The stacked cell according to claim 1 or 2, characterized by The rounded radius of the top of each of the second rounded pyramid structures is smaller than the rounded radius of the top of each of the first rounded pyramid structures, and the rounded radius of the bottom of each of the second rounded pyramid structures is smaller than the rounded radius of the bottom of each of the first rounded pyramid structures. Optionally, the rounded radius of the top and the bottom of each of the second rounded pyramid structures is smaller than or equal to 2 nm.

5. The stacked battery of claim 4, wherein, The bottom cell is a heterojunction cell.

6. The stacked battery of claim 1, 2, or 5, wherein, One or more of the following conditions is met: (1) the material of the composite layer includes one or both of indium tin oxide and indium zinc oxide; (2) the thickness of the composite layer is 20-30 nm; (3) the band gap of the perovskite absorption layer is 1.63-1.75 eV; (4) the material of the perovskite absorption layer includes ABX3, the A-site cation includes one or more of cesium ion, formamidinium ion and methylamine ion, the B-site cation includes lead ion, and the X-site ion includes iodine ion; optionally, the X-site ion further includes one or more of chlorine ion and bromine ion; (5) the thickness of the perovskite absorption layer is 600-1200 nm.

7. The stacked battery of claim 6, wherein, The top cell includes a first carrier transport layer, a perovskite absorption layer, a second carrier transport layer and a first transparent electrode layer arranged in sequence on the composite layer, one of the first carrier transport layer and the second carrier transport layer is a hole transport layer, and the other is an electron transport layer; The stacked cell further includes a first electrode and a second electrode, the first electrode forms an ohmic contact with the first transparent electrode layer, and the second electrode forms an ohmic contact with the bottom cell.

8. The stacked battery of claim 7, wherein, One or more of the following conditions is met: (1) a hole modification layer is further arranged between the hole transport layer and the perovskite absorption layer, and the material of the hole modification layer includes a monomolecular self-assembly material; optionally, the material of the hole modification layer includes one or both of 2PACz and 4PACz. (2) A passivation layer is further arranged between the electron transport layer and the perovskite absorption layer; optionally, the material of the passivation layer comprises LiF; (3) A buffer layer is further arranged between the second carrier transport layer and the transparent electrode layer; optionally, the material of the buffer layer comprises SnO2; (4) A reflection-reducing layer is further arranged on the side of the first transparent electrode layer away from the second carrier transport layer; optionally, the material of the reflection-reducing layer comprises one or both of MgF2 and LiF.

9. A method of manufacturing a stacked battery, characterized by, The method comprises the following steps: obtaining a bottom cell, the bottom cell comprising a silicon substrate, a first surface of the silicon substrate having a first textured structure, the first textured structure comprising a plurality of first rounded pyramid structures, each of the first rounded pyramid structures having a texture size of 1 μm to 3.5 μm and a rounded radius of 5 nm to 300 nm at a top and a bottom of the pyramid structure; stacking a composite layer and a top cell on the first surface of the silicon substrate in sequence, the top cell comprising a perovskite absorption layer, to obtain a stacked cell.

10. The method of claim 9, wherein the step of forming the stack of cells is performed by a method comprising: The bottom cell is obtained by a method comprising the following steps: ​ performing a first texturing treatment on the first surface of the silicon substrate to form a plurality of first pyramid structures, each of the first pyramid structures comprising a top and a bottom, and a flat portion between the bottoms of two adjacent first pyramid structures, the flat portion having a width of 50 nm to 400 nm, and each of the first pyramid structures having a texture size of 1 μm to 3.5 μm; performing a first chemical polishing treatment on the first surface after the first texturing treatment to form the first textured structure on the first surface of the silicon substrate; optionally, the first texturing treatment is performed for 350 s to 390 s, and the first chemical polishing treatment is performed for 135 s to 175 s.

11. The method of claim 10, wherein the step of forming the stack of cells is performed by a method comprising: forming a first cell on the substrate; forming a second cell on the first cell; and forming a third cell on the second cell. The method for preparing the bottom cell further comprises: performing a second texturing treatment on a second surface of the silicon substrate opposite to the first surface, the second texturing treatment being performed for 3% to 12% more than the first texturing treatment; performing a second chemical polishing treatment on the second surface after the second texturing treatment, the second chemical polishing treatment being performed for 5% to 20% less than the first chemical polishing treatment, to form a second textured structure on the second surface; optionally, the second textured structure comprises a plurality of second rounded pyramid structures, the rounded radius of the top of the second rounded pyramid structure is smaller than the rounded radius of the top of the first rounded pyramid structure, and the rounded radius of the bottom of the second rounded pyramid structure is smaller than the rounded radius of the bottom of the first rounded pyramid structure; optionally, the rounded radius of the top and the bottom of the second rounded pyramid structure is smaller than or equal to 2 nm.

12. The method of claim 9, 10 or 11, wherein the method further comprises the step of: The step of preparing the perovskite absorption layer comprises: ​ preparing a skeleton layer; spinning a cation solution on the skeleton layer and performing annealing to prepare the perovskite absorption layer; in the step of spinning the cation solution, the spinning speed is 2500 rpm to 6000 rpm; optionally, the spinning speed is 2500 rpm to 5500 rpm; optionally, the material of the skeleton layer comprises lead iodide and cesium halide; Optionally, the solute in the cationic solution comprises one or more of FAI, FABr, FACl, MAI, MABr and MACl.

13. The method of claim 9, 10 or 11, wherein the method further comprises the step of: 15 applying a layer of a conductive material to the surface of the substrate prior to the step of applying the first layer of the first material. 20 The step of laminating the first surface composite layer and the top cell on the silicon substrate comprises: laminating the first surface composite layer on the silicon substrate; laminating a first carrier transport layer, a perovskite absorption layer, a second carrier transport layer and a first transparent electrode layer on the composite layer in sequence to prepare the top cell; one of the first carrier transport layer and the second carrier transport layer is a hole transport layer, and the other is an electron transport layer; Optionally, a hole modification layer is further arranged between the hole transport layer and the perovskite absorption layer, and the preparation step of the hole modification layer comprises: obtaining a self-assembled monomolecular material solution; spin-coating the self-assembled monomolecular material solution on the hole transport layer and annealing to prepare the hole modification layer; In the step of spin-coating the self-assembled monomolecular material solution on the hole transport layer, the spin-coating speed is 2500 rpm to 5000 rpm; optionally, the spin-coating speed is 2500 rpm to 4500 rpm.

14. A photovoltaic module, characterized by The solar cell is the laminated cell according to any one of claims 1 to 8 or is prepared by the preparation method according to any one of claims 9 to 13, and the packaging structure is used for packaging the solar cell.

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