Fan-out wafer level packaging unit
By using a method of filling metal paste and then grinding to manufacture conductive lines in fan-out wafer-level packaging units, and using flip-chip technology to connect bare dies, the high cost and environmental protection issues of conductive lines are solved, achieving thin, light, short and efficient electrical connections, thus enhancing the competitiveness of products.
Patent Information
- Application Number
- CN202410931422.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-12
- Publication Date
- 2026-01-20
AI Technical Summary
In existing fan-out wafer-level packaging technologies, the fabrication cost of the redistribution layer's conductive lines is high and not environmentally friendly. At the same time, when increasing the number of bare dies to improve performance, internal electrical connections become difficult.
The technique involves filling the grooves with metal paste and then grinding them to form the conductive lines, thus creating the first and second conductive lines. The second bare die is then connected using flip-chip technology, combined with a silicon, glass, or ceramic substrate, to achieve precision manufacturing of the conductive lines.
It reduces the manufacturing cost of conductive lines, simplifies the manufacturing process, improves the thinness, compactness, and reliability of the packaging unit, and enhances the product's diversified applications and market competitiveness.
Smart Images
Figure CN121368412A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to a package unit, in particular to a fan-out wafer level package unit. BACKGROUND
[0002] A package technology with light, thin, short and high efficiency and high reliability is a development trend of semiconductor industry, and the fan-out wafer level packaging (FOWLP) is an existing package technology.
[0003] In the advanced FOWLP, the redistribution layer (RDL) is the most critical, because the redistribution layer (RDL) can make the multiple pads on the die have the XY plane electrical extension and interconnection effect, so that multiple pads can be formed around the die, thereby effectively improving the design space and reliability of the redistribution layer (RDL), but how to make the redistribution layer (RDL) have the XY plane electrical extension and interconnection effect while also maintaining or achieving a certain degree of light, thin, short and small effect is the most critical for the redistribution layer (RDL).
[0004] However, the redistribution layer (RDL) technology used in the existing FOWLP package technology is formed by plating or electroplating, so that the material cost and manufacturing cost are relatively high, and the process in the existing technology does not meet or is not conducive to environmental protection requirements.
[0005] In addition, when the FOWLP package unit needs to increase performance or computing power, it is necessary to additionally increase the number of dies, and how to make external or internal electrical connection between the dies inside and outside the package unit is also an important problem to be solved. SUMMARY
[0006] The main purpose of the present application is to provide a fan-out wafer level package unit, which includes a carrier plate, at least one first die, a first dielectric layer, a plurality of first conductive lines, a second dielectric layer, a plurality of second conductive lines, and at least one second die; wherein the vertical chip area of the second surface of each first die is defined as a chip area; wherein the second dielectric layer has a plurality of second grooves for the external exposure of each second conductive line to form a pad, and each pad located around the chip area is a first pad; wherein each second die is disposed above the second dielectric layer by flip-chip technology and is electrically connected to each first die; and wherein each first die can be electrically connected externally by each first pad, effectively solving the problem of high manufacturing cost and environmental protection in the existing fan-out package technology when manufacturing each conductive line.
[0007] To achieve the above object, the present application provides a fan-out wafer level package unit, which comprises a carrier plate, at least one first die, a first dielectric layer, a plurality of first conductive lines, a second dielectric layer, a plurality of second conductive lines and at least one second die; wherein each of the first die is separated from a wafer, each of the first die has a first surface and an opposite second surface, the first surface of each of the first die is fixed on the carrier plate, the second surface of each of the first die has a plurality of die pads, and the vertical chip area of the second surface is defined as a chip area; wherein the first dielectric layer is arranged on the carrier plate and the second surface of each of the first die, the first dielectric layer has a plurality of first grooves which are horizontally extended, wherein each of the die pads of each of the first die is exposed outside by the plurality of the first grooves; wherein each of the first conductive lines is composed of metal paste filled in the plurality of the first grooves, and each of the first conductive lines is electrically connected with the plurality of the die pads of each of the first die; wherein the second dielectric layer is arranged on the first dielectric layer, the second dielectric layer has a plurality of second grooves which are horizontally extended, and each of the second grooves is communicated with each of the first grooves; wherein each of the second conductive lines is composed of metal paste filled in the plurality of the second grooves, and each of the second conductive lines is electrically connected with each of the first conductive lines, wherein each of the second grooves exposes the plurality of the second conductive lines outside to form a solder pad in each of the second grooves, wherein the solder pads formed in the plurality of the second grooves around the chip area on the second surface of each of the first die are first solder pads, and each of the first solder pads is further electrically connected with each of the first conductive lines around the chip area, wherein the solder pads formed in the plurality of the second grooves within the range of the chip area on the second surface of each of the first die are second solder pads, and each of the second solder pads is further electrically connected with the plurality of the first conductive lines within the range of the chip area; wherein each of the second die is separated from a wafer, each of the second die has a first surface and an opposite second surface, and the second surface of each of the second die has at least two die pads; wherein the at least two die pads of each of the second die are electrically connected on the at least two second solder pads by flip-chip technology, so that each of the second die is located above the second dielectric layer, and each of the second die can be electrically connected with each of the first die through the plurality of the first conductive lines within the range of the chip area; wherein each of the first die can be electrically connected outside in sequence through the plurality of the die pads of each of the first die, the plurality of the first conductive lines around the chip area, the plurality of the second conductive lines and the plurality of the first solder pads around the chip area on the second surface of each of the first die, so as to form the fan-out wafer level package unit.The manufacturing method of the fan-out wafer level package unit comprises the following steps: step S1: providing a carrier plate; step S2: spacingly arranging a plurality of first dies separated from at least one wafer on the carrier plate, wherein each first die has a first surface and an opposite second surface, the first surface of each first die is arranged on the carrier plate, the second surface of each first die has a plurality of die pads, and the vertical chip region of the second surface is defined as a chip region; step S3: using the technology of filling metal paste into grooves and then grinding to form a plurality of first conductive lines on the second surface of each first die, a first dielectric layer is first laid on the carrier plate and the second surface of each first die, then a plurality of first grooves are horizontally formed on the first dielectric layer, and each die pad of each first die can be exposed outside by the plurality of first grooves, then metal paste is filled into each first groove, and the thickness of the metal paste is higher than the surface of the first dielectric layer, finally the metal paste higher than the surface of the first dielectric layer is ground to make the surface of the metal paste flush with the surface of the first dielectric layer to form a plurality of first conductive lines; step S4: using the technology of filling metal paste into grooves and then grinding to form a plurality of second conductive lines on the first dielectric layer: a second dielectric layer is first laid on the first dielectric layer, then a plurality of second grooves are horizontally formed on the second dielectric layer, and each second groove can communicate with each first groove, then metal paste is filled into the plurality of second grooves, and the thickness of the metal paste is higher than the surface of the second dielectric layer, finally the metal paste higher than the surface of the second dielectric layer is ground to make the surface of the metal paste flush with the surface of the second dielectric layer to form a plurality of second conductive lines, wherein the plurality of second grooves are used for exposing the second conductive lines outside to form pads in the plurality of second grooves, wherein the pads formed in the plurality of second grooves around the chip region on the second surface of each first die are first pads, and each first pad is further electrically connected with the plurality of first conductive lines around the chip region, wherein the pads formed in the plurality of second grooves within the range of the chip region on the second surface of each first die are second pads, and each second pad is further electrically connected with the plurality of first conductive lines within the range of the chip region.Step S5: a plurality of second dies separated from at least one wafer are arranged above the second dielectric layer by flip-chip technology, wherein each of the second dies has a first surface and an opposite second surface, and at least two pads are arranged on the second surface of each of the second dies, wherein the at least two pads of each of the second dies are electrically connected to the at least two second pads by flip-chip technology, and each of the second dies is electrically connected to each of the first dies through the plurality of first via lines in the chip region; and step S6: a separation operation is performed to form a plurality of fan-out wafer level packaging units.
[0008] In a preferred embodiment of the present application, each of the first dies and each of the second dies is further separated from the same wafer.
[0009] In a preferred embodiment of the present application, each of the first dies and each of the second dies is further separated from different wafers.
[0010] In a preferred embodiment of the present application, the carrier plate comprises a silicon (Si) carrier plate, a glass carrier plate, or a ceramic carrier plate.
[0011] In a preferred embodiment of the present application, the metal paste constituting each of the first via lines comprises silver paste, nano-silver paste, copper paste, or nano-copper paste.
[0012] In a preferred embodiment of the present application, the metal paste constituting each of the second via lines comprises silver paste, nano-silver paste, copper paste, or nano-copper paste.
[0013] In a preferred embodiment of the present application, the first surface of each of the first dies is further arranged on the carrier plate by a die attach film (DAF).
[0014] In a preferred embodiment of the present application, each of the pads of each of the second dies is further electrically connected to the at least two pads through a solder ball.
[0015] In a preferred embodiment of the present application, each of the second recesses is further provided with a solder ball, and each of the solder balls is electrically connected to the plurality of pads in the plurality of second recesses.
[0016] In a preferred embodiment of the present application, the fan-out wafer level packaging unit is electrically connected to a printed circuit board (PCB) by each of the solder balls. BRIEF DESCRIPTION OF DRAWINGS
[0017] Figure 1 is a schematic plan view of a side cross-sectional view of an application embodiment of the fan-out wafer level packaging unit of the present application.
[0018] Figure 2 is a plan view of a side sectional view of a carrier plate of the present application.
[0019] Figure 3 is a plan view of a side sectional view of the carrier plate in Figure 2 with a first dielectric layer laid thereon.
[0020] Figure 4 is a plan view of a side sectional view of the carrier plate in Figure 3 with metal paste filled in each first recess.
[0021] Figure 5 is a plan view of a side sectional view of the carrier plate in Figure 4 with the metal paste above the surface of the first dielectric layer being polished.
[0022] Figure 6 is a plan view of a side sectional view of the carrier plate in Figure 5 with a second dielectric layer laid on the first dielectric layer.
[0023] Figure 7 is a plan view of a side sectional view of the carrier plate in Figure 6 with metal paste filled in each second recess.
[0024] Figure 8 is a plan view of a side sectional view of the carrier plate in Figure 7 with the metal paste above the surface of the second dielectric layer being polished.
[0025] Figure 9 is a plan view of a side sectional view of the carrier plate in Figure 8 with a second die in a flip chip technique disposed above the second dielectric layer.
[0026] Figure 10 is a plan view of a side sectional view of the carrier plate in Figure 9 with a solder ball disposed on each second recess.
[0027] BRIEF DESCRIPTION OF DRAWINGS 1 - fan-out wafer level package unit; 1a - chip region; 10 - carrier plate; 20 - first die; 21 - first surface; 22 - second surface; 23 - bump pad; 30 - first dielectric layer; 31 - first recess; 40 - first via line; 40a - metal paste; 50 - second dielectric layer; 51 - second recess; 60 - second via line; 60a - metal paste; 61 - first solder pad; 62 - second solder pad; 70 - chip adhesive film; 80 - second die; 81 - first surface; 82 - second surface; 83 - bump pad; 90 - solder ball; 2 - printed circuit board. DETAILED DESCRIPTION
[0028] With reference to the drawings, the configuration of the present application and its technical features are described in detail as follows, wherein each drawing is only used to illustrate the structural relationship and related functions of the present application, thus the size of each element in each drawing is not drawn according to the actual proportion and is not used to limit the present application.
[0029] With reference to the drawings, the configuration of the present application and its technical features are described in detail as follows, wherein each drawing is only used to illustrate the structural relationship and related functions of the present application, thus the size of each element in each drawing is not drawn according to the actual proportion and is not used to limit the present application. Figure 1 Figure 9 The present application provides a fan-out wafer level packaging unit 1, which comprises a carrier plate 10, at least one first die 20, a first dielectric layer 30, a plurality of first conductive lines 40, a second dielectric layer 50, a plurality of second conductive lines 60, a die attach film 70, and at least one second die 80, but is not limited thereto.
[0030] Each first die 20 is divided from a wafer, each first die 20 has a first surface 21 and an opposite second surface 22, the first surface 21 of each first die 20 is fixed on the carrier plate 10, the second surface 22 of each first die 20 has a plurality of die pads 23, and the vertical chip region of the second surface 22 is defined as a chip region la, as shown in Figure 2 ; wherein the first surface 21 of each first die 20 is further disposed on the carrier plate 10 by the die attach film (DAF) 70, but is not limited thereto, as shown in Figure 2 ; in Figure 2 , each die pad 23 of the first die 20 is exemplarily illustrated by four die pads 23, but is not used to limit the present application.
[0031] The first dielectric layer 30 is disposed on the carrier plate 10 and the second surface 22 of each first die 20, the first dielectric layer 30 has a plurality of first grooves 31 extending horizontally, as shown in Figure 3 ; wherein each die pad 23 of each first die 20 is exposed outwardly by each first groove 31, as shown in Figure 3 .
[0032] Each first conductive line 40 is composed of a metal paste 40a filled in each first groove 31, each first conductive line 40 is electrically connected with each die pad 23 of each first die 20, as shown in Figure 5 .
[0033] The second dielectric layer 50 is disposed on the first dielectric layer 30, the second dielectric layer 50 has a plurality of second grooves 51 extending horizontally, each second groove 51 is in communication with each first groove 31, as shown in Figure 6 .
[0034] Each second conductive line 60 is formed by filling the second groove 51 with metal paste 60a. Each second conductive line 60 is electrically connected to each first conductive line 40, such as... Figure 8 As shown; wherein the bonding pads formed in the second grooves 51 surrounding the chip region 1a on the second surface 22 of each first bare die 20 are first bonding pads 61, and each first bonding pad 61 is electrically connected to each first conductive line 40 surrounding the chip region 1a, such as Figure 9 As shown; wherein the bonding pads formed in the second grooves 51 within the chip region 1a on the second surface 22 of each first bare die 20 are second bonding pads 62, and each second bonding pad 62 is electrically connected to each first conductive line 40 within the chip region 1a, such as Figure 9 As shown.
[0035] Each second die 80 is cleaved from a wafer. Each second die 80 has a first surface 81 and an opposing second surface 82. The second surface 82 of each second die 80 has at least two die pads 83. Figure 9 As shown; at least two of the die pads 83 of each second bare die 80 are electrically connected on at least two second bonding pads 62 using flip-chip technology, so that each second bare die 80 is located above the second dielectric layer 70, and each second bare die 80 can be electrically connected to each first bare die 20 via each first conductive line 40 located within the chip region 1a, such as Figure 9 As shown. In Figure 9 The second bare crystal 80 is illustrated using two crystal pads 83 as an example, but is not intended to limit the invention.
[0036] Each first bare die 20 can be electrically connected to the external circuit via each die pad 23 of each first bare die 20, each first conductive line 40 around the chip region 1a, each second conductive line 60, and each first bonding pad 61 located on the second surface 22 of each first bare die 20 around the chip region 1a, thereby forming the fan-out wafer-level package unit 1, such as Figure 9 As shown.
[0037] The manufacturing method of the fan-out wafer-level packaging unit 1 includes the following steps:
[0038] Step S1: Provide a carrier board 10, such as Figure 2 As shown.
[0039] Step S2: A plurality of first dies 20, diced from at least one wafer, are spaced apart and disposed on the carrier plate 10, such as... Figure 2As shown in FIG. 1, the first die 20 has a first surface 21 and an opposite second surface 22. The first surface 21 of each first die 20 is disposed on the carrier plate 10. The second surface 22 of each first die 20 has a plurality of die pads 23. The vertical chip region of the second surface 22 defines a chip region la, as shown in FIG. 1. Figure 2 As shown in FIG. 1.
[0040] In step S3, a plurality of first conductive lines 40 are formed on the second surface 22 of each first die 20 by using a technique of filling metal paste into a groove and then grinding. First, a first dielectric layer 30 is disposed on the carrier plate 10 and the second surface 22 of each first die 20. Then, a plurality of first grooves 31 are horizontally formed on the first dielectric layer 30, and each die pad 23 of each first die 20 is exposed outside through each first groove 31, as shown in FIG. 2. Then, metal paste 40a is filled into each first groove 31, and the thickness of the metal paste 40a is higher than the surface of the first dielectric layer 30, as shown in FIG. 3. Finally, the metal paste 40a higher than the surface of the first dielectric layer 30 is ground, so that the surface of the metal paste 40a is flush with the surface of the first dielectric layer 30, thereby forming the plurality of first conductive lines 40, as shown in FIG. 4. Figure 3 Figure 4 Figure 5
[0041] In step S4, a plurality of second conductive lines 60 are formed on the first dielectric layer 30 by using a technique of filling metal paste into a groove and then grinding. First, a second dielectric layer 50 is disposed on the first dielectric layer 30. Then, a plurality of second grooves 51 are horizontally formed on the second dielectric layer 50, and each second groove 51 is in communication with each first groove 31, as shown in FIG. 5. Then, metal paste 60a is filled into each second groove 51, and the thickness of the metal paste 60a is higher than the surface of the second dielectric layer 50, as shown in FIG. 6. Finally, the metal paste 60a higher than the surface of the second dielectric layer 50 is ground, so that the surface of the metal paste 60a is flush with the surface of the second dielectric layer 50, thereby forming the plurality of second conductive lines 60, as shown in FIG. 7. Figure 6 Figure 7 Figure 8 Figure 8 Figure 9 The soldering pads formed in the second grooves 51 within the range of the chip region 1a on the second surface 22 of each first die 20 are second soldering pads 62, and each second soldering pad 62 is electrically connected with each first conducting line 40 within the range of the chip region 1a, as shown in Figure 9
[0042] Step S5: The second dies 80 separated from the wafer are arranged above the second dielectric layer 70 by flip-chip technology, as shown in Figure 9 Figure 9 Figure 9
[0043] Step S6: The separation operation is performed to separate a plurality of fan-out wafer level packaging units 1, as shown in Figure 9
[0044] The steps S3-S4 in the manufacturing method of the fan-out wafer level packaging unit 1 are the key steps for manufacturing the redistribution layer (RDL) of the fan-out wafer level packaging unit 1. In step S3, the first conducting lines 40 are formed on the second surface 22 of each first die 20 by the technology of filling the metal paste into the grooves and then grinding the conducting lines. In step S4, the second conducting lines 60 are formed on the second dielectric layer 50 and the first conducting lines 40 by the technology of filling the metal paste into the grooves and then grinding the conducting lines. Since steps S3-S4 are easy to implement precisely, the manufacturing process is simplified, and the first conducting lines 40 and the second conducting lines 60 in the redistribution layer can be extended and interconnected in the XY plane, and the fan-out wafer level packaging unit 1 can still be thin and small.
[0045] Reference Figure 9 The first dies 20 and the second dies 80 are separated from the same wafer, but the specifications of the dies are not limited to be the same, which is beneficial to the performance of the stacked operation.
[0046] Reference Figure 9 The first and second dies 20 and 80 are further formed by cutting from different wafers, but the application is not limited thereto. The first and second dies 20 and 80 have different specifications, which is beneficial to increase the diversified applications of products.
[0047] Referring to Figure 2 The carrier plate 10 includes a silicon (Si) carrier plate, a glass carrier plate or a ceramic carrier plate, but the application is not limited thereto. The carrier plate 10 is beneficial to increase the diversified applications of products.
[0048] Referring to Figure 5 The metal paste 40a forming the first conductive lines 40 includes silver paste, nano-silver paste, copper paste or nano-copper paste, but the application is not limited thereto. The nano-silver paste has the characteristics of low cost, high conductivity and low-temperature sintering, but the nano-silver paste is a common material, and thus will not be described herein.
[0049] Referring to Figure 8 The metal paste 60a forming the second conductive lines 60 includes silver paste, nano-silver paste, copper paste or nano-copper paste, but the application is not limited thereto.
[0050] Referring to Figure 9 The pads 83 of the second dies 80 are further electrically connected to the solder pads 61 through the solder balls 90, but the application is not limited thereto.
[0051] Referring to Figure 10 The second recesses 51 are further provided with the solder balls 90, but the application is not limited thereto. The solder balls 90 can be electrically connected to the solder pads 61 in the second recesses 51.
[0052] Referring to Figure 1 The fan-out wafer level packaging unit 1 can be electrically connected to the printed circuit board (PCB) 2 through the solder balls 90, but the application is not limited thereto.
[0053] Compared with the prior art, the fan-out wafer level packaging unit 1 has the following advantages:
[0054] (1) The steps S3 and S4 in the manufacturing method of the fan-out wafer level packaging unit 1 are simple and easy to implement. In particular, the thickness of the packaging unit is reduced, and thus the process is simplified, the cost is saved, and the use efficiency and reliability of the fan-out wafer level packaging unit 1 are improved.
[0055] (2) The plurality of the first conductive lines 40 of the present application are formed on the second surface 22 of each first die 20 by a technique of filling metal paste into a groove and then grinding the conductive lines, so that the present application can effectively solve the problem of high manufacturing cost and environmental unfriendliness in the prior art fan-out package technology.
[0056] (3) The plurality of the second conductive lines 60 of the present application are formed on the second dielectric layer 50 and the plurality of the first conductive lines 40 by a technique of filling metal paste into a groove and then grinding the conductive lines, so that the present application can effectively solve the problem of high manufacturing cost and environmental unfriendliness in the prior art fan-out package technology.
[0057] (4) At least two of the pads 83 of each second die 80 of the present application are electrically connected to at least two of the second solder pads 62 by flip-chip technology, so that each second die 80 is located above the second dielectric layer 70 and can be electrically connected to each first die 20 through each first conductive line 40 located within the chip region la, as shown in FIG. 1, to increase the number of die combination modes of the product and improve the market competitiveness of the product. Figure 9
[0058] The above is only the preferred embodiment of the present application, which is only illustrative but not restrictive; those skilled in the art understand that many changes, modifications and even equivalent changes can be made to the present application within the spirit and scope defined by the claims of the present application, but all will fall within the protection scope of the present application.
Claims
1. A fan-out wafer level package unit, characterized by, Comprising: a carrier plate; at least one first die, each of the first die is singulated from a wafer, each of the first die has a first surface and an opposite second surface, the first surface of each of the first die is fixed on the carrier plate, the second surface of each of the first die has a plurality of die pads, and a vertical chip region of the second surface is defined as a chip region; a first dielectric layer disposed on the carrier plate and the second surface of each of the first die, the first dielectric layer has a plurality of first grooves formed horizontally; wherein each of the die pads of each of the first die is exposed outside by a plurality of the first grooves; a plurality of first conductive lines, each of the first conductive lines is composed of metal paste filled in a plurality of the first grooves, each of the first conductive lines is electrically connected with a plurality of the die pads of each of the first die; a second dielectric layer disposed on the first dielectric layer, the second dielectric layer has a plurality of second grooves formed horizontally, each of the second grooves is communicated with each of the first grooves; a plurality of second conductive lines, each of the second conductive lines is composed of metal paste filled in a plurality of the second grooves, each of the second conductive lines is electrically connected with each of the first conductive lines; wherein each of the second grooves exposes a plurality of the second conductive lines outside to form a solder pad in the plurality of the second grooves; wherein the solder pads formed in a plurality of the second grooves around the chip region on the second surface of each of the first die are first solder pads, and each of the first solder pads is electrically connected with a plurality of the first conductive lines around the chip region; wherein the solder pads formed in a plurality of the second grooves within the range of the chip region on the second surface of each of the first die are second solder pads, and each of the second solder pads is electrically connected with a plurality of the first conductive lines within the range of the chip region; and at least one second die, each of the first die is singulated from a wafer, each of the second die has a first surface and an opposite second surface, the second surface of each of the second die has at least two die pads; wherein at least two of the die pads of each of the second die are electrically connected on at least two of the second solder pads by flip-chip technology, so that each of the second die is located above the second dielectric layer, and each of the second die can be electrically connected with each of the first die through a plurality of the first conductive lines within the range of the chip region; wherein each of the first die can be electrically connected outside in sequence through a plurality of the die pads of each of the first die, a plurality of the first conductive lines around the chip region, a plurality of the second conductive lines, and a plurality of the first solder pads around the chip region on the second surface of each of the first die, thereby forming the fan-out wafer level package unit; wherein the manufacturing method of the fan-out wafer level package unit comprises the following steps: Step S1: providing a carrier plate; Step S2: The first dies separated from at least one wafer are arranged on the carrier board; each of the first dies has a first surface and an opposite second surface; the first surface of each of the first dies is arranged on the carrier board; the second surface of each of the first dies has a plurality of pads; and a vertical chip region of the second surface is defined as a chip region; Step S3: A plurality of first conductive lines are formed on the second surface of each of the first dies by a technique of filling metal paste into grooves and then polishing: a first dielectric layer is first arranged on the carrier board and the second surface of each of the first dies; a plurality of first grooves are then horizontally formed on the first dielectric layer, and each of the pads of each of the first dies is exposed outside by the plurality of first grooves; metal paste is then filled into each of the first grooves, and the thickness of the metal paste is higher than the surface of the first dielectric layer; and finally, the metal paste higher than the surface of the first dielectric layer is polished, so that the surface of the metal paste is flush with the surface of the first dielectric layer to form the plurality of first conductive lines; Step S4: A plurality of second conductive lines are formed on the first dielectric layer by a technique of filling metal paste into grooves and then polishing: a second dielectric layer is first arranged on the first dielectric layer; a plurality of second grooves are then horizontally formed on the second dielectric layer, and each of the second grooves is in communication with each of the first grooves; metal paste is then filled into each of the second grooves, and the thickness of the metal paste is higher than the surface of the second dielectric layer; and finally, the metal paste higher than the surface of the second dielectric layer is polished, so that the surface of the metal paste is flush with the surface of the second dielectric layer to form the plurality of second conductive lines; each of the second grooves is for exposing each of the second conductive lines outside to form a pad in each of the second grooves; the pads in the plurality of second grooves around the chip region on the second surface of each of the first dies are first pads, and each of the first pads is electrically connected to the plurality of first conductive lines around the chip region; the pads in the plurality of second grooves within the range of the chip region on the second surface of each of the first dies are second pads, and each of the second pads is electrically connected to the plurality of first conductive lines within the range of the chip region; Step S5: A plurality of second dies separated from at least one wafer are arranged above the second dielectric layer by flip-chip technology; each of the second dies has a first surface and an opposite second surface; and each of the second dies has at least two pads on the second surface by flip-chip technology; the at least two pads of each of the second dies are electrically connected to the at least two second pads, and each of the second dies is electrically connected to each of the first dies through the plurality of first conductive lines within the range of the chip region; and Step S6: A separation operation is performed to separate a plurality of fan-out wafer level package units.
2. The fan-out wafer level package unit of claim 1, wherein, Each of the first dies and each of the second dies is formed by singulation from the same wafer.
3. The fan-out wafer level packaging unit of claim 1, wherein, Each of the first dies and each of the second dies is formed by singulation from different wafers.
4. The fan-out wafer level packaging unit of claim 1, wherein, The carrier board comprises a silicon carrier board, a glass carrier board, or a ceramic carrier board.
5. The fan-out wafer level packaging unit of claim 1, wherein, The metal paste constituting each of the first conductive lines comprises silver paste, nano-silver paste, copper paste, or nano-copper paste.
6. The fan-out wafer level packaging unit of claim 1, wherein, The metal paste constituting each of the second conductive lines comprises silver paste, nano-silver paste, copper paste, or nano-copper paste.
7. The fan-out wafer level packaging unit of claim 1, wherein, The first surface of each of the first dies is disposed on the carrier board by a die attach film.
8. The fan-out wafer level package unit of claim 1, wherein, The plurality of the pads of each of the second dies are electrically connected to the at least two of the pads by a solder ball.
9. The fan-out wafer level package unit of claim 1, wherein, Each of the second recesses is provided with a solder ball, and each of the solder balls is capable of being electrically connected to the plurality of the pads in the plurality of the second recesses.
10. The fan-out wafer level packaging unit of claim 9, wherein, The fan-out wafer level package unit is capable of being disposed on a printed circuit board by the plurality of the solder balls in an electrically connected manner.