Method for inhibiting stripping of film layer on inner wall of cavity and semiconductor process equipment
By pre-depositing a stress buffer layer on the inner wall of the process chamber, the problem of easy peeling of silicon nitride films was solved, achieving a stable film formation rate and high yield, extending the equipment maintenance cycle, and improving production efficiency and chamber life.
Patent Information
- Application Number
- CN202511307991.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-12
- Publication Date
- 2026-01-23
AI Technical Summary
In existing technologies, silicon nitride films are easily peeled off from the inner wall of quartz chambers, leading to particle contamination and damage to the chamber surface, which affects product yield and equipment lifespan.
A stress buffer layer is pre-deposited on the inner wall of the process chamber, using SiO2, SiON, SiCO or PSG as components to form a composite film with the silicon nitride film. Through physical and chemical bonding, the stress of the silicon nitride film is buffered, and its peeling is inhibited.
It effectively reduces the number of particles in the chamber, extends the equipment maintenance cycle, improves product yield and production efficiency, prolongs the chamber life, and optimizes film thickness uniformity and film formation rate.
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Figure CN121380901A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, in particular to a method for inhibiting peeling of a film layer on an inner wall of a chamber and a semiconductor process equipment. BACKGROUND
[0002] With the development of the times, emerging technologies such as 5G technology, artificial intelligence, cloud computing and Internet of Vehicles are emerging in an endless stream. The development of these fields cannot be separated from chips. With the development of these emerging fields, not only the demand for chips increases, but also the performance requirements for chips are becoming higher and higher, such as low power consumption, high refresh rate, etc. As an indispensable device for semiconductor process, the process stability, particle level and film thickness uniformity of the chemical vapor deposition equipment are key factors affecting product yield, and low product yield will cause huge economic losses.
[0003] In the related art, a layer of silicon nitride film is pre-deposited on the inner surface of the quartz chamber before the process. The pre-deposited layer can improve the surface properties of the chamber and to some extent can play a role in covering and blocking foreign matter, thereby ensuring the repeatability of the subsequent process. However, the silicon nitride film has high hardness and stress and poor adhesion, and is prone to peeling into particles after being covered on the quartz surface for 0.5 um, resulting in serious particle pollution in the chamber environment, and the stress generated during the peeling of the silicon nitride film will pull the quartz surface, causing cracks and roughness deterioration on the quartz surface, and thus leading to poor film thickness uniformity and film formation rate, affecting product yield. SUMMARY
[0004] The present application aims to provide a method for inhibiting peeling of a film layer on an inner wall of a chamber and a semiconductor process equipment to alleviate the technical problem of easy peeling of the silicon nitride layer pre-deposited on the inner wall of the chamber in the related art.
[0005] The method for inhibiting peeling of a film layer on an inner wall of a chamber provided by the present application comprises:
[0006] A first pre-deposition step of pre-depositing a stress buffer layer on the inner wall of the process chamber, the stress buffer layer being composed of SiO2, SiON, SiCO or PSG;
[0007] A second pre-deposition step of pre-depositing a silicon nitride film layer on the inner wall of the process chamber.
[0008] Preferably, as an implementable manner, in the first pre-deposition step,
[0009] The process gas comprises DCS and N2O;
[0010] Alternatively, the process gas comprises TEOS, and further comprises any one of O3 and O2;
[0011] Or, the process gas includes SiH4, and further includes any one of N2O and O2.
[0012] Or, the process gas includes SiCl4and O2.
[0013] Preferably, as an implementable manner, in the first pre-deposition step, the flow rate of DCS is 100-500sccm, and the flow rate of N2O is 1000-5000sccm.
[0014] And / or, in the first pre-deposition step, the process temperature is 750-800℃, and the process pressure is 0.2-2Torr.
[0015] Preferably, as an implementable manner, in the second pre-deposition step, the process gas includes NH3, and further includes any one of DCS, SiH4and BTBAS.
[0016] Preferably, as an implementable manner, in the second pre-deposition step, the flow rate ratio of NH3to DCS is greater than 5.
[0017] And / or, in the second pre-deposition step, the process temperature is 750-800℃, and the process pressure is 0.2-2Torr.
[0018] Preferably, as an implementable manner, after the second pre-deposition step, the method further includes:
[0019] A process step, sequentially performing corresponding process treatment on multiple batches of wafers until the core process parameter of the wafer continuously deteriorates;
[0020] A covering step, sequentially performing the first pre-deposition step and the second pre-deposition step;
[0021] Wherein, the process step and the covering step are cyclically executed until the core process parameter of the wafer cannot be restored to the ideal range.
[0022] Preferably, as an implementable manner, the core process parameter includes the uniformity, refractive index and deposition rate of the thin film formed on the wafer surface by the process step.
[0023] Preferably, as an implementable manner, the method further includes:
[0024] Obtaining the number of particles in the process chamber;
[0025] If the rising speed of the number of particles in the process chamber exceeds a threshold value, emergency shutdown.
[0026] Preferably, as an implementable manner, between the first pre-deposition step and the second pre-deposition step, the method further includes:
[0027] The process chamber is vacuumed, inert gas is introduced into the process chamber for purging, and the process chamber is vacuumed again.
[0028] The semiconductor process equipment provided by the application comprises a process chamber, a gas inlet assembly and a controller, the controller comprises at least one processor and at least one memory, the memory stores a computer program, and the computer program is executed by the processor to realize the method for inhibiting the peeling of the film layer on the inner wall of the chamber.
[0029] Compared with the prior art, the application has the following beneficial effects:
[0030] In the application, a stress buffer layer is added between the inner wall of the process chamber and the silicon nitride film layer, and the stress buffer layer and the silicon nitride film layer can form a composite film layer attached to the inner wall of the process chamber. After the process of pre-deposition film layer on the inner wall of the process chamber is completed, the wafer can be transmitted into the process chamber for processing to form a thin film on the wafer surface, and the silicon nitride film layer attached to the inner wall of the process chamber can serve as the surface contacted by the process.
[0031] SiO2, SiON, SiCO and PSG (phosphor-silicon glass) are selected as the components of the stress buffer layer, so that the stress buffer layer has the characteristics of loose and soft film quality, good adhesion and small stress, thereby the stress buffer layer can buffer the stress of the silicon nitride film layer and optimize the cumulative stress of the pre-deposition film layer. Meanwhile, the stress buffer layer and the silicon nitride film layer are physically covered and chemically bonded, the chemical bonding can realize the firm combination of the stress buffer layer and the silicon nitride film layer, and the two can synergistically inhibit the cracking and peeling of the pre-deposition film layer, thereby the number of particles in the process chamber can be reduced, and the inner wall of the chamber is not easy to crack due to being pulled by the pre-deposition film layer. In addition, the physical properties of the stress buffer layer not only protect the inner wall of the process chamber and prolong the service life of the chamber, but also cover the inner wall of the chamber to planarize the surface of the inner wall of the chamber, thereby improving the roughness of the inner wall of the chamber and repairing the surface damage of the inner wall of the chamber. In summary, the method provided by the application can optimize the film thickness uniformity of the thin film on the wafer surface and obtain a stable film forming rate, and the product yield is high.
[0032] In addition, since the pre-deposition film layer attached to the inner wall of the chamber is not easy to crack and fall off, the number of processes for processing the wafer before the pre-deposition film layer reaches the cracking state can be increased, thereby the equipment maintenance period can be prolonged, the operation and maintenance cost can be reduced, and the production efficiency can be improved. BRIEF DESCRIPTION OF DRAWINGS
[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed in the embodiments or prior art description. Obviously, the drawings described below are only a part of the embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor on the basis of the provided drawings.
[0034] Figure 1 The schematic flow chart of the method for inhibiting the peeling of the film layer on the inner wall of the chamber provided by the embodiments of the present application is shown in the figure.
[0035] Figure 2 The process flow chart of the method for inhibiting the peeling of the film layer on the inner wall of the chamber provided by the embodiments of the present application is shown in the figure.
[0036] Figures 3a-3g The film layer change schematic diagram of the inner wall surface of the process chamber in the embodiments of the present application is shown in the figure.
[0037] Figure 4 The structural schematic diagram of the semiconductor process equipment provided by the embodiments of the present application is shown in the figure. DETAILED DESCRIPTION
[0038] The vertical furnace is an indispensable equipment in the semiconductor process, which is mainly divided into two categories: the normal pressure tube and the low pressure tube. The normal pressure tube mainly performs the processes of oxidation, annealing, alloying, etc. The low pressure tube mainly performs the deposition of SIO, SIN, Poly, etc. film layer in the process mode of LPCVD (low pressure chemical vapor deposition). The process chamber of the low pressure tube mainly adopts the double-layer nested structure of the inner tube and the outer tube. The inner tube is used to constrain the process gas to react, so as to deposit the film layer on the surface of the wafer placed on the inner crystal boat. The by-product and residual gas flow through the gap between the inner tube and the outer tube, and is pumped away by the exhaust pipeline through the vacuum pump. The deposition process of hundreds of wafers can be completed at one time.
[0039] The low pressure chemical vapor deposition silicon nitride equipment is often used to deposit the Pad Nitride (pad layer silicon nitride), Spacer Nitride (spacer silicon nitride), Hardmask (hard mask) and the like in semiconductor devices, which can prepare the silicon nitride film layer with good mechanical properties, high density and good isolation performance. However, due to the hardness and stress of the silicon nitride film layer, peeling occurs easily, which affects the product yield and increases the chip cost.
[0040] The technical solutions of the present application will be described clearly and completely in combination with the drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.
[0041] The application will be further described in detail below with reference to specific examples and in conjunction with the accompanying drawings.
[0042] Figure 1 A schematic flow chart of the method for inhibiting the peeling of the film layer on the inner wall of the chamber is provided for an embodiment of the application, and the method comprises:
[0043] S102, a first pre-deposition step, pre-depositing a stress buffer layer on the inner wall of the process chamber, the stress buffer layer being composed of SiO2, SiON, SiCO or PSG;
[0044] S104, a second pre-deposition step, pre-depositing a silicon nitride film layer on the inner wall of the process chamber.
[0045] In this embodiment, a stress buffer layer is added between the inner wall of the process chamber and the silicon nitride film layer, and the stress buffer layer and the silicon nitride film layer can form a composite film layer attached to the inner wall of the process chamber. After the process of pre-depositing the film layer on the inner wall of the process chamber is completed, the wafer can be transferred into the process chamber for processing to form a thin film on the wafer surface, and the silicon nitride film layer attached to the inner wall of the process chamber can serve as the surface contacted by the process.
[0046] SiO2, SiON, SiCO and PSG (phosphor-silicon glass) are selected as the components of the stress buffer layer, so that the stress buffer layer has the characteristics of loose and soft film quality, good adhesion and small stress, thereby the stress buffer layer can buffer the stress of the silicon nitride film layer and optimize the cumulative stress of the pre-deposited film layer. At the same time, the stress buffer layer and the silicon nitride film layer are not only physically overlapped but also chemically bonded, and the chemical bonding can achieve firm combination of the stress buffer layer and the silicon nitride film layer, and the two can work together to well inhibit the cracking and peeling of the pre-deposited film layer, thereby reducing the number of particles in the process chamber and preventing the inner wall of the chamber from being cracked due to being pulled by the pre-deposited film layer. In addition, the physical properties of the stress buffer layer not only protect the inner wall of the process chamber and prolong the service life of the chamber, but also flatten the surface of the inner wall of the chamber when covering the inner wall of the chamber, thereby improving the roughness of the inner wall of the chamber and repairing the surface damage of the inner wall of the chamber. In summary, the method provided in this embodiment can optimize the film thickness uniformity of the thin film on the wafer surface and obtain a stable film formation rate, thereby achieving a high product yield.
[0047] In addition, since the pre-deposited film layer attached to the inner wall of the chamber is not easy to crack and peel off, the number of processes for processing the wafer before the pre-deposited film layer reaches the cracking state can be increased, thereby prolonging the equipment maintenance period, reducing the operation and maintenance cost, and improving the production efficiency.
[0048] In step S102, any of the following gas combinations can be used as the process gas: 1) DCS (dichlorosilane) and N2O, 2) TEOS (tetraethyl orthosilicate) and any of O3 and O2, 3) SiH4 and any of N2O and O2, and 4) SiCl4 and O2. Any of the above gas combinations can form the stress buffer layer with SiO2 composition on the inner wall surface of the process chamber.
[0049] The first gas combination is preferably used as the process gas for pre-depositing the stress buffer layer with SiO2 composition, which has lower temperature and cost requirements compared to the second gas combination, and is safer and less likely to generate particles compared to the third and fourth gas combinations.
[0050] As an alternative, in step S102, any of SiH4 and DCS and N2O and NH3 can be used as the process gas, which can pre-deposit a SiON film layer on the inner wall of the process chamber. As another alternative, in step S102, an organosilicon source (e.g., TMCTS) and O2 can be used as the process gas, which can pre-deposit a SiCO film layer on the inner wall of the process chamber. As yet another alternative, in step S102, any of SiH4 and TEOS and O2 and PH3 can be used as the process gas, which can pre-deposit a PSG film layer on the inner wall of the process chamber.
[0051] Further, in step S102, the flow rate of DCS is set to 100-500 sccm, the flow rate of N2O is set to 1000-5000 sccm, the process temperature is set to 750-800 °C, and the process pressure is set to 0.2-2 Torr, which can successfully form the stress buffer layer with SiO2 composition on the inner wall surface of the process chamber. Specifically, the deposition time can be determined according to the target thickness of the stress buffer layer (e.g., 200 nm), which can be determined through preliminary process tests.
[0052] In step S104, NH3 and any of DCS, SiH4 and BTBAS can be used as the process gas, which can form a silicon nitride film layer on the inner wall surface of the process chamber.
[0053] NH3 and DCS are preferably used as the process gas for pre-depositing the silicon nitride film layer, which is safer and less likely to generate particles, has lower cost, and has a faster deposition rate compared to other gas combination schemes.
[0054] Further, in step S104, the flow ratio of NH3 to DCS is set to be greater than 5 to ensure the nitriding atmosphere and reduce the plugging of the pipeline by the by-product ammonium chloride (NH4Cl).
[0055] In step S104, the process temperature can be set to 750-800°C and the process pressure can be set to 0.2-2 Torr. Under such process conditions, the silicon nitride film layer can be formed smoothly on the inner wall surface of the process chamber. Specifically, the deposition time can be determined according to the target thickness of the silicon nitride film layer. The thickness of the silicon nitride film layer as a surface in contact with the subsequent process needs to be able to guarantee the repeatability of the process. For example, the thickness of the silicon nitride film layer can be set to about 200 nm.
[0056] The target thickness of the stress buffer layer can be determined by preliminary process tests.
[0057] After step S104, the method provided by the embodiment further includes the following steps:
[0058] The process step is to sequentially perform corresponding process treatment on multiple batches of wafers until the core process parameter exceeds the safe range.
[0059] The covering step is to sequentially perform the first pre-deposition step and the second pre-deposition step.
[0060] The above process step and the above covering step are cyclically performed until the core process parameter cannot be restored to the safe range.
[0061] In the process step, a batch of wafers can be first transferred into the process chamber for processing, and after the processing is completed, the batch of wafers is transferred out of the process chamber; then, the next batch of wafers is transferred into the process chamber for processing, and after the processing is completed, the batch of wafers is transferred out of the process chamber, and so on, to sequentially process multiple batches of wafers. When a certain number of processes are reached, the silicon nitride film layer covering the inner wall of the process chamber will gradually approach a cracking state, at which time the core process parameters of the wafers will continue to deteriorate; in order to avoid cracking and peeling of the silicon nitride film layer, the above steps S102 and S104 can be sequentially executed when the core process parameters of the wafers continue to deteriorate, and a new composite film layer (including a stress buffer layer and a silicon nitride film layer deposited in turn from the inside out) is pre-deposited on the surface of the original composite film layer on the inner wall of the process chamber. The new silicon oxide layer can penetrate into the microcracks of the old silicon nitride film layer, achieve "in-situ repair", and serve as a brand new stress buffer layer to prepare for the deposition of the silicon nitride film layer; after the pre-deposition repair of the composite film layer is completed, the wafer can continue to be processed until the core process parameters of the wafer continue to deteriorate again, and then the composite film layer is repaired by pre-depositing a new composite film layer on the surface of the original composite film layer on the inner wall of the process chamber. If the core process parameters of the wafer cannot be restored to the ideal range after repair, it indicates that the composite film layer on the surface of the inner wall of the chamber cannot improve the cracking or film peeling problem through repair, at which time the process operation is stopped. In this way, the layer-by-layer superimposed and periodic repair method can further prolong the equipment maintenance period, reduce operation and maintenance costs, and improve work efficiency.
[0062] Specifically, the above-mentioned core process parameters can include the uniformity, refractive index, and deposition rate of the thin film formed on the wafer surface by the process step, which can well reflect the environmental quality in the process chamber. The closer the silicon nitride film layer on the inner wall of the process chamber approaches the cracking state, the worse these parameters will be. When the core process parameters show a persistent and irreversible deterioration trend, but have not yet caused the product yield to exceed the standard, it can be determined that the silicon nitride film layer covering the inner wall of the process chamber will soon reach the cracking state, at which time it is the best time to perform the pretreatment. The ideal range of the core process parameters of the wafer can be determined according to actual needs. After the composite film layer on the surface of the inner wall of the chamber cannot improve the cracking or film peeling problem through repair, the process chamber can be maintained, and specifically, the quartz piece can be replaced, which is equivalent to a "hardware reset" of the equipment.
[0063] It should be noted that by early warning and periodic pretreatment, intervention is carried out before the peeling of the silicon nitride film layer occurs, thereby fundamentally avoiding the occurrence of large-area peeling, so that the large-size film layer fragments caused by peeling can be avoided from directly falling on the wafer to cause scratches, pattern damage or become killer particles, resulting in the entire batch of wafers being scrapped; at the same time, the peeling can be avoided from falling on the heater or the air flow channel to damage the uniformity of the thermal field and block the exhaust pipeline.
[0064] Specifically, in the above process step, the silicon nitride film layer can be deposited on the wafer surface, and under this condition, when the second pre-deposition step is performed, a reaction environment consistent with subsequent wafer deposition can be provided, and the repeatability of the process can be ensured.
[0065] The method provided by the embodiment can further include the following steps: acquiring the number of particles in the process chamber; if the rising speed of the number of particles in the process chamber exceeds a threshold value, performing emergency shutdown to reduce losses. After the emergency shutdown, the replacement of the quartz piece can be immediately arranged.
[0066] If the silicon nitride film layer peels off, a thorough manual cleaning is performed on all areas where fragments may fall, such as the interior of the furnace body, the heater, the base, etc., for example, a high-purity dust-free cloth can be used to wipe with a solvent (such as IPA), and a vacuum cleaner can be used to suck the particles; the gas pipeline and the vacuum pump pipeline are checked and cleaned to prevent the fallen fragments from blocking the system.
[0067] Between the steps S102 and S104, the method provided by the embodiment can further include: pumping down the process chamber to remove residual reaction byproducts and gas contaminants in the process chamber to create an absolutely necessary prerequisite for subsequent formation of a well-bonded film layer: ① removing pollution sources (such as residual gas, water vapor, etc.); ② creating a pure reaction environment; ③ ensuring the purity (i.e., proportion) of the gas composition.
[0068] After completing the step of pumping down the process chamber, most of the residual reaction byproducts and gas contaminants in the process chamber can be removed, and after that, inert gas can be introduced into the process chamber for purging to "blow" out the residual gas that is difficult to pump out from the dead angle in the process chamber; then, the process chamber is pumped down again to remove the residual reaction byproducts and gas contaminants to improve the cleanliness of the process chamber. PURGE and PUMP DOWN can be performed in a cycle to ensure thorough cleaning and ensure good bonding between the film layers.
[0069] Participation Figure 2As shown, one embodiment of the present application provides a method for inhibiting the peeling of the inner wall film layer in the chamber, which comprises:
[0070] Step 1, providing a process chamber (such as a quartz chamber) as the substrate 11; at this time, the cross section of the inner wall of the process chamber is as shown in Figure 3a
[0071] Step 2, introducing DCS and N2O into the process chamber to pre-deposit a layer of silicon oxide film 12 (Coating SIO) on the inner wall surface of the process chamber; after this step is completed, the cross section of the inner wall of the process chamber is as shown in Figure 3b
[0072] Step 3, pumping down the process chamber;
[0073] Step 4, introducing DCS and NH3 into the process chamber to deposit a dense layer of silicon nitride film 13 (Coating SIN) on the silicon oxide film 12; after this step is completed, the cross section of the inner wall of the process chamber is as shown in Figure 3c
[0074] Step 5, introducing process gas (such as DCS and NH3) into the process chamber to deposit a silicon nitride film on the wafer (Process SIN); during this step, the silicon nitride film layer 14 will be accumulated on the inner wall of the chamber, increasing the thickness and stress of the silicon nitride film layer, but at the same time, the stress of the silicon nitride film layer on the inner wall of the chamber is continuously accumulated, and micro-cracks begin to incubate; after this step is completed, the cross section of the inner wall of the process chamber is as shown in Figure 3d
[0075] Step 5, before the core process parameters of the wafer are monitored to deteriorate (such as uniformity deterioration), but before large-area peeling occurs, silicon oxide deposition (Coating SIO) is performed again; after this step is completed, the cross section of the inner wall of the process chamber is as shown in Figure 3e
[0076] Step 6, depositing a brand new layer of silicon nitride film 13 (Coating SIN) again; after this step is completed, a perfect and stable process surface can be re-established, and the cross section of the inner wall of the process chamber is as shown in Figure 3f
[0077] Step 7, repeating steps 4-6, the film layer structure of the inner wall of the chamber becomes thicker and thicker, showing a multi-layer structure; at this time, the cross section of the inner wall of the process chamber is as shown in Figure 3g
[0078] Step 8, when the multi-layer structure is too thick, the uniformity, refractive index, deposition rate of the film on the wafer surface cannot be restored to the ideal state, that is, the film layer peeling risk is extremely high, at this time, stop maintenance and replace the entire quartz piece.
[0079] Figure 4 A semiconductor process equipment is provided for an embodiment of the present application, which comprises a process chamber 21, a gas inlet assembly and a controller (not shown in FIG. 3). The controller comprises at least one processor and at least one memory, and the memory stores a computer program which is executed by the processor to implement the method of any of the above embodiments.
[0080] Exemplarily, the controller can be an upper computer or a lower computer. The controller can control the opening of the valve of the gas inlet assembly to introduce the corresponding process gas into the interior of the process chamber 21, and can control the opening degree of the valve of the gas inlet assembly to control the flow of the process gas. The controller can also control the gas pressure in the interior of the process chamber 21 by controlling the exhaust assembly to exhaust the interior of the process chamber 21, and can also exhaust the reaction by-products.
[0081] The gas inlet assembly can comprise a plurality of gas inlet pipes 22, and each gas inlet pipe 22 is used to introduce different process gas. For example, the gas inlet pipe 22 can have three, which are used to introduce DCS, N2O and NH3 respectively. The exhaust assembly can comprise an exhaust port 23.
[0082] The semiconductor process equipment provided by the embodiment can further comprise a furnace body 24, an outer pipe 25, an inner pipe 26, a wafer boat 27 and a manifold 28. The part of the wafer boat 27 used to place the wafer extends into the inner pipe 26, the outer pipe 25 is sleeved outside the inner pipe 26 and communicates with the inner pipe 26, and the outer pipe 25 is arranged in the furnace body 24.
[0083] The semiconductor process equipment provided by the embodiment can be a low-pressure chemical vapor deposition equipment, and further can be a low-pressure chemical vapor deposition silicon nitride equipment. The type of the semiconductor process equipment is not limited in the embodiment.
[0084] The semiconductor process equipment provided by the embodiment has the same technical features as the method for inhibiting the peeling of the film layer on the inner wall of the chamber provided by the above embodiment, so it can also solve the same technical problem and achieve the same technical effect.
[0085] The embodiment further provides a machine readable storage medium, which stores machine executable instructions. When the machine executable instructions are called and executed by a processor, the machine executable instructions cause the processor to implement the above method for inhibiting the peeling of the film layer on the inner wall of the chamber.
[0086] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above-described device and apparatus can refer to the corresponding process in the foregoing method embodiments, and will not be repeated here.
[0087] If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a nonvolatile computer readable storage medium executable by a processor. Based on this understanding, the technical solutions of the present application or the part of the prior art or the part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiments of the present application. The foregoing storage medium includes a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various program code storage media.
[0088] In the description of the present application, it should be noted that, unless otherwise explicitly specified and limited, the terms "first" and "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.
[0089] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A method of inhibiting peeling of a film layer from an inner wall of a chamber, the method comprising: The method comprises: a first pre-deposition step of pre-depositing a stress buffer layer on the inner wall of the process chamber, the stress buffer layer being composed of SiO2, SiON, SiCO or PSG; a second pre-deposition step of pre-depositing a silicon nitride film on the inner wall of the process chamber.
2. The method of claim 1, wherein, In the first pre-deposition step, the process gas comprises DCS and N2O; or, the process gas comprises TEOS, and further comprises any one of O3 and O2; or, the process gas comprises SiH4, and further comprises any one of N2O and O2; or, the process gas comprises SiCl4 and O2.
3. The method of claim 2, wherein the method further comprises: In the first pre-deposition step, the flow rate of DCS is 100-500 sccm, and the flow rate of N2O is 1000-5000 sccm. In the second pre-deposition step, the process gas comprises NH3, and further comprises any one of DCS, SiH4 and BTBAS.
4. The method of claim 1, wherein the method further comprises: In the second pre-deposition step, the flow rate ratio of NH3 to DCS is greater than 5.
5. The method of claim 4, wherein the method further comprises: In the first pre-deposition step, the process temperature is 750-800°C, and the process pressure is 0.2-2 Torr. After the second pre-deposition step, the method further comprises:
6. The method of claim 1, wherein the method further comprises: a process step of sequentially performing corresponding process treatment on multiple batches of wafers until the core process parameter of the wafers continuously deteriorates; a covering step of sequentially performing the first pre-deposition step and the second pre-deposition step; wherein the process step and the covering step are cyclically performed until the core process parameter of the wafers cannot be restored to the ideal range. The core process parameter comprises the uniformity, refractive index and deposition rate of the film formed on the wafer surface by the process step.
7. The method of claim 6, wherein the method further comprises, The method further comprises:
8. The method of claim 1, wherein the method further comprises: acquiring the number of particles in the process chamber; if the rising speed of the number of particles in the process chamber exceeds a threshold value, performing emergency shutdown. Between the first pre-deposition step and the second pre-deposition step, the method further comprises:
9. The method of inhibiting flaking of the membrane layer from the interior wall of the chamber of any of claims 1-8, wherein, vacuumizing the process chamber, introducing inert gas into the process chamber for purging, and vacuumizing the process chamber again. The controller comprises at least one processor and at least one memory, the memory storing a computer program, and the computer program is executed by the processor to implement the method for inhibiting film peeling of the inner wall of the chamber according to any one of claims 1-9.
10. A semiconductor process apparatus comprising a process chamber, a gas inlet assembly, and a controller, wherein,