Voltage stabilization control device and method, chip and electronic equipment

Abstract

The invention discloses a voltage stabilization control device and method, a chip and electronic equipment, and belongs to the technical field of electronic information. The voltage stabilization control device comprises a voltage stabilizer which is used for receiving input voltage through an input end, converting the input voltage into output voltage and outputting the output voltage through an output end; the discharge path is used for extracting current from a branch where the output end is located so as to reduce the output voltage, and the reduced output voltage is provided for the load circuit, so that the load circuit starts to work based on the reduced output voltage when the reduced output voltage is higher than the threshold voltage; and the discharge path is also used for stopping extracting current from the branch where the output end is located under the condition that the output voltage is higher than the threshold voltage so as to stop reducing the output voltage, so that the load circuit works based on the output voltage. Therefore, the output voltage reduction caused after the load circuit starts to work and the output voltage rise caused after the discharge path is disconnected react with each other, and the amplitude jitter of the output voltage can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic information, in particular to a voltage stabilizing control device and method, chip and electronic equipment. BACKGROUND

[0002] A regulator is a circuit capable of outputting a stable voltage, which is often used to provide a driving voltage to a load of a display driver, a power management circuit, and the like, to drive the load to work. Therefore, how to ensure the stability of the output voltage of the regulator is a problem to be solved. SUMMARY

[0003] The present application provides a voltage stabilizing control device and method, chip and electronic equipment, to solve the problems in the related art.

[0004] In one aspect, a regulator is provided, and the voltage stabilizing control device includes a regulator and a current bleeding path. The regulator is configured to receive an input voltage through an input terminal, convert the input voltage into an output voltage, and output the output voltage through an output terminal. The current bleeding path is configured to draw current from a branch in which the output terminal is located, to reduce the output voltage, and the reduced output voltage is used to provide a load circuit, so that the load circuit starts to work based on the reduced output voltage when the reduced output voltage is higher than a threshold voltage. The current bleeding path is further configured to stop drawing current from the branch in which the output terminal is located, to stop reducing the output voltage, when the output voltage is higher than the threshold voltage, so that the load circuit works based on the output voltage.

[0005] In one possible implementation, the load circuit stops working when the output voltage is lower than or equal to the threshold voltage. The current bleeding path is configured to draw current from the branch in which the output terminal is located, to reduce the output voltage, when the output voltage is lower than or equal to the threshold voltage.

[0006] In one possible implementation, the current bleeding path includes a load resistor and a first switch tube. One end of the load resistor is connected to the branch in which the output terminal is located, and the other end of the load resistor is connected to a ground terminal through the first switch tube. The first switch tube is configured to be turned off or turned on according to the relationship between the output voltage and the threshold voltage.

[0007] In one possible implementation, the current bleeding path further includes at least one second switch tube connected in parallel to the first switch tube. The second switch tube is used for being turned off or turned on according to the relationship between the output voltage and the threshold voltage, and the on-off state of the second switch tube is the same as that of the first switch tube.

[0008] In a possible implementation, the voltage stabilizing control device further comprises a power-on reset circuit. The power-on reset circuit is used for detecting the reduced output voltage, and in the case that the reduced output voltage is higher than the threshold voltage, sending a first level signal to the load circuit, so that the load circuit determines that the reduced output voltage is higher than the threshold voltage in the case that the first level signal is received, and starts to work based on the reduced output voltage.

[0009] In a possible implementation, the voltage stabilizing control device further comprises an inverter. The power-on reset circuit is further used for sending the first level signal to the inverter. The inverter is used for inverting the first level signal to obtain a second level signal, and sending the second level signal to the current leakage path. The current leakage path is used for determining that the reduced output voltage is higher than the threshold voltage in the case that the second level signal is received, and stopping the current from being drawn from the branch where the output terminal is located.

[0010] In another aspect, a voltage stabilizing control method is provided, and the method comprises: receiving an input voltage through an input terminal, converting the input voltage into an output voltage, and outputting the output voltage through an output terminal; drawing current from a branch where the output terminal is located through a current leakage path, so as to reduce the output voltage; in the case that the reduced output voltage is higher than a threshold voltage, starting a load to work based on the reduced output voltage, and stopping the current from being drawn from the branch where the output terminal is located, so as to stop reducing the output voltage, and the load works based on the output voltage.

[0011] In a possible implementation, the method further comprises: in the case that the output voltage is lower than or equal to the threshold voltage, controlling the load to stop working, and drawing current from the branch where the output terminal is located through the current leakage path, so as to reduce the output voltage.

[0012] In another aspect, a chip is provided, and the chip comprises a load and a voltage stabilizing control device as described in any of the above aspects. The voltage stabilizing control device is connected with the load, and is used for providing an output voltage for the load, so as to drive the load to work through the output voltage.

[0013] In another aspect, an electronic device is provided, which includes the chip according to the above another aspect.

[0014] The technical solutions provided in the present application can bring at least the following beneficial effects: In the voltage stabilizing control device, the current is drawn from the branch where the output terminal is located through the current leakage path to reduce the output voltage, so that when the reduced output voltage is higher than the threshold voltage, the load circuit starts to work at the same time, the current leakage path is disconnected, that is, the current drawn from the branch where the output terminal is located is stopped, so as to stop reducing the output voltage. Wherein, the output voltage will be reduced after the load circuit starts to work, forming a set of negative feedback mechanism; and the output voltage will be increased after the current leakage path is disconnected, forming a set of positive feedback mechanism. Therefore, the reverse action between the negative feedback mechanism and the positive feedback mechanism can reduce the amplitude jitter of the output voltage, and improve the stability and reliability. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0016] Figure 1 is a timing diagram of the output voltage changing with time provided by the embodiments of the present application; Figure 2 is a signal timing diagram provided by the embodiments of the present application; Figure 3 is a structural schematic diagram of a voltage stabilizing control device provided by the embodiments of the present application; Figure 4 is a structural schematic diagram of another voltage stabilizing control device provided by the embodiments of the present application; Figure 5 is a structural schematic diagram of another voltage stabilizing control device provided by the embodiments of the present application; Figure 6 is a structural schematic diagram of another voltage stabilizing control device provided by the embodiments of the present application; Figure 7 is a structural schematic diagram of another voltage stabilizing control device provided by the embodiments of the present application; Figure 8 is a structural schematic diagram of another voltage stabilizing control device provided by the embodiments of the present application; Figure 9 is a working flowchart of a voltage stabilizing control device provided by the embodiments of the present application; Figure 10is a signal timing diagram of a voltage stabilizing control device provided by an embodiment of the present application. Figure 11 is a flow chart of a voltage stabilizing control method provided by an embodiment of the present application. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0018] With the development of display electronic technology, display drive integrated circuits (DDIC) often use more advanced processes to meet the ability of high-speed data transmission. More advanced processes mean lower operating voltage, but in actual applications, DDIC still needs to work in the original power supply network. Therefore, a low dropout regulator (LDO) needs to be added to the DDIC to provide stable power supply for the DDIC through the LDO. The LDO is a commonly used power management module, which is used to convert a higher input voltage into a stable lower output voltage.

[0019] Exemplarily, the LDO circuit receives an input voltage Vin through an input terminal and outputs the output voltage Vddr through an output terminal. The core function of the LDO circuit is to convert the input voltage Vin stably into the output voltage Vddr, and the output voltage Vddr is connected to a load circuit to provide a stable power output to the load circuit. The LDO circuit includes an error amplifier (EA), a power tube PM, and resistors R1 and R2.

[0020] The power tube PM refers to a P-type metal-oxide-semiconductor field-effect transistor (MOSFET) device, and the P-type MOSFET device is also called a PMOS tube. The PMOS tube is turned on when the gate is low voltage, and is turned off when the gate is high voltage. Alternatively, the power tube PM can also be replaced by an NMOS tube or a bipolar junction transistor (BJT). The NMOS tube is also called an N-type MOSFET device, and the NMOS tube is turned on when the gate is high voltage, and is turned off when the gate is low voltage. When the NMOS tube is used as the power tube of the LDO circuit, the positive and negative input terminals of the error amplifier EA need to be adjusted in polarity accordingly.

[0021] The resistors R1 and R2 are voltage dividing resistors, which are used to divide the output voltage Vddr to obtain a feedback voltage (Vfb) with a division ratio of R2 / (R1+R2), i.e., Vfb=R2 / (R1+R2)*Vddr. The feedback voltage Vfb is fed back to the positive input terminal (+) of the error amplifier EA, thereby forming a negative feedback loop. The error amplifier EA is used to compare the deviation between the feedback voltage Vfb and a reference voltage (Vref) and output a deviation signal Vg. The deviation signal Vg is connected to the gate of the power transistor PM, which is used to control the conduction degree of the power transistor PM. The source of the power transistor PM is connected to the input terminal of the input voltage, and the drain of the power transistor PM is connected to the output terminal of the output voltage. By controlling the conduction degree of the power transistor PM, the output voltage Vddr is maintained stable.

[0022] For example, the error amplifier EA compares the reference voltage Vref and the feedback voltage Vfb. If VfbVref, it means that the output voltage Vddr is too low, and the error amplifier EA outputs a lower deviation signal Vg, so that the conduction of the power transistor PM is enhanced, and the output voltage Vddr is increased. If Vfb>Vref, it means that the output voltage Vddr is too high, and the error amplifier EA outputs a higher deviation signal Vg, so that the conduction of the power transistor PM is weakened, and the output voltage Vddr is decreased. In this way, the output voltage Vddr closely follows the reference voltage Vref. When the LDO reaches a stable output state, Vfb≈Vref, and Vddr≈Vfb*(R1+R2) / R2.

[0023] In addition, the output voltage Vddr of the LDO circuit is connected to a power-on reset (POR) circuit and a load circuit. The POR circuit is used to detect the on-off timing of the output voltage Vddr of the LDO circuit and provide a reset signal to the load circuit to set the initial state. The POR is a reset mechanism integrated in the chip, which is realized by monitoring the power voltage change to initialize. The reset mechanism includes: when it is detected that the power voltage is lower than a preset threshold, the internal load circuit is in a reset state, and the load circuit stops working. After the power voltage exceeds the preset threshold, a reset cancellation signal is sent.

[0024] For example, the POR circuit detects the amplitude of the output voltage Vddr and outputs a signal RSTN to the load circuit according to the detection result. The signal RSTN is used to control the working state of the load circuit. When the output voltage Vddr is less than the detection voltage of the POR circuit, the RSTN is at a low level; when the output voltage Vddr is greater than or equal to the detection voltage of the POR circuit, the RSTN is at a high level. The load circuit is in a reset state and does not work based on the low level of the RSTN; and the load circuit is in a non-reset state and starts to work based on the high level of the RSTN, and generates a corresponding output (OUT).

[0025] In this case, the output voltage Vddrof the LDO circuit varies differently in the power-on and power-off processes due to different load intensity of the load circuit. For example, as shown in the voltage variation diagram of FIG. 1, in the light load state, the output voltage Vddris close to the input voltage Vin, i.e., the voltage difference between the output voltage Vddrand the input voltage Vinis small; in the heavy load state, the voltage difference between the output voltage Vddrand the input voltage Vinis large. Thus, the degree of deviation of the output voltage Vddrof the LDO from the input voltage Vinis positively correlated with the load intensity, i.e., the heavier the load, the larger the voltage difference between the output voltage Vddrand the input voltage Vinin the power-on and power-off processes; the lighter the load, the smaller the voltage difference between the output voltage Vddrand the input voltage Vinin the power-on and power-off processes. Figure 1

[0026] In this case, the LDO circuit will oscillate in the negative feedback formed by the POR circuit and the load circuit. For example, as shown in FIG. 2, for a system including a voltage regulator, a load circuit and a POR circuit, in the system power-on process, the output voltage Vddrof the LDO circuit starts to rise following the input voltage Vin, at this time, the output voltage Vddris lower than the detection voltage of the POR circuit, the signal RSTN output by the POR circuit is at low level to control the load circuit to be in the reset state, i.e., not to work, and the load current Iloadis small and close to zero. Figure 2

[0027] Subsequently, the output voltage Vddrreaches and exceeds the detection voltage of the POR, the signal RSTN output by the POR circuit jumps to high level, the load circuit starts to work immediately, the load current Iloadsurges, forming the effect of drawing current from the branch where the output terminal of the LDO circuit is located, so that the output voltage Vddrof the LDO circuit decreases rapidly. In this case, for the heavy load scenario, the output voltage Vddrwill decrease to less than the detection voltage of the POR circuit, then the signal RSTN jumps to low level again, and the load current Iloadinstantly decreases to zero. As the output voltage Vddrcontinues to rise and exceeds the detection voltage of the POR again, the system oscillates in this way.

[0028] Similarly, as shown in FIG. 3, in the system power-off process, the output voltage Vddrof the LDO circuit starts to decrease following the input voltage Vin, at this time, the output voltage Vddris higher than the detection voltage of the POR circuit, the signal RSTN output by the POR circuit is at high level to control the load circuit to be in the working state, and the load current Iloadis large. Figure 2 ​​As shown, during the system power-down process, the output voltage Vddr of the LDO circuit follows the input voltage Vin to drop, at this time, the output voltage Vddr is higher than the detection voltage of the POR circuit, the signal RSTN output by the POR circuit is high, the load circuit continues to work, and the load current Iload is close to the rated current. Subsequently, the output voltage Vddr is lower than the detection voltage of the POR circuit, the signal RSTN jumps to low, and the load circuit is controlled to stop working, and the load current Iload suddenly drops to zero, so that the current of the branch where the output end of the LDO circuit is located is no longer shared to the load circuit, and the output voltage Vddr of the LDO circuit is rapidly lifted. In this case, for the heavy load scenario, the output voltage Vddr will be higher than the detection voltage of the POR circuit again, then the signal RSTN jumps to high again, the load circuit works again, and the load current Iload suddenly increases again, which causes the output Vddr to be lower than the detection voltage of the POR circuit, and so on, the system oscillates.

[0029] In summary, during the system power-up and power-down, the POR circuit, the LDO circuit and the load circuit form a negative feedback loop, when the output voltage Vddr reaches the detection threshold of the POR circuit, the signal RSTN triggers the output voltage Vddr in the opposite direction, so that the output voltage Vddr oscillates, that is, the amplitude of the output voltage Vddr oscillates around the detection threshold of the POR circuit, the signal RSTN oscillates between high and low, and the load circuit oscillates between working and not working, which reduces the stability of the system. Among them, the current peak value of the load circuit under multiple oscillations changes suddenly, which causes the power supply line to be difficult to withstand the pressure of the peak current, and there is a risk of burning, which reduces the reliability of the power supply system. And the digital circuit and the analog circuit in the load circuit repeatedly reset, which will make the output signal OUT disorder, and finally will affect the abnormality of the display screen.

[0030] The embodiment of the application provides a voltage stabilizing control device, as shown in the figure Figure 3 As shown, the voltage stabilizing control device comprises a voltage stabilizer 01 and a discharge path 03, and the output end of the voltage stabilizer 01 is connected with the discharge path 03. Optionally, the voltage stabilizing control device is connected with a load circuit 02, for example, the output end of the voltage stabilizer 01 is connected with the load circuit 02.

[0031] The voltage stabilizer 01 is configured to receive an input voltage Vin through an input terminal, convert the input voltage Vin into an output voltage Vddr, and output the output voltage Vddr through an output terminal. The current leakage path 03 is configured to draw current from a branch where the output terminal is located, so as to reduce the output voltage Vddr. The reduced output voltage Vddr is used to provide the load circuit 02, so that the load circuit 02 starts to work based on the reduced output voltage Vddr when the reduced output voltage Vddr is higher than a threshold voltage. The current leakage path 03 is also configured to stop drawing current from the branch where the output terminal is located when the output voltage Vddr is higher than the threshold voltage, so as to stop reducing the output voltage Vddr, and make the load circuit 02 work based on the output voltage Vddr. The threshold voltage can be the working voltage of the load circuit.

[0032] Therefore, Figure 3 The voltage stabilizer control device shown in the figure can control the current leakage path 03 to be disconnected, i.e., stop drawing current from the branch where the output terminal is located, when the load circuit 02 starts to work based on the reduced output voltage Vddr being higher than the threshold voltage. After the load circuit 02 starts to work, the load current Iload of the load circuit 02 increases. Based on the foregoing, the increased load current Iload is equivalent to drawing current from the branch where the output terminal is located, which will reduce the output voltage Vddr, forming a set of negative feedback mechanisms. The current leakage path 03 originally draws current from the branch where the output terminal is located. If the current leakage path 03 stops drawing current from the branch where the output terminal is located, it is equivalent to increasing the current of the branch where the output terminal is located, which will increase the output voltage Vddr, forming a set of positive feedback mechanisms. Therefore, when the load circuit 02 starts to draw current from the branch where the output terminal is located, the current leakage path 03 stops drawing current from the branch where the output terminal is located, forming two sets of feedback mechanisms that act in opposite directions, which can reduce the amplitude jitter of the output voltage Vddr and improve the stability of the voltage stabilizer 01.

[0033] Further, in the power-on process of the voltage stabilizer control device, the amplitude jitter of the output voltage Vddr is small, so the amplitude of the output voltage Vddr will not oscillate around the threshold voltage of the POR circuit. If the load circuit 02 is triggered to start working during the power-on process, it will remain in the working state and will not oscillate between working and not working. Further, the load current Iload of the load circuit 02 will not change multiple times, reducing the peak current duration of the power supply trace, and the output signal of the load circuit 02 is more stable.

[0034] In the embodiment of the present application, the load circuit 02 stops working when the output voltage Vddr is lower than or equal to the threshold voltage; the bleeder path 03 is also used to re-draw the current from the branch where the output terminal is located to reduce the output voltage Vddr when the output voltage Vddr is lower than or equal to the threshold voltage. Wherein, the load current Iload of the load circuit 02 is reduced after the load circuit 02 stops working, and the reduced load current Iload is equivalent to stopping drawing the current from the branch where the output terminal is located, which will cause the output voltage Vddr to rise; while the bleeder path 03 starts to draw the current from the branch where the output terminal is located again, which will cause the output voltage Vddr to decrease. Thus, during the power-down process of the voltage stabilizing control device, system oscillation will not occur.

[0035] In a possible implementation, the bleeder path 03 is connected between the output voltage Vddr and the ground terminal, forming a bleeder path. The present application does not limit the size of the bleeder current of the bleeder path 03, and the size of the bleeder current of the bleeder path 03 can be determined according to the size of the load current Iload, for example, the larger the load current Iload, the larger the bleeder current of the bleeder path 03, and the smaller the load current Iload, the smaller the bleeder current of the bleeder path 03. Exemplarily, the bleeder current of the bleeder path 03 can be approximately equal to the load current Iload.

[0036] In the embodiment of the present application, referring to Figure 4 , the voltage stabilizing control device further comprises a power-on reset (POR) circuit; in the case that the bleeder path 03 draws the current from the branch where the output terminal is located, the power-on reset circuit is used to detect the reduced output voltage Vddr, and in the case that the reduced output voltage Vddr is higher than the threshold voltage, the power-on reset circuit sends a first level signal to the load circuit 02 and the bleeder path 03. The load circuit 02 and the bleeder path 03 are used to determine that the reduced output voltage is higher than the threshold voltage in the case that the first level signal is received; and then the load circuit 02 starts to work based on the reduced output voltage in the case that the reduced output voltage is determined to be higher than the threshold voltage, and the bleeder path 03 stops drawing the current from the branch where the output terminal is located in the case that the reduced output voltage is determined to be higher than the threshold voltage. In this case, the threshold voltage is the detection voltage of the power-on reset circuit.

[0037] In the case that the bleeder path 03 stops drawing current from the branch where the output terminal is located, the power-on reset circuit is configured to detect the output voltage Vddr, and in the case that the output voltage Vddr is lower than or equal to the threshold voltage, send a second level signal to the load circuit 02 and the bleeder path 03. The load circuit 02 and the bleeder path 03 are configured to determine that the output voltage is lower than or equal to the threshold voltage in the case that the second level signal is received. Optionally, the first level signal is high level and the second level signal is low level, or the first level signal is low level and the second level signal is high level.

[0038] Optionally, the bleeder path 03 comprises a load resistor Rload and a first switch tube; one end of the load resistor Rload is connected to the branch where the output terminal is located, and the other end of the load resistor Rload is connected to the ground terminal through the first switch tube. The first switch tube is configured to be turned off or turned on according to the relationship between the output voltage and the threshold voltage. For example, the first switch tube is turned off in the case that the reduced output voltage is higher than the threshold voltage, i.e., the bleeder path 03 is turned off; and the first switch tube is turned on in the case that the output voltage is lower than or equal to the threshold voltage, i.e., the bleeder path 03 is turned on. The resistance value of the load resistor Rload is approximately equal to the resistance value of the working impedance of the load circuit 02. For example, refer to Figure 4 In the case that the voltage stabilizing control device further comprises a power-on reset (POR) circuit, the first switch tube receives a signal output by the power-on reset circuit, and determines whether the output voltage is higher than the threshold voltage according to the signal output by the power-on reset circuit.

[0039] In a possible implementation, the bleeder path 03 further comprises at least one second switch tube connected in parallel with the first switch tube; the second switch tube is configured to be turned off or turned on according to the relationship between the output voltage and the threshold voltage, and the second switch tube has the same on-off state as the first switch tube. For example, if the first switch tube is turned off in the case that the reduced output voltage is higher than the threshold voltage, and is turned on in the case that the output voltage is lower than or equal to the threshold voltage, then the second switch tube is also turned off in the case that the reduced output voltage is higher than the threshold voltage, and is turned on in the case that the output voltage is lower than or equal to the threshold voltage. In this way, by connecting multiple switch tubes in parallel, the on-resistance of the switch tube can be reduced, and the influence of the on-resistance of the switch tube on the bleeder current can be avoided, so that the control of the bleeder path is more accurate.

[0040] The switch tube can be implemented by an NMOS tube or a PMOS tube. In the case that the first level signal sent by the above power-on reset circuit is high when the reduced output voltage Vddr is higher than the threshold voltage, the switch tube in the electric path 03 is implemented by a PMOS tube, the output end of the power-on reset circuit is directly connected with the gate of the PMOS tube, and the PMOS tube is turned off when the gate voltage is high. In the case that the switch tube in the electric path 03 is implemented by an NMOS tube, the output end of the power-on reset circuit is connected with the gate of the NMOS tube through an inverter, and the NMOS tube is turned off when the gate voltage is low.

[0041] Optionally, the voltage stabilizing control device further comprises an inverter on the basis of the power-on reset circuit. The power-on reset circuit is further configured to send the first level signal to the inverter when the reduced output voltage is higher than the threshold voltage. The inverter is configured to obtain the second level signal by inverting the first level signal, and send the second level signal to the electric path 03. The electric path 03 is configured to determine that the reduced output voltage is higher than the threshold voltage when the second level signal is received. Similarly, the power-on reset circuit is further configured to send the second level signal to the inverter when the output voltage is lower than or equal to the threshold voltage. The inverter is configured to obtain the first level signal by inverting the second level signal, and send the first level signal to the electric path 03. The electric path 03 is configured to determine that the output voltage is lower than or equal to the threshold voltage when the first level signal is received.

[0042] For example, the first switch tube and the second switch tube are both implemented by PMOS tubes. Referring to FIG. 3, the electric path 03 comprises a load resistor Rload and a plurality of PMOS tubes, and the plurality of PMOS tubes are PM0, PM1 and PM2. Figure 5 For example, the first switch tube and the second switch tube are both implemented by NMOS tubes. Referring to FIG. 4, the electric path 03 comprises a load resistor Rload and a plurality of NMOS tubes, and the gate of the plurality of NMOS tubes is connected with the inverter, and the plurality of NMOS tubes are NM0, NM1 and NM2. Figure 6 For example, the first switch tube and the second switch tube are both implemented by PMOS tubes. Referring to FIG. 3, the electric path 03 comprises a load resistor Rload and a plurality of PMOS tubes, and the plurality of PMOS tubes are PM0, PM1 and PM2.

[0043] Optionally, the voltage stabilizer 01 in the embodiment of the present application can be the low dropout linear voltage regulator LDO as mentioned above, which can be referred to the related description of the LDO circuit as mentioned above. The voltage stabilizer 01 comprises an error amplifier EA, a first power transistor PM, and a resistor divider composed of R1 and R2. The feedback voltage Vfb and the reference voltage Vref are applied to the positive terminal and the negative terminal of the error amplifier EA respectively, and the deviation signal Vg output by the EA is used to control the working state of the power transistor PM. The source and the drain of the first power transistor PM are connected to the input voltage Vin and the output voltage Vddr of the external power supply respectively. For example, the first power transistor is used to conduct under the action of the deviation signal Vg, and injects current to the branch where the output end is located based on the input voltage Vin input at the input end. The Vddr generates the feedback voltage Vfb through the resistor divider composed of R1 and R2, thereby forming a complete feedback loop. When the load current Iload increases or decreases, the output voltage Vddr decreases or increases, and the power transistor PM output is controlled to be enhanced or weakened through the feedback loop, thereby maintaining the stability of the output voltage Vddr.

[0044] Referring to Figure 7 , Figure 7 The structure schematic diagram of another voltage stabilizing control device provided by the embodiment of the present application is shown. The voltage stabilizing control device comprises an LDO circuit, a load resistor R Load, a switch transistor NM, an inverter, and a POR circuit. The LDO circuit corresponds to the voltage stabilizer 01 as described above, the load circuit corresponds to the load circuit 02 as described above, and the load resistor R Load and the switch transistor NM correspond to the discharge path 03 as described above.

[0045] The LDO circuit is used to provide a stable power supply voltage, i.e. the output voltage Vddr, for the load (Load) circuit. The POR circuit is used to detect the amplitude state of the output voltage Vddr of the LDO circuit. When the output voltage Vddr is higher / lower than the detection voltage of the POR circuit, the output signal RSTN is high / low, which is used to control whether the Load circuit works.

[0046] The signal RSTN is connected to the load circuit as a reset signal, and forms a negative feedback network with the load circuit and the output voltage Vddr. The negative feedback network means that when the signal RSTN jumps to high level, the load circuit is used to reduce the output voltage Vddr. The signal RSTP is the inverse logic of the signal RSTN through the inverter, and the signal RSTP controls the gate of the NMOS transistor NM. The source and the drain of the NMOS transistor NM are connected to the ground and one end of the load resistor Rload respectively, and the other end of the load resistor Rload is connected to the output voltage Vddr. When the signal RSTN is high, the NM is disconnected, and when the signal RSTN is low, the NM is turned on. A discharge path is formed between the output end and the ground through the load resistor Rload.

[0047] In the embodiments of the present application, the NM can adopt a low threshold voltage device, and the turn-on voltage of the NM is lower than the detection voltage of the POR circuit. In addition, a plurality of NMOS transistors in parallel can be adopted to further reduce the on-resistance of the NM. At this time, the signal RSTN and the NM and the load resistor Rload form a positive feedback network, which means that when the signal RSTN jumps to high level, the NM and the load resistor Rload are used to raise the output voltage Vddr.

[0048] In a possible implementation, the number of load circuits 02 connected by the voltage stabilizing control device can be multiple, for example, the voltage stabilizing control device is connected with two load circuits, a first load circuit and a second load circuit. In the case where the voltage stabilizing control device is connected with multiple load circuits, the number of discharge paths 03 can also be multiple, for example, if one load circuit starts to work when the output voltage is higher than the threshold voltage, one discharge path 03 is disconnected; if two load circuits start to work when the output voltage is higher than the threshold voltage, two discharge paths 03 are disconnected.

[0049] In the case where the voltage stabilizing control device is connected with the first load circuit and the second load circuit, taking the case where the voltage stabilizing control device includes a first discharge path and a second discharge path as an example, the first discharge path is used to disconnect when the first load circuit starts to work, and is used to conduct when the first load circuit stops working; the second discharge path is used to disconnect when the second load circuit starts to work, and is used to conduct when the second load circuit stops working. The implementation of the second load circuit and the second discharge path can refer to the implementation of the load circuit 02 and the discharge path 03 described above, and will not be described here.

[0050] Exemplarily, in the voltage stabilizing control device shown in Figure 8 In the voltage stabilizing control device shown in

[0051] Next, taking the voltage stabilizing control device shown in Figure 7 as an example, the working process of the voltage stabilizing control device in the power-on and power-off process of the external power supply is described in combination with the working flowchart shown in Figure 9 .

[0052] The first step, the external power supply starts to power on.

[0053] In the beginning of power-on stage, the output voltage Vddr is lower than the threshold voltage of the POR circuit, the POR circuit outputs a low level signal RSTN, the signal RSTN controls the load circuit to be in the reset state and not to work, and the load current is close to zero. But the inverse logic signal RSTP of the signal RSTN controls the switch tube NM to be turned on, and there is a Rload discharge path.

[0054] The second step, the external power supply continues to rise into the second power-on stage.

[0055] In the second power-on stage, the output voltage Vddr exceeds the threshold voltage of the POR circuit, the POR circuit triggers the output of a high level signal RSTN, and the load circuit is controlled to start working based on the high level signal RSTN. The load current increases in a short period of time, and has a tendency to pull down the output voltage Vddr. At the same time, the inverse logic signal RSTP of the signal RSTN controls the NM to be turned off, and the discharge path is disconnected, so that the current on the branch where the output terminal is located increases, and has a tendency to lift the output voltage Vddr. The two opposite trends offset each other, narrow the jitter range of the output voltage Vddr, and achieve the effect that the signal RSTN is not reset repeatedly.

[0056] The third step, the external power supply is powered on.

[0057] The LDO circuit provides stable power supply voltage for the load circuit under the control of Vref1. In the power-on process, the discharge path is switched between conduction and disconnection to generate a change trend opposite to the load feedback for the output voltage Vddr, which avoids the oscillation phenomenon of RSTN when the load current suddenly increases, that is, ensures that the POR circuit triggers once, and avoids the frequent switching phenomenon between the working and non-working of the load circuit.

[0058] The fourth step, the external power supply starts to power off.

[0059] In the beginning of power-off stage, the output voltage Vddr is higher than the threshold voltage of the POR circuit, and the load circuit keeps working, and the discharge path is always disconnected.

[0060] The fifth step, the external power supply continues to fall into the second power-off stage.

[0061] In the second power-down stage, the output voltage Vddr is lower than the threshold voltage of the POR circuit, the POR circuit is reset, the RSTN jumps to low level and controls the load circuit to enter the reset state, the load current is close to zero, and the output voltage Vddr has a tendency to rise. At the same time, the inverse logic signal RSTP of the signal RSTN controls the NM to be turned on, the discharge path is connected, the current in the branch where the output terminal is located is reduced, and the output voltage Vddr has a tendency to decrease. The two opposite tendencies offset each other, narrow the jitter range of the output voltage Vddr, and achieve the effect that the load circuit is not repeatedly reset.

[0062] In the sixth step, the external power supply power-down ends.

[0063] With the end of the power-down of the external power supply, the output voltage Vddr of the LDO circuit also slowly decreases to a low level, and no longer provides effective power output for the load circuit. In the power-down process, the switching of the discharge path between disconnection and connection produces a change tendency opposite to the load feedback to the output voltage Vddr, avoiding the oscillation phenomenon of RSTN when the load current suddenly becomes zero.

[0064] Referring to Figure 10 The signal timing diagram shown in the above input voltage Vin, output voltage Vddr, signal RSTN, signal RSTP and load current Iload change over time are illustrated. In the power-up process, the input voltage Vin starts to power up from a low level, and the output voltage Vddr starts to power up following the input voltage Vin. At this time, the signal RSTN is low, the load circuit does not work, and the load current Iload is close to zero; the signal RSTP is high, and if the signal RSTP is higher than the threshold voltage V1 of the switch tube NM, the discharge path is connected and effective, and a certain load current is generated between the output terminal and the ground terminal.

[0065] With the increase of the output voltage Vddr, the RSTN jumps to high level and controls the load circuit to work, and the load current Iload suddenly increases. At the same time, the RSTP jumps to low level, and the discharge path is disconnected, i.e. closed. The discharge path and the load circuit are regarded as an integral load connected to the output terminal. When the load circuit starts to work, the discharge path is disconnected, so that the load current change difference of the integral load is reduced. In this case, the output voltage Vddr only has a small amplitude jitter in a short period of time, but does not decrease below the threshold voltage range of the POR circuit, until the input voltage Vin is in a stable state.

[0066] In the power down process, the input voltage Vin starts to power down from the steady state, before the POR circuit resets, the RSTN keeps high, the power transistor PM0 and the load circuit work all the time, and the load current Iload decreases slowly. As the input voltage Vin continues to decrease, when the output voltage Vddr is lower than the threshold voltage of the POR circuit, the POR circuit resets, the RSTN jumps to low and controls the load circuit to stop working, and the load current Iload drops to zero. At the same time, the RSTP jumps to high, the discharge path is connected and opened, and the discharge path and the load circuit are regarded as an integral load connected to the output end. The discharge path is opened at the same time when the load circuit stops working, so that the load current change difference of the integral load is reduced. In this case, the output voltage Vddr only has a small amplitude jitter in a short time, but does not exceed the threshold voltage range of the POR circuit, until the input Vin decreases to zero potential.

[0067] In the whole power up and down process, the influence of the RSTN jump on the output voltage Vddr is reduced, so that the reliability of the regulator output power supply is improved, and the stability of the voltage control device is improved.

[0068] Referring to Figure 11 , Figure 11 is a flowchart of a voltage control method provided by an embodiment of the present application. As Figure 11 shown, the voltage control method includes but is not limited to the following steps 1201-1203.

[0069] Step 1201, receiving an input voltage through an input end, converting the input voltage into an output voltage, and outputting the output voltage through an output end.

[0070] Step 1202, extracting current from a branch where the output end is located through a discharge path, to reduce the output voltage.

[0071] Step 1203, in the case that the reduced output voltage is higher than a threshold voltage, starting the load to work based on the reduced output voltage, and stopping extracting current from the branch where the output end is located, to stop reducing the output voltage, so that the load works based on the output voltage.

[0072] In a possible implementation, the method further includes: in the case that the output voltage is lower than or equal to the threshold voltage, controlling the load to stop working, and extracting current from the branch where the output end is located through the discharge path, to reduce the output voltage.

[0073] Exemplarily, the method is applied to Figures 3-8Any of the voltage stabilizing control devices. Taking the voltage stabilizing control device including the voltage stabilizer and the current bleeding path as an example, the method comprises: receiving, by the voltage stabilizer, an input voltage from an input end, converting the input voltage into an output voltage, and outputting the output voltage from an output end; bleeding, by the current bleeding path, a current from a branch where the output end is located, to reduce the output voltage, the reduced output voltage being provided to the load, so that the load starts to work based on the reduced output voltage in a case that the reduced output voltage is higher than a threshold voltage; and stopping, by the current bleeding path, bleeding of the current from the branch where the output end is located in a case that the output voltage is higher than the threshold voltage, to stop reducing the output voltage, so that the load works based on the output voltage.

[0074] It can be understood that, in the case that the method is applied to the voltage stabilizing control device described above, the implementation and technical effects of the method can be referred to the relevant description in the voltage stabilizing control device described above, which will not be described herein again.

[0075] The embodiments of the present application further provide a chip, which comprises a load, and the voltage stabilizing control device described above. Figures 3-8 Any of the voltage stabilizing control devices. The voltage stabilizing control device is connected with a load, and is configured to provide an output voltage to the load, to drive the load to work by the output voltage.

[0076] Optionally, the chip is a display driving chip, for example, a DDIC. The DDIC is driven by the voltage stabilizing control device, and reliably displays a picture by controlling a display panel connected by the load.

[0077] It can be understood that, since the chip has basically the same technical effects as the voltage stabilizing control device described above, the technical effects of the chip will not be described herein again for the purpose of simplicity.

[0078] The embodiments of the present application further provide an electronic device, which comprises the chip described above; or the electronic device comprises the voltage stabilizing control device described above. Figures 3-8 Any of the voltage stabilizing control devices. Optionally, the electronic device can be a display device. For example, the display device can be a mobile phone, a computer, or the like.

[0079] It can be understood that, since the electronic device has basically the same technical effects as the voltage stabilizing control device described above, the technical effects of the electronic device will not be described herein again for the purpose of simplicity.

[0080] The terms "first", "second", "third", and "fourth" and the like in the description and in the claims of the present application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the descriptive terms used herein are to be interpreted in the context as exercised by those of ordinary skill in the art and according to the doctrine of equivalents. Furthermore, the terms "comprise", "comprising", "include", "including", and the like characterizing unites and / or method steps are used herein to permit the specification to be read as comprising, and / or including, but not limiting to, the listed steps or elements thereof, and vice versa.

[0081] In this document, unless otherwise indicated or implied, the terms "mounting", "connected", "connecting" should be interpreted broadly, for example, can be fixed connection, can also be detachable connection, or integral connection; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, can be internal communication of two elements. For those skilled in the art, the specific meaning of the above terms in this application can be understood according to the specific circumstances.

[0082] The above is only an optional embodiment of the present application, and is not used to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A voltage stabilizing control device, characterized by comprising: The voltage stabilizing control device comprises a voltage stabilizer and a current leakage path; The voltage stabilizer is configured to receive an input voltage through an input terminal, convert the input voltage into an output voltage, and output the output voltage through an output terminal; The current leakage path is configured to draw current from a branch where the output terminal is located, so as to reduce the output voltage, and the reduced output voltage is used to supply a load circuit, so that the load circuit starts to work based on the reduced output voltage in a case where the reduced output voltage is higher than a threshold voltage; The current leakage path is further configured to stop drawing current from the branch where the output terminal is located, so as to stop reducing the output voltage, in a case where the output voltage is higher than the threshold voltage, so that the load circuit works based on the output voltage.

2. The voltage stabilizing control device according to claim 1, characterized by The load circuit stops working in a case where the output voltage is lower than or equal to the threshold voltage; The current leakage path is configured to draw current from the branch where the output terminal is located, so as to reduce the output voltage, in a case where the output voltage is lower than or equal to the threshold voltage.

3. The voltage stabilizing control device according to claim 2, characterized by The current leakage path comprises a load resistor and a first switch tube; One end of the load resistor is connected to the branch where the output terminal is located, and the other end of the load resistor is connected to a ground terminal through the first switch tube; The first switch tube is configured to be turned off or turned on according to the relationship between the output voltage and the threshold voltage.

4. The voltage stabilizing control device according to claim 3, wherein The current leakage path further comprises at least one second switch tube connected in parallel with the first switch tube; The second switch tube is configured to be turned off or turned on according to the relationship between the output voltage and the threshold voltage, and the on-off state of the second switch tube is the same as that of the first switch tube.

5. The voltage control device according to any one of claims 1 to 4, characterized by The voltage stabilizing control device further comprises a power-on reset circuit; The power-on reset circuit is configured to detect the reduced output voltage, and send a first level signal to the load circuit in a case where the reduced output voltage is higher than the threshold voltage, so that the load circuit determines that the reduced output voltage is higher than the threshold voltage in a case where the first level signal is received, and starts to work based on the reduced output voltage.

6. The voltage control device according to claim 5, wherein The voltage stabilizing control device further comprises an inverter; The power-on reset circuit is further configured to send the first level signal to the inverter; The inverter is configured to invert the first level signal to obtain a second level signal, and send the second level signal to the current leakage path; The current leakage path is configured to determine that the reduced output voltage is higher than the threshold voltage in a case where the second level signal is received, and stop drawing current from the branch where the output terminal is located.

7. A voltage stabilizing control method characterized by comprising: The method comprises: receiving an input voltage through an input terminal, converting the input voltage into an output voltage, and outputting the output voltage through an output terminal; drawing current from a branch where the output terminal is located through a current leakage path, so as to reduce the output voltage; starting a load to work based on the reduced output voltage in a case where the reduced output voltage is higher than a threshold voltage, and stopping drawing current from the branch where the output terminal is located, so as to stop reducing the output voltage, the load working based on the output voltage.

8. The method of claim 7, wherein, The method further comprises: In the case that the output voltage is lower than or equal to the threshold voltage, the load is controlled to stop working, and current is extracted from the branch where the output terminal is located through a bleeder path to reduce the output voltage.

9. A chip, characterized by The chip comprises a load and the voltage stabilizing control device as claimed in any one of claims 1 to 6. The voltage stabilizing control device is connected with the load and is configured to provide an output voltage for the load to drive the load to work through the output voltage.

10. An electronic device, comprising: The electronic device comprises the chip as claimed in claim 9.

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