Artificial intelligence chip and debugging method
By integrating debugging and storage modules into the artificial intelligence chip, key signals can be acquired and stored in real time, solving the problem of difficult-to-reproduce faults during long-term operation, achieving efficient fault diagnosis and monitoring, and reducing resource consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-19
- Publication Date
- 2026-05-15
AI Technical Summary
Existing technologies struggle to efficiently reproduce faults that occur during long-term operation of AI chips, especially non-static faults such as race conditions and timing-related errors. Furthermore, accelerator simulation methods are time-consuming and resource-intensive.
Design an artificial intelligence chip that includes a debugging module, a data scheduling module, a storage module, and an interrupt control module. The chip can acquire and encapsulate key signals into data packets in real time and store them in the chip's internal storage module to achieve real-time backup and monitoring of key signals.
It enables fault reproduction consistent with actual operating time, simplifies the diagnosis of long-term faults, reduces chip space occupation and resource consumption, and is particularly effective in monitoring non-static faults.
Smart Images
Figure CN121387692B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of artificial intelligence chip technology, and in particular to an artificial intelligence chip and its debugging method. Background Technology
[0002] Artificial intelligence chips include general-purpose computing on graphics processing units (GPGPUs). GPGPUs can be widely used for training and inference of large models, but the programs have long running times, many running nodes, and a lot of logic. Using accelerators for simulation is generally time-consuming. The running speed of accelerators is much slower than that of real chips. A task that takes a day on a real chip may take months or even years in a simulation environment. This makes it completely impractical to use accelerators for simulation to completely "reproduce" a real training task that takes several weeks. Summary of the Invention
[0003] This application provides an artificial intelligence chip and a debugging method, which enables in-depth insight into the runtime state of the artificial intelligence chip and provides powerful tool support for hardware debugging, performance analysis and software optimization.
[0004] In a first aspect, embodiments of this application provide an artificial intelligence chip, including: a debugging module, a data scheduling module, a storage module, an interrupt control module, and multiple core processing modules;
[0005] The data scheduling module, the storage module, and the multiple core processing modules are configured to provide multiple key signals to the debugging module in real time.
[0006] The interrupt control module is configured to send a trigger command to the debugging module when an error event is detected.
[0007] The debugging module is configured to acquire the multiple key signals from the target module in real time, encapsulate the multiple key signals into multiple data packets, configure corresponding address information for the multiple data packets, transmit the multiple data packets with the address information to the storage module through the data scheduling module, and stop providing the data packets to the storage module in response to a trigger command; wherein, the target module represents one or more modules of the data scheduling module, the storage module, and the core processing module; the address information is used to indicate the storage location of the data packets in the storage module; the key signals are used to indicate the real-time status information of the target module during operation;
[0008] The storage module is used to store the multiple data packets according to the address information.
[0009] In some embodiments, the debugging module is further configured to, in response to the trigger command, control the provision of a preset number or a preset time of the data packets to the storage module.
[0010] In some embodiments, the debugging module is further configured to acquire the plurality of key signals according to preset capture information; wherein the preset capture information includes bit width information of the captured key signals and enable information for capturing the key signals.
[0011] In some embodiments, the debugging module is further configured to encapsulate the plurality of data packets into a fixed-length data frame; wherein the data packets contain a module identifier of the key signal and a program segment identifier of the key signal; the data frame contains a frame header, the frame header including time information and sideband information.
[0012] In some embodiments, the storage module includes N storage units that can be used to store the data packets, and each storage unit corresponds to an address; N is a preset value;
[0013] The debugging module is further configured to configure an address information for the data frame. After determining that the Nth address information has been configured to a certain data frame, the N address information is reconfigured to the newly received data frame in a preset order.
[0014] In some embodiments, the storage module is further configured to, when storing the data frame according to the address information, if the storage unit corresponding to any address information includes a historical data frame, delete the historical data frame and store the newly received data frame in the storage unit corresponding to the address information.
[0015] In some embodiments, the core processing module further includes: key signals in the core processing module include: instruction information being executed by the core processing module, operand information of the core processing module, intermediate result information of the core processing module, and pipeline status information of the core processing module;
[0016] The key signals in the data scheduling module include: the incomplete request counter information of the data scheduling module, the routing status information of the data scheduling module, and the congestion level information of the data scheduling module.
[0017] The key signals in the storage module include: the accessed address sequence information of the storage module and the access type information of the storage module.
[0018] Secondly, embodiments of this application provide a debugging method for an artificial intelligence chip, including:
[0019] Provides multiple key signals in real time;
[0020] The multiple key signals are acquired in real time from the target module and encapsulated into multiple data packets; wherein, the key signals are used to indicate the real-time status information of the target module during operation; the target module represents one or more modules of the artificial intelligence chip;
[0021] Configure corresponding address information for the multiple data packets, and transmit the multiple data packets with the address information to the storage module through the data scheduling module; wherein, the address information is used to indicate the storage location of the data packets in the storage module;
[0022] The plurality of data packets are stored in the storage module according to the address information;
[0023] When an error event is detected, a trigger command is sent;
[0024] The trigger command will stop the delivery of the data packet to the storage module.
[0025] In some embodiments, the method further includes: in response to the triggering instruction, controlling the provision of a preset number or a preset time of the data packets to the storage module.
[0026] Thirdly, embodiments of this application provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the above-described debugging method.
[0027] In this embodiment, through the cooperation of a debugging module, a data scheduling module, a storage module, an interrupt control module, and multiple core processing modules, multiple key signals in the target module are acquired in real time. These key signals are then encapsulated into multiple data packets, which are transmitted to the storage module via the data scheduling module. The storage module stores these data packets. This is equivalent to backing up key signals through the chip's internal storage module, resulting in a consistency between the reproduction time and the actual running time. This is much simpler than existing accelerator simulations and solves the problem of difficulty in reproducing faults that occur during long-term chip operation. Furthermore, backing up key signals in real time facilitates comprehensive real-time monitoring of the chip's internal state, which is beneficial for identifying non-static faults within the chip. This is particularly effective for diagnosing complex faults that require complete context for understanding (such as race conditions, timing-related errors, etc.).
[0028] Furthermore, since key signals are stored in the chip's internal storage module, i.e., the chip's internal storage module is reused, no additional space is required within the chip, resulting in low area cost; and the large bandwidth within the chip allows for precise storage of key signals, which facilitates subsequent analysis to identify faults. Attached Figure Description
[0029] Figure 1 This application provides schematic diagrams of the structures of some artificial intelligence chips in its embodiments.
[0030] Figure 2 Schematic diagrams of other artificial intelligence chips provided in the embodiments of this application;
[0031] Figure 3 This application provides further structural schematic diagrams of some artificial intelligence chips in its embodiments;
[0032] Figure 4 This application provides further structural schematic diagrams of some artificial intelligence chips in its embodiments;
[0033] Figure 5 A flowchart illustrating some debugging methods for artificial intelligence chips provided in the embodiments of this application;
[0034] Figure 6 The diagram shows the structure of some electronic devices provided in the embodiments of this application. Detailed Implementation
[0035] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Furthermore, the embodiments and features in the embodiments of this application can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this application without creative effort are within the scope of protection of this application.
[0036] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Furthermore, in the description of the embodiments in this application, unless otherwise stated, "a plurality of" means two or more.
[0037] In the actual operation of AI chips, if a fault (bug) occurs within a short period of time, the operation process can generally be reproduced using accelerometer simulation waveforms to identify the fault. However, if a fault occurs after a long period of operation, it becomes very difficult to reproduce the operation process using accelerometer simulation waveforms, making fault identification challenging. For example, the ratio of the actual chip operation time to the accelerometer simulation time is typically 1:1000; that is, if the chip operates for 1 second, the accelerometer needs to run for 1000 seconds. If the fault occurs after 1 minute of chip operation, accelerometer simulation reproduction can be used, but in this case, the accelerometer may need to run for 1000 minutes to identify the fault. If the fault occurs after 1 day of chip operation, accelerometer simulation reproduction may require 1000 days to identify the fault, making this method of reproduction clearly impractical. In other words, accelerometer simulation waveforms are unlikely to identify faults that occur within the chip over a long period of time.
[0038] Furthermore, although there are readable registers inside the chip to check the program running status, the readable registers are relatively static, and it is difficult to find the specific cause of the fault in real time through the readable registers. In other words, the readable registers are difficult to use to find non-static faults inside the chip.
[0039] Based on the above problems, this application provides an artificial intelligence chip 100, such as... Figure 1 As shown, it includes: a debugging module 10, a data scheduling module 20, a storage module 30, an interrupt control module 40, and multiple core processing modules 50;
[0040] The data scheduling module 20, storage module 30, and multiple core processing modules 50 are configured to provide multiple key signals to the debugging module 10 in real time;
[0041] The interrupt control module 40 is configured to send a trigger command to the debug module 10 when an error event is detected.
[0042] The debugging module 10 is configured to acquire multiple key signals from the target module in real time, encapsulate the key signals into multiple data packets, configure corresponding address information for the multiple data packets, transmit the multiple data packets with address information to the storage module 30 through the data scheduling module 20, and stop providing data packets to the storage module 30 in response to a trigger command; wherein, the target module represents one or more modules of the data scheduling module 20, the storage module 30, and the core processing module 50; the address information is used to indicate the storage location of the data packets in the storage module; the key signals are used to indicate the real-time status information of the target module during operation;
[0043] The storage module 30 is used to store multiple data packets according to address information.
[0044] This application embodiment utilizes the cooperation of a debugging module, a data scheduling module, a storage module, an interrupt control module, and multiple core processing modules to acquire multiple key signals from the target module in real time. These key signals are then encapsulated into multiple data packets, which are transmitted to the storage module via the data scheduling module. The storage module stores these data packets. This is equivalent to backing up key signals through the chip's internal storage module, resulting in a consistency between the reproduction time and the actual running time. This is much simpler than existing accelerator simulations and solves the problem of difficulty in reproducing faults that occur during long-term chip operation. Furthermore, the real-time backup of key signals facilitates comprehensive real-time monitoring of the chip's internal state, which is beneficial for identifying non-static faults within the chip. This is particularly effective for diagnosing complex faults that require complete context for understanding (such as race conditions, timing-related errors, etc.).
[0045] Furthermore, since key signals are stored in the chip's internal storage module, i.e., the chip's internal storage module is reused, no additional space is required within the chip, resulting in low area cost; and the large bandwidth within the chip allows for precise storage of key signals, which facilitates subsequent analysis to identify faults.
[0046] For example, such as Figure 2 As shown, the debugging module 10 may specifically include: an arbitration unit 101, an encapsulation unit 102, and a control unit 103;
[0047] The arbitration unit 101 is used to receive instructions sent by the processor 200, determine the target module according to the instructions, capture multiple key signals in the target module in real time, and send the multiple key signals to the packaging unit 102.
[0048] The encapsulation unit 102 is used to receive multiple key signals and encapsulate the multiple key signals. While encapsulating each key signal into a data packet, it adds the module identifier and program segment identifier of the key signal and sends the multiple data packets to the control unit 103.
[0049] The control unit 103 is used to receive multiple data packets and configure corresponding address information for the multiple data packets, and transmit the multiple data packets with address information to the storage module 30 through the data scheduling module 20; and the control unit 103 is also used to stop providing data packets to the storage module 30 in response to a trigger command.
[0050] For example, when the interrupt control module 40 detects an error event, it will interrupt the operation and simultaneously send a trigger command to the control unit 103.
[0051] It should be noted that the trigger command is not limited to being provided by the interrupt control module. The trigger command can also be sent by the user through software. For example, when the chip is running a certain program instruction, the interrupt control module does not detect an error event, but the user wants to know the current operating status of certain modules in the chip. Therefore, the user can send a trigger command to the control unit of the debugging module through software.
[0052] For example, such as Figure 1 and Figure 2 As shown, it may also include a processor 200; wherein, the processor 200 includes a central processing unit (CPU), etc., which are not specifically limited here; the user can select an arbitration mode through the processor 200 according to actual needs, wherein the arbitration mode includes: single module mode and polling mode; if the single module mode is selected, the processor 200 issues an instruction to instruct the arbitration unit 101 to capture key signals from a specified target module in real time; if the polling mode is selected, the processor 200 issues an instruction to instruct the arbitration unit 101 to capture key signals from some specified target modules in turn according to time slices.
[0053] For example, the artificial intelligence chip 100 may include a graphics processing unit (GPU), a general-purpose graphics processing unit (GPGPU), a domain-specific architecture (DSA), etc., without being specifically limited here.
[0054] In some embodiments of this application, the debugging module 10 is further configured to control the provision of a preset number or preset time of data packets to the storage module in response to a trigger command.
[0055] This application sets the debugging module to respond to trigger commands and controls the supply of a preset number or preset time of data packets to the storage module. This ensures that the data packets in the storage module can contain complete key signals before and after the trigger, which further facilitates analysis by relevant personnel based on the data packets.
[0056] For example, the preset quantity or preset time can be set according to requirements. For instance, if the preset quantity is set to 50, the control unit 103 in the debugging module 10 will respond to the trigger command and determine the preset quantity as 50 based on the information in the trigger command. Then, the control unit 103 will control the transmission of 50 data packets to the storage module 30 through the data scheduling module 20, and then stop providing data packets to the storage module 30. For instance, if the preset time is set to a certain time period, the control unit 103 in the debugging module 10 will respond to the trigger command and determine the time period based on the information in the trigger command. Then, the control unit 103 will control the transmission of data packets within the time period to the storage module 30 through the data scheduling module 20, and then stop providing data packets to the storage module 30.
[0057] In some embodiments of this application, the debugging module 10 is further configured to acquire multiple key signals according to preset capture information; wherein, the preset capture information includes the bit width information of the captured key signals and the enable information of the captured key signals.
[0058] For example, the bit width information of the critical signal represents the bit width of the critical signal that needs to be captured, and the enable information of the critical signal represents when to start capturing the critical signal.
[0059] It should be noted that the captured key signal may have many bits, but during debugging, only a part of the key signal may be needed. In this case, the bit width can be configured to capture only the part of interest, thereby improving the capture efficiency. Since capturing only the part of interest can reduce the data packet size, storage space and transmission bandwidth can be saved.
[0060] For example, the bit width configuration of the key signal may include: full bit width mode, indicating the capture of the full bit width of the key signal; 32-bit mode, capturing the lower 32 bits of the key signal; 64-bit mode, capturing the lower 64 bits of the key signal; and a custom bit selection mode, selecting to capture a specific bit segment of the key signal. Of course, the bit width configuration of the key signal may have other modes, such as a 16-bit mode, capturing the lower 16 bits of the key signal, which is not specifically limited here. Figure 2 As shown, the bit width configuration can be set by the processor 200, which sends instructions about the bit width configuration mode to the arbitration unit 101.
[0061] It should be noted that certain key signals need to be captured at different times. Therefore, it is necessary to set the enable information for key signals so that the arbitration unit can determine whether to capture the key signal based on its current state. For example, if the key signals include handshake signals, which include Valid and Ready signals, and if only the key signal of successful transmission is of concern, then the capture of the key signal should begin when both the Valid and Ready signals are valid. If only whether the sender is blocked is of concern, then the capture of the key signal should begin when the Valid signal is valid, regardless of whether the Ready signal is valid.
[0062] For example, the enabling configuration of the critical signal may include: a first mode, where capturing the critical signal begins when the Valid signal is valid; a second mode, where capturing the critical signal begins when both the Valid and Ready signals are valid; of course, the enabling configuration of the critical signal may have other modes, such as a third mode, where capturing the critical signal begins when the Ready signal is valid, which is not specifically limited here; wherein, such as Figure 2 As shown, the enable configuration of the critical signal can be set by the processor 200, and the processor 200 sends an instruction on the enable configuration mode of the critical signal to the arbitration unit 101.
[0063] In some embodiments of this application, the debugging module 10 is further configured to encapsulate multiple data packets into a fixed-length data frame; wherein the data packets contain module identifiers of key signals and program segment identifiers of key signals; the data frame contains a frame header, which includes time information and sideband information.
[0064] For example, the module identifier (Client id) is used to indicate which module's key signal it is, and the program segment identifier (Kernel id) is used to indicate what program the target module is running.
[0065] For example, the length of multiple data packets in each data frame is pre-designed, such as 32 bytes. This means that regardless of the actual amount of data in the critical signal, it will be packaged into this fixed length. The length of the data packets can be designed according to requirements. For instance, if the actual critical signal is only 4 bits, it will still be packaged into 32 bytes; if the actual critical signal is 128 bits, it will be truncated or split to fit the 32-byte limit. Furthermore, the length of the data frame is also pre-designed, and the specific length of the data frame can be designed based on how much data the data scheduling module can transmit at once.
[0066] For example, the frame header can be used for sorting data frames, and the time information in the frame header can be used to record the clock cycle when key signals are acquired; the sideband information contains some other necessary information, which is not specifically limited here.
[0067] In some embodiments of this application, such as Figure 3 As shown, the storage module 30 includes N storage units 301 that can be used to store data packets, and each storage unit 301 corresponds to an address information; N is a preset value;
[0068] The debugging module 10 is further configured to configure an address information for a data frame. After determining that the Nth address information has been configured to a certain data frame, the N address information is reconfigured to the newly received data frame in a preset order.
[0069] For example, such as Figure 3 As shown, the storage module 30 has multiple storage units 301, of which N storage units 301 are specifically used to store data packets, and the specific number can be set according to requirements.
[0070] For example, the control unit 103 in the debugging module 10 can configure an address information for each data frame, and then the data frame can be stored in the corresponding storage unit 301 according to the address information. Since the number of storage units 301 used to store data packets is limited, for example, N is 30, then there are 30 address information, such as address 1, address 2, address 3... address 30. Therefore, after the control unit 103 determines that the 30th address information (e.g., address 30) has been configured to a certain data frame, it will reconfigure the 30 address information (e.g., address 1, address 2, address 3... address 30) to the newly received data frame in the preset order of the 30 address information (e.g., address 1, address 2, address 3... address 30). That is, the address information can be reused.
[0071] In some embodiments of this application, the storage module 30 is further configured to, when storing data frames according to address information, if the storage unit 301 corresponding to any address information includes historical data frames, delete the historical data frames and store the newly received data frames in the storage unit corresponding to any address information.
[0072] This storage module configuration allows newly received data frames to overwrite historical data frames, meaning the data packets stored in the storage module can be updated in real time, thus ensuring that users can analyze key signals based on the latest data frames.
[0073] In some embodiments of this application, key signals in the core processing module 50 include: instruction information being executed by the core processing module, operand information of the core processing module, intermediate result information of the core processing module, and pipeline status information of the core processing module.
[0074] Key signals in the data scheduling module 20 include: the incomplete request counter information of the data scheduling module, the routing status information of the data scheduling module, and the congestion level information of the data scheduling module;
[0075] The key signals in storage module 30 include: the accessed address sequence information of the storage module and the access type information of the storage module.
[0076] The following will be based on Figures 1 to 4 Taking the structure diagram of the artificial intelligence chip shown as an example, the overall workflow will be explained:
[0077] When an AI chip executes a program instruction, a malfunction may occur. To avoid being unable to find the specific cause of the malfunction, the processor sends an instruction to the debugging module when the AI chip executes a program instruction, and then the various modules in the debugging module start working.
[0078] When executing the program instructions, the user initially judges that the core processing module 50 is likely to malfunction. Therefore, the user selects the single-module mode through the processor 200, that is, instructs the arbitration unit 101 in the debugging module 10 to capture the key signals in the core processing module 50; and the user sends preset capture information to the arbitration unit 101 through the processor 200; then the arbitration unit 101 can obtain multiple key signals in the core processing module 50 according to the preset capture information.
[0079] The encapsulation unit 102 receives multiple key signals from the core processing module 50 and encapsulates the multiple key signals. While encapsulating each key signal into a data packet, it adds the module identifier and program segment identifier of the key signal, and encapsulates the multiple data packets into a fixed-length data frame, and configures a frame header for the data frame.
[0080] The control unit 103 receives data frames and configures an address information for each data frame. The data frame with the address information is then transmitted to the storage unit 301 in the storage module 30 through the data scheduling module 20. Each data frame can then be stored in the corresponding storage unit 301 according to the address information.
[0081] When the control unit 103 receives a trigger command (which can be sent by the interrupt control module or by the user via software), the control unit 103 can decide, based on the information carried in the trigger command, whether to immediately stop transmitting data frames with address information to the storage unit 301 in the storage module 30 through the data scheduling module 20; or to decide, after providing a preset number or preset time of data frames to the storage unit 301 in the storage module, to stop transmitting data frames with address information to the storage unit 301 in the storage module 30 through the data scheduling module 20.
[0082] End users can retrieve data frames from multiple storage units 301 in real time according to the actual situation, and make judgments and analyses based on multiple key signals in the data frames to find the cause of the fault.
[0083] This application embodiment, through the cooperation of the debugging module, data scheduling module, and storage module, can build a complete observation, capture, and storage pipeline system inside the chip, realizing a deep insight into the chip's runtime state and providing powerful tool support for hardware debugging, performance analysis, and software optimization.
[0084] Based on the same technical concept, embodiments of this application also provide a debugging method for an artificial intelligence chip, such as... Figure 5 As shown, it includes:
[0085] S100 provides multiple key signals in real time;
[0086] S200: Obtain multiple key signals from the target module in real time and encapsulate the multiple key signals into multiple data packets;
[0087] Specifically, key signals are used to indicate the real-time status information of the target module during operation; the target module represents one or more modules in the artificial intelligence chip;
[0088] S300: Configure corresponding address information for multiple data packets, and transmit the multiple data packets with address information to the storage module through the data scheduling module;
[0089] Specifically, the address information is used to indicate the storage location of the data packet in the storage module;
[0090] S400: Store multiple data packets in the storage module according to their address information;
[0091] S500: When an error event is detected, a trigger command is sent.
[0092] S600, stop providing data packets to the storage module according to the trigger command.
[0093] In some embodiments of this application, it further includes: in response to a trigger command, controlling the provision of a preset number or preset time of data packets to the storage module.
[0094] Based on the same technical concept, this application also provides an electronic device, such as... Figure 6 As shown, electronic devices can perform the functions of the aforementioned artificial intelligence chips;
[0095] Specifically, it includes at least one artificial intelligence chip 100 and a memory 300 connected to at least one artificial intelligence chip 100. In this embodiment, the specific connection medium between the artificial intelligence chip 100 and the memory 300 is not limited. Figure 6 Taking the connection between the AI chip 100 and the memory 300 via a bus as an example, the bus can be divided into address bus, data bus, control bus, etc.
[0096] In this embodiment, the memory 300 stores instructions that can be executed by at least one artificial intelligence chip 100. By executing the instructions stored in the memory 300, the at least one artificial intelligence chip 100 can perform the steps of the above-described debugging method.
[0097] Among them, the artificial intelligence chip 100 is the control center of the computer device. It can connect to various parts of the computer device through various interfaces and lines. By running or executing instructions stored in the memory 300 and calling data stored in the memory 300, it can control the operation of various modules.
[0098] Optionally, the artificial intelligence chip 100 may include one or more processing modules. The artificial intelligence chip 100 may integrate an application processor and a modem processor, wherein the application processor primarily handles the operating system, user interface, and applications, while the modem processor primarily handles wireless communication. It is understood that the modem processor may not be integrated into the artificial intelligence chip 100. In some embodiments, the artificial intelligence chip 100 and the memory 300 may be implemented on the same chip; in some embodiments, they may be implemented separately on independent chips.
[0099] The artificial intelligence chip 100 may include a general-purpose processor, such as a central processing unit, a general-purpose image processor, a digital signal processor, an application-specific integrated circuit (ASIC), a field-programmable gate array or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules in the processor.
[0100] Memory 300, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. Memory 300 may include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card-type memory, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic storage, magnetic disk, optical disk, etc. Memory 300 can be any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer device, but is not limited thereto. In the embodiments of this application, memory 300 may also be a circuit or any other device capable of implementing storage functions for storing program instructions and / or data.
[0101] Based on the same inventive concept, embodiments of this application provide a computer-readable storage medium storing a computer program executable by a computer device, which, when run on the computer device, causes the computer device to perform the steps of the above-described debugging method.
[0102] Those skilled in the art will understand that embodiments of this application can be provided as methods or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0103] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer apparatus or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0104] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer device or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0105] These computer program instructions may also be loaded onto a computer device or other programmable data processing equipment to cause a series of operational steps to be performed on the computer device or other programmable equipment to produce a process implemented by the computer device, thereby providing instructions that execute on the computer device or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0106] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.
[0107] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.
Claims
1. An artificial intelligence chip, characterized in that, include: The system includes a debugging module, a data scheduling module, a storage module, an interrupt control module, and several core processing modules. The data scheduling module, the storage module, and the multiple core processing modules are configured to provide multiple key signals to the debugging module in real time. The debugging module includes: an arbitration unit, a packaging unit, and a control unit; The arbitration unit is configured to determine a target module according to user instructions and acquire the multiple key signals from the target module in real time. The target module represents one or more modules of the data scheduling module, the storage module, and the core processing module. The key signals are used to indicate the real-time status information of the target module during operation. The encapsulation unit is configured to receive the plurality of key signals and encapsulate the plurality of key signals into a plurality of data packets; The control unit is configured to assign corresponding address information to the plurality of data packets and transmit the plurality of data packets with the address information to the storage module through the data scheduling module; wherein, the address information is used to indicate the storage location of the data packets in the storage module; The storage module is used to cyclically store the multiple data packets according to the address information, so as to back up the multiple key signals in real time; The interrupt control module is configured to send a trigger command to the control unit in the debugging module when an error event is detected. The control unit is also configured to stop providing the data packet to the storage module in response to the trigger command.
2. The artificial intelligence chip as described in claim 1, characterized in that, The debugging module is further configured to respond to the trigger command by controlling the provision of a preset number or preset time of the data packets to the storage module.
3. The artificial intelligence chip as described in claim 2, characterized in that, The debugging module is further configured to acquire the plurality of key signals according to preset capture information; wherein, the preset capture information includes the bit width information of the captured key signals and the enable information for capturing the key signals.
4. The artificial intelligence chip as described in any one of claims 1-3, characterized in that, The debugging module is further configured to encapsulate the plurality of data packets into a fixed-length data frame; wherein the data packet contains the module identifier of the key signal and the program segment identifier of the key signal; the data frame contains a frame header, the frame header including time information and sideband information.
5. The artificial intelligence chip as described in claim 4, characterized in that, The storage module includes N storage units that can be used to store the data packets, and each storage unit corresponds to one address information; N is a preset value; The debugging module is further configured to configure an address information for the data frame. After determining that the Nth address information has been configured to a certain data frame, the N address information is reconfigured to the newly received data frame in a preset order.
6. The artificial intelligence chip as described in claim 5, characterized in that, The storage module is further configured to, when storing the data frame according to the address information, if the storage unit corresponding to any address information includes a historical data frame, delete the historical data frame and store the newly received data frame in the storage unit corresponding to the address information.
7. The artificial intelligence chip as described in any one of claims 1-3, characterized in that, The key signals in the core processing module include: the instruction information being executed by the core processing module, the operand information of the core processing module, the intermediate result information of the core processing module, and the pipeline status information of the core processing module. The key signals in the data scheduling module include: the incomplete request counter information of the data scheduling module, the routing status information of the data scheduling module, and the congestion level information of the data scheduling module. The key signals in the storage module include: the accessed address sequence information of the storage module and the access type information of the storage module.
8. A debugging method for an artificial intelligence chip, characterized in that, include: Provide multiple key signals to the debugging module in real time; The target module is determined according to user instructions, and the multiple key signals are obtained from the target module in real time. The target module represents one or more modules of the data scheduling module, storage module, and core processing module. The key signals are used to indicate the real-time status information of the target module during operation. Receive the multiple key signals and encapsulate the multiple key signals into multiple data packets; The multiple data packets are configured with corresponding address information, and the multiple data packets with the address information are transmitted to the storage module through the data scheduling module; wherein, the address information is used to indicate the storage location of the data packets in the storage module; The multiple data packets are stored cyclically according to the address information in order to back up the multiple key signals in real time. When an error event is detected, a trigger command is sent to the control unit in the debugging module; In response to the trigger command, the provision of the data packet to the storage module is stopped.
9. The debugging method as described in claim 8, characterized in that, Also includes: In response to the trigger command, the system controls the supply of a preset number or a preset time of data packets to the storage module.
10. An electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the debugging method as described in claim 8 or 9.