Configurable cache structure, access method thereof and MCU (Microprogrammed Control Unit) chip

Abstract

The invention relates to the technical field of caches, and discloses a configurable cache structure and an access method thereof, and an MCU chip, the configurable cache structure comprises: a system SRAM space including an application storage space and an instruction or data cache space, the instruction or data cache space including a cache line storage space and a tag storage space, the cache line storage space is used for storing instructions or data, the label storage space is used for storing label information of the high-speed cache line, and the label is used for uniquely identifying the corresponding cache line; the function register configures initial addresses and space sizes of a cache line storage space and a tag storage space in a system SRAM (Static Random Access Memory) storage space; the access address judgment unit is used for judging whether an access address belongs to a cacheable space or not, and selecting to access a cache space or directly access a target address according to a judgment result, so that the cache can be flexibly configured and dynamically adjusted, the performance is improved, and the SRAM resource utilization of the system is optimized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of cache, in particular to a configurable cache structure and an access method thereof and an MCU chip. BACKGROUND

[0002] A microcontroller unit (MCU) is a highly integrated chip designed for embedded systems, integrating processor cores, memory, peripheral interfaces and functional modules into a single chip, and is widely used in smart home, industrial control, automotive electronics and other fields.

[0003] The instruction cache (ICache) of the MCU usually adopts a fixed architecture, and the core implementation specifications such as cache capacity (usually small capacity such as 4KB / 8KB), cache line length and cache line quantity are pre-set fixed, and special storage spaces (such as CacheLine SRAM, Tag SRAM, and some contain LRU SRAM) are provided. Such special storage is only used to store cache-related data and does not belong to the system general SRAM, and software cannot access it. Although this fixed architecture can achieve good performance for some applications, it has obvious limitations in adaptability: because the architecture parameters cannot be adjusted, the performance difference is significant when facing different types of applications, and it is difficult to achieve high-quality performance coverage for all or most applications.

[0004] At the same time, the area of the MCU chip is strictly limited, and the cache capacity is generally small, which further aggravates the limitations of performance adaptation: the same fixed capacity cache may be efficient when adapting to a certain type of application, but the performance will drop significantly when switching to another type of application, ultimately resulting in weak universality of the MCU with fixed cache capacity, and it is difficult to meet the performance requirements of diversified application scenarios. SUMMARY

[0005] Therefore, in order to improve the overall performance and universality of the MCU, the present application provides a configurable cache structure and an access method thereof and an MCU chip, which can flexibly configure the key architecture indicators of the cache according to the running characteristics of the application program, so as to optimize the running performance of the application program, and improve the overall performance, universality and applicable scenarios of the MCU.

[0006] In a first aspect, the present application provides a configurable cache structure, comprising: The system SRAM space includes an application storage space and an instruction or data cache space, the instruction or data cache space includes a cache line storage space for storing instructions or data and a tag storage space for storing tag information of the cache line, and the tag is used for uniquely identifying the corresponding cache line. A function register is configured to configure a starting address and a space size of the cache line storage space and the tag storage space in the system SRAM storage space. An access address judgment unit is configured to judge whether an access address belongs to a cacheable space, and select to access the cache space or directly access a target address according to a judgment result. The configurable cache structure provided by the embodiment of the application divides the system SRAM space into an application storage space and an instruction / data cache space, does not depend on a Cache special SRAM, fully utilizes system general storage resources, avoids waste caused by special storage idling, and is especially suitable for a scenario in which an MCU chip area is limited and storage resources are nervous. The starting address and the space size of the cache line storage space and the tag storage space can be flexibly configured through the function register, storage resources can be dynamically allocated according to cache capacity requirements of different applications, the problem that a traditional fixed architecture Cache cannot adapt to diversified storage requirements is solved, the access address judgment unit can quickly distinguish between a cacheable space and a non-cacheable space, the cacheable space directly accesses the cache, the non-cacheable space directly accesses the target address, invalid cache operations are avoided, CPU waiting time is reduced, and the overall operation efficiency of the MCU is improved. In an optional embodiment, the function register includes: A cache line number register is configured to configure a number M of cache lines. A cache line length register is configured to configure a length L of the cache line, and a total capacity of the cache line storage space is MxL. A cache line starting address register is configured to configure a starting address of the cache line storage space. A tag starting address register is configured to configure a starting address of the tag storage space.

[0007] Embodiments of the present application realize accurate control of cache core parameters through a special register, and the number of cache lines register and the length register can flexibly adjust the number M and the length L, thereby defining the total capacity (MxL) of the cache storage, which can adapt to the locality characteristics of different applications, such as configuring short cache lines for applications with more loop instructions, and configuring long cache lines for applications with more continuous instructions. The cache line and the tag start address register can explicitly specify the specific location of the two types of storage spaces in the system SRAM, support allocation to any available area, avoid conflict with application storage, and improve the rationality and safety of space allocation. In addition, developers do not need to adjust the application code due to the fixed cache parameters of the MCU, and can match the requirements only by configuring the register, which greatly reduces the development cycle and debugging cost, and improves the universality of the MCU for different applications.

[0008] In an optional embodiment, the structure further comprises an access hit judgment unit configured to perform tag comparison according to a currently accessed cacheable space address to determine whether a cache access hits, and read corresponding data from the cache line storage space when the tag comparison matches.

[0009] The access hit judgment unit of the embodiment of the present application accurately identifies whether the current access address is cached through the tag comparison mechanism, avoids blind access of the CPU to the main memory, reduces memory access delay, and verifies the source of the cache data during the tag comparison process. Only when the tags match, the cache line data is read to prevent instruction / data errors caused by mismatch between data and target address, and to ensure stable and reliable operation of the MCU. At the same time, efficient hit judgment can maximize the use of effective cache data, reduce the dependence of the CPU on the main memory, significantly improve the instruction execution efficiency in the scenario where the main memory speed of the MCU is slow, and effectively alleviate the main memory bandwidth pressure. In an optional embodiment, the access hit judgment unit further comprises a tag buffer configured to cache tag information of part of the tag storage space, the tag information comprising a tag value; and the access hit judgment unit is configured to access the cache line storage space when the tag comparison of the tag buffer matches, and otherwise access the tag storage space for tag comparison.

[0010] The tag buffer in the embodiment of the application caches part of the tag information with high frequency access, and when the CPU accesses these high frequency addresses, the tag comparison can be completed directly in the tag buffer, and if matched, there is no need to access the tag storage space, and the access to the cache line is completed in the next clock cycle, so that the cache access latency is reduced from 2 cycles of “accessing the tag SRAM + accessing the cache line SRAM” to 1 cycle, and the speed of CPU instruction and data acquisition is greatly improved. The high frequency tag information is processed in the tag buffer, repeated access to the tag storage space is reduced, the SRAM read-write power consumption is reduced, and the design requirement of the ultra-low power MCU is particularly suitable, and the device endurance time is prolonged. Moreover, all the tag information does not need to be stored in the tag buffer, and only the high frequency data is cached, so that the balance between performance improvement and cost control is realized while the high hit rate is ensured, and the chip area increase caused by the excessive size of the tag buffer is avoided.

[0011] In an optional embodiment, when the tag comparison matching is performed by accessing the tag storage space, the cache line storage space is accessed, and when the tag comparison matching is not performed, it is determined that the cache access is a miss.

[0012] In the embodiment of the application, when the tag buffer does not match, the secondary comparison is performed by accessing the tag storage space, so that the “false miss” caused by the fact that the tag buffer does not cover all tags is avoided, the comprehensiveness of the cache hit determination is ensured, and unnecessary main memory access is reduced. Only when the tag storage space comparison also does not match, it is determined that the cache access is a miss, so that the effective data stored in the cache can be maximized, the cache resource waste caused by the local tag buffer loss is avoided, and the cache utilization rate is improved. At the same time, the two-level judgment logic of “tag buffer - tag storage space” is clear, the standardized hit determination process is formed, the memory access exception caused by the confusion of the judgment logic is avoided, the continuity of the MCU instruction execution is ensured, and strong support is provided for stable operation.

[0013] In an optional embodiment, the structure further includes: The replacement control unit is configured to load the missing cache line into the cache line storage space and update the tag information of the tag storage space and the tag buffer when the cache access is a miss; The bus interface unit is configured to access the next level storage space when the replacement control unit loads the missing cache line.

[0014] The replacement control unit of the embodiment of the present application automatically triggers loading of the missing cache line and tag update when a cache miss occurs, without intervention of the CPU, thereby reducing CPU waiting time. For example, when the CPU accesses a new instruction or data address, the replacement control unit can complete main memory loading and cache writing in parallel, thereby reducing CPU waiting time. After loading the missing cache line, the tag storage space and the tag cache are updated synchronously, thereby ensuring that subsequent access to the address can be quickly hit, avoiding repeated cache miss, and improving long-term use efficiency of the cache. In addition, the bus interface unit is responsible for interaction with the next level of storage space, and the CPU does not need to directly process details of main memory access, thereby reducing hardware complexity and software control difficulty of the CPU, so that the CPU can focus on core functions of instruction execution.

[0015] In an alternative embodiment, the structure further comprises: The SRAM access control unit is configured to calculate access addresses of the cache line storage space and the tag storage space according to the configured start address, and to realize read and write operations of cache data. The SRAM access control unit calculates access addresses of the cache line storage space and the tag storage space according to the configured start address, comprising: When reading the tag, the address in the tag storage space corresponding to the current access address is calculated according to the index in the current access address, and the calculation formula is: tag storage space address = start address of the tag storage space in the system SRAM space + index of the access address; When reading the cache data, the address in the cache line storage space corresponding to the current access address is calculated according to the index information and the offset address in the current access address, and the calculation formula is: cache line storage space address = start address of the cache line storage space in the system SRAM space + cache line index × length of the cache line + offset address; When updating the tag of the cache line, the address in the tag storage space corresponding to the index information of the access address when the cache miss occurs is calculated, and the calculation formula is: tag storage space address = start address of the tag storage space in the system SRAM space + index of the access address; When updating the data of the cache line, the address in the cache line storage space is calculated according to the index information and the offset address of the access address when the cache miss occurs, and the calculation formula is: cache line storage space address = starting address of the cache line storage space in the system SRAM space + cache line index * length of the cache line + offset address. According to different access operations and the calculated SRAM access address, the corresponding access operation is completed, including: loading the missing cache line data to the calculated cache line storage space address, or writing the new cache line data back to the corresponding lower address space, wherein the new cache line data is the data written by the CPU. Through the explicit address calculation formula, combined with the configured starting address, index, offset and the like, the access address of the tag storage space and the cache line storage space is accurately calculated, the storage access exception caused by incorrect address calculation is avoided, and the accuracy of cache reading and writing is ensured. The configurable parameters such as the number of cache lines and the length are integrated in the formula, and when these parameters are adjusted (such as changing the cache line length from 16 bytes to 32 bytes), the address calculation can be automatically adapted without modifying the hardware logic, which significantly improves the flexibility and scalability of the cache architecture. At the same time, the standardized address calculation logic can be realized by a simple hardware circuit without a complex control unit, which reduces the chip design difficulty and area cost, and is especially suitable for scenes sensitive to hardware complexity such as MCUs.

[0016] In a second aspect, the application provides an access method of a configurable cache structure, comprising: configuring the starting addresses and space sizes of the cache line storage space and the tag storage space in the system SRAM storage space through a function register; judging whether the address to be accessed belongs to the cacheable space through an access address judgment unit, and selecting to access the cache space or directly access the target address according to the judgment result.

[0017] The access method of the configurable cache structure provided by the embodiment of the application can enable the developer to complete the cache storage area setting through the configuration of the function register, without modifying the hardware circuit or the underlying driver, simplify the cache configuration process, and greatly shorten the application adaptation period. According to the storage requirements of different applications, the cache space size and position can be dynamically adjusted through the register, the limitation of traditional fixed cache on application scenarios is avoided, and the universality of the MCU is significantly improved. Moreover, the access address judgment unit automatically selects the memory access path, and the developer does not need to manually control the "cache access / direct access", which reduces the software control logic, reduces the risk of human operation errors, and ensures the stability and efficiency of the memory access process.

[0018] In an optional embodiment, the method further comprises: The tag comparison is performed by the access hit judgment unit based on the current access address to determine whether the cache access hits, and when the cache access hits, the corresponding data is read from the cache line storage space, and when the cache access does not hit, it is determined that the cache line is missing.

[0019] The tag comparison is performed by the access hit judgment unit based on the current access address to determine whether the cache access hits, and when the cache access hits, the corresponding data is read from the cache line storage space, and when the cache access does not hit, it is determined that the cache line is missing.

[0020] In an optional embodiment, the tag comparison is performed by the access hit judgment unit based on the current access address to determine whether the cache access hits, including: performing tag comparison by accessing a tag cache, the tag cache being used to cache tag information of part of a tag storage space, and if the tag comparison result is a match, the data of the cache line storage space is accessed; when the tag cache access does not match, tag comparison is performed by accessing a tag storage space, and if the tag comparison result is a match, the data of the cache line storage space is accessed, and if it still does not match, it is determined that the cache line is missing.

[0021] The embodiment of the application realizes the hierarchical hit judgment logic of the tag cache priority and the tag storage space backup, reduces the access times of the tag storage space while ensuring a high hit rate, and balances the memory access speed and resource consumption. When the tag cache does not match, the second verification is performed by the tag storage space to correct the false miss caused by the tag cache not covering, ensure that the cache resources are fully utilized, and improve the overall hit rate of the cache. In addition, the two-level judgment logic keeps the cache access delay at a low level (1 cycle in most scenarios and 2 cycles in a few scenarios), avoids the situation that one cache access takes 2 cycles due to the absence of a tag cache, guarantees the stability of the MCU operation, and provides continuous and efficient instruction or data support for various applications.

[0022] In an optional embodiment, when it is determined that the cache line is missing, the next level storage space is accessed by the bus interface unit, and the missing cache line is loaded into the cache line storage space by the replacement control unit and the tag information of the tag storage space and the tag cache is updated.

[0023] In the embodiment of the present application, when judging the cache line miss, the bus interface unit accesses the next level storage space, the replacement control unit loads the missing cache line to the cache line storage space through the bus interface unit, and updates the tag information of the tag storage space and the tag cache. The whole process does not need CPU intervention, the CPU can continue to execute other instructions or enter low power consumption state, reduces the waste of CPU resources, and improves the overall efficiency of the system. Updating the tag information ensures that the subsequent access to the address can hit quickly, avoids repeated missing, and guarantees the real-time performance of the cache data. At the same time, accessing the main memory on demand reduces the main memory read and write operation, reduces the main memory power consumption and access conflict, especially adapts to the design requirements of ultra-low power MCU, prolongs the device endurance, and improves the system reliability.

[0024] In an optional embodiment, updating the tag information of the tag cache includes: When the access to the tag cache is not hit, and there is unused tag information cache space in the tag cache, an unused tag information cache space is allocated, and the tag information is updated; When the access to the tag cache is not matched, and when the tag item is full, the old tag information is deleted according to the replacement algorithm, and the tag information of the current access address is updated to the released tag information cache space; if the access to the tag cache is not matched but the access to the tag storage space is matched, the corresponding tag information in the tag storage space is read, and the tag cache is written according to the replacement algorithm.

[0025] In the embodiment of the present application, when updating the tag cache, if it is not matched and there is unused space, the tag information is preferentially allocated and updated; if it is not matched and the tag item is full, the old information is deleted according to the replacement algorithm and the information is updated; if the tag cache is not matched but the tag storage space is matched, the tag information of the tag storage space is read and written into the tag cache according to the replacement algorithm. This updating mechanism can maximize the utilization rate of the tag cache, ensure that the tag information of high-frequency access is always stored, reduce the access to the tag storage space, save power consumption. At the same time, the content of the tag cache is updated in time to adapt to the change of the access address in the application running (such as switching from a loop instruction to a function call), so that the tag cache always maintains high effectiveness and provides reliable support for fast hit judgment.

[0026] In an optional embodiment, the access to the next level storage space by the bus interface unit includes: Reading the complete cache line data from the lower level storage; writing the cache line data into the cache line storage space according to the cache line index and offset address.

[0027] The bus interface unit in the embodiment of the application reads complete cache line data from the lower-level storage, conforms to the CacheLine storage logic, avoids subsequent access missing caused by incomplete reading, writes the cache line storage space according to the cache line index and offset address, ensures that the cache line data is stored in the correct position, avoids conflict with other cache line data, and guarantees the accuracy of the cache data. The tag information of the tag storage space is updated, so that the tag corresponds to the cache line data one by one, provides a correct basis for subsequent hit judgment, avoids judgment errors caused by tag update, ensures stable operation of the cache system, and improves the overall memory efficiency.

[0028] In a third aspect, the application provides an MCU chip integrating the configurable cache structure as described in the first aspect.

[0029] After the MCU chip integrating the configurable cache structure provided in the embodiment of the application, the cache parameters can be adjusted according to different application requirements, for example, a large cache is configured for industrial control application to improve real-time performance, and a small cache is configured for consumer electronic application to save power consumption, thereby solving the poor universality problem of the traditional MCU fixed Cache. The cache function is realized by using the system SRAM, without the need of additional special SRAM, thereby reducing the MCU chip area and cost, and being particularly suitable for low-cost and small-size MCU application scenarios (such as smart home sensors and portable devices). In addition, the "high performance - low power consumption - high adaptation" advantages brought by the configurable cache enable the MCU to cover more application fields, significantly improve the product market competitiveness, meet the diversified customer demand, and help expand the market share. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the specific embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0031] Figure 1 is a system SRAM space division schematic diagram according to the embodiment of the application; Figure 2 is a connection relationship schematic diagram of the function register, access address judgment unit, access hit judgment unit, replacement control unit, bus interface unit and SRAM access control unit according to the embodiment of the application; Figure 3 is a composition schematic diagram of the tag buffer according to the embodiment of the application; Figure 4 is a principle diagram of access matching judgment of the Tag Buffer according to the embodiment of the application; Figure 5 is a Cache access schematic diagram of Tag Buffer according to an embodiment of the present application; Figure 6 is a flow chart of an access method of configurable cache structure according to an embodiment of the present application; Figure 7 is a flow chart of flexibly configuring key parameters of Cache according to requirements of different application programs according to an embodiment of the present application; Figure 8 is a Cache access flow chart of Tag Buffer according to an embodiment of the present application. DETAILED DESCRIPTION

[0032] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0033] The configurable cache structure provided by the embodiments of the present application can be applied to an ultra-low power MCU adopting a Von Neumann architecture. The main features of the MCU are as follows: 1. The MCU integrates a single-core CPU, and the CPU has a low frequency, generally below 100 MHz; 2. The MCU generally adopts a 32-bit Princeton bus architecture, that is, a shared bus for instructions and data; 3. The on-chip storage space is generally based on a single-port SRAM, without a large-capacity memory such as DDR; 4. The Cache has a dedicated CacheLine SRAM and a Tag SRAM, and the data width of each SRAM is fixed. For example, the CacheLine data width is 4-word, and the Tag data width is 20-bit. These SRAMs are dedicated to the Cache and cannot be accessed by software; 5. The total capacity of the Cache space is fixed, and for the ultra-low power MCU, the capacity is generally small, for example, 2 KB, 4 KB or 8 KB, etc.

[0034] The configurable cache structure provided in this invention uses the system's single-port SRAM as its storage foundation. The composition of the ICache (Instruction Cache) can be flexibly configured according to application requirements. Through function register configuration and multi-module collaborative operation, it achieves "configurable parameters, resource reuse, and low-latency access." Its core architecture includes: system SRAM space, function registers, access address judgment unit, access hit judgment unit, replacement control unit, bus interface unit, and SRAM access control unit. The system SRAM space is divided as follows: Figure 1 As shown, the connection relationships of the function register, access address judgment unit, access hit judgment unit, replacement control unit, bus interface unit, and SRAM access control unit are as follows: Figure 2 As shown. Specifically: 1. System SRAM space, including application storage space (Normal SRAM) and instruction or data cache space. The instruction or data cache space includes cache line storage space (CacheLine SRAM) and tag storage space (Tag SRAM). CacheLine SRAM is used to store instructions or data, and Tag SRAM is used to store tag information of cache lines. The tag is used to uniquely identify the corresponding cache line.

[0035] It should be noted that system SRAM space typically refers to the "on-chip SRAM" within a SoC / MCU, mapped by the operating system or bus matrix to a uniformly addressed physical storage area accessible to the CPU, DMA, cache, and various master-slave devices. It can function as part of main memory or be further divided into several logical segments (such as TCM, DMA buffer, stack, code area, etc.). Generally, the CPU can directly access it via the bus, providing a unified bus interface.

[0036] 2. Function registers are used to configure the starting address and size of the cache line storage space and tag storage space within the system SRAM storage space; they can flexibly divide the cache space and application space according to the total capacity of the system SRAM and application memory requirements. Specifically, the function registers include: (1) Cache line count register, used to configure the number of cache lines M. For example, M=64 means there are 64 CacheLines. This value determines the width of the Index. For example, if there are 64 CacheLines, the width of the Index is 6 bits, Index[5:0]; where Index represents the index, used to access the storage space of the Cache. The storage space is divided into units of CacheLines. Each CacheLine is marked by an Index. For example, if there are 16 CacheLines in the Cache space, the width of the Index is 4 bits. The storage space of the CacheLine is addressed by 4 bits. Since the Tag and CacheLine are one-to-one, the storage space of the Tag is addressed by the Index while addressing the storage space of the CacheLine.

[0037] (2) Cache line length register, used to configure the length L of the cache line, then the total capacity of the cache line storage space is M×L; the length L of the cache line determines the width of the offset bit. For example, if L=32Byte, then the width of the offset bit is 5bit, Offset[4:0]; where Offset represents the offset address, used to address the target address in a CacheLine, the lower two bits are always 0, Offset[1:0]=00 (it should be noted that the data width of SRAM and Bus is 32-bit / 4-byte / 1-word, Offset is addressed in bytes, so Offset[1:0]=00, because each access is 1 Word / 4Byte). For example, after reading a CacheLine in the CacheLine space using the Index, the specific target address in this CacheLine is located using the Offset. For example, if the length of the CacheLine is 4 Words, from Word 0 to Word 3, the corresponding Word is found in the 4 Words using the Offset and returned to the CPU. For example, if Offset =

[1100] , which is 0xC, then the third Word in the CacheLine is accessed, and Word 3 is returned to the CPU; if the Offset is 0x0, then the first Word in the CacheLine is accessed, and Word 0 is returned to the CPU.

[0038] (3) Cache line start address register, used to configure the start address of the cache line storage space Instruction_SRAM_Start_Address, for example, in the system's SRAM space Instruction_SRAM_Start_Address = 0x00001000.

[0039] (4) Tag start address register, used to configure the starting address of tag storage space Tag_SRAM_Start_Address, for example, in the system's SRAM space Tag_SRAM_Start_Address=0x00002000.

[0040] The function registers support configuring the "cache line storage space start address" and "tag storage space start address," allowing for flexible allocation of cache space and application space based on the total system SRAM capacity (e.g., 128KByte) and application memory requirements. For example, when an application needs more memory, the cache space can be allocated to the high address segment of the system SRAM (e.g., 4K-6K), leaving the low address segment (0-4K) for the application; when an application needs higher cache performance, the cache space can be expanded to 8K-12K without hardware modification, avoiding the "non-expandable space" problem of traditional dedicated caches and adapting to diverse application needs.

[0041] It should be noted that each address space in the Tag SRAM stores not only the Tag but also the Index and a Valid bit, with a total bit width of less than 32 bits. For a CacheLine, its Tag and Index can be stored in the high-order bits of the corresponding address in the Tag SRAM space according to their positions in the Program Counter (PC), while the Valid bit is stored in the lowest-order bit, i.e., bit 0. Figure 1 As shown. The Valid bit here indicates whether the Tag and other information stored in this Tag SRAM space are valid; 1 indicates valid, and 0 indicates invalid. Based on PC[31:0]={Tag, Index, Offset}, the Index bit width is 5 bits, the Offset bit width is 5 bits, and the Tag bit width is 22 bits. Therefore, we get: PC[31:0]={Tag[21:0], Index[4:0], Offset[4:0]}, where Tag[21:0]=PC[31:10]; Index[4:0]=PC[9:5]; Offset[4:0]=PC[4:0].

[0042] The address access determination unit is used to determine whether the access address belongs to the cacheable space, and selects to access the cache space or directly access the target address based on the determination result. If it is, the cache space, such as the tag space, is accessed to determine whether a cache hit occurs; otherwise, the target address is accessed directly through the bus interface unit without accessing the cache space.

[0043] The access address determination unit optimizes the memory access path through the cacheable space identification function, which can reduce invalid cache operations, reduce memory access latency and reduce the dynamic power consumption of the cache module, and avoid invalid read and write operations of Tag SRAM and CacheLine SRAM.

[0044] 4. Access hit determination unit, which is used to compare the tag with the currently accessed cacheable space address to determine whether there is a hit, and when the tag comparison matches, it is determined that the cache access hit, and the corresponding data is read from the cache line storage space.

[0045] The access hit determination unit includes a tag buffer, which caches tag information, including tag values, in a portion of the tag storage space. The unit is configured to access the cache line storage space only when a tag match is found in the tag buffer; otherwise, it accesses the tag storage space for tag matching. During tag matching in the tag storage space, the unit accesses the cache line storage space; if no match is found, a cache miss is determined.

[0046] Specifically, such as Figure 3 As shown, the tag buffer can consist of: Valid (1 bit) + Tag (configurable bit width) + Index (configurable bit width) + replacement algorithm history information flag bits (e.g., LRU algorithm, N bits, 2^N = number of tag entries), where the replacement algorithm is optional; where: (1) Valid (1 bit): This indicates whether the current Tag Entry in the Tag Buffer is valid. Generally, 1 indicates valid and 0 indicates invalid. Invalid situations include: the current Tag Entry has not been used yet. For example, after the Cache is enabled, the Cache is still empty, all space is unused, and the Tag Buffer is not used. At this time, all Tag Entry are empty, and the corresponding Valid bit is 0, which means the Tag Entry is invalid. After the Cache is invalidated, all CacheLines are invalidated, and all Tag Entry in the Tag Buffer are also invalidated, and the corresponding Valid bit is cleared to 0.

[0047] (2) The Cache Identifier (Tag Info) field consists of {Tag (configurable bit width) + Index (configurable bit width)}, used to determine whether accessing the Tag Buffer has been successful. For configurable caches, the bit width of the Tag is configurable, the bit width of the Index is configurable, and therefore the total width of Tag + Index is also configurable. This value is affected by the length of the CacheLine (which is also configurable). The length of the CacheLine is generally 4 Words (16 Bytes), 8 Words (32 Bytes), etc. To improve configuration flexibility, the length of the CacheLine is designed to be 2^P, where P is the bit width of the length, which can be configured to 1, 2, 3....Q, and 2^Q is the maximum length of the CacheLine. For example, if Q is 10, then the maximum is 2^10 bytes, or 2^8 words, which should be determined according to application requirements. If P is 10, the total width of Tag + Index = 32 (total PC width) - 10 (bit width of CacheLine length) = 22 bits. In this case, Tag Info = PC[31:10] = {Tag, Index}. Index can be configured as 4 bits, meaning 2^4 = 16 CacheLines can be configured. Therefore, Tag = PC[31:14], Index = PC[13:10]. To support configurable cache, the total width of {Tag + Index} is designed to be 30 bits, meaning it supports a maximum of PC[31:2] information storage, thus supporting any combination of Tag + Index + Offset.

[0048] (3) Replacement Algorithm History Information Flag: Each Tag Entry has a replacement algorithm history information flag, and the information in the history flag is different for each replacement algorithm. It should be noted that the content of the history information flag varies depending on the replacement algorithm. For example, in the LRU algorithm, the flag width is N bits, and 2^N represents the number of Tag Entry. The replacement algorithm for updating the Tag Buffer is not limited here, nor is the content of the history information flag. It is determined based on the algorithm selected in the implementation. The CacheLine corresponding to the Tag information stored in the Tag Entry must be in the storage space of the Cache. If it is replaced, the Tag Entry must also be updated. The number of Entry given in the Tag Buffer should not be greater than the number of CacheLines. It is generally designed to be 2^S, where S is the bit width of the number of Entry, which can be 1, 2, 3, etc. S is not greater than the bit width of the Index, that is, the number of Entry is not greater than the number of CacheLines.

[0049] likeFigure 4 The diagram shown illustrates the principle behind the Tag Buffer hit detection. The Tag Buffer detection process is as follows: (1) Obtain the CPU access address Mem_Address, which is divided into three parts: Tag: The tag part is used to uniquely identify the original memory region corresponding to the cache line; Index: The index section, used to locate a specific group or entry in the cache; Offset: The offset portion, used to locate specific data within the cache line.

[0050] (2) Based on the length and number of CacheLines configured by the system, obtain the bit width of Offset and Index respectively, and thus also obtain the bit width of Tag; (3) Obtain Tag Info = {Tag, Index} from Mem_Address; (4) Compare the Tag Info stored in all Entries in Tag Buffer with the Tag Info in Mem_Address, and at the same time determine the Valid bit of each Entry. The calculation formula is Valid&&(Mem_Address{Tag, Index}==Tag_Entry{Tag, Index}); that is, check whether the Valid bit of the entry is 1 (to ensure that the entry stores valid information), compare whether the Tag stored in the entry is equal to the Tag split from the access address, and compare whether the Index stored in the entry is equal to the Index split from the access address. (5) Perform an OR operation on the judgment result of each Entry. If any Entry meets the matching condition, the final output will be Tag Buffer Hit. If none of the Entry meets the matching condition, the output will be Tag Buffer Miss.

[0051] A diagram illustrating Tag Buffer cache access is shown below. Figure 5As shown, the bit field corresponding to the PC fetched by the instruction is compared with the corresponding bit field of all Tag Buffer Entry. If there is a match, the access is a cache hit. If there is no match, the access address needs to be calculated according to the index, and the corresponding space in the Tag SRAM needs to be accessed. Then the read Tag value is compared. If there is a match, the access is a cache hit. Otherwise, a cache miss occurs, and cache miss processing is required. That is, the missing cache line needs to be retrieved, and the instruction or data at the corresponding address is returned to the core.

[0052] Integrating a Tag Buffer reduces cache access latency to 1 when a Tag Buffer hit occurs, significantly improving cache performance. Tag Buffer hit rate = number of Buffer Entries / number of CacheLines. (This hit rate is not the same as the cache hit rate). To further improve the Tag Buffer hit rate, the number of Tag BufferEntries can be increased, up to the number of CacheLines, at which point the Tag Buffer hit rate is 100%.

[0053] 5. Replacement control unit, used to load the missing cache line into the cache line storage space and update the tag information of the tag storage space and tag cache when a cache access miss occurs; Specifically, when a cache miss occurs, the replacement control unit accesses the next memory space via the bus interface unit, retrieves the missing CacheLine, and generates an access address via the SRAM access address generation unit. The CacheLine is then written to the corresponding address in the cache memory space according to the access address, including the Tag and CacheLine, written to the Tag SRAM and CacheLine SRAM respectively. The cache miss handling is then notified to the cache hit determination unit, and the Tag Buffer may be updated optionally.

[0054] The update process of the tag buffer is as follows: Whenever a cache miss occurs, update the CacheLine SRAM space, Tag SRAM space, and TagBuffer. If all entries are already valid, replace them according to the LRU algorithm. If the Tag Buffer does not match, but the Tag SRAM is accessed and the Tag matches, the Tag information will be updated to the Tag Buffer according to the LRU algorithm.

[0055] The replacement control unit optimizes the missing process through closed-loop management of "missing data handling - data loading - tag update", quickly replenishes missing cache lines, reduces CPU wait time, maintains consistency between tag buffer and tag SRAM, and ensures hit accuracy.

[0056] 6. Bus interface unit, used to access the next level of storage space when the replacement control unit loads the missing cache line through the bus interface unit.

[0057] The bus interface unit in this embodiment of the invention mainly performs two memory access operations: (1) Complete the access to the Uncacheable space (which can be understood as pass-through, where the Cache does not do anything and directly puts the access on the bus); it can meet the direct access requirements of the storage area in special scenarios, avoid the interference of the Cache mechanism on such special accesses, and ensure the accuracy and real-time performance of the access.

[0058] (2) When a cache miss occurs, the missing cache line is retrieved from the next level of storage and returned to the replacement control unit. This ensures that missing data in the cache is replenished in a timely manner, maintaining the cache's efficient supply of CPU instructions and data, thereby indirectly improving the overall system efficiency.

[0059] The SRAM access control unit is used to calculate the access addresses of the cache line storage space and tag storage space based on the configured starting address, so as to realize the read and write operations of cached data.

[0060] Specifically, the SRAM access address is calculated, and the corresponding access operation is completed based on the SRAM access address calculated for different access operations. This can be categorized into the following cases: (1) When reading a tag, calculate the address in the tag storage space corresponding to the current access address based on the index in the current access address. The calculation formula is: tag storage space address = starting address of tag storage space in system SRAM space + index of access address; (2) When reading cached data, calculate the address in the cache line storage space corresponding to the current access address based on the index information and offset address in the current access address. The calculation formula is: Cache line storage space address = starting address of cache line storage space in system SRAM space + cache line index × length of cache line + offset address; (3) When updating the label of the cache line, calculate the address in the corresponding label storage space based on the index information of the access address when a cache miss occurs. The calculation formula is: Label storage space address = starting address of the label storage space in the system SRAM space + index of the access address; (4) When updating cache line data, the address in the corresponding cache line storage space is calculated based on the index information and offset address of the access address when a cache miss occurs. The calculation formula is: Cache line storage space address = Starting address of cache line storage space in system SRAM space + Cache line index × Length of cache line + Offset address. Based on different access operations and the calculated SRAM access address, the corresponding access operation is completed, including: loading the missing cache line data into the calculated cache line storage space address, or writing the new cache line data back to the corresponding lower-level address space, where the new cache line data is the data written by the CPU. The corresponding lower-level address space refers to the storage space of the corresponding lower-level address from which the original cache line data before the update came.

[0061] It should be noted that since SRAM addresses are generally word-aligned, the Index needs to be shifted left by 2 bits (multiplied by 4), becoming {Index, 2'b00}. Therefore: Accessing the Tag SRAM address: Tag_SRAM_addr = Tag_SRAM_Start_Address + {Index, 2'b00}; Accessing the CacheLine SRAM address: CacheLine_SRAM_addr =CacheLine_SRAM_Start_Address + {Index, 2'b00} ×CacheLine_Length + Offset.

[0062] The CacheLine_Length above is in units of words. For example, a CacheLine length of 4 means a length of 4 words, or 16 bytes.

[0063] This invention ensures the accurate storage location of CacheLine and Tag through address calculation. The SRAM access control unit solves the address location problem under configurable parameters through a standardized address calculation formula, and ensures the correctness of cache read and write by accurately calculating the storage address.

[0064] In the configurable cache structure of this invention, the modules do not work independently, but form a closed-loop collaborative process of "configuration-judgment-hit-miss-store", ultimately achieving: 1. Performance Improvement: By shortening high-frequency access latency through Tag Buffer and optimizing miss handling through replacement control unit, the average cache access latency is reduced, thereby improving CPU instruction throughput; 2. Power consumption optimization: Reduce invalid operations by accessing the address judgment unit and reduce Tag SRAM access by Tag Buffer, thereby reducing the dynamic power consumption of the Cache module and adapting to ultra-low power MCU scenarios; 3. High resource efficiency: By multiplexing system SRAM and bus interface units through function registers, bus usage is optimized, improving system SRAM utilization and bus utilization. 4. Enhanced versatility: With fully configurable parameters, a single MCU can adapt to various applications such as loop-intensive, sequence-intensive, and peripheral-intensive applications, reducing the number of hardware versions and lowering R&D and production costs.

[0065] This invention also provides a method for accessing a configurable cache structure, the main process of which is as follows: Figure 6 As shown, it specifically includes: S1 configures the starting address and size of the cache line storage space and tag storage space in the system SRAM storage space through the function register.

[0066] The specific configuration process, such as Figure 7 As shown, it supports flexible configuration of key cache parameters, such as cacheline length, number, and starting address in the system SRAM space, according to the needs of different applications. This allows the cache to better adapt to the data caching requirements of different applications, improving the targeting and effectiveness of the cache. Furthermore, after the application finishes execution, the cache configuration can be modified based on the actual situation. If it is necessary to optimize the caching effect to adapt to subsequent programs, adjustments can be made promptly; if the current configuration meets the requirements, it can remain unchanged, providing the system with dynamic adjustment capabilities and enhancing the system's adaptability and resource utilization efficiency.

[0067] S2, the access address judgment unit determines whether the address to be accessed belongs to the cacheable space, and selects to access the cache space or directly access the target address based on the judgment result.

[0068] Specifically, in traditional caching architectures, a more complex cache access process is executed regardless of whether the accessed address is suitable for caching. This can lead to unnecessary cache lookups and comparisons, wasting time. However, the address determination unit can pre-determine whether an address belongs to the cacheable space. For addresses that are clearly not cacheable (such as peripheral register addresses, system configuration addresses, etc.), it directly bypasses the cache and accesses the target address. This avoids invalid operations by the caching system, saves cache access time overhead, and improves the overall system access speed. When the address determination unit identifies an uncacheable address and prevents it from entering the cache access process, it reduces invalid read / write operations of cache modules (such as tag storage space and cache line storage space related circuits), lowers the dynamic power consumption of the cache modules, and enables the system to more clearly distinguish different types of address access paths. This helps the system to perform more reasonable resource scheduling and management as a whole, improving the efficiency of system resource utilization.

[0069] S3 uses the access hit judgment unit to compare tags based on the current access address to determine whether the cache access is hit. When the cache access is hit, the corresponding data is read from the cache line storage space. When it is not hit, the cache line is determined to be missing.

[0070] Specifically, the access hit determination unit performs tag comparison based on the current access address to determine whether the cache access is hit. This includes: accessing the tag buffer for tag comparison. The tag buffer is used to cache tag information in part of the tag storage space. If the tag comparison result is a match, the corresponding data in the cache line storage space is accessed. When the tag buffer access does not match, the tag storage space is accessed for tag comparison. If the tag comparison result is a match, the corresponding data in the cache line storage space is accessed. If it still does not hit, the cache line is determined to be missing.

[0071] The flowchart of cache access with integrated Tag Buffer is as follows: Figure 8 As shown, this invention illustrates how the system reads instructions from SRAM (Static Random Access Memory) based on the matching of access addresses (Tag & Index) within three clock cycles, and the different processing logic when the cache hits or misses. The embodiment of this invention takes the instruction cache space as an example, but this invention does not limit the data type stored in the cache space, that is, the following embodiment is also applicable to the data cache space or other data forms of cache.

[0072] (1) Clock cycle 1: Initial address matching and instruction fetching Starting with "instruction fetch," the core process is to determine whether the address (Tag & Index) matches, thus determining the source of the instruction to be fetched. If the "Tag & Index match": directly calculate the "address of the instruction in SRAM", then "read the instruction from the SRAM space", and finally "return the instruction". This path allows for fast fetching of the instruction from SRAM, resulting in high efficiency. If "Tag & Index do not match": calculate "the address of the Tag in SRAM", then "read the Tag SRAM space" to obtain the "Tag value", and proceed to the subsequent judgment in clock cycle 2.

[0073] (2) Clock cycle 2: Secondary address matching and cache processing Based on the address of the Tag in the Tag SRAM obtained from the "mismatch" path in clock cycle 1, the Tag information is read, and the match is checked again to determine whether to read the instruction or handle the cache miss: If the "Tag & Index match": calculate the "address of the instruction in SRAM", then "read the instruction SRAM space", and finally "return the instruction". This case belongs to the follow-up processing of "cache hit", and the instruction is still fetched from the CacheLine SRAM space.

[0074] If "Tag & Index do not match", the "Cache Miss Handling" process will begin. This process usually requires reading data from a lower level of memory (such as main memory) into the cache, which will consume more clock cycles (not detailed in the diagram, only process nodes are marked).

[0075] (3) Clock cycle 3: Instruction read complete (matching scenario) If a match is found in the "secondary match" of clock cycle 2 (i.e., "Tag & Index match"), then in clock cycle 3, the "read instruction SRAM space" is completed and the "instruction is returned", and the Tag information of CacheLine is updated to TagBuffer, and the process ends.

[0076] The key to the above process is two address matching operations (Tag & Index): The first match allows for fast instruction fetching directly from SRAM; if the first match fails, a second match must be verified using the Tag to determine whether to quickly fetch the instruction from SRAM and update the Tag Buffer or handle the miss. When the addresses match, the complex memory hierarchy can be bypassed, and the instruction can be fetched directly from SRAM; otherwise, miss handling must be triggered.

[0077] In a system SRAM cache space based on a single data interface, multiple SRAM accesses are required during access if tag comparison is needed, reducing transmission efficiency. The access hit determination unit in this embodiment of the invention optimizes the hit determination process by integrating a "Tag Buffer," reducing the number of Tag SRAM accesses without increasing access latency. It also supports flexible cache configuration, improves CPU instruction throughput, reduces Tag SRAM accesses, lowers power consumption, and increases efficiency. Simultaneously, through a dual determination of "Tag comparison + Valid bit verification" (e.g., a hit is determined only if the tag matches and the Valid bit = 1), it avoids erroneous hits caused by "Valid bit not being cleared to 0" in traditional caches (e.g., instruction errors caused by old tags not being invalidated after cache invalidation).

[0078] Due to the temporal and spatial locality of data access, recently accessed data is likely to be accessed again in the near future. A tag buffer specifically caches frequently accessed tag information. When this frequently accessed data is accessed again, tag matching can be performed directly in the tag buffer. Since the tag buffer is much faster than the tag storage space (Tag SRAM), if a match is found, the cache line storage space (CacheLineSRAM) can be accessed directly without waiting for the tag SRAM to be read. This reduces the critical step of cache hit from an extra clock cycle of "Tag SRAM read + matching" to the current clock cycle of "Tag Buffer matching," without affecting the response speed of data access due to the shared interface between TagSRAM and CacheLineSRAM.

[0079] S4, when a cache line is determined to be missing, the next-level storage space is accessed through the bus interface unit, and the missing cache line is loaded into the cache line storage space through the replacement control unit via the bus interface unit, and the tag information of the tag storage space and the tag cache is updated. Updating the tag information of the tag cache includes: 1. When the access tag cache is not hit, and there is unused tag information cache space in the tag cache, then allocate an unused tag information cache space and update the tag information; 2. When the access tag cache does not match, and the tag item is full, delete the old tag information according to the replacement algorithm, and update the tag information of the current access address to the released tag information cache space; if the access tag cache does not match but the access tag storage space matches, read the corresponding tag information in the tag storage space, and write it to the tag cache according to the replacement algorithm.

[0080] The above process ensures the effectiveness of the tag cache, promptly allocating unused space to new tags and replacing old tags according to the replacement algorithm when the cache is full. It also synchronizes tag storage space and tag cache information to avoid misjudgments; improves cache hit rate, reduces access to the next level of storage, adapts to various access modes, and helps the system maintain performance in different scenarios; reduces system power consumption, reduces access to the next level of high-power storage, and optimizes invalid operations of the tag cache; ensures data consistency, copes with complex access scenarios, and enhances system stability and reliability.

[0081] The process of accessing the next-level storage space through the bus interface unit in this invention includes: reading complete cache line data from the lower-level storage; writing the cache line storage space according to the cache line index and offset address; and updating the tag information in the tag storage space. Accessing the next-level storage through "reading the complete cache line → writing to the cache line storage → updating the tag storage," the CacheLine is designed as a basic unit of high-speed caching. Completely reading the cache line avoids instruction truncation / errors, ensuring the CPU obtains valid instructions and meeting system stability requirements. Synchronously updating the Tag value and Valid bit in the tag storage conforms to the "one-to-one correspondence between Tag and CacheLine" logic, ensuring accurate subsequent hit judgments and avoiding misjudgments. Simultaneously, it reduces the number of interactions between the bus and the lower-level storage, meeting the requirements of ultra-low-power MCUs, reducing bus power consumption, shortening the time spent on miss handling, alleviating the high latency problem of traditional caches, and improving the instruction throughput efficiency of the MCU.

[0082] This invention also provides an MCU chip that integrates the configurable cache structure described in the above embodiments. Taking a 32-bit ultra-low-power MCU chip adapted for industrial control scenarios (based on the von Neumann architecture, with a main frequency of 80MHz, a total SRAM capacity of 64KB per system port, and 512KB Flash memory as the underlying storage) as an example, its integrated configurable cache structure parameters and workflow are as follows: 1. Hardware integration parameters: Configure the number of cache lines to 64 and the length to 8 words through the function registers. The starting address of the cache line storage space is 0x00008000 (occupying 2KB), the starting address of the tag storage space is 0x00009000 (occupying 256 bytes), and the Tag Buffer is set to 8 Entries; 2. Typical application adaptation: When running the industrial cycle detection program (40% of the instructions are loop instructions), the software reconfigures the cache line length to 4 words and the number to 128 through the function register, expands the cache line storage space to 2KB (0x00008000-0x000087FF), and adjusts the tag storage space to 0x00008800 (occupying 512 bytes). 3. Workflow: After the CPU fetch address is identified as cacheable space by the access address judgment unit, the access hit judgment unit first compares it with the Tag Buffer. If there is a miss, the tag storage space is read. When the cache is missing, the bus interface unit reads the complete cache line data of 4 words from Flash. The replacement control unit writes it into the cache line storage space according to the index and offset address, and updates the tag storage and Tag Buffer synchronously. The whole process is adapted to the timing of the single-port SRAM of the system and there is no read / write conflict.

[0083] By integrating a configurable high-speed cache into the MCU chip structure, it can meet the low-conflict requirements of industrial control cyclic instruction scenarios and adapt to the high space utilization requirements of consumer electronics sequential instruction scenarios. There is no need to develop dedicated MCUs for different scenarios, enabling the MCU to cover more application areas, significantly improving product market competitiveness, meeting diverse customer needs, and helping to expand market share.

[0084] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A configurable cache structure, characterized in that, include: The system SRAM space includes application storage space and instruction or data cache space. The instruction or data cache space includes cache line storage space and tag storage space. The cache line storage space is used to store instructions or data, and the tag storage space is used to store tag information of cache lines. The tag is used to uniquely identify the corresponding cache line. The function register is used to configure the starting address and size of the cache line storage space and tag storage space in the system SRAM storage space; The access address determination unit is used to determine whether the access address belongs to the cacheable space, and select to access the cache space or directly access the target address based on the determination result.

2. The configurable cache structure according to claim 1, characterized in that, The function register includes: The cache line count register is used to configure the number of cache lines M; The cache line length register is used to configure the length L of the cache line, and the total storage capacity of the cache line is M×L; The cache line start address register is used to configure the starting address of the cache line storage space; The tag start address register is used to configure the starting address of the tag storage space.

3. The configurable cache structure according to claim 1, characterized in that, Also includes: The access hit determination unit is used to compare the tag with the currently accessed cacheable space address to determine whether there is a hit. When the tag comparison matches, it is determined that the cache access hit has occurred, and the corresponding data is read from the cache line storage space.

4. The configurable cache structure according to claim 3, characterized in that, The access hit determination unit includes a tag cache for caching tag information in a portion of the tag storage space, the tag information including tag values; the access hit determination unit is configured to access the cache line storage space when the tag comparison in the tag cache matches, otherwise access the tag storage space for tag comparison.

5. The configurable cache structure according to claim 4, characterized in that, It also includes accessing the cache line storage space when performing tag comparison and matching in the tag storage space, and determining that the cache access miss is determined when there is no match.

6. The configurable cache structure according to claim 5, characterized in that, Also includes: The replacement control unit is used to load the missing cache line into the cache line storage space and update the tag information of the tag storage space and the tag cache when a cache access miss occurs. The bus interface unit is used to access the next level of storage space when the replacement control unit loads the missing cache line.

7. The configurable cache structure according to any one of claims 1-6, characterized in that, Also includes: The SRAM access control unit is used to calculate the access addresses of the cache line storage space and tag storage space according to the configured starting address, so as to realize the read and write operations of cache data; The SRAM access control unit calculates the access addresses of the cache line storage space and the tag storage space based on the configured starting address, including: When reading a tag, the address in the tag's storage space corresponding to the current access address is calculated based on the index in the current access address. The calculation formula is: Tag storage space address = starting address of tag storage space in system SRAM space + index of access address; When reading cached data, the address in the cache line storage space corresponding to the current access address is calculated based on the index information and offset address in the current access address. The calculation formula is: Cache line storage space address = Start address of cache line storage space in system SRAM space + Cache line index × Length of cache line + Offset address; When updating the tag of a cache line, the address in the corresponding tag storage space is calculated based on the index information of the access address when a cache miss occurs. The calculation formula is: Tag storage space address = starting address of tag storage space in system SRAM space + index of access address; When updating cache line data, the address in the corresponding cache line storage space is calculated based on the index information and offset address of the access address when a cache miss occurs. The calculation formula is: Cache line storage space address = starting address of cache line storage space in system SRAM space + cache line index × cache line length + offset address. Based on different access operations and the calculated SRAM access address, the corresponding access operation is completed, including: loading the missing cache line data into the calculated cache line storage space address, or writing the new cache line data back to the corresponding lower-level address space, where the new cache line data is the data written by the CPU.

8. A method for accessing a configurable cache structure, characterized in that, include: Configure the starting address and size of the cache line storage space and tag storage space in the system SRAM storage space through the function registers; The access address determination unit determines whether the address to be accessed belongs to the cacheable space, and selects to access the cache space or directly access the target address based on the determination result.

9. The method according to claim 8, characterized in that, Also includes: The access hit determination unit compares the tags based on the current access address to determine whether the cache access is hit. When the cache access is hit, the corresponding data is read from the cache line storage space. When it is not hit, the cache line is determined to be missing.

10. The method according to claim 9, characterized in that, The method of determining whether a cache access has been hit by comparing tags based on the current access address by the access hit judgment unit includes: accessing the tag cache for tag comparison, wherein the tag cache is used to cache tag information of part of the tag storage space; if the tag comparison result is a match, the corresponding data in the cache line storage space is accessed; when the tag cache access does not match, the tag storage space is accessed for tag comparison; if the tag comparison result is a match, the corresponding data in the cache line storage space is accessed; if it still does not match, the cache line is determined to be missing.

11. The method according to any one of claims 9-10, characterized in that, Also includes: When a cache line is determined to be missing, the next level of storage space is accessed through the bus interface unit, and the missing cache line is loaded into the cache line storage space through the replacement control unit, and the tag information of the tag storage space and tag cache is updated.

12. The method according to claim 11, characterized in that, Updating the tag information of the tag cache includes: If the access to the tag cache is not found, and there is unused tag information cache space in the tag cache, then an unused tag information cache space is allocated and the tag information is updated. When the accessed tag cache does not match, and when the tag item is full, the old tag information is deleted according to the replacement algorithm, and the tag information of the current access address is updated to the released tag information cache space; if the accessed tag cache does not match but the accessed tag storage space matches, the corresponding tag information in the tag storage space is read and written to the tag cache according to the replacement algorithm.

13. The method according to claim 12, characterized in that, Accessing the next-level storage space via the bus interface unit includes: Read complete cache line data from the lower-level storage; write it to the cache line storage space according to the cache line index and offset address.

14. An MCU chip, characterized in that, Integrate the configurable cache structure as described in any one of claims 1-7.

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