Branch prediction table updating method, terminal device and computer program product

Abstract

The invention provides a branch prediction table updating method, terminal equipment and a computer program product, and the method comprises the steps: obtaining an actual execution result of a target branch instruction, and obtaining time sequence information of the target branch instruction in a program sequence; creating a target entry in the buffer structure, and recording the actual execution result, the identification information of the target branch instruction and the time sequence information in the target entry; and updating the branch prediction table by using an actual execution result based on the time sequence information of each entry in the buffer structure. According to the method, caching is carried out according to the program sequence of branch instructions so as to manage and control items including actual execution results, identification information of target branch instructions and time sequence information, and a branch prediction table is updated by utilizing the actual execution results based on the time sequence information of the items in a buffer structure. The possibility of pollution caused by disordered updating of the branch prediction table is avoided, and the accuracy of the prediction table can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of general-purpose processors, and in particular to a branch prediction table updating method, a terminal device, and a computer program product. BACKGROUND

[0002] With the development of high-performance general-purpose processor design technology, speculative execution technology represented by branch prediction and out-of-order execution has become the core means to improve instruction-level parallelism. The branch instruction prediction unit (BPU) predicts the prediction direction and prediction target address of the branch instruction by analyzing the program history behavior, so that the instruction fetch unit can obtain the instructions in advance, thereby realizing efficient instruction jumping and program running. At present, the branch instruction prediction unit of the processor is usually composed of multiple prediction tables, and the prediction accuracy directly determines the overall performance of the processor.

[0003] In the traditional technology, in order to quickly respond to program running, the branch prediction table usually adopts an execution-immediately-updating strategy. That is, when the branch instruction is completed in the out-of-order execution back end and its actual result is calculated, the branch prediction unit immediately updates the corresponding prediction table entry using the result. This method can update the correct branch behavior to the branch instruction prediction unit with the lowest delay, so that it can quickly adapt to the dynamic changes of the program. However, in a processor with deep out-of-order execution, the execution order of the branch instruction is not consistent with its original order in the program (program order). A young branch instruction (appearing later in the program) may be executed earlier than an old branch instruction (appearing earlier in the program). If the traditional technical solution is adopted, the prediction result of the young branch instruction will be written into the prediction table first, but if a more old branch instruction subsequently occurs, the processor pipeline needs to flush (flush) all the speculation states from the old branch (including all the young branches) and roll back to the correct execution path. In this process, the update of the prediction table by the young branches based on the incorrect path is essentially invalid pollution to the prediction table. These pollution information not only cannot accurately reflect the real behavior of the program, but also may cover the originally valid historical information in the prediction table, resulting in a decrease in the branch prediction accuracy.

[0004] Therefore, how to improve the accuracy of the prediction table when updating the prediction table in the out-of-order execution environment is a technical problem that needs to be solved by those skilled in the art. SUMMARY

[0005] The present application aims to provide a branch prediction table updating method, device, terminal device, computer readable storage medium and computer program product, which can improve the accuracy of the prediction table when updating the prediction table in the out-of-order execution environment.

[0006] In a first aspect, the present application provides a method for updating a branch prediction table. The method comprises: obtaining an actual execution result of a target branch instruction, and obtaining timing information of the target branch instruction in program order; creating a target entry in a buffer structure, and recording the actual execution result, identification information of the target branch instruction, and the timing information in the target entry; updating the branch prediction table based on the timing information of each entry in the buffer structure and the actual execution result.

[0007] In one embodiment, the updating the branch prediction table based on the timing information of each entry in the buffer structure and the actual execution result comprises: checking whether each entry in the buffer structure satisfies an update condition; the update condition is determined according to the timing information; if any of the entries satisfies the update condition, updating the branch prediction table using the actual execution result corresponding to the entry.

[0008] In one embodiment, determining that the entry satisfies the update condition comprises: if the entry is determined to be the oldest entry according to the program order of the entry, determining that the entry satisfies the update condition.

[0009] In one embodiment, the creating a target entry in a buffer structure, and recording the actual execution result, identification information of the target branch instruction, and the timing information in the target entry comprises: if it is determined that a branch misprediction occurs, creating a target entry in a buffer structure, and recording the actual execution result, identification information of the target branch instruction, and the timing information in the target entry, and setting a trustworthiness state of the target entry to high trustworthiness; determining that the entry satisfies the update condition comprises: if the trustworthiness state of the entry is high trustworthiness, and the trustworthiness state of all entries older than the entry is high trustworthiness, determining that the entry satisfies the update condition.

[0010] In one embodiment, the updating the branch prediction table based on the timing information of each entry in the buffer structure and the actual execution result comprises: creating a target entry in a buffer structure, and recording state information of the target branch instruction, the actual execution result, identification information of the target branch instruction, and the timing information in the target entry; updating the branch prediction table based on the actual execution result; if it is determined that a branch misprediction occurs, determining, from the buffer structure, a rollback entry whose timing information is greater than or equal to timing information of a target branch instruction corresponding to the branch misprediction, according to the timing information of the target branch instruction; restoring the branch prediction table according to state information before updating of each of the rollback entries.

[0011] In one of the embodiments, the step of querying the branch prediction table according to the current PC address to obtain a prediction result comprises: querying the branch prediction table and the buffer structure according to the current PC address respectively to obtain a prediction result.

[0012] In one of the embodiments, the step of determining that a branch misprediction occurs comprises: querying the branch prediction table according to the current PC address to obtain a prediction result; determining a target branch instruction from branch instructions that are ready for operation, and performing emission and execution based on the target branch instruction to obtain an actual execution result; if the prediction result is inconsistent with the actual execution result, determining that a branch misprediction occurs.

[0013] In one of the embodiments, after determining that the prediction result is inconsistent with the actual execution result, the method further comprises: generating a global flush request according to timing information of the target branch instruction; the global flush request is used to clear all entries that are younger than the target branch instruction in program order.

[0014] In a second aspect, the present application further provides an updating device of a branch prediction table. The device comprises: an obtaining module, configured to obtain an actual execution result of a target branch instruction, and obtain timing information of the target branch instruction in program order; a recording module, configured to create a target entry in a buffer structure, and record the actual execution result, identification information of the target branch instruction and the timing information in the target entry; an updating module, configured to update the branch prediction table based on the timing information of each of the entries in the buffer structure, and using the actual execution result.

[0015] In a third aspect, the present application further provides a terminal device. The terminal device comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the steps of the method as described above when executing the computer program.

[0016] In a fourth aspect, the present application provides a computer readable storage medium. The computer readable storage medium stores a computer program, and the computer program, when executed by a processor, implements the steps of the above method.

[0017] In a fifth aspect, the present application provides a computer program product. The computer program product comprises a computer program, and the computer program, when executed by a processor, implements the steps of the above method.

[0018] The present application provides a branch prediction table updating method, obtaining an actual execution result of a target branch instruction and timing information of the target branch instruction in program order; creating a target entry in a buffer structure and recording the actual execution result, identification information of the target branch instruction and the timing information in the target entry; and updating the branch prediction table based on the timing information of each entry in the buffer structure and the actual execution result. It can be seen that the present method controls each entry comprising the actual execution result, the identification information of the target branch instruction and the timing information based on the program order of the branch instruction, i.e. manages the entries in the buffer structure based on the program order, updates the branch prediction table based on the timing information of each entry in the buffer structure and the actual execution result, and avoids the possibility of pollution caused by out-of-order updating of the branch prediction table. Therefore, the present method can improve the accuracy of the prediction table when updating the prediction table in an out-of-order execution environment.

[0019] It can be understood that the branch prediction table updating device, terminal device, computer readable storage medium and computer program product provided by the embodiments of the present application have the same beneficial effects as the above branch prediction table updating method, and will not be described here. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings needed to be used in the specific embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0021] Figure 1 A flowchart of a branch prediction table updating method provided by an embodiment of the present application; Figure 2 A structural schematic diagram of a branch prediction table updating device provided by an embodiment of the present application; Figure 3 A structural schematic diagram of a terminal device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0022] In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular architectures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known methods, devices, circuits, and

[0023] It is to be understood that the terminology "includes", "has", "holds", "contains" and / or "comprising", "including", "having" and their conjugates, as used herein, means "including but not limited to", and not to the exclusion of any other term or aspect.

[0024] It is also to be understood that the terminology "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items, as well as the lack of any associated listed items.

[0025] As used in the description of the application and the appended claims, the term "if" can be interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting" depending on the context. Similarly, the phrase "if it is determined" or "if [a described condition or event] is detected" can be interpreted to mean "upon determining" or "in response to determining" or "upon [the described condition or event] being detected" or "in response to [the described condition or event] being detected", depending on the context.

[0026] In addition, the terms "first", "second", "third", etc. as used in the description of embodiments herein and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the application described herein are, for example, capable of use in either order.

[0027] Reference throughout this specification to "an embodiment" or "some embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. Thus, the appearances of the phrases "in one embodiment", "in some embodiments", "in other embodiments", "in additional embodiments", and so on, in various places throughout this specification are not necessarily referring to the same embodiment, unless otherwise specified. The terms "comprising", "including", "containing", and variations thereof, as well as the terms "consisting of" and "consisting essentially of", when used in this specification, are inclusive or open-ended and do not exclude additional, unrecited elements or method steps. The term "multiple" means "two or more".

[0028] The method for updating a branch prediction table provided by the embodiments of the present application can be executed by a processor of a terminal device when running a corresponding computer program.

[0029] Figure 1 A flowchart of a method for updating a branch prediction table according to an embodiment of the present application is shown in FIG. 1. For ease of illustration, only the parts related to the present embodiment are shown. The method according to the present embodiment comprises the following steps: S100: Obtain the actual execution result of a target branch instruction and the timing information of the target branch instruction in program order.

[0030] The target branch instruction refers to the branch instruction with the smallest (oldest) timing information in program order.

[0031] The actual execution result refers to the result actually calculated by the branch execution unit for the target branch instruction. The actual execution result includes the actual direction and the actual target address. The actual direction refers to the actual flow direction of the target branch instruction, i.e. Taken (jump) or NotTaken (no jump). The actual target address refers to the specific instruction address corresponding to the jump when the actual direction is jump.

[0032] The timing information refers to an identifier uniquely defining the logical order of the branch instruction in the program. Generally, the smaller the timing information, the older the branch instruction. In a specific example, the ROB ID is assigned to each branch instruction according to the ROB allocation pointer provided by the ROB, i.e. the timing information can be the ROB ID. The smaller the ROB ID, the older the program order (age).

[0033] S200: Create a target entry in the buffer structure and record the actual execution result, the identification information of the target branch instruction and the timing information in the target entry.

[0034] The buffer structure refers to a buffer for temporarily storing entries. The buffer structure can be an FBC, which is not limited in the present embodiment.

[0035] The target entry refers to the data record currently set for the prediction table update request of the target branch instruction. The actual execution result, the identification information of the target branch instruction and the timing information are recorded in the target entry. The identification information of the target branch instruction refers to the information uniquely determining which branch instruction, which can be the program counter address (PC address) of the target branch instruction.

[0036] Specifically, a target entry is created in the buffer structure for the target branch instruction, and the actual execution result corresponding to the target branch instruction, the identification information of the target branch instruction and the timing information are respectively filled in the corresponding fields of the created target entry.

[0037] S300: updating the branch prediction table based on the timing information of each entry in the buffer structure and the actual execution result.

[0038] Specifically, the timing information of each entry in the buffer structure is checked to determine whether each entry meets the update condition, and if any entry meets the update condition, the branch prediction table is updated based on the actual execution result; or the branch prediction table is immediately updated based on the actual execution result, and when a misprediction is determined, the branch prediction table is rolled back based on the timing information.

[0039] The branch prediction table refers to a series of lookup tables inside a branch predictor (BPU), such as BHT, PHT, and BTB, etc. The branch prediction table stores the behavior patterns of each branch instruction in the history record, such as the branch of address A 80% jumping to address B. When prediction is needed, the BPU queries the branch prediction table using the current PC address to obtain the prediction result; the prediction result includes the prediction direction and the predicted target address.

[0040] Specifically, updating the branch prediction table based on the actual execution result means replacing the history record in the branch prediction table with the actual execution result; including replacing the prediction direction with the actual direction, and / or replacing the predicted target address with the actual target address.

[0041] The embodiment of the present application provides a branch prediction table updating method, which obtains the actual execution result of a target branch instruction and the timing information of the target branch instruction in program order; creates a target entry in a buffer structure, and records the actual execution result, the identification information of the target branch instruction, and the timing information in the target entry; and updates the branch prediction table based on the timing information of each entry in the buffer structure and the actual execution result. It can be seen that this method caches the branch instructions according to the program order to control each entry including the actual execution result, the identification information of the target branch instruction, and the timing information, that is, to manage the entries in the buffer structure using the program order, to update the branch prediction table based on the timing information of each entry in the buffer structure and the actual execution result, and to avoid the possibility of pollution caused by out-of-order updating of the branch prediction table; therefore, this method can improve the accuracy of the prediction table when updating the prediction table in an out-of-order execution environment.

[0042] Based on the above embodiment, the technical solution is further described and optimized in the embodiment, specifically, in the embodiment, the branch prediction table is updated based on the timing information of each entry in the buffer structure and the actual execution result, including: checking whether each entry in the buffer structure meets the update condition; the update condition is determined according to the timing information; If any entry meets the update condition, the branch prediction table is updated by using the actual execution result corresponding to the entry.

[0043] In this embodiment, the FBC checks each entry in the buffer structure according to a preset period, and determines whether each entry meets the update condition. The update condition is determined according to the timing information.

[0044] If the entry does not meet the update condition, no further action is needed, and the entry continues to wait in the buffer structure; if the entry meets the update condition, the branch prediction table is updated by using the actual execution result recorded in the entry.

[0045] According to the method of this embodiment, whether each entry in the buffer structure meets the update condition is determined based on the timing information, and the branch prediction table is updated, which can improve the accuracy of the branch prediction table.

[0046] In a specific embodiment, determining that the entry meets the update condition comprises: If it is determined that the entry is the oldest entry according to the program order of the entry, it is determined that the entry meets the update condition.

[0047] In this embodiment, each entry records the timing information of the program order of the corresponding branch instruction, such as the ROB ID, the actual execution result, and the identification information of the branch instruction; in each preset period, the FBC checks each entry, and determines whether the entry is the entry with the smallest timing information (i.e., the oldest entry) according to the timing information corresponding to the entry; if yes, it is determined that the entry meets the update condition, and thus the branch prediction table is updated by using the actual execution result in the entry. After the update is completed, the entry is marked as invalid, so that subsequent other entries can be determined as the oldest entry.

[0048] Suppose that there are three entries in the current FBC, and the entries are in the order from old to young as follows: entry A (ROB ID=5), entry B (ROB ID=8), and entry C (ROB ID=12); when the FBC checks according to the preset period, the ROB ID of entry A is the smallest, i.e., entry A meets the update condition, and thus the branch prediction table is updated by using the actual execution result of entry A, and then entry A is marked as invalid; in the next period, the ROB ID of entry B is the smallest, and the branch prediction table is updated by using the actual execution result corresponding to entry B, and so on.

[0049] According to the method of this embodiment, the branch prediction table is updated according to the program order, which avoids the pollution of the branch prediction table caused by the update operation of the branch prediction table by the young branch instruction execution prediction table of the wrong path, and guarantees the accuracy of the branch prediction table.

[0050] On the basis of the above-mentioned embodiments, the technical solutions are further explained and optimized in the present embodiment. Specifically, in the present embodiment, a target entry is created in the buffer structure, and the actual execution result, the identification information of the target branch instruction, and the timing information are recorded in the target entry, including: If it is determined that a branch misprediction occurs, a target entry is created in the buffer structure, and the actual execution result, the identification information of the target branch instruction, and the timing information are recorded in the target entry, and the credibility state of the target entry is set to high credibility. The entry is determined to satisfy the update condition, including: If the credibility state of the entry is high credibility, and the credibility state of all entries older than the entry is high credibility, it is determined that the entry satisfies the update condition.

[0051] Specifically, when it is determined that a branch misprediction occurs, a prediction table update request is generated using the actual execution result corresponding to the target branch instruction; the prediction table update request specifically includes the actual execution result, the identification information of the target branch instruction, and the timing information; the prediction table update request is sent to the BPU; after the BPU receives the prediction table update request, a target entry is created in the buffer structure, and the prediction table update request including the actual execution result, the identification information of the target branch instruction, and the timing information is recorded in the target entry.

[0052] It should be noted that the entry determined according to the actual execution result is determined to be high credibility; the speculative entry is set to low credibility. Moreover, after it is determined that the path corresponding to the speculative entry is the correct path, the credibility state of the entry can be modified from low credibility to high credibility.

[0053] In the present embodiment, since the target entry is determined according to the actual execution result (non-speculative), the credibility state of the target entry is set to high credibility.

[0054] Correspondingly, when checking whether each entry in the buffer structure satisfies the update condition, for each entry, it is determined whether the credibility state of the entry itself is high credibility, and it is determined whether all entries older than the entry are high credibility; if the credibility state of the entry is high credibility, and the credibility state of all entries older than the entry is high credibility, it is determined that the entry satisfies the update condition, indicating that the branch instruction corresponding to the entry and the branch instruction generated before the entry are all accurate, i.e., the path is confirmed to be the correct path, and therefore the actual execution result recorded in the entry is used to update the branch prediction table.

[0055] According to the method of the present embodiment, the branch prediction table is updated according to the program order and the credibility state, which can further guarantee the accuracy of the branch prediction table.

[0056] On the basis of the above-mentioned embodiments, the technical solutions are further described and optimized in the present embodiment. Specifically, in the present embodiment, based on the timing information of each entry in the buffer structure, the branch prediction table is updated using the actual execution result, including: creating a target entry in the buffer structure, and recording the state information of the target branch instruction, the actual execution result, the identification information of the target branch instruction, and the timing information in the target entry; updating the branch prediction table using the actual execution result; if it is determined that branch misprediction occurs, determining the rollback entries from the buffer structure according to the timing information of the target branch instruction corresponding to the branch misprediction, wherein the timing information of the rollback entries is greater than or equal to the timing information of the target branch instruction; restoring the branch prediction table according to the state information before the update of each rollback entry.

[0057] In the present embodiment, before updating the branch prediction table, a target entry is created in the buffer structure, and the state information of the target branch instruction, the actual execution result, the identification information of the target branch instruction, and the timing information are recorded in the target entry, that is, the state information of the target branch instruction is stored in the target entry before updating the branch prediction table.

[0058] After determining the actual execution result of the target branch instruction, the branch prediction table is immediately updated using the actual execution result.

[0059] Among them, the rollback entry refers to the entry that needs to be revoked when branch misprediction occurs, that is, all entries with ROB ID greater than or equal to the ROB ID of the target branch instruction of the branch misprediction. If the timing information (ROB ID) corresponding to the target branch instruction of the branch misprediction is X, that is, the entries with ROB ID greater than or equal to ROB ID X are determined from the buffer structure, these entries are the entries that need to perform rollback operation, that is, the rollback entries are determined.

[0060] Specifically, if it is determined that branch misprediction occurs, the timing information of the target branch instruction corresponding to the branch misprediction is determined, and the rollback entries with timing information greater than or equal to the timing information of the target branch instruction are determined from the buffer structure, that is, the entries no earlier than the target branch instruction are determined as the rollback entries, and the branch prediction table is restored according to the state information before the update of each rollback entry. In the present embodiment, the branch prediction table can be updated immediately to improve the efficiency of updating the branch prediction table, and the state of the branch instruction before updating the branch prediction table can be backed up, so that the branch prediction table can be restored when branch misprediction occurs, thereby avoiding the pollution of the branch prediction table and improving the accuracy of the branch prediction table.

[0061] Based on the above embodiments, this embodiment further explains and optimizes the technical solution. Specifically, in this embodiment, the prediction result is obtained by querying the branch prediction table according to the current PC address, including: The prediction results are obtained by querying the branch prediction table and the buffer structure based on the current PC address.

[0062] It is understandable that the entries stored in the buffer structure include the actual execution result determined immediately after the branch instruction has finished executing. In this embodiment, when branch prediction is required, the branch prediction table and the buffer structure are queried respectively. If there is an entry in the buffer structure that matches the current PC address, the actual execution result in the buffer structure is used as the prediction result corresponding to the current PC address; otherwise, the prediction result corresponding to the current PC address is retrieved from the branch prediction table.

[0063] In each preset cycle, FBC checks each entry and determines whether it is the entry with the smallest time sequence information (i.e., the oldest entry) based on the time sequence information corresponding to the entry. If so, the entry meets the update conditions, and the branch prediction table is updated using the actual execution result in that entry. After the update is completed, the entry is marked as invalid so that other subsequent entries can be identified as the oldest entries.

[0064] According to the method of this embodiment, the prediction result is determined based on the branch prediction table and the buffer structure. If there is an entry in the buffer structure corresponding to the current PC address, the accuracy of the prediction information can be improved and the efficiency of updating the branch prediction table can be increased.

[0065] Based on the above embodiments, this embodiment further explains and optimizes the technical solution. Specifically, in this embodiment, the process of determining when a branch misprediction occurs includes: The prediction result is obtained by querying the branch prediction table based on the current PC address; The target branch instruction is determined from the branch instructions with operands ready, and the instruction is issued and executed based on the target branch instruction to obtain the actual execution result; If the predicted result is inconsistent with the actual execution result, then a branch misprediction has occurred.

[0066] In this embodiment, the branch prediction table is first queried based on the current PC address to determine the prediction result corresponding to the current PC address. The prediction result includes the prediction direction and the prediction target address; the prediction direction indicates whether the branch instruction is to "jump" or "not jump"; the prediction target address refers to the target address corresponding to the prediction direction being "jump".

[0067] The target branch instruction refers to a branch instruction with the minimum (oldest) timing information. The target branch instruction is determined among the branch instructions that are operand-ready, and is emitted and executed based on the target branch instruction to obtain an actual result. The actual result includes an actual direction and an actual target address. The actual direction indicates whether the branch instruction is actually executed by a jump (Taken) or a non-jump (Not Taken) operation, and the actual target address refers to a target address corresponding to the jump operation.

[0068] In a specific example, a PU (branch instruction predictor) accesses a branch prediction table according to a current PC address to obtain a prediction result, and sends the prediction result to an IFU. After the IFU obtains the prediction result, the IFU obtains an instruction stream from an instruction cache (high-speed memory) according to a prediction target address. A decode module (Decode) identifies a branch instruction in the instruction stream to generate a corresponding decode packet. The branch instruction includes BEQ, BNE, JAL, and the like. The decode packet includes an instruction type, registers required, and an identifier indicating whether the instruction is a branch instruction. A rename module (Rename) allocates a ROB ID (reorder buffer) for all instructions. The ROB ID defines an age order of the instructions in a program, and the smaller the ID, the older the instruction. A dispatch module (Dispatch) writes the decode packet into a ROB entry corresponding to the instruction. The identified branch instruction, together with its operand (if ready) and ROB ID, is sent to a waiting queue of a corresponding branch execution unit. After receiving the branch instruction, the branch execution unit selects an old (i.e., with the smallest ROB ID) instruction from the branch instructions that are operand-ready to emit and execute (i.e., out-of-order emission) the instruction to obtain an actual result.

[0069] Then, the branch execution unit compares whether the prediction result is consistent with the actual result. If the prediction result is consistent with the actual result, it indicates that the prediction is correct, and thus the branch instruction is marked as “completed” in the ROB of the branch instruction, and a path of a subsequent instruction of the branch instruction is confirmed to be valid. If the prediction result is not consistent with the actual result, a prediction table update request is generated according to the actual result, and the prediction table update request is sent to the BPU.

[0070] According to the method of the embodiment, the prediction table update request can be accurately determined to improve the accuracy of the branch prediction table.

[0071] Based on the above embodiment, the technical solution is further described and optimized in the embodiment. Specifically, after determining that the prediction result is not consistent with the actual execution result, the method further includes: generating a global flush request according to timing information of the target branch instruction. The global flush request is used to clear all entries that are younger than the target branch instruction in program order.

[0072] In this embodiment, after determining that the prediction result is inconsistent with the actual execution result, that is, after determining that branch misprediction occurs, a global flush request is generated according to the timing information of the target branch instruction. Specifically, a global flush request is initiated to all related modules, such as the BPU, the IFU, the register mapping table, and the like; the content of the global flush request is: deleting all branch instructions and corresponding state information whose timing information is not earlier than the timing information of the target branch instruction.

[0073] The embodiment further deletes the error information of the target branch instruction corresponding to the branch misprediction through the global flush request, thereby guaranteeing the accuracy of the branch prediction table.

[0074] In order for those skilled in the art to better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be described in detail below in combination with actual application scenarios. In the embodiments of the present application, the specific steps of the updating method of the branch prediction table are as follows: Step 1: The BPU (branch instruction predictor) accesses the branch prediction table according to the current PC address to obtain a prediction result, and sends the prediction result to the IFU; the prediction result includes a prediction direction and a prediction target address; wherein the prediction direction indicates whether the branch instruction is “jump” or “not jump”; the prediction target address refers to the target address corresponding to the case where the prediction direction is “jump”; Step 2: After the IFU obtains the prediction result, the instruction stream is obtained from the instruction Cache (high-speed memory) according to the prediction target address; Step 3: The decode module (Decode) identifies the branch instruction in the instruction stream to generate a corresponding decode packet; wherein the branch instruction includes BEQ, BNE and JAL, etc.; the decode packet includes the instruction type, the registers required, and the identification of whether it is a branch instruction; Step 4: The renaming module (Rename) allocates a ROB ID for all instructions; the ROB ID defines the age order of the instructions in the program, and the smaller the ID, the older the instruction; Step 5: The dispatch module (Dispatch) writes the decode packet into the ROB entry corresponding to the instruction; the identified branch instruction, together with its operand (if ready) and ROB ID, is sent to the waiting queue of the corresponding branch execution unit; Step 6: After receiving the branch instruction, the branch execution unit selects an old (i.e. ROB ID smaller) instruction from the branch instruction with operands ready to be issued and executed (i.e. out-of-order issue), and obtains the actual result; the actual result includes the actual direction and the actual target address; wherein the actual direction indicates whether the branch instruction actually performs a jump (Taken) or a non-jump (Not Taken) operation, and the actual target address refers to the corresponding target address when the jump operation is performed; the branch execution unit compares whether the predicted result recorded in the ROB is consistent with the actual result; If consistent, it means that the prediction is correct, so the branch instruction in the ROB is marked as "complete", and the path of the subsequent instructions is confirmed to be valid; If inconsistent, it means that branch misprediction occurs; therefore, the ROB is sent a misprediction notification, such as "instruction with ROB ID X is mispredicted"; after the ROB receives one or more misprediction notifications, the oldest one is selected as the target branch instruction from all mispredicted instructions that need to be processed according to the timing information (ROB ID), and the corresponding timing information ROB ID = X is determined; Step 7: The ROB controller initiates a global flush request to all relevant modules of the CPU (including the BPU, the IFU, the register mapping table, etc.); the content of the global flush request is: all instructions with ROB ID greater than or equal to X and all related state information are emptied, and the PC is reset to the correct address of the mispredicted instruction; the ROB simultaneously generates a prediction table update request according to the actual execution result, and sends the prediction table update request to the BPU, requesting the BPU to update the branch prediction table accordingly; Step 8: After receiving the prediction table update request, the BPU places the prediction table update request (including the actual execution result, the identification information of the target branch instruction, and the timing information) into the buffer structure FBC; Step 9: The FBC checks whether each entry meets the update condition in each prediction cycle: whether the credibility state of the entry is high credibility, and whether the credibility state of all entries older than the entry is high credibility; If the update condition is met, the branch prediction table is updated using the actual execution result in the entry; If the update condition is not met, no other operation is performed, and the entry continues to wait in the FBC. During the waiting period, the entry may be confirmed to have correct prediction information, and the credibility state of the entry can be adjusted from low credibility to high credibility.

[0075] The embodiment of the present application provides a branch prediction table updating method, actual execution results of a target branch instruction are acquired, and timing information of the target branch instruction in program order is acquired; a target entry is created in a buffer structure, and the actual execution results, identification information of the target branch instruction and the timing information are recorded in the target entry; and the branch prediction table is updated based on the timing information of each entry in the buffer structure and the actual execution results. It can be seen that the method is based on the program order of the branch instruction to cache each entry including the actual execution results, the identification information of the target branch instruction and the timing information, that is, the program order is used to manage the entries in the buffer structure, the branch prediction table is updated based on the timing information of each entry in the buffer structure and the actual execution results, and the possibility of pollution caused by out-of-order updating of the branch prediction table is avoided. Therefore, the method can improve the accuracy of the prediction table when the prediction table is updated in an out-of-order execution environment.

[0076] It should be understood that the size of the serial number of each step in the above embodiment does not mean the order of execution, and the execution order of each process should be determined according to its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application.

[0077] It should be noted that the information collection process (such as the face image collection process, the fingerprint information collection process, etc.) / feature extraction process involved in the present application is executed with the user's knowledge and permission, that is, the information collection process / feature extraction process meets the legal and regulatory requirements and does not belong to the act of obstructing public interests.

[0078] Figure 2 As shown, the embodiment of the present application provides a structure schematic diagram of a branch prediction table updating device. As shown, the branch prediction table updating device of the embodiment comprises: Figure 2 An obtaining module 210 is configured to obtain actual execution results of a target branch instruction, and obtain timing information of the target branch instruction in program order. An obtaining module 210 is configured to obtain actual execution results of a target branch instruction, and obtain timing information of the target branch instruction in program order. A recording module 220 is configured to create a target entry in a buffer structure, and record the actual execution results, identification information of the target branch instruction and the timing information in the target entry. An updating module 230 is configured to update the branch prediction table based on the timing information of each entry in the buffer structure and the actual execution results.

[0079] The branch prediction table updating device provided by the embodiment of the present application has the same beneficial effects as the branch prediction table updating method.

[0080] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.

[0081] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0082] Figure 3 This is a schematic diagram of the structure of a terminal device provided in an embodiment of this application. Figure 3 As shown, the terminal device 300 of this embodiment includes a memory 310, a processor 320, and a computer program 330 stored in the memory 310 and executable on the processor 320; when the processor 320 executes the computer program 330, it implements the steps in the above-described branch prediction table update method embodiments; or when the processor 320 executes the computer program 330, it implements the functions of each module / unit in the above-described device embodiments.

[0083] For example, computer program 330 can be divided into one or more modules / units, one or more of which are stored in memory 310 and executed by processor 320 to implement the method of the embodiments of this application. One or more modules / units can be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of computer program 330 in terminal device 300. For example, computer program 330 can be divided into multiple modules, each with the following specific functions: The acquisition module is used to acquire the actual execution result of the target branch instruction and acquire the timing information of the target branch instruction in the program sequence; The recording module is used to create a target entry in the buffer structure and record the actual execution result, the identification information of the target branch instruction, and the timing information in the target entry; An updating module is configured to update the branch prediction table based on the actual execution result and the time sequence information of each entry in the buffer structure.

[0084] In applications, the terminal device 300 can be a desktop computer, a notebook computer, a palm computer, a cloud server, and the like. The terminal device 300 can include but is not limited to a memory 310 and a processor 320. Those skilled in the art can understand that the terminal device 300 can include more or fewer components than those shown in the figure, or some components can be combined, or different components can be included, for example, the terminal device can also include an input / output device, a network access device, a bus, and the like; the input / output device can include a camera, an audio acquisition / play device, a display screen, and the like; the network access device can include a communication module for wireless communication with an external device. Figure 3 The terminal device is only an example and does not constitute a limitation on the terminal device, and can include more or fewer components than those shown in the figure, or some components can be combined, or different components can be included, for example, the terminal device can also include an input / output device, a network access device, a bus, and the like; the input / output device can include a camera, an audio acquisition / play device, a display screen, and the like; the network access device can include a communication module for wireless communication with an external device.

[0085] In applications, the processor can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic components, discrete hardware components, and the like. The general-purpose processor can be a microprocessor or the processor can be any conventional processor.

[0086] In applications, the memory can be an internal storage unit of the terminal device, for example, a hard disk or a memory of the terminal device; or can be an external storage device of the terminal device, for example, a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, and the like; or can include both the internal storage unit and the external storage device. The memory is used to store an operating system, application programs, a boot loader, data, and other programs, for example, program codes of computer programs, and the like. The memory can also be used to temporarily store data that has been output or will be output.

[0087] The embodiment of the present application further provides a computer readable storage medium, which stores a computer program. When the computer program is executed by a processor, the steps in each of the above-mentioned method embodiments can be implemented.

[0088] The computer program codes can be in the form of source codes, object codes, executable files or some intermediate form. The computer readable medium can include any entity or device capable of carrying the computer program codes, recording medium, computer memory, Read-Only Memory (ROM), Random Access Memory (RAM), electric carrier signal, telecommunication signal and software distribution medium. For example, the U disk, mobile hard disk, magnetic disk or optical disk, etc.

[0089] The computer readable storage medium provided by the embodiments of the present application has the same beneficial effects as the updating method of the branch prediction table.

[0090] The computer program product provided by the embodiments of the present application has the same beneficial effects as the updating method of the branch prediction table.

[0091] The computer program product provided by the embodiments of the present application has the same beneficial effects as the updating method of the branch prediction table.

[0092] In the above embodiments, the description of each embodiment has its own focus, and the parts not described or recorded in a certain embodiment can be referred to the relevant description of other embodiments.

[0093] Those skilled in the art can realize that the devices and algorithm steps of the examples described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solutions. The skilled person can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0094] In the embodiments provided by the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, and another point is that the coupling or direct coupling or communication connection between the shown or discussed mutual elements can be through some interface, indirect coupling or communication connection between devices can be electrical, mechanical or other forms.

[0095] The above-described embodiments are only used to illustrate the technical solutions of the present application, but not limit them; although the present application is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A method of updating a branch prediction table, characterized by, The method comprises: acquiring actual execution result of a target branch instruction and time sequence information of the target branch instruction in program order; creating a target entry in a buffer structure and recording the actual execution result, identification information of the target branch instruction and the time sequence information in the target entry; updating the branch prediction table based on the time sequence information of each entry in the buffer structure and the actual execution result.

2. The method of claim 1, wherein, The updating of the branch prediction table based on the time sequence information of each entry in the buffer structure and the actual execution result comprises: checking whether each entry in the buffer structure meets an updating condition; the updating condition is determined according to the time sequence information; if any of the entries meets the updating condition, updating the branch prediction table with the actual execution result corresponding to the entry.

3. The method of claim 2, wherein, The determination that the entry meets the updating condition comprises: if the entry is determined to be the oldest entry according to the program order of the entry, it is determined that the entry meets the updating condition.

4. The method of claim 2, wherein, The creating of the target entry in the buffer structure and the recording of the actual execution result, the identification information of the target branch instruction and the time sequence information in the target entry comprise: if it is determined that branch misprediction occurs, creating a target entry in the buffer structure and recording the actual execution result, the identification information of the target branch instruction and the time sequence information in the target entry, and setting the credibility state of the target entry to high credibility; The determination that the entry meets the updating condition comprises: if the credibility state of the entry is high credibility and the credibility state of all entries older than the entry is high credibility, it is determined that the entry meets the updating condition.

5. The method of claim 1, wherein, The updating of the branch prediction table based on the time sequence information of each entry in the buffer structure and the actual execution result comprises: creating a target entry in the buffer structure and recording the state information of the target branch instruction, the actual execution result, the identification information of the target branch instruction and the time sequence information in the target entry; updating the branch prediction table with the actual execution result; if it is determined that branch misprediction occurs, determining rollback entries from the buffer structure according to the time sequence information of the target branch instruction corresponding to the branch misprediction, wherein the time sequence information of the target branch instruction is greater than or equal to the time sequence information of the target branch instruction; restoring the branch prediction table according to the state information before updating of each rollback entry.

6. The method according to any one of claims 2 to 5, characterized in that, The process of determining that branch misprediction occurs comprises: inquiring the branch prediction table according to a current PC address to obtain a prediction result; determining a target branch instruction from branch instructions with operands ready and performing emission and execution based on the target branch instruction to obtain an actual execution result; if the prediction result is inconsistent with the actual execution result, it is determined that branch misprediction occurs.

7. The method of claim 6, wherein, The inquiring of the branch prediction table according to the current PC address to obtain the prediction result comprises: inquiring the branch prediction table and the buffer structure according to the current PC address respectively to obtain the prediction result.

8. The method of claim 7, wherein, After determining that the predicted result is inconsistent with the actual execution result, the method further comprises: generating a global flush request according to the timing information of the target branch instruction; the global flush request is used to clear all entries that are younger than the target branch instruction in program order.

9. A terminal device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, The processor implements the steps of the method of any one of claims 1 to 8 when executing the computer program.

10. A computer program product comprising a computer program, characterized in that, The computer program, when executed by a processor, implements the steps of the method of any one of claims 1 to 8.

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