Electronic paper driving circuit and electronic paper

Abstract

An electronic paper driving circuit and electronic paper, comprising a first scan line, a second scan line, a data line, a display unit and a compensation unit, the display unit comprising a pixel electrode, a first thin film transistor, a second thin film transistor and a storage capacitor, the compensation unit comprising a third thin film transistor and a comparator, the second end of the first thin film transistor is electrically connected with the second end of the second thin film transistor and the pixel electrode, the control end is connected with the first scan line, and the first end is connected with the data line; the first end of the second thin film transistor is electrically connected with the storage capacitor, the first end of the third thin film transistor and the positive input end of the comparator, the control end is connected with the second scan line, the second end of the third thin film transistor is connected with the data line, the control end is connected with the output end of the comparator, the negative input end is connected with a reference voltage, and the comparator is used for receiving a storage voltage and controlling the data line to perform charge compensation on the storage capacitor through the third thin film transistor according to the storage voltage and the reference voltage, so that the power consumption of the electronic paper is reduced.

Description

Technical Field

[0001] This application relates to the field of electronic paper technology, specifically to an electronic paper driving circuit and electronic paper. Background Technology

[0002] Electronic paper is a novel display technology designed to mimic the look and reading experience of traditional paper. Its key features include low power consumption, clear readability even in sunlight, flexible display, and portability. While electronic paper requires maintaining a static image for extended periods due to its ultra-low power consumption, it is forced to increase its refresh rate when the potential of the storage capacitors continuously decays due to leakage current in the off-state, leading to image retention, reduced contrast, and other picture defects. This results in increased power consumption. Summary of the Invention

[0003] The purpose of this application is to provide an electronic paper driving circuit and electronic paper, which solves the problem that the storage capacitor potential continuously decays due to the leakage current in the off state, which easily causes image ghosting, decreased contrast, and increased power consumption due to forced increase in refresh rate.

[0004] To achieve the objectives of this application, the following technical solution is provided: In a first aspect, the present invention provides an electronic paper driving circuit, comprising: a first scan line, a second scan line, and a data line, wherein the first scan line is used to output a first scan signal, the second scan line is used to output a second scan signal, and the data line is used to output a data signal; a display unit, comprising a pixel electrode, a first thin-film transistor, a second thin-film transistor, and a storage capacitor, wherein the second terminal of the first thin-film transistor is electrically connected to the second terminal of the second thin-film transistor and the pixel electrode, the control terminal of the first thin-film transistor is electrically connected to the first scan line, the first terminal of the first thin-film transistor is electrically connected to the data line, the control terminal of the second thin-film transistor is electrically connected to the second scan line, one end of the storage capacitor is electrically connected to the first terminal of the second thin-film transistor, and the other end is used for... The device is electrically connected to a common electrode; a compensation unit includes a third thin-film transistor and a comparator. A first terminal of the third thin-film transistor is electrically connected to a first terminal of a second thin-film transistor, a second terminal of the third thin-film transistor is electrically connected to the data line, a control terminal of the third thin-film transistor is electrically connected to the output terminal of the comparator, a positive input terminal of the comparator is electrically connected to the storage capacitor, and a negative input terminal of the comparator is used to input a reference voltage. The comparator receives the storage voltage of the storage capacitor and outputs a compensation signal to the control terminal of the third thin-film transistor based on the storage voltage and the reference voltage. The third thin-film transistor is turned on according to the compensation signal, so that the data line compensates the charge of the storage capacitor through the third thin-film transistor.

[0005] In one embodiment, the second thin-film transistor is an auxiliary high-resistivity thin-film transistor.

[0006] In one embodiment, the storage capacitor includes a first electrode plate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a second electrode plate stacked sequentially. One of the first electrode plate and the second electrode plate is electrically connected to a first terminal of the second thin-film transistor, and the other is used to be electrically connected to a common electrode. The surface dielectric constants of the first dielectric layer and the third dielectric layer are equal and both are greater than the surface dielectric constant of the second dielectric layer.

[0007] In one embodiment, the compensation unit further includes a detection capacitor, one end of which is connected between the storage capacitor and the positive input terminal of the comparator, and the other end is used to connect to the ground terminal.

[0008] In one embodiment, the compensation unit further includes a first resistor, a second resistor, and a third resistor. One end of the first resistor is electrically connected to the positive input terminal of the comparator, and the other end is electrically connected to both the output terminal of the comparator and one end of the second resistor. The other end of the second resistor is electrically connected to the detection capacitor. One end of the third resistor is electrically connected to the negative input terminal of the comparator, and the other end is used to input the reference voltage.

[0009] In one embodiment, there are multiple display units arranged in N rows and M columns. There are N first scan lines and N second scan lines, arranged sequentially along the column direction. The N second scan lines correspond one-to-one with the N first scan lines. There are M data lines arranged sequentially along the row direction. The M display units in the nth row are electrically connected to the nth first scan line and the nth second scan line. The N display units in the mth column are electrically connected to the mth data line. N and M are both positive integers greater than 1, n is a positive integer and 1 ≤ n ≤ N, and m is a positive integer and 1 ≤ m ≤ M. There are multiple compensation units, each connected to at least two display units. Each compensation unit includes multiple third thin-film transistors. The first terminals of the multiple third thin-film transistors are electrically connected one-to-one with multiple storage capacitors. The first terminals of the multiple third thin-film transistors are all electrically connected to the data lines. The control terminals of the multiple third thin-film transistors are all electrically connected to the output terminal of the same comparator.

[0010] In one embodiment, there are M compensation units, and N display units in the m-th column are all electrically connected to the same compensation unit.

[0011] In one embodiment, at least two adjacent display units in any direction are electrically connected to the same compensation unit, and each display unit is electrically connected to one compensation unit.

[0012] In one embodiment, the compensation unit further includes a plurality of fourth thin-film transistors, a plurality of fifth thin-film transistors, a detection line, a compensation control line, and an analog multiplexer. The first terminals of the plurality of fourth thin-film transistors are electrically connected to the plurality of storage capacitors in a one-to-one correspondence. The second terminals of the plurality of fourth thin-film transistors are all electrically connected to the detection line. The control terminals of the plurality of fourth thin-film transistors are electrically connected to the plurality of second scan lines in a one-to-one correspondence. The second terminals of the plurality of fifth thin-film transistors are electrically connected to the control terminals of the plurality of third thin-film transistors in a one-to-one correspondence. The first terminals of the plurality of fifth thin-film transistors are all electrically connected to the compensation control line. The control terminals of the plurality of fifth thin-film transistors are electrically connected to the plurality of second scan lines in a one-to-one correspondence. The analog multiplexer connects the detection line and the positive input terminal of the comparator. The compensation control line is electrically connected to the output terminal of the comparator. The analog multiplexer is used for electrical connection with a timing controller.

[0013] In a second aspect, the present invention also provides an electronic paper, comprising a source driver, a gate driver, and an electronic paper driving circuit as described in any one of the embodiments of the first aspect, wherein the electronic paper driving circuit is electrically connected to both the source driver and the gate driver.

[0014] The electronic paper driving circuit provided by this invention comprises a first scan line, a second scan line, a data line, a display unit, and a compensation unit. The first scan line outputs a first scan signal, the second scan line outputs a second scan signal, and the data line outputs a data signal. The display unit includes a pixel electrode, a first thin-film transistor, a second thin-film transistor, and a storage capacitor. The second terminal of the first thin-film transistor is electrically connected to both the second terminal of the second thin-film transistor and the pixel electrode. The control terminal of the first thin-film transistor is electrically connected to the first scan line, and the first terminal of the first thin-film transistor is electrically connected to the data line. The control terminal of the second thin-film transistor is electrically connected to the second scan line. One end of the storage capacitor is electrically connected to the first terminal of the second thin-film transistor, and the other end is electrically connected to a common electrode. The compensation unit includes a third thin-film transistor. The circuit consists of a body transistor and a comparator. The first terminal of the third thin-film transistor is electrically connected to the first terminal of the second thin-film transistor, the second terminal of the third thin-film transistor is electrically connected to the data line, the control terminal of the third thin-film transistor is electrically connected to the output terminal of the comparator, the positive input terminal of the comparator is electrically connected to the storage capacitor, and the negative input terminal of the comparator is used to input a reference voltage. The comparator receives the storage voltage of the storage capacitor and outputs a compensation signal to the control terminal of the third thin-film transistor according to the storage voltage and the reference voltage. The third thin-film transistor is turned on according to the compensation signal, so that the data line can perform charge compensation on the storage capacitor through the third thin-film transistor. This allows the electronic paper driving circuit to detect the potential of the storage capacitor and perform charge compensation through the compensation module, preventing poor image quality on the electronic paper and reducing the power consumption of the electronic paper. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0016] Figure 1 This is a circuit diagram of an electronic paper driving circuit according to one embodiment; Figure 2 This is a circuit diagram of an electronic paper driving circuit according to another embodiment; Figure 3 This is a potential diagram of an electronic paper driving circuit according to one embodiment; Figure 4 This is a cross-sectional view of a storage capacitor according to one embodiment; Figure 5 This is a schematic diagram of the panel structure of an electronic paper according to one embodiment; Figure 6 This is a schematic diagram of the panel structure of an electronic paper according to another embodiment; Figure 7 This is a schematic diagram of the panel structure of electronic paper according to another embodiment.

[0017] Explanation of reference numerals in the attached figures: 1000-Electronic Paper; 100-Electronic paper driving circuit; 10 - Display unit, P - Pixel electrode, T1 - First thin film transistor, T2 - Second thin film transistor, Cs - Storage capacitor, A1 - First electrode plate, A2 - Second electrode plate, B1 - First dielectric layer, B2 - Second dielectric layer, B3 - Third dielectric layer; 20-Compensation unit, 21-Comparator, 22-Analog multiplexer, 23-Selector, T3-Third thin-film transistor, T6-Switch, Cd-Detection capacitor, R1-First resistor, R2-Second resistor, R3-Third resistor, T4-Fourth thin-film transistor, T5-Fifth thin-film transistor, L1-Detection line, L2-Compensation control line; G1 - First scan line, G2 - Second scan line, D - Data line, Vcom - Common electrode, GND - Ground terminal, Gate1 - First scan signal, Gate2 - Second scan signal, S - Data signal, Vref - Reference voltage, V1 - First threshold voltage, V2 - Second threshold voltage, V3 - Storage voltage, V4 - Compensation signal; SOC - Source Driver, GOA - Gate Driver, TCON - Timing Controller; T - driving cycle, t1 - refresh period, t2 - hold period, t3 - compensation period. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] It should be noted that when a component is said to be "fixed" to another component, it can be directly on the other component or it can be in a middle component. When a component is said to be "connected" to another component, it can be directly connected to the other component or it may be in a middle component.

[0020] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology used in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items.

[0021] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0022] Please refer to Figures 1 to 3 This invention provides an electronic paper driving circuit 100, including a first scan line G1, a second scan line G2, a data line D, a display unit 10, and a compensation unit 20. The first scan line G1 is used to output a first scan signal Gate1, the second scan line G2 is used to output a second scan signal Gate2, and the data line D is used to output a data signal S. The display unit 10 includes a pixel electrode P, a first thin-film transistor T1, a second thin-film transistor T2, and a storage capacitor Cs. The second terminal of the first thin-film transistor T1 is electrically connected to the second terminal of the second thin-film transistor T2 and the pixel electrode P. The control terminal of the first thin-film transistor T1 is electrically connected to the first scan line G1, the first terminal of the first thin-film transistor T1 is electrically connected to the data line D, the control terminal of the second thin-film transistor T2 is electrically connected to the second scan line G2, and one end of the storage capacitor Cs is connected to the first terminal of the second thin-film transistor T2. The compensation unit 20 includes a third thin-film transistor T3 and a comparator 21. The first end of the third thin-film transistor T3 is electrically connected to the first end of the second thin-film transistor T2, the second end of the third thin-film transistor T3 is electrically connected to the data line D, the control terminal of the third thin-film transistor T3 is electrically connected to the output terminal of the comparator 21, the positive input terminal of the comparator 21 is electrically connected to the storage capacitor Cs, and the negative input terminal of the comparator 21 is used to input the reference voltage Vref. The comparator 21 is used to receive the storage voltage V3 of the storage capacitor Cs and output a compensation signal V4 to the control terminal of the third thin-film transistor T3 according to the storage voltage V3 and the reference voltage Vref. The third thin-film transistor T3 is used to turn on according to the compensation signal V4 so that the data line D performs charge compensation on the storage capacitor Cs through the third thin-film transistor T3.

[0023] In a specific implementation, the second thin-film transistor T2 is an auxiliary high-resistivity thin-film transistor. Specifically, the electronic paper driving circuit 100 sequentially passes through a refresh period t1, a hold period t2, and a compensation period t3 within one driving cycle T. When the electronic paper driving circuit 100 is in the refresh period t1, the first scan signal Gate1 is the target grayscale voltage, the second scan signal Gate2 is at a low level, and the data signal S is the target grayscale voltage. This causes the first thin-film transistor T1 to turn on, the second thin-film transistor T2 and the third thin-film transistor T3 to turn off, and the data line D to charge the pixel electrode P through the first thin-film transistor T1, making the voltage of the pixel electrode P the target grayscale voltage, and forming a driving electric field between it and the common electrode Vcom. The electronic ink particles move under the action of the electric field to present an image of the corresponding grayscale. At the same time, since the second thin-film transistor T2 remains in a high-resistivity state (i.e., not completely insulated) when it is off, while the data line D charges the pixel electrode P, the charge on the pixel electrode P will slowly move through the second thin-film transistor T2 to the storage capacitor Cs to slowly charge the storage capacitor Cs until the storage capacitor Cs is charged to the target grayscale voltage.

[0024] In this circuit, when the storage voltage V3 is lower than the reference voltage Vref, to prevent the third thin-film transistor T3 from turning on during the refresh period t1 and affecting the charging process of the storage capacitor Cs, a switch T6 is provided between the control terminal of the third thin-film transistor T3 and the ground terminal GND. The control terminal of the switch T6 is electrically connected to the timing controller TCON. When the electronic paper driving circuit 100 is in the refresh period t1, the timing controller TCON controls the switch T6 to turn on, so that the control terminal of the third thin-film transistor T3 is grounded, making the voltage input to the control terminal of the third thin-film transistor T3 low, and the compensation unit 20 is in a silent state. Optionally, the switch T6 is a thin-film transistor, with its control terminal electrically connected to the timing controller TCON, its first terminal connected to the ground terminal GND, and its second terminal electrically connected to the control terminal of the third thin-film transistor T3.

[0025] For a detailed implementation, please refer to Figure 4The storage capacitor Cs includes a first electrode A1, a first dielectric layer B1, a second dielectric layer B2, a third dielectric layer B3, and a second electrode A2 stacked sequentially. One of the first electrode A1 and the second electrode A2 is electrically connected to the first terminal of the second thin-film transistor T2, and the other is used to be electrically connected to the common electrode Vcom. The surface dielectric constants of the first dielectric layer B1 and the third dielectric layer B3 are equal and both are greater than the surface dielectric constant of the second dielectric layer B2. In this embodiment, the first dielectric layer B1 and the third dielectric layer B3 are both made of HfO2, and the second dielectric layer B2 is made of SiO2, so that the surface dielectric constants of the first dielectric layer B1 and the third dielectric layer B3 are higher than the surface dielectric constant of the second dielectric layer B2. The first dielectric layer B1 and the third dielectric layer B3 are used to achieve rapid charge storage, and the second dielectric layer B2 has good insulation properties to suppress leakage current penetration and reduce charge loss.

[0026] When the electronic paper driving circuit 100 is in the holding period t2, the first scan signal Gate1 is low, the second scan signal Gate2 is high, and the data signal S is low. The timing controller TCON controls the aforementioned switch T6 to close, so that the first thin film transistor T1 is closed, the second thin film transistor T2 is open, and the compensation unit 20 enters the monitoring state from the silent state. That is, the compensation signal V4 is high or low, which is controlled by the comparator 21. The storage capacitor Cs is connected to the pixel electrode P through the second thin film transistor T2 to maintain the voltage of the pixel electrode P at the target gray level. Since the impedance of the second thin film transistor T2 is high, the amount of charge on the storage capacitor Cs lost through the first thin film transistor T1 is reduced, which effectively reduces the leakage current of the electronic paper driving circuit 100 and avoids additional charge loss. At the same time, since the storage voltage V3 is higher than the reference voltage Vref, the compensation signal V4 output by the comparator 21 is low.

[0027] When the electronic paper 1000 maintains a static image for an extended period, i.e., during the long holding period t2, the storage voltage V3 will continue to decay due to the off-state leakage current of the first thin-film transistor T1. When the storage voltage V3 decreases from the target grayscale voltage and is greater than or equal to the reference voltage Vref, the compensation signal V4 output by the comparator 21 is low. When the storage voltage V3 decreases from the target grayscale voltage to below the reference voltage Vref, the compensation unit 20 switches from the monitoring state to the working state, and the compensation signal V4 output by the comparator 21 becomes high, causing the third thin-film transistor T3 to turn on. The data signal S switches from low to high, allowing the data line D to charge the storage capacitor Cs through the third thin-film transistor T3, causing the storage voltage V3 to rise until it is greater than or equal to the target grayscale voltage. When the storage voltage V3 is greater than or equal to the target grayscale voltage, the compensation signal V4 output by the comparator 21 switches from high to low, and the system re-enters the monitoring state.

[0028] Specifically, when the electronic paper driving circuit 100 enters the hold period t2 after the self-refresh period t1, or after a period of time after entering the hold period t2, the timing controller TCON controls the data signal S to switch from low level to high level without restriction.

[0029] For a detailed implementation, please refer to Figure 1 and Figure 2 The compensation unit 20 also includes a detection capacitor Cd. One end of the detection capacitor Cd is connected between the storage capacitor Cs and the positive input terminal of the comparator 21, and the other end is connected to the ground terminal GND. The capacitance of the detection capacitor Cd is much smaller than that of the storage capacitor Cs. For example, the capacitance of the detection capacitor Cd is 1 fF, so as to amplify the change in the storage voltage V3 through voltage amplification to improve the accuracy of the comparator 21 in receiving the storage voltage V3.

[0030] For a detailed implementation, please refer to Figure 2 The compensation unit 20 also includes a first resistor R1, a second resistor R2 and a third resistor R3. One end of the first resistor R1 is electrically connected to the positive input terminal of the comparator 21, and the other end is electrically connected to the output terminal of the comparator 21 and one end of the second resistor R2. The other end of the second resistor R2 is electrically connected to the detection capacitor Cd. One end of the third resistor R3 is electrically connected to the negative input terminal of the comparator 21, and the other end is used to input the reference voltage Vref.

[0031] When comparator 21 controls compensation signal V4 based on storage voltage V3 and reference voltage Vref, the storage voltage V3 fluctuates and oscillates when compensation unit 20 compensates storage capacitor Cs. This causes the third thin-film transistor T3 to switch frequently, making it impossible for storage voltage V3 to be stably maintained near the target gray level voltage, thus exacerbating the oscillation and reducing the lifespan of the third thin-film transistor T3.

[0032] The first resistor R1 is used to limit the current or divide the storage voltage V3 input to the comparator 21 of the storage capacitor Cs. The second resistor R2 forms positive feedback with the comparator 21 to form a first threshold voltage V1 and a second threshold voltage V2. The first threshold voltage V1 is greater than the reference voltage Vref, and the second threshold voltage V2 is less than the reference voltage Vref. When the storage voltage V3 is greater than the first threshold voltage V1, the compensation signal V4 output by the comparator 21 is low. When the storage voltage V3 is less than the second threshold voltage V2, the compensation signal V4 output by the comparator 21 is high. When the storage voltage V3 is greater than or equal to the second threshold voltage V2 and less than or equal to the first threshold voltage V1, the compensation signal V4 output by the comparator 21 remains unchanged. This ensures that when the storage voltage V3 is compensated to near the target gray level voltage, it will not cause the third thin film transistor T3 to switch frequently, avoiding the risk of oscillation. This is beneficial to ensuring that the amount of charge injected into the storage capacitor Cs matches the leakage loss of the storage capacitor Cs, and ensuring that the voltage of the storage capacitor Cs is stably maintained within the target range.

[0033] In a specific implementation, there are multiple display units 10, arranged in N rows and M columns. There are N first scan lines G1 and N second scan lines G2. The N first scan lines G1 are arranged sequentially along the column direction. The N second scan lines G2 are arranged in a one-to-one correspondence with the N first scan lines G1. There are M data lines D, arranged sequentially along the row direction. The M display units 10 in the nth row are electrically connected to the nth first scan line G1 and the nth second scan line G2. The N display units 10 in the mth column are electrically connected to the mth data line D. N and M are both positive integers greater than 1, n is a positive integer and 1 ≤ n ≤ N, and m is a positive integer and 1 ≤ m ≤ M.

[0034] In one implementation, please refer to Figure 5 There are multiple compensation units 20, and each compensation unit 20 is set to correspond one-to-one with a multiple display unit 10. Each compensation unit 20 compensates one display unit 10.

[0035] In another implementation method, please refer to Figure 6 and Figure 7 There are multiple compensation units 20, each compensation unit 20 is connected to at least two display units 10, each compensation unit 20 includes multiple third thin film transistors T3, the first terminal of the multiple third thin film transistors T3 is electrically connected to multiple storage capacitors Cs one by one, the first terminal of the multiple third thin film transistors T3 is electrically connected to the data line D, and the control terminal of the multiple third thin film transistors T3 is electrically connected to the output terminal of the same comparator 21, so as to reduce the number of compensation units 20 and the space occupied by the compensation units 20 in the display area.

[0036] For a detailed implementation, please refer to Figure 6 The compensation unit 20 also includes multiple fourth thin-film transistors T4, multiple fifth thin-film transistors T5, a detection line L1, a compensation control line L2, and an analog multiplexer 22. The first terminals of the multiple fourth thin-film transistors T4 are electrically connected to multiple storage capacitors Cs one-to-one. The second terminals of the multiple fourth thin-film transistors T4 are all electrically connected to the detection line L1. The control terminals of the multiple fourth thin-film transistors T4 are electrically connected to multiple second scan lines G2 one-to-one. The second terminals of the multiple fifth thin-film transistors T5 are electrically connected to the control terminals of multiple third thin-film transistors T3 one-to-one. The first terminals of the multiple fifth thin-film transistors T5 are all electrically connected to the compensation control line L2. The control terminals of the multiple fifth thin-film transistors T5 are electrically connected to multiple second scan lines G2 one-to-one. The analog multiplexer 22 is connected to the detection line L1 and the positive input terminal of the comparator 21. The compensation control line L2 is electrically connected to the output terminal of the comparator 21. The analog multiplexer 22 is used to be electrically connected to the timing controller TCON.

[0037] When multiple display units 10 connected to the same comparator 21 and located in the same row are in the compensation period t3, the corresponding fourth thin-film transistor T4 and fifth thin-film transistor T5 are turned on under the control of the corresponding second scan line G2, so that the corresponding storage capacitor Cs is connected to the detection line L1. The analog multiplexer 22 transmits the corresponding storage voltage V3 to the positive input terminal of the comparator 21 to control the opening or closing of the corresponding third thin-film transistor T3, thereby completing the compensation operation.

[0038] In one embodiment, please refer to Figure 6 There are M compensation units 20, and N display units 10 in the m-th column are all electrically connected to the same compensation unit 20. Specifically, when the n-th row display unit 10 enters the holding period t2 under the control of the first scan line G1 and the second scan line G2, the corresponding multiple fourth thin-film transistors T4 and fifth thin-film transistors T5 are turned on under the control of the second scan line G2, so that the storage capacitor Cs of the n-th row display unit 10 is connected to the corresponding detection line L1. The storage capacitor Cs of the m-th pixel unit in the n-th row outputs the storage voltage V3 to the positive input terminal of the comparator 21 of the m-th compensation unit 20 through the analog multiplexer 22 of the m-th compensation unit 20, so as to compensate for the storage voltage V3. The storage capacitor Cs is monitored. When the storage voltage V3 is greater than or equal to the reference voltage Vref, the comparator 21 outputs a compensation signal V4 to the first terminal of the fifth thin-film transistor T5 in the nth row and mth layer, which is low level, so that the third thin-film transistor T3 of the compensation module in the nth row and mth layer is turned off. When the storage voltage V3 is lower than the reference voltage Vref, the comparator 21 outputs a compensation signal V4 to the first terminal of the fifth thin-film transistor T5 in the nth row and mth layer, which is high level, so that the third thin-film transistor T3 of the compensation module in the nth row and mth layer is turned on to perform compensation operation.

[0039] In one embodiment, please refer to Figure 7 At least two adjacent display units 10 in any direction are electrically connected to the same compensation unit 20, and each display unit 10 is electrically connected to a compensation unit 20. The compensation process in this embodiment is similar to that in the above embodiments, and can be referred to without further description. The difference is that the compensation unit 20 also includes a selector 23, which is electrically connected to the output of the comparator 21, the analog multiplexer 22, and multiple compensation controllers. When multiple pixel units located in the same row, different columns, and connected to the same compensation unit 20 enter the holding period t2, the analog multiplexer 22 is used to input the stored voltage V3 output by a single pixel unit to the comparator 21 under the control of the timing controller TCON. The selector 23 is used to input the compensation signal V4 output by the comparator 21 to the first terminal of the corresponding fifth thin-film transistor T5 under the control of the analog multiplexer 22, so as to further reduce the number of comparators 21 and analog multiplexers 22. Optionally, selector 23 can also be directly electrically connected to timing controller TCON. Selector 23 is used to input the compensation signal V4 output by comparator 21 to the first terminal of the corresponding fifth thin film transistor T5 under the control of timing controller TCON.

[0040] The electronic paper driving circuit 100 provided by this invention comprises a first scan line G1, a second scan line G2, a data line D, a display unit 10, and a compensation unit 20. The first scan line G1 outputs a first scan signal Gate1, the second scan line G2 outputs a second scan signal Gate2, and the data line D outputs a data signal S. The display unit 10 includes a pixel electrode P, a first thin-film transistor T1, a second thin-film transistor T2, and a storage capacitor Cs. The second terminal of the first thin-film transistor T1 is electrically connected to the second terminal of the second thin-film transistor T2 and the pixel electrode P. The control terminal of the first thin-film transistor T1 is electrically connected to the first scan line G1, and the first terminal of the first thin-film transistor T1 is electrically connected to the data line D. The control terminal of the second thin-film transistor T2 is electrically connected to the second scan line G2. One end of the storage capacitor Cs is electrically connected to the first terminal of the second thin-film transistor T2, and the other end is electrically connected to the common electrode Vcom. The compensation unit 20 includes a third thin-film transistor... The body transistor T3 and comparator 21 are configured such that the first terminal of the third thin-film transistor T3 is electrically connected to the first terminal of the second thin-film transistor T2, the second terminal of the third thin-film transistor T3 is electrically connected to the data line D, the control terminal of the third thin-film transistor T3 is electrically connected to the output terminal of the comparator 21, the positive input terminal of the comparator 21 is electrically connected to the storage capacitor Cs, and the negative input terminal of the comparator 21 is used to input the reference voltage Vref. The comparator 21 is used to receive the storage voltage V3 of the storage capacitor Cs and outputs a compensation signal V4 to the control terminal of the third thin-film transistor T3 according to the storage voltage V3 and the reference voltage Vref. The third thin-film transistor T3 is turned on according to the compensation signal V4, so that the data line D performs charge compensation on the storage capacitor Cs through the third thin-film transistor T3. This allows the electronic paper driving circuit 100 to perform potential detection and charge compensation on the storage capacitor Cs through the compensation module, preventing poor image quality in the electronic paper 1000 and reducing the power consumption of the electronic paper 1000.

[0041] Please refer to Figures 6 to 7The present invention also provides an electronic paper 1000, including a source driver SOC, a gate driver GOA, and an electronic paper driving circuit 100 according to the embodiments of the present invention. The electronic paper driving circuit 100 is electrically connected to both the source driver SOC and the gate driver GOA. The gate driver GOA is electrically connected to multiple first scan lines G1 and multiple second scan lines G2. The source driver SOC is electrically connected to multiple data lines D. The electronic paper 1000 also includes a timing controller TCON, which is electrically connected to both the source driver SOC and the gate driver GOA. The timing controller TCON is used to control the source driver SOC to output data signals S to the multiple data lines D according to timing requirements, and to control the gate driver GOA to output first scan signals Gate1 to the multiple first scan lines G1 and second scan signals Gate2 to the multiple second scan lines G2. The timing controller TCON is also electrically connected to a compensation module.

[0042] In the description of the embodiments of this application, it should be noted that the orientation or positional relationship of the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and other indicators are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0043] The above-disclosed embodiments are merely preferred embodiments of this application and should not be construed as limiting the scope of this application. Those skilled in the art will understand that all or part of the processes for implementing the above embodiments and equivalent variations made in accordance with the claims of this application are still within the scope of this application.

Claims

1. An electronic paper driving circuit, characterized in that, include: The system includes a first scan line, a second scan line, and a data line. The first scan line is used to output a first scan signal, the second scan line is used to output a second scan signal, and the data line is used to output a data signal. The display unit includes a pixel electrode, a first thin-film transistor, a second thin-film transistor, and a storage capacitor. The second terminal of the first thin-film transistor is electrically connected to the second terminal of the second thin-film transistor and the pixel electrode. The control terminal of the first thin-film transistor is electrically connected to the first scan line. The first terminal of the first thin-film transistor is electrically connected to the data line. The control terminal of the second thin-film transistor is electrically connected to the second scan line. One end of the storage capacitor is electrically connected to the first terminal of the second thin-film transistor, and the other end is used to be electrically connected to a common electrode. The compensation unit includes a third thin-film transistor and a comparator. The first terminal of the third thin-film transistor is electrically connected to the first terminal of the second thin-film transistor, the second terminal of the third thin-film transistor is electrically connected to the data line, the control terminal of the third thin-film transistor is electrically connected to the output terminal of the comparator, the positive input terminal of the comparator is electrically connected to the storage capacitor, and the negative input terminal of the comparator is used to input a reference voltage. The comparator is used to receive the storage voltage of the storage capacitor and output a compensation signal to the control terminal of the third thin-film transistor according to the storage voltage and the reference voltage. The third thin-film transistor is used to turn on according to the compensation signal so that the data line performs charge compensation on the storage capacitor through the third thin-film transistor.

2. The electronic paper driving circuit according to claim 1, characterized in that, The second thin-film transistor is an auxiliary high-resistivity thin-film transistor.

3. The electronic paper driving circuit according to claim 1, characterized in that, The storage capacitor includes a first electrode plate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a second electrode plate stacked sequentially. One of the first electrode plate and the second electrode plate is electrically connected to the first terminal of the second thin-film transistor, and the other is used to be electrically connected to the common electrode. The surface dielectric constants of the first dielectric layer and the third dielectric layer are equal and both are greater than the surface dielectric constant of the second dielectric layer.

4. The electronic paper driving circuit according to any one of claims 1-3, characterized in that, The compensation unit also includes a detection capacitor, one end of which is connected between the storage capacitor and the positive input terminal of the comparator, and the other end is used to connect to the ground terminal.

5. The electronic paper driving circuit according to claim 4, characterized in that, The compensation unit further includes a first resistor, a second resistor, and a third resistor. One end of the first resistor is electrically connected to the positive input terminal of the comparator, and the other end is electrically connected to both the output terminal of the comparator and one end of the second resistor. The other end of the second resistor is electrically connected to the detection capacitor. One end of the third resistor is electrically connected to the negative input terminal of the comparator, and the other end is used to input the reference voltage.

6. The electronic paper driving circuit according to any one of claims 1-3, characterized in that, The display units are multiple, arranged in N rows and M columns. There are N first scan lines and N second scan lines. The N first scan lines are arranged sequentially along the column direction. The N second scan lines are arranged in a one-to-one correspondence with the N first scan lines. There are M data lines, arranged sequentially along the row direction. The M display units in the nth row are electrically connected to the nth first scan line and the nth second scan line. The N display units in the mth column are electrically connected to the mth data line. N and M are both positive integers greater than 1, n is a positive integer and 1 ≤ n ≤ N, and m is a positive integer and 1 ≤ m ≤ M. There are multiple compensation units, each of which is connected to at least two display units. Each compensation unit includes multiple third thin-film transistors. The first terminals of the multiple third thin-film transistors are electrically connected to the multiple storage capacitors in a one-to-one correspondence. The first terminals of the multiple third thin-film transistors are all electrically connected to the data line. The control terminals of the multiple third thin-film transistors are all electrically connected to the output terminal of the same comparator.

7. The electronic paper driving circuit according to claim 6, characterized in that, There are M compensation units, and N display units in the m-th column are all electrically connected to the same compensation unit.

8. The electronic paper driving circuit according to claim 6, characterized in that, At least two adjacent display units in any direction are electrically connected to the same compensation unit, and each display unit is electrically connected to one compensation unit.

9. The electronic paper driving circuit according to any one of claims 6-8, characterized in that, The compensation unit further includes multiple fourth thin-film transistors, multiple fifth thin-film transistors, a detection line, a compensation control line, and an analog multiplexer. The first terminals of the multiple fourth thin-film transistors are electrically connected to the multiple storage capacitors in a one-to-one correspondence. The second terminals of the multiple fourth thin-film transistors are all electrically connected to the detection line. The control terminals of the multiple fourth thin-film transistors are electrically connected to the multiple second scan lines in a one-to-one correspondence. The second terminals of the multiple fifth thin-film transistors are electrically connected to the control terminals of the multiple third thin-film transistors in a one-to-one correspondence. The first terminals of the multiple fifth thin-film transistors are all electrically connected to the compensation control line. The control terminals of the multiple fifth thin-film transistors are electrically connected to the multiple second scan lines in a one-to-one correspondence. The analog multiplexer connects the detection line and the positive input terminal of the comparator. The compensation control line is electrically connected to the output terminal of the comparator. The analog multiplexer is used for electrical connection with a timing controller.

10. An electronic paper, characterized in that, It includes a source driver, a gate driver, and an electronic paper driving circuit as described in any one of claims 1-9, wherein the electronic paper driving circuit is electrically connected to both the source driver and the gate driver.

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