Adjusting method and adjusting circuit of driving current, driving device and electronic equipment

Abstract

The invention provides a driving current adjusting method and circuit, a driving device and electronic equipment, and relates to the technical field of current adjustment. The resistance value of a series resistor of the short-channel FDSOI transistor is adjusted by applying a target back bias voltage to a substrate electrode of the short-channel FDSOI transistor, and finally the purpose of adjusting a driving current when a driving voltage is applied to the short-channel FDSOI transistor is achieved. Therefore, according to the technical scheme provided by the invention, the resistance value adjustment of the series resistor can be realized without changing the structure, the material and the preparation process of the FDSOI transistor, and finally the purpose of adjusting the driving current is achieved.

Description

Technical Field

[0001] This invention relates to the field of current regulation technology, and more specifically, to a method for regulating driving current, a regulating circuit, a driving device, and an electronic device. Background Technology

[0002] FDSOI (Fully Depleted Silicon On Insulator) transistors, as an alternative to planar silicon MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), offer the advantage of fabrication processes compatible with planar silicon MOSFETs, and their fabrication process is simpler. Furthermore, the ultra-thin active layer in FDSOI transistors enhances the gate's control over the channel, suppressing the short-channel effect (SCE). As the channel size of FDSOI transistors shrinks, the channel resistance continuously decreases, while the proportion of series resistance in the total resistance continuously increases, making series resistance one of the main factors affecting the performance of short-channel transistors. Simultaneously, series resistance is also one of the main factors affecting the magnitude of the drive current generated when a drive voltage is applied to an FDSOI transistor. Summary of the Invention

[0003] In view of this, the present invention provides a method for regulating the driving current, as well as a regulating circuit, driving device, and electronic device, which effectively solves the technical problems existing in the prior art. It can achieve the adjustment of the series resistance value of the FDSOI transistor without changing the structure, materials, and manufacturing process, and ultimately achieve the purpose of regulating the driving current.

[0004] To achieve the above objectives, the technical solution provided by the present invention is as follows:

[0005] A method for regulating drive current, applied to a driving device, the driving device including a short-channel FDSOI transistor and a driving power supply electrically connected to the source and drain of the short-channel FDSOI transistor, wherein the method for regulating drive current includes:

[0006] Generate adjustment signals;

[0007] The target back bias voltage is generated according to the adjustment signal;

[0008] The target back bias voltage is applied to the substrate electrode of the short-channel FDSOI transistor, and the series resistance of the short-channel FDSOI transistor is adjusted to the target resistance value so that the drive current is adjusted when the drive voltage output by the drive power supply is applied to the short-channel FDSOI transistor.

[0009] Optionally, the generation of the adjustment signal includes:

[0010] The adjustment signal is generated by looking up the data table.

[0011] Optionally, the data table includes one-to-one correspondence data between multiple back bias voltages and multiple series resistors.

[0012] Optionally, the data table includes conversion data between back bias voltage and series resistance values.

[0013] Based on the same inventive concept, the present invention also provides a driving current regulation circuit applied to a driving device, the driving device including a short-channel FDSOI transistor and a driving power supply electrically connected to the source and drain of the short-channel FDSOI transistor, wherein the driving current regulation circuit includes:

[0014] Processor, the processor being used to generate adjustment signals;

[0015] A voltage generation circuit is provided, which generates a target back bias voltage according to the adjustment signal and applies the target back bias voltage to the substrate electrode of the short-channel FDSOI transistor. The series resistance of the short-channel FDSOI transistor is adjusted to a target resistance value so that the drive current is adjusted when the drive voltage output by the drive power supply is applied to the short-channel FDSOI transistor.

[0016] Optionally, the processor is used to generate an adjustment signal by looking up a data table.

[0017] Optionally, the data table includes one-to-one correspondence data between multiple back bias voltages and multiple series resistors.

[0018] Optionally, the data table includes conversion data between back bias voltage and series resistance values.

[0019] Based on the same inventive concept, the present invention also provides a driving device, the driving device comprising:

[0020] Short-channel FDSOI transistor;

[0021] The driving power supply is electrically connected to the source and drain of the short-channel FDSOI transistor.

[0022] And, an adjustment circuit electrically connected to the substrate electrode of the short-channel FDSOI transistor, wherein the adjustment circuit is the aforementioned drive current adjustment circuit.

[0023] Based on the same inventive concept, the present invention also provides an electronic device, which includes the above-described driving device.

[0024] Compared with the prior art, the technical solution provided by the present invention has at least the following advantages:

[0025] This invention provides a method and circuit for regulating drive current, a driving device, and an electronic device. The driving device includes a short-channel FDSOI transistor and a driving power supply electrically connected to the source and drain of the short-channel FDSOI transistor. The method for regulating drive current includes: generating a regulation signal; generating a target back bias voltage based on the regulation signal; applying the target back bias voltage to the substrate electrode of the short-channel FDSOI transistor; and adjusting the series resistance of the short-channel FDSOI transistor to a target resistance value so that the driving current is regulated when the driving voltage output by the driving power supply is applied to the short-channel FDSOI transistor.

[0026] As described above, by applying a target back-bias voltage to the substrate electrode of the short-channel FDSOI transistor, the resistance value of the series resistance of the short-channel FDSOI transistor is adjusted, ultimately achieving the purpose of regulating the drive current when the drive voltage is applied to the short-channel FDSOI transistor. Therefore, the technical solution provided by this invention can achieve the adjustment of its series resistance value and ultimately the purpose of driving current regulation without changing the structure, materials, and fabrication process of the FDSOI transistor. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0028] Figure 1 A flowchart illustrating a method for adjusting drive current according to an embodiment of the present invention;

[0029] Figure 2 This is a schematic diagram of the structure of a driving device provided in an embodiment of the present invention;

[0030] Figure 3 An IV characteristic curve of a short-channel FDSOI transistor provided for an embodiment of the present invention;

[0031] Figure 4 A graph of series resistance extracted using a TLM model is provided for an embodiment of the present invention;

[0032] Figure 5 A curve showing the change in drive current when the series resistance of a short-channel FDSOI transistor is changed by a simulator, provided as an embodiment of the present invention.

[0033] Figure 6 A graph showing the variation of series resistance and total resistance with driving voltage in a short-channel FDSOI transistor, provided as an embodiment of the present invention;

[0034] Figure 7 A flowchart of another method for adjusting the drive current provided in an embodiment of the present invention;

[0035] Figure 8 A schematic diagram of a drive current adjustment circuit provided in an embodiment of the present invention;

[0036] Figure 9 This is a schematic diagram of a driving device provided in an embodiment of the present invention. Detailed Implementation

[0037] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0038] As described in the background section, FDSOI transistors, as an alternative to planar silicon MOSFETs, offer the advantage of fabrication processes compatible with planar silicon MOSFETs, and the fabrication process of FDSOI transistors is simpler. Furthermore, the ultra-thin active layer in FDSOI transistors enhances the gate's control over the channel, achieving suppression of source-channel interference (SCE). With the miniaturization of the FDSOI transistor channel size, the channel resistance continues to decrease, while the proportion of series resistance in the total resistance continues to increase. The series resistance (i.e., the parasitic resistance Rd of the source-drain region of the FDSOI transistor)... SD This has become one of the main factors affecting the performance of short-channel transistors. At the same time, series resistance is also one of the main factors affecting the magnitude of the drive current generated when a drive voltage is applied to an FDSOI transistor.

[0039] In existing technologies, adjusting the series resistance of an FDSOI transistor typically involves regulating the source-drain annealing temperature during the FDSOI transistor fabrication process. This adjusts the depth of diffusion from the source-drain region into the spacer and channel regions, thereby controlling the series resistance. The principle is to change the transport length of charge carriers in regions other than the channel to regulate the series resistance. However, this method of adjusting the series resistance of an FDSOI transistor by changing the source-drain annealing temperature alters the effective channel length. This is particularly true in short-channel FDSOI transistors, where diffusion in the source-drain region changes the effective channel length. In short-channel FDSOI transistors, performance is highly sensitive to changes in the effective channel length. Therefore, all techniques involving changing the annealing temperature degrade the stability of the FDSOI transistor, ultimately leading to a decrease in circuit performance.

[0040] In addition, existing methods also involve adjusting the series resistance of FDSOI transistors by regulating the thickness of the spacer region (the region of the gate sidewall) or by adjusting the dielectric constant. The principle is that adjusting the spacer thickness changes the length of the silicon layer beneath the spacer, thereby adjusting the transport length of the FDSOI transistor outside the channel, and thus adjusting the series resistance. Alternatively, adjusting the dielectric constant of the spacer can change the gate edge field strength, thereby controlling the conductivity of the silicon layer beneath the spacer, and thus changing the series resistance. However, in the design process of different FDSOI transistor fabrication processes, the gate pitch of a single FDSOI transistor is fixed. Changing the spacer width means compressing the width of the source and drain regions, which increases the difficulty of carrier injection from the metal electrode into the semiconductor layer, resulting in increased contact resistance and reduced mobility and drive current. Changes in spacer width and dielectric constant also alter the parasitic capacitance of the FDSOI transistor, affecting its response frequency.

[0041] Based on this, embodiments of the present invention provide a method for adjusting the driving current, an adjusting circuit, a driving device, and an electronic device, which effectively solves the technical problems existing in the prior art. It can achieve the adjustment of the series resistance value of the short-channel FDSOI transistor without changing the structure, materials, and fabrication process, and ultimately achieve the purpose of adjusting the driving current.

[0042] To achieve the above objectives, the technical solutions provided by the embodiments of the present invention are as follows, in detail... Figures 1 to 9The technical solutions provided in the embodiments of the present invention will be described in detail. It should be noted that the driving current is the current generated when a driving voltage is applied to the short-channel FDSOI transistor, and the back bias voltage is the voltage applied to the substrate electrode of the short-channel FDSOI transistor.

[0043] Combination Figure 1 and Figure 2 As shown, Figure 1 The flowchart illustrates a method for adjusting the driving current according to an embodiment of the present invention. Figure 2 This is a schematic diagram of a driving device provided in an embodiment of the present invention. The driving current adjustment method provided in this embodiment is applied to the driving device, which includes a short-channel FDSOI transistor 100 and a driving power supply 200 electrically connected to the source and drain of the short-channel FDSOI transistor 100. A control structure (not shown) is connected to the gate of the short-channel FDSOI transistor 100. The driving current adjustment method includes:

[0044] S1, Generate adjustment signal.

[0045] S2. Generate the target back bias voltage according to the adjustment signal.

[0046] S3. Apply the target back bias voltage to the substrate electrode of the short-channel FDSOI transistor, and adjust the series resistance of the short-channel FDSOI transistor to the target resistance value so that the driving current is adjusted when the driving voltage output by the driving power supply is applied to the short-channel FDSOI transistor.

[0047] Combination Figure 2 As shown, the short-channel FDSOI transistor 100 provided in this embodiment of the invention has a length L of less than 70 nm. The specific channel length L can be less than 60 nm, 50 nm, 40 nm, 30 nm, 26 nm, 20 mm, etc., and this invention does not impose specific limitations on this. The short-channel FDSOI transistor 100 includes a substrate electrode (the substrate electrode is the semiconductor bottom layer), an intermediate dielectric buried layer (the intermediate dielectric buried layer can be called a buried oxide layer) located on the substrate electrode, a semiconductor top layer located on the intermediate dielectric buried layer (the semiconductor top layer includes a channel region, a source, and a drain), and a gate structure disposed on the channel region and a gate sidewall surrounding the gate structure (the gate structure includes a gate dielectric layer and a gate). This is the same as the structure in the prior art, so this invention will not elaborate further. Furthermore, the short-channel FDSOI transistor provided in this embodiment of the invention is not limited to... Figure 2 The structure shown can also be other types of short-channel FDSOI transistor structures in other embodiments of the present invention.

[0048] Understandably, by applying a target back-bias voltage to the substrate electrode of the short-channel FDSOI transistor, the resistance value of the series resistance of the short-channel FDSOI transistor can be adjusted, ultimately achieving the purpose of regulating the drive current when the drive voltage is applied to the short-channel FDSOI transistor. Therefore, the technical solution provided by the embodiments of the present invention can achieve the adjustment of the series resistance value of the FDSOI transistor without changing its structure, materials, and fabrication process, thereby achieving the purpose of driving current regulation.

[0049] Specifically, the short-channel FDSOI transistor is a four-terminal device (see reference for details). Figure 2 The structure of the short-channel FDSOI transistor 100 (the four terminals of the short-channel FDSOI transistor 100 are the substrate electrode, source, drain, and gate) shows that the inventors discovered that the electrical performance of the FDSOI can be adjusted by applying a back bias voltage to the substrate electrode. Specifically, in conjunction with... Figure 3 and Figure 4 As shown, Figure 3 An IV characteristic curve of a short-channel FDSOI transistor provided in an embodiment of the present invention. Figure 4 This is a graph illustrating the series resistance extracted using a TLM model, provided as an embodiment of the present invention. Taking a short-channel FDSOI transistor with a channel length of 26nm as an example, the structure of the short-channel FDSOI transistor is constructed using Sentaurus simulation software. Using an electrical simulator, different back bias voltages (such as...) are applied to the substrate electrode of the short-channel FDSOI transistor. Figure 3 The arrows indicate that the four IV curves, from bottom to top, represent the back bias voltage V. BG The IV curves (corresponding to -2V, -1V, 0V, and 1V) were used to obtain the IV characteristics of the short-channel FDSOI transistor under different back bias voltages. The series resistance of the short-channel FDSOI transistor was extracted using the TLM (Transmission Line Method) model, and the effect of back bias voltage on the series resistance of the short-channel FDSOI transistor was compared.

[0050] Continue as Figure 3 As shown, by simulating the specific IV curves of short-channel FDSOI transistors under different back bias voltages, it was found that the short-channel FDSOI transistor exhibits a significant change in performance when a back bias voltage V is applied. BG After applying a voltage in the range of -2V to 1V, the back bias voltage will affect the drive current generated by the short-channel FDSOI transistor (the drive current passes through...). Figure 3 The drain current (shown in the diagram) is adjusted by approximately 10%. And as... Figure 4As shown, after extracting the series resistance of the short-channel FDSOI transistor using the TLM model, it was found that in a short-channel FDSOI transistor structure with a BOX (the thickness of the intermediate dielectric buried layer) of 20 nm, when a back bias voltage V is applied to the substrate electrode... BG When the voltage range is from -2V to 1V, the series resistor R SD The size was reduced from 145 Ω·μm to 135 Ω·μm, and the series resistance R of the short-channel FDSOI transistor was reduced. SD The resistance decreased by approximately 6%.

[0051] Combination Figure 5 and Figure 6 As shown, Figure 5 This invention provides a graph showing the change in drive current when the series resistance of a short-channel FDSOI transistor is changed using a simulator, as part of an embodiment of the invention. Figure 6 This invention provides a graph illustrating the variation of series resistance and total resistance with driving voltage in a short-channel FDSOI transistor. The graph uses a short-channel FDSOI transistor with a channel length L of 26 nm as an example. Figure 5 The arrow points inward, and the curves from bottom to top represent series resistances of 145 Ω·μm, 141 Ω·μm, 138 Ω·μm, and 135 Ω·μm, respectively; Figure 6 The arrows point in the curves, and the curves from bottom to top represent the series resistance and total resistance of the short-channel FDSOI transistor. The series resistances of the short-channel FDSOI transistor were set to 145 Ω·μm, 141 Ω·μm, 138 Ω·μm, and 135 Ω·μm using a simulator, corresponding to back bias voltages of V. BG =-2V, V BG =-1V, V BG =0V, V BG When the back bias voltage is 1V, the series resistance of the short-channel FDSOI transistor is such that a change of approximately 6% in the series resistance directly leads to a change of approximately 5% in the drive current generated by the short-channel FDSOI transistor. In other words, in a short-channel FDSOI transistor with a channel length L of 26nm, 50% of the increase in drive current due to the back bias voltage is caused by the change in series resistance. Simulations show that in a short-channel FDSOI transistor with a channel length L of 26nm, at a drive voltage V... GTAt voltages greater than 0.65V, the series resistance in a short-channel FDSOI transistor accounts for approximately 65% ​​of the total resistance. This further verifies that the series resistance gradually becomes dominant in short-channel FDSOI transistors. Therefore, adjusting the drive current by applying a back bias voltage to regulate the series resistance is effective in short-channel FDSOI transistors. Consequently, in circuit applications, a back bias voltage can be used to reduce the series resistance of the short-channel FDSOI transistor to improve its performance. In applications such as differential circuits, increasing the series resistance can also reduce the drive current, thus meeting the performance matching requirements of the short-channel FDSOI transistor.

[0052] Based on the above-mentioned effect of back bias voltage applied to the substrate electrode on the short-channel FDSOI transistor, it can be understood that the principle of adjusting the series resistance of the short-channel FDSOI transistor by back bias voltage is as follows: First, it needs to be clarified that the total resistance of the short-channel FDSOI transistor can be simply divided into the sum of the series resistance and the channel resistance (i.e., the total resistance R). total =Series resistance R SD + Channel resistance R channel The back bias voltage primarily affects the silicon layer in the source and drain regions. The change in resistance in this region with the back bias voltage dominates the change in the series resistance of the entire short-channel FDSOI transistor with respect to the back bias voltage. Positive back bias voltage (for an N-type transistor, the positive back bias voltage is V). BG A voltage greater than 0V leads to the accumulation of charge carriers in the silicon layer of the source and drain regions, causing the center of mass of the charge carriers to shift downwards, resulting in a larger cross-sectional area of ​​the transistor channel and consequently a decrease in series resistance. Conversely, when a reverse back bias voltage is applied (for an N-type transistor, the reverse back bias voltage is V), the reverse back bias voltage decreases. BG When the voltage drops below 0V, the silicon layer carriers in the source and drain regions are depleted, and the carrier centroid shifts upward, resulting in a decrease in the conduction cross-sectional area of ​​the transistor. This leads to an increase in the series resistance of the transistor. Therefore, according to actual needs, a positive back bias voltage or a reverse back bias voltage is applied to the substrate electrode of the short-channel FDSOI transistor to adjust the series resistance of the short-channel FDSOI transistor to the target resistance value.

[0053] refer to Figure 7 The diagram shows a flowchart of another method for adjusting the drive current provided by an embodiment of the present invention. The generation of the adjustment signal provided by the embodiment of the present invention includes: S1, generating the adjustment signal by looking up a data table. The table lookup method facilitates the acquisition of relevant adjustment signals according to requirements, thereby improving the adjustment efficiency of the drive current.

[0054] In one embodiment of the invention, the data table provided by this embodiment includes one-to-one correspondence data between multiple back bias voltages and multiple series resistor values. This allows for direct lookup of the back bias voltage based on the required resistance value, thereby generating a corresponding adjustment signal and improving response and adjustment speed. Alternatively, the data table provided by this embodiment includes conversion relationship data between back bias voltage and series resistor values. Based on the required resistance value, the back bias voltage is calculated and analyzed to generate a corresponding adjustment signal, reducing data storage space requirements.

[0055] Furthermore, after applying the target back bias voltage to the substrate electrode, the drive current can be monitored. When there is a difference between the drive current and the target drive current, a compensation voltage is applied to the substrate electrode of the short-channel FDSOI transistor to adjust the drive current to the target drive current. This avoids the problem of inaccurate drive current generated by the short-channel FDSOI transistor due to environmental factors, and improves the regulation effect of the drive current.

[0056] Based on the same inventive concept, embodiments of the present invention also provide a driving current adjustment circuit. (See reference...) Figure 8 The diagram shown is a schematic representation of a drive current adjustment circuit according to an embodiment of the present invention. The drive current adjustment circuit is applied to a drive device, which includes a short-channel FDSOI transistor 100 and a drive power supply 200 electrically connected to the source and drain of the short-channel FDSOI transistor 100. The drive current adjustment circuit includes:

[0057] Processor 310 is configured to generate an adjustment signal. A voltage generation circuit 320 is configured to generate a target back bias voltage based on the adjustment signal, apply the target back bias voltage to the substrate electrode of the short-channel FDSOI transistor, and adjust the series resistance of the short-channel FDSOI transistor to a target resistance value so that the drive current is adjusted when the drive voltage output from the drive power supply is applied to the short-channel FDSOI transistor.

[0058] Understandably, by applying a target back-bias voltage to the substrate electrode of the short-channel FDSOI transistor, the resistance value of the series resistance of the short-channel FDSOI transistor can be adjusted, ultimately achieving the purpose of regulating the drive current when the drive voltage is applied to the short-channel FDSOI transistor. Therefore, the technical solution provided by the embodiments of the present invention can achieve the adjustment of the series resistance value of the FDSOI transistor without changing its structure, materials, and fabrication process, thereby achieving the purpose of driving current regulation.

[0059] In one embodiment of the present invention, the processor provided in this embodiment is used to generate an adjustment signal by looking up a data table. The table lookup method facilitates the acquisition of relevant adjustment signals according to requirements, improving the adjustment efficiency of the drive current. Optionally, the data table provided in this embodiment includes one-to-one correspondence data between multiple back bias voltages and multiple series resistor values. This allows the back bias voltage to be directly looked up based on the required resistance value to generate the corresponding adjustment signal, improving response and adjustment speed. Alternatively, the data table provided in this embodiment includes conversion relationship data between back bias voltage and series resistor values. This allows the back bias voltage to be calculated and analyzed based on the required resistance value before generating the corresponding adjustment signal, reducing data storage space.

[0060] Furthermore, the drive current adjustment circuit provided in this application embodiment may further include an auxiliary processor and a compensation circuit. The auxiliary processor monitors the drive current generated by the short-channel FDSOI transistor. When there is a difference between the drive current and the target drive current, it controls the compensation circuit to generate a compensation voltage. The compensation circuit applies the compensation voltage to the substrate electrode of the short-channel FDSOI transistor to adjust the drive current to the target drive current. This avoids the problem of inaccurate drive current generated by the short-channel FDSOI transistor due to environmental factors, thus improving the adjustment effect of the drive current. Optionally, the auxiliary processor may be the same device as the processor, and this invention does not impose specific limitations on this.

[0061] Based on the same inventive concept, embodiments of the present invention also provide a driving device. (See reference...) Figure 9 The diagram shown is a structural schematic of a driving device provided in an embodiment of the present invention. The driving device provided in this embodiment includes:

[0062] Short-channel FDSOI transistor 100.

[0063] A drive power supply 200 is electrically connected to the source and drain of the short-channel FDSOI transistor 100.

[0064] And, an adjustment circuit 300 electrically connected to the substrate electrode of the short-channel FDSOI transistor 100, wherein the adjustment circuit 300 is a drive current adjustment circuit provided in any of the above embodiments.

[0065] Based on the same inventive concept, embodiments of the present invention also provide an electronic device, which includes the driving device provided in any of the above embodiments.

[0066] This invention provides a method and circuit for adjusting drive current, a driving device, and an electronic device. The driving device includes a short-channel FDSOI transistor and a driving power supply electrically connected to the source and drain of the short-channel FDSOI transistor. The method for adjusting drive current includes: generating an adjustment signal; generating a target back bias voltage based on the adjustment signal; applying the target back bias voltage to the substrate electrode of the short-channel FDSOI transistor; and adjusting the series resistance of the short-channel FDSOI transistor to a target resistance value so that the driving current is adjusted when the driving voltage output by the driving power supply is applied to the short-channel FDSOI transistor.

[0067] As described above, by applying a target back-bias voltage to the substrate electrode of the short-channel FDSOI transistor, the resistance value of the series resistance of the short-channel FDSOI transistor is adjusted, ultimately achieving the purpose of regulating the drive current when the drive voltage is applied to the short-channel FDSOI transistor. Therefore, the technical solution provided by the embodiments of the present invention can achieve the adjustment of the series resistance value of the FDSOI transistor without changing its structure, materials, and fabrication process, thereby achieving the purpose of driving current regulation.

[0068] In the description of this invention, it should be understood that terms such as "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0069] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0070] In this invention, unless otherwise explicitly specified and limited, terms such as "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between components; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0071] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0072] In this invention, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0073] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A method for adjusting drive current, applied to a drive device, characterized in that, The driving device includes a short-channel FDSOI transistor and a driving power supply electrically connected to the source and drain of the short-channel FDSOI transistor, wherein the method for adjusting the driving current includes: Generate adjustment signals; The target back bias voltage is generated according to the adjustment signal; The target back bias voltage is applied to the substrate electrode of the short-channel FDSOI transistor, and the series resistance of the short-channel FDSOI transistor is adjusted to the target resistance value so that the drive current is adjusted when the drive voltage output by the drive power supply is applied to the short-channel FDSOI transistor.

2. The method for adjusting the driving current according to claim 1, characterized in that, The generated adjustment signal includes: The adjustment signal is generated by looking up the data table.

3. The method for adjusting the driving current according to claim 2, characterized in that, The data table includes one-to-one correspondence data between multiple back bias voltages and multiple series resistor values.

4. The method for adjusting the driving current according to claim 2, characterized in that, The data table includes conversion data between back bias voltage and series resistance values.

5. A driving current regulating circuit, applied to a driving device, characterized in that, The driving device includes a short-channel FDSOI transistor and a driving power supply electrically connected to the source and drain of the short-channel FDSOI transistor, wherein the driving current adjustment circuit includes: Processor, the processor being used to generate adjustment signals; A voltage generation circuit is provided, which generates a target back bias voltage according to the adjustment signal and applies the target back bias voltage to the substrate electrode of the short-channel FDSOI transistor. The series resistance of the short-channel FDSOI transistor is adjusted to a target resistance value so that the drive current is adjusted when the drive voltage output by the drive power supply is applied to the short-channel FDSOI transistor.

6. The driving current adjustment circuit according to claim 5, characterized in that, The processor is used to generate adjustment signals by looking up a data table.

7. The driving current adjustment circuit according to claim 6, characterized in that, The data table includes one-to-one correspondence data between multiple back bias voltages and multiple series resistor values.

8. The driving current adjustment circuit according to claim 6, characterized in that, The data table includes conversion data between back bias voltage and series resistance values.

9. A driving device, characterized in that, The driving device includes: Short-channel FDSOI transistor; The driving power supply is electrically connected to the source and drain of the short-channel FDSOI transistor. And, an adjustment circuit electrically connected to the substrate electrode of the short-channel FDSOI transistor, wherein the adjustment circuit is the driving current adjustment circuit according to any one of claims 5-8.

10. An electronic device, characterized in that, The electronic device includes the driving device as described in claim 9.

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