Push-pull buffer circuit with nonlinear current compensation
By designing a push-pull buffer circuit with nonlinear current compensation, the problem of linearity degradation under high-frequency signals was solved, the signal-to-noise ratio and linearity were improved, and the output signal quality of the push-pull buffer was enhanced.
Patent Information
- Application Number
- CN202511364934.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-23
- Publication Date
- 2026-01-23
AI Technical Summary
In the prior art, push-pull buffers suffer from linearity degradation under high-frequency signals, resulting in a deterioration in the linearity of the output signal. This is mainly due to the current imbalance caused by the asymmetrical bias of the drain-source voltages of NMOS and PMOS and the channel length modulation effect.
A push-pull buffer circuit with nonlinear current compensation is designed, including a main input buffer module, a nonlinear current compensation circuit module, a nonlinear current compensation capacitor module, and a common-mode feedback module. Through current compensation and capacitor compensation mechanisms, the current matching of MOSFETs is balanced, the output common-mode level is stabilized, and the linearity is improved.
It effectively compensates for the effects of current mismatch, improves the signal-to-noise ratio and linearity, enhances the output signal quality, and strengthens the linear performance of the overall sampling network.
Smart Images
Figure CN121396201A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the technical field of push-pull buffer, and particularly relates to a push-pull buffer circuit with nonlinear current compensation. BACKGROUND
[0002] With the evolution of radio frequency communication technology, the signal frequency range continues to expand to the high frequency band, which poses a severe challenge to the input stage design of an analog-to-digital converter (ADC). In order to meet the driving demand of high-frequency signals, modern ADCs generally use input buffers with a source follower structure, but this architecture has a significant linearity degradation problem in high-frequency scenarios. Specifically, when the input signal changes, the drain-source voltage of the upper half NMOS and the lower half PMOS of the push-pull buffer is asymmetrically biased. Due to the channel length modulation effect, the drain current of the MOS tube and the drain-source voltage present a nonlinear relationship, causing the current matching of the upper and lower parts to be unbalanced. At this time, the current change on the load capacitor will further amplify this mismatch, and the two mechanisms together cause the output signal linearity to deteriorate, limiting the linearity of the overall sampling network. SUMMARY
[0003] In order to solve the above problems existing in the prior art, the application provides a push-pull buffer circuit with nonlinear current compensation. The technical problem to be solved by the application is solved by the following technical scheme: The application provides a push-pull buffer circuit with nonlinear current compensation, comprising: a main input buffer module, configured to buffer and output an input differential signal, so as to isolate the input differential signal and a driven later-stage circuit and reduce the influence of the later-stage circuit on the input differential signal; a nonlinear current compensation circuit module, configured to realize the opening or closing of a compensation function according to a control signal, and to compensate the output node of the main input buffer module according to the received input differential signal when the current matching of the main input buffer module is unbalanced; a nonlinear current compensation capacitor module, configured to couple the change of the input differential signal to an internal node of the main input buffer module according to the received input differential signal, and to provide additional charging and discharging current for the output node of the main input buffer module; a common-mode feedback module, configured to generate a feedback signal according to the output differential signal of the main input buffer module and an ideal output common-mode voltage, and to stabilize the common-mode level of the output differential signal by using the feedback signal.
[0004] Compared with the prior art, the application has the beneficial effects that: The push-pull buffer circuit with nonlinear current compensation of the application, when the input differential signal changes, the nonlinear current compensation circuit module compensates the current to the output node of the main input buffer module, to compensate the current mismatch imbalance phenomenon in the upper and lower parts of the main input buffer module, to balance the gm value of the upper and lower MOS tubes, to reduce the signal-to-noise ratio and linearity deterioration caused by current mismatch, and the conduction and shutdown of the compensation path can be selected; and the input differential signal also charges the main input buffer module through the nonlinear current compensation capacitor module, to compensate the current change on the load capacitor, both of which can improve the nonlinearity of the push-pull buffer and improve the linearity of the output signal and the overall sampling network.
[0005] The above description is only a summary of the technical scheme of the application, in order to enable the technical means of the application to be more clearly understood, and to be implemented according to the content of the specification, and in order to enable the above and other purposes, features and advantages of the application to be more obvious and easy to understand, the following preferred embodiments are described in detail below, and the accompanying drawings are described as follows. BRIEF DESCRIPTION OF DRAWINGS
[0006] Figure 1 is a structural block diagram of a push-pull buffer circuit with nonlinear current compensation provided by an embodiment of the application; Figure 2 is a unit structural block diagram of a push-pull buffer circuit with nonlinear current compensation provided by an embodiment of the application; Figure 3 is a circuit diagram of a push-pull buffer circuit with nonlinear current compensation provided by an embodiment of the application; Figure 4 is an output signal spectrum diagram of a push-pull buffer circuit without nonlinear current compensation provided by an embodiment of the application; Figure 5 is an output signal spectrum diagram of a push-pull buffer circuit with nonlinear current compensation provided by an embodiment of the application. DETAILED DESCRIPTION
[0007] In order to further illustrate the technical means and effects adopted by the application to achieve the predetermined purpose, the following describes in detail a push-pull buffer circuit with nonlinear current compensation according to the application, in combination with the drawings and specific embodiments.
[0008] The foregoing and other technical contents, features and effects of the application can be clearly presented in the following detailed description of the specific embodiments in combination with the drawings. Through the description of the specific embodiments, the technical means and effects adopted by the application to achieve the predetermined purpose can be more deeply and specifically understood, however, the attached drawings are provided for reference and explanation only, and are not used to limit the technical scheme of the application.
[0009] The embodiment of the present application provides a push-pull buffer circuit with nonlinear current compensation, please refer to Figure 1 , Figure 1 The embodiment of the present application provides a push-pull buffer circuit with nonlinear current compensation, please refer to Figure 1 The embodiment of the present application provides a push-pull buffer circuit with nonlinear current compensation, please refer to
[0010] The main input buffer module is used for buffering and outputting the input differential signal, so as to isolate the input differential signal and the driven later-stage circuit and reduce the influence of the later-stage circuit on the input differential signal; the nonlinear current compensation circuit module realizes the opening or closing of the compensation function according to the control signal, and performs current compensation on the output node of the main input buffer module according to the received input differential signal when the current matching of the main input buffer module is unbalanced; the nonlinear current compensation capacitor module couples the change of the input differential signal to the internal node of the main input buffer module according to the received input differential signal, and provides additional charging and discharging current for the output node of the main input buffer module; and the common-mode feedback module is used for generating a feedback signal according to the output differential signal of the main input buffer module and the ideal output common-mode voltage, and stabilizing the common-mode level of the output differential signal by using the feedback signal.
[0011] The embodiment of the present application provides a push-pull buffer circuit with nonlinear current compensation, please refer to Figure 2 , Figure 2 The embodiment of the present application provides a push-pull buffer circuit with nonlinear current compensation, please refer to Figure 2 The main input buffer module includes a first main input buffer unit 101 and a second main input buffer unit 102; the nonlinear current compensation circuit module includes a first nonlinear current compensation circuit unit 103 and a second nonlinear current compensation circuit unit 104; and the nonlinear current compensation capacitor module includes a first nonlinear current compensation capacitor unit 105 and a second nonlinear current compensation capacitor unit 106.
[0012] The output end of the first main input buffer unit 101 and the second main input buffer unit 102 are connected with the input end of the common mode feedback module, the feedback signal input end is connected with the output end of the common mode feedback module, and the feedback signal is received; the input end of the first main input buffer unit 101 inputs the differential signal Vin_n, and the output end outputs the differential signal Voutn; the input end of the second main input buffer unit 102 inputs the differential signal Vin_p, and the output end outputs the differential signal Voutp; the input end of the first nonlinear current compensation circuit unit 103 inputs the differential signal Vin_p, and the output end is connected with the output end of the first main input buffer unit 101; the input end of the second nonlinear current compensation circuit unit 104 inputs the differential signal Vin_n, and the output end is connected with the output end of the second main input buffer unit 102; the input end of the first nonlinear current compensation capacitor unit 105 inputs the differential signal Vin_n, and the output end is connected with the internal node of the first main input buffer unit 101; the input end of the second nonlinear current compensation capacitor unit 106 inputs the differential signal Vin_p, and the output end is connected with the internal node of the second main input buffer unit 102.
[0013] The push-pull buffer circuit with nonlinear current compensation in the embodiment of the application can compensate the current to the output node of the main input buffer module when the input differential signal changes, so as to compensate the current mismatch imbalance in the main input buffer module, balance the gm values of the upper and lower MOS tubes, alleviate the signal-to-noise ratio and linearity deterioration caused by current mismatch, and select the on and off of the compensation path; and the input differential signal also charges the main input buffer module through the nonlinear current compensation capacitor module to compensate the current change on the load capacitor, so that the two methods can improve the nonlinearity of the push-pull buffer and improve the linearity of the output signal and the overall sampling network.
[0014] Further combining Figure 3 The specific circuit structure of the push-pull buffer circuit with nonlinear current compensation in the embodiment of the application is described. As shown in the figure, Figure 3 In the embodiment, the first main input buffer unit 101 includes: a PMOS tube PM1, a PMOS tube PM2, an NMOS tube NM1, an NMOS tube NM2, a capacitor C1, a capacitor C2, a capacitor C4, a capacitor C5, a resistor R1, a resistor R2, a resistor R3 and a resistor R4.
[0015] The gate of the PMOS tube PM1 is connected with the first end of the resistor R4 and the upper plate of the capacitor C5, the drain is connected with the GND end, and the source is connected with the drain of the PMOS tube PM2 and the first nonlinear current compensation capacitor unit 105; the gate of the PMOS tube PM2 is connected with the first end of the resistor R3 and the upper plate of the capacitor C4, and the source is connected with the source of the NMOS tube NM1.
[0016] The gate of the NMOS tube NM1 is connected to the first end of the resistor R2 and the upper plate of the capacitor C1, respectively, the source is the output end of the first main input buffer unit 101, and the drain is connected to the source of the NMOS tube NM2; the gate of the NMOS tube NM2 is connected to the first end of the resistor R1 and the upper plate of the capacitor C2, respectively, the source is connected to the first nonlinear current compensation capacitor unit 105, and the drain is connected to the power supply end VDD1.
[0017] The lower plates of the capacitors C1, C2, C4 and C5 input the differential signal Vin_n; the second end of the resistor R1 is connected to the bias end Vbias_N1, the second end of the resistor R2 is the feedback signal input end, the second end of the resistor R3 is connected to the bias end Vbias_P1, and the second end of the resistor R4 is connected to the bias end Vbias_P2.
[0018] In the embodiment, the second main input buffer unit 102 includes: a PMOS tube PM3, a PMOS tube PM4, an NMOS tube NM3, an NMOS tube NM4, a capacitor C7, a capacitor C8, a capacitor C10, a capacitor C11, a resistor R9, a resistor R10, a resistor R11 and a resistor R12.
[0019] The gate of the PMOS tube PM3 is connected to the first end of the resistor R12 and the upper plate of the capacitor C11, respectively, the drain is connected to the GND end, and the source is connected to the drain of the PMOS tube PM4 and the second nonlinear current compensation capacitor unit 106; the gate of the PMOS tube PM4 is connected to the first end of the resistor R11 and the upper plate of the capacitor C10, respectively, and the source is connected to the source of the NMOS tube NM3.
[0020] The gate of the NMOS tube NM3 is connected to the first end of the resistor R10 and the upper plate of the capacitor C7, respectively, the source is the output end of the second main input buffer unit 102, and the drain is connected to the source of the NMOS tube NM4; the gate of the NMOS tube NM4 is connected to the first end of the resistor R9 and the upper plate of the capacitor C8, respectively, the source is connected to the second nonlinear current compensation capacitor unit 106, and the drain is connected to the power supply end VDD1.
[0021] The lower plates of the capacitors C7, C8, C10 and C11 input the differential signal Vin_p; the second end of the resistor R9 is connected to the bias end Vbias_N1, the second end of the resistor R10 is the feedback signal input end, the second end of the resistor R11 is connected to the bias end Vbias_P1, and the second end of the resistor R12 is connected to the bias end Vbias_P2.
[0022] In the embodiment, the NMOS tube NM1, the NMOS tube NM3, the PMOS tube PM2 and the PMOS tube PM4 are push-pull source follower tubes, which can provide low output impedance and are easy to drive large loads, and the advantage is that the gm can be doubled to improve current efficiency; the NMOS tube NM2, the NMOS tube NM4, the PMOS tube PM1 and the PMOS tube PM3 are common-source common-gate source follower tubes, which can output the input signal to the source end through the capacitor, so that the output source follower Vds remains unchanged, the current change caused by the channel length modulation effect is reduced, and the linearity is improved. In the embodiment, the NMOS tube is a deep N-well transistor, and the substrate and the source end are connected, so as to reduce the influence of the substrate modulation effect.
[0023] In the embodiment, the first nonlinear current compensation circuit unit 103 comprises an NMOS tube NM5, a PMOS tube PM5, an NMOS tube NM7, a PMOS tube PM7, a capacitor C13, a capacitor C14, a resistor R5 and a resistor R6.
[0024] The gate of the NMOS tube NM5 is connected to the first end of the resistor R5 and the upper plate of the capacitor C13, the drain is connected to the drain of the PMOS tube PM5 and the output end of the first main input buffer unit 101, and the source is connected to the GND end; the gate of the PMOS tube PM5 is connected to the first end of the resistor R6 and the upper plate of the capacitor C14, and the source is connected to the power supply end VDD2.
[0025] The gate of the NMOS tube NM7 is input as a first control signal end to control the signal NCC_EN, the drain is connected to the drain of the PMOS tube PM7, and the source is connected to the lower plate of the capacitor C13, the lower plate of the capacitor C14 and the source of the PMOS tube PM7; the gate of the PMOS tube PM7 is input as a second control signal end to control the signal NCC_EN_B, and the drain is input as an input end of the first nonlinear current compensation circuit unit 103. The second end of the resistor R5 is connected to the bias end Vbias_N2, and the second end of the resistor R6 is connected to the bias end Vbias_P3.
[0026] In the embodiment, the second nonlinear current compensation circuit unit 104 comprises an NMOS tube NM6, a PMOS tube PM6, an NMOS tube NM8, a PMOS tube PM8, a capacitor C15, a capacitor C16, a resistor R7 and a resistor R8.
[0027] The gate of the NMOS tube NM6 is connected to the first end of the resistor R8 and the upper plate of the capacitor C15, the drain is connected to the drain of the PMOS tube PM6 and the output end of the second main input buffer unit 102, and the source is connected to the GND end; the gate of the PMOS tube PM6 is connected to the first end of the resistor R7 and the upper plate of the capacitor C16, and the source is connected to the power supply end VDD2.
[0028] The gate of the NMOS tube NM8 is inputted with the control signal NCC_EN as the first control signal end, the drain is connected with the drain of the PMOS tube PM8, and the source is connected with the lower plate of the capacitor C15, the lower plate of the capacitor C16 and the source of the PMOS tube PM8 respectively; the gate of the PMOS tube PM8 is inputted with the control signal NCC_EN_B as the second control signal end, and the drain is inputted as the input end of the second nonlinear current compensation circuit unit 104; the second end of the resistor R8 is connected with the bias end Vbias_N2, and the second end of the resistor R7 is connected with the bias end Vbias_P3.
[0029] It should be noted that the input signals of the first main input buffer unit 101 and the first nonlinear current compensation circuit unit 103 are reverse differential signals, and the input signals of the second main input buffer unit 102 and the second nonlinear current compensation circuit unit 104 are also reverse differential signals. Taking the first main input buffer unit 101 and the first nonlinear current compensation circuit unit 103 as an example for detailed explanation: when the first main input buffer unit 101 inputs a sinusoidal signal, the Vds of the source follower of the upper and lower halves of the buffer will not match with the change of the input signal. When the input signal is large, the Vds of the source follower of the upper half is small, and the current generated is correspondingly small, while the Vds of the source follower of the lower half is large, and the current generated is correspondingly large, resulting in a mismatch of the currents of the upper and lower halves, which deteriorates the linearity of the output signal. The input signal of the first nonlinear current compensation circuit unit 103 is reverse to that of the first main input buffer unit 101. When the input signal of the first main input buffer unit 101 is large, the input signal of the first nonlinear current compensation circuit unit 103 is small, which will turn on the PMOS tube PM5, and a current will flow from the power supply end VDD2 to the output end of the first main input buffer unit 101, optimizing the phenomenon of small current of the upper half of the first main input buffer unit 101. At this time, the currents of the upper and lower halves of the output end of the first main input buffer unit 101 are well matched, and the linearity of the output signal is optimized. In addition, the opening and closing of the compensation path can be controlled by the PMOS tube PM7 and the NMOS tube NM7 and their gate end control signals NCC_EN_B and NCC_EN to adapt to different situations, so that the linearity of the output signal of the first main input buffer unit 101 reaches the best, wherein the control signals NCC_EN_B and NCC_EN are reverse to each other. The working principles of the second main input buffer unit 102 and the second nonlinear current compensation circuit unit 104 are similar, which will not be repeated here.
[0030] In the embodiment, the first nonlinear current compensation capacitor unit 105 comprises: a capacitor C3 and a capacitor C6; wherein the lower plates of the capacitor C3 and the capacitor C6 are both input with the differential signal Vin_n; the upper plate of the capacitor C3 is connected with the source of the NMOS tube NM2; and the upper plate of the capacitor C6 is connected with the source of the PMOS tube PM1.
[0031] In the embodiment, the second nonlinear current compensation capacitor unit 106 comprises: a capacitor C9 and a capacitor C12; wherein the lower plates of the capacitor C9 and the capacitor C12 are both input with the differential signal Vin_p; the upper plate of the capacitor C9 is connected with the source of the NMOS tube NM4; and the upper plate of the capacitor C12 is connected with the source of the PMOS tube PM3.
[0032] In the embodiment, when the input differential signal changes, due to the existence of the load capacitor, the output node of the main input buffer module will have a leakage phenomenon, and a nonlinear factor will also be introduced, which will worsen the linearity of the output differential signal, therefore, the capacitor C3, the capacitor C6, the capacitor C9 and the capacitor C12 are introduced, the changing input differential signal will charge the main input buffer path through these capacitors, which compensates the leakage phenomenon of the output node of the main input buffer module, and improves the linearity of the output differential signal.
[0033] In the embodiment, the common-mode feedback module comprises: a resistor R13, a resistor R14 and an error amplifier EA; wherein the first end of the resistor R13 is connected with the first end of the resistor R14 and the negative input end of the error amplifier EA respectively; the second end of the resistor R13 is connected with the output end of the first main input buffer unit 101; the second end of the resistor R14 is connected with the output end of the second main input buffer unit 102; the positive input end of the error amplifier EA is input with the ideal output common-mode voltage; and the output end of the error amplifier EA outputs the feedback signal.
[0034] In the embodiment, the common-mode feedback module collects the output voltage common-mode value of the main input buffer module through the resistor, and inputs the value into the error amplifier EA together with the ideal output common-mode voltage, and then feeds back the output of the error amplifier EA to the gate end of the NMOS tube NM1 and the NMOS tube NM3 of the main input buffer module, so that the output common-mode of the main input buffer module is kept at a stable value under different process corners and temperatures.
[0035] Please refer to Figure 4 and Figure 5 , Figure 4 is the output signal spectrum diagram of the push-pull buffer circuit without nonlinear current compensation provided by the embodiment of the application; Figure 5 is the output signal spectrum diagram of the push-pull buffer circuit with nonlinear current compensation provided by the embodiment of the application. It can be seen through comparison that the linearity of the output signal is significantly improved and the SFDR is significantly improved through nonlinear current compensation.
[0036] It should be noted that, as used in this document, the terms "first," "second," etc. are used only to distinguish one entity or action from another, and do not necessarily require or imply any actual relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element. The terms "connected" or "coupled" or any other variant thereof are intended to cover a connection between or among two or more entities or actions, whether mechanical, electrical, or electromechanical. The terms "connected" or "coupled" are not restricted to direct or physical connections or couplings. The terms "upper," "lower," "left," "right," and the like are used for ease of description to orient a person viewing the figures of the drawings, and are not intended to orient the device or element described with respect thereto, and are not intended to limit the device or element to a particular orientation, configuration, or operation.
[0037] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific feature or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. The illustrative expressions of the above terms in the present specification do not necessarily refer to the same embodiment or example. Also, the specific features or characteristics described can be combined in any one or more embodiments or examples in an appropriate manner. In addition, a person skilled in the art can combine and integrate different embodiments or examples described in the present specification.
[0038] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and cannot be deemed to limit the specific implementation of the present invention to these descriptions. For those of ordinary skill in the art to which the present invention belongs, without departing from the concept of the present invention, a number of simple deductions or replacements can also be made, which should be considered to fall within the protection scope of the present invention.
Claims
1. A push-pull buffer circuit with nonlinear current compensation, characterized by The application relates to a differential input buffer circuit, which comprises the following modules: a main input buffer module for buffering and outputting an input differential signal to isolate the input differential signal and a driven subsequent circuit and reduce the influence of the subsequent circuit on the input differential signal; a nonlinear current compensation circuit module for realizing the opening or closing of a compensation function according to a control signal and compensating the output node of the main input buffer module with current according to the received input differential signal when the current matching of the main input buffer module is unbalanced; a nonlinear current compensation capacitor module for coupling the change of the input differential signal to the internal node of the main input buffer module according to the received input differential signal and providing additional charging and discharging current for the output node of the main input buffer module; a common-mode feedback module for generating a feedback signal according to the output differential signal of the main input buffer module and an ideal output common-mode voltage and stabilizing the common-mode level of the output differential signal by using the feedback signal.
2. The push-pull buffer circuit with non-linear current compensation according to claim 1, characterized in that, The main input buffer module comprises a first main input buffer unit (101) and a second main input buffer unit (102); the nonlinear current compensation circuit module comprises a first nonlinear current compensation circuit unit (103) and a second nonlinear current compensation circuit unit (104); the nonlinear current compensation capacitor module comprises a first nonlinear current compensation capacitor unit (105) and a second nonlinear current compensation capacitor unit (106); wherein, the output ends of the first main input buffer unit (101) and the second main input buffer unit (102) are connected to the input ends of the common-mode feedback module, the feedback signal input ends are connected to the output ends of the common-mode feedback module, and the feedback signal is received; the input end of the first main input buffer unit (101) inputs a differential signal Vin_n, and the output end outputs a differential signal Voutn; the input end of the second main input buffer unit (102) inputs a differential signal Vin_p, and the output end outputs a differential signal Voutp; the input end of the first nonlinear current compensation circuit unit (103) inputs the differential signal Vin_p, and the output end is connected to the output end of the first main input buffer unit (101); the input end of the second nonlinear current compensation circuit unit (104) inputs the differential signal Vin_n, and the output end is connected to the output end of the second main input buffer unit (102); the input end of the first nonlinear current compensation capacitor unit (105) inputs the differential signal Vin_n, and the output end is connected to the internal node of the first main input buffer unit (101); the input end of the second nonlinear current compensation capacitor unit (106) inputs the differential signal Vin_p, and the output end is connected to the internal node of the second main input buffer unit (102).
3. Push-pull buffer circuit with non-linear current compensation according to claim 2, characterized in that The first main input buffer unit (101) comprises: a PMOS tube PM1, a PMOS tube PM2, an NMOS tube NM1, an NMOS tube NM2, a capacitor C1, a capacitor C2, a capacitor C4, a capacitor C5, a resistor R1, a resistor R2, a resistor R3 and a resistor R4; wherein, the gate of the PMOS tube PM1 is connected to the first end of the resistor R4 and the upper plate of the capacitor C5 respectively, the drain is connected to the GND terminal, and the source is connected to the drain of the PMOS tube PM2 and the first nonlinear current compensation capacitor unit (105) respectively; the gate of the PMOS tube PM2 is connected to the first end of the resistor R3 and the upper plate of the capacitor C4 respectively, and the source is connected to the source of the NMOS tube NM1; the gate of the NMOS tube NM1 is connected to the first end of the resistor R2 and the upper plate of the capacitor C1 respectively, the source is used as the output terminal of the first main input buffer unit (101), and the drain is connected to the source of the NMOS tube NM2; the gate of the NMOS tube NM2 is connected to the first end of the resistor R1 and the upper plate of the capacitor C2 respectively, the source is connected to the first nonlinear current compensation capacitor unit (105), and the drain is connected to the power supply terminal VDD1; the lower plates of the capacitor C1, the capacitor C2, the capacitor C4 and the capacitor C5 are all input terminals of the differential signal Vin_n; the second end of the resistor R1 is connected to the bias terminal Vbias_N1, the second end of the resistor R2 is used as the feedback signal input terminal, the second end of the resistor R3 is connected to the bias terminal Vbias_P1, and the second end of the resistor R4 is connected to the bias terminal Vbias_P2.
4. The push-pull buffer circuit with non-linear current compensation of claim 2, wherein, The second main input buffer unit (102) comprises: a PMOS tube PM3, a PMOS tube PM4, an NMOS tube NM3, an NMOS tube NM4, a capacitor C7, a capacitor C8, a capacitor C10, a capacitor C11, a resistor R9, a resistor R10, a resistor R11 and a resistor R12; wherein, the gate of the PMOS tube PM3 is connected to the first end of the resistor R12 and the upper plate of the capacitor C11 respectively, the drain is connected to the GND terminal, and the source is connected to the drain of the PMOS tube PM4 and the second nonlinear current compensation capacitor unit (106) respectively; the gate of the PMOS tube PM4 is connected to the first end of the resistor R11 and the upper plate of the capacitor C10 respectively, and the source is connected to the source of the NMOS tube NM3; the gate of the NMOS tube NM3 is connected to the first end of the resistor R10 and the upper plate of the capacitor C7 respectively, the source is used as the output terminal of the second main input buffer unit (102), and the drain is connected to the source of the NMOS tube NM4; the gate of the NMOS tube NM4 is connected to the first end of the resistor R9 and the upper plate of the capacitor C8 respectively, the source is connected to the second nonlinear current compensation capacitor unit (106), and the drain is connected to the power supply terminal VDD1; The lower plates of the capacitors C7, C8, C10 and C11 all input the differential signal Vin_p; The second end of the resistor R9 is connected to the bias end Vbias_N1, the second end of the resistor R10 is used as the feedback signal input end, the second end of the resistor R11 is connected to the bias end Vbias_P1, and the second end of the resistor R12 is connected to the bias end Vbias_P2.
5. The push-pull buffer circuit with non-linear current compensation of claim 2, wherein, The first nonlinear current compensation circuit unit (103) comprises an NMOS tube NM5, a PMOS tube PM5, an NMOS tube NM7, a PMOS tube PM7, a capacitor C13, a capacitor C14, a resistor R5 and a resistor R6; wherein, The gates of the NMOS tube NM5 are respectively connected to the first end of the resistor R5 and the upper plate of the capacitor C13, the drains are respectively connected to the drain of the PMOS tube PM5 and the output end of the first main input buffer unit (101), and the sources are connected to the GND end; The gates of the PMOS tube PM5 are respectively connected to the first end of the resistor R6 and the upper plate of the capacitor C14, and the sources are connected to the power supply end VDD2; The gate of the NMOS tube NM7 is used as the first control signal end to input the control signal NCC_EN, the drain is connected to the drain of the PMOS tube PM7, and the source is respectively connected to the lower plate of the capacitor C13, the lower plate of the capacitor C14 and the source of the PMOS tube PM7; The gate of the PMOS tube PM7 is used as the second control signal end to input the control signal NCC_EN_B, and the drain is used as the input end of the first nonlinear current compensation circuit unit (103); The second end of the resistor R5 is connected to the bias end Vbias_N2, and the second end of the resistor R6 is connected to the bias end Vbias_P3.
6. The push-pull buffer circuit with non-linear current compensation of claim 2, wherein, The second nonlinear current compensation circuit unit (104) comprises an NMOS tube NM6, a PMOS tube PM6, an NMOS tube NM8, a PMOS tube PM8, a capacitor C15, a capacitor C16, a resistor R7 and a resistor R8; wherein, The gates of the NMOS tube NM6 are respectively connected to the first end of the resistor R8 and the upper plate of the capacitor C15, the drains are respectively connected to the drain of the PMOS tube PM6 and the output end of the second main input buffer unit (102), and the sources are connected to the GND end; The gates of the PMOS tube PM6 are respectively connected to the first end of the resistor R7 and the upper plate of the capacitor C16, and the sources are connected to the power supply end VDD2; The gate of the NMOS tube NM8 is used as the first control signal end to input the control signal NCC_EN, the drain is connected to the drain of the PMOS tube PM8, and the source is respectively connected to the lower plate of the capacitor C15, the lower plate of the capacitor C16 and the source of the PMOS tube PM8; The gate of the PMOS tube PM8 is used as the second control signal end to input the control signal NCC_EN_B, and the drain is used as the input end of the second nonlinear current compensation circuit unit (104); The second end of the resistor R7 is connected to the bias end Vbias_N3, and the second end of the resistor R8 is connected to the bias end Vbias_P4. The second end of the resistor R8 is connected to the bias end Vbias_N2, and the second end of the resistor R7 is connected to the bias end Vbias_P3.
7. The push-pull buffer circuit with non-linear current compensation of claim 3, wherein, The first nonlinear current compensation capacitor unit (105) comprises a capacitor C3 and a capacitor C6; wherein the lower plates of the capacitor C3 and the capacitor C6 are both inputted with the differential signal Vin_n; the upper plate of the capacitor C3 is connected to the source of the NMOS tube NM2; and the upper plate of the capacitor C6 is connected to the source of the PMOS tube PM1.
8. The push-pull buffer circuit with non-linear current compensation of claim 4, wherein, The second nonlinear current compensation capacitor unit (106) comprises a capacitor C9 and a capacitor C12; wherein the lower plates of the capacitor C9 and the capacitor C12 are both inputted with the differential signal Vin_p; the upper plate of the capacitor C9 is connected to the source of the NMOS tube NM4; and the upper plate of the capacitor C12 is connected to the source of the PMOS tube PM3.
9. The push-pull buffer circuit with non-linear current compensation of claim 2, wherein, The common-mode feedback module comprises a resistor R13, a resistor R14 and an error amplifier EA; wherein, the first end of the resistor R13 is connected to the first end of the resistor R14 and the negative input end of the error amplifier EA respectively; the second end of the resistor R13 is connected to the output end of the first main input buffer unit (101); and the second end of the resistor R14 is connected to the output end of the second main input buffer unit (102); the positive input end of the error amplifier EA is inputted with the ideal output common-mode voltage; and the output end of the error amplifier EA outputs the feedback signal.