A semiconductor structure and method of operation thereof

Abstract

Embodiments of the present disclosure provide a semiconductor structure and an operating method thereof. The semiconductor structure includes: a first transistor and a second transistor located on a substrate and having a shared channel region, the first transistor including at least a first gate layer and a first storage layer, and the second transistor including at least a second gate layer and a second storage layer; a first extension and a second extension located at two ends of the shared channel region in a first direction, the first extension connected to an end of the shared channel region adjacent to a side of the second gate layer, and the second extension connected to an end of the shared channel region adjacent to a side of the first gate layer; the shared channel region and the first extension have a same doping type, and the doping type is opposite to that of the second extension; data writing of the first storage layer is implemented based on a voltage difference between the first gate layer and a reference voltage being within a first preset range, and data writing of the second storage layer is implemented based on a voltage difference between the second gate layer and the reference voltage being within a second preset range.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and its operation method. Background Technology

[0002] With technological advancements, semiconductor devices are continuously evolving towards miniaturization and higher integration. Memory, as an important semiconductor device, is used to store data or programs for data processing in electronic devices. However, while the size and linewidth of memory continue to decrease, many problems still exist during operation that require improvement. Summary of the Invention

[0003] This disclosure provides a semiconductor structure, the semiconductor structure comprising:

[0004] Substrate;

[0005] A first transistor and a second transistor are disposed adjacently, the first transistor and the second transistor are located on the substrate and have a common channel region, the common channel region extending along a first direction, the first direction being parallel to the surface of the substrate, the first transistor including at least a first gate layer and a first storage layer, and the second transistor including at least a second gate layer and a second storage layer;

[0006] The first extension and the second extension are respectively located at both ends of the common channel region in the first direction. The first extension is connected to the end of the common channel region adjacent to the second gate layer, and the second extension is connected to the end of the common channel region adjacent to the first gate layer.

[0007] The common channel region and the first extension have the same doping type, and the doping type is opposite to that of the second extension. The voltage difference between the second extension and the first extension during operation is recorded as the reference voltage. The data writing of the first storage layer is implemented based on the voltage difference between the first gate layer and the reference voltage within a first preset range, and the data writing of the second storage layer is implemented based on the voltage difference between the second gate layer and the reference voltage within a second preset range.

[0008] In some embodiments, the semiconductor structure further includes:

[0009] A third transistor is located between the first transistor and the second transistor, and the third transistor shares a common channel region with the first transistor and the second transistor; the third transistor includes at least a third gate layer and a third memory layer;

[0010] The data writing process of the third storage layer is performed simultaneously with the data writing process of the second storage layer, and the data writing of the third storage layer is achieved based on the voltage difference between the third gate layer and the reference voltage within a third preset range.

[0011] In some embodiments, the doping type of the common channel region and the first extension is P-type, and the doping type of the second extension is N-type.

[0012] In some embodiments, the first storage layer, the second storage layer, and the third storage layer each independently include one of the following structures:

[0013] The first stacked structure includes an oxide layer, a nitride layer, and an oxide layer stacked from bottom to top in a direction from near the common channel region to away from the common channel region;

[0014] The second stacked structure includes oxide layers, nitride layers, oxide layers, nitride layers and oxide layers stacked from bottom to top in a direction from near the common channel region to away from the common channel region;

[0015] as well as,

[0016] Floating gate.

[0017] In some embodiments, when the materials of the first storage layer, the second storage layer, and the third storage layer include the first stacked structure, the thickness of the oxide layer disposed adjacent to the common channel region is between 2 nm and 3 nm, the thickness of the oxide layer disposed away from the common channel region is between 4 nm and 5 nm, and the thickness of the nitride layer is between 4 nm and 6 nm.

[0018] In some embodiments, the semiconductor structure further includes:

[0019] The first word line is connected to the first gate layer and extends along the second direction;

[0020] The second word line is connected to the second gate layer and extends along the second direction;

[0021] The third word line is connected to the third gate layer and extends along the second direction and the third direction;

[0022] Wherein, the second direction is perpendicular to the surface of the substrate, and the third direction is parallel to the surface of the substrate and intersects the first direction.

[0023] In some embodiments, along the fourth direction, the semiconductor structure includes a multilayer memory cell, the memory cell including at least the first transistor and the second transistor, and the semiconductor structure further includes:

[0024] A source line and multiple bit lines, the source line extending along a second direction and a third direction and connected to the second extension, the multiple bit lines extending along the second direction and each bit line connected to the first extension located on the same layer;

[0025] Wherein, the second direction is perpendicular to the surface of the substrate, the third direction is parallel to the surface of the substrate and intersects the first direction, and the fourth direction is parallel to the second direction.

[0026] In some embodiments, the doping concentration of the common channel region ranges from 1 × 10⁻⁶. 16 atoms / cm³ ~1×10 18 The doping concentrations of the first and second extensions are between atoms / cm³ and within the range of 1×10⁻⁶. 19 atoms / cm³ ~1×10 20 Between atoms / cm³.

[0027] This disclosure also provides a method for operating a semiconductor structure, the semiconductor structure comprising:

[0028] A first transistor and a second transistor are disposed adjacent to each other on a substrate, the first transistor and the second transistor having a common channel region, the first transistor including at least a first gate layer and a first storage layer, the second transistor including at least a second gate layer and a second storage layer; a first extension and a second extension, the first extension being connected to the end of the common channel region adjacent to the second gate layer, and the second extension being connected to the end of the common channel region adjacent to the first gate layer.

[0029] The operation method includes performing a write operation, which includes: applying a first write voltage to the first gate layer, and using the voltage difference between the second extension and the first extension as a reference voltage; and writing data to the first memory layer based on the voltage difference between the first write voltage and the reference voltage within a first preset range; and...

[0030] A second write voltage is applied to the second gate layer, and the voltage difference between the second extension and the first extension is the reference voltage. Data is written to the second memory layer based on the voltage difference between the second write voltage and the reference voltage within a second preset range.

[0031] The common channel region has the same doping type as the first extension and the opposite doping type to the second extension.

[0032] In some embodiments, the semiconductor structure further includes a third transistor, the third transistor including at least a third gate layer and a third memory layer, the third transistor being located between the first transistor and the second transistor, and the third transistor having the common channel region with the first transistor and the second transistor; the write operation further includes:

[0033] While applying the second write voltage to the second gate layer, a third write voltage is applied to the third gate layer, and data is written to the third memory layer based on the voltage difference between the third write voltage and the reference voltage within a third preset range;

[0034] The third write voltage has the same voltage direction as the second write voltage.

[0035] In some embodiments, the operation method further includes performing a read operation, the read operation including: applying a first read voltage to the first extension to read data stored in the first storage layer and the second storage layer;

[0036] or,

[0037] A first read voltage is applied to the first extension, a second read voltage is applied to the first gate layer, and a third read voltage is applied to the second gate layer to read data stored in the first memory layer and the second memory layer.

[0038] In some embodiments, the operation method further includes performing a read operation, the read operation comprising:

[0039] A first read voltage is applied to the first extension to read the data stored in the first storage layer, the second storage layer, and the third storage layer;

[0040] or,

[0041] A first read voltage is applied to the first extension, and a second read voltage, a third read voltage, and a fourth read voltage are applied to the first gate layer, the second gate layer, and the third gate layer, respectively, to read data stored in the first memory layer, the second memory layer, and the third memory layer.

[0042] In some embodiments, the absolute values ​​of the first preset range, the second preset range, and the third preset range are each independently 10V~12V.

[0043] In some embodiments, the operation method further includes: when no write operation is performed, recording the voltage difference between the second extension and the first extension as a preset voltage, wherein the absolute value of the difference between the voltage applied to the first gate layer and the preset voltage is not greater than 8V; and / or, the absolute value of the difference between the voltage applied to the second gate layer and the preset voltage is not greater than 8V; and / or, the absolute value of the difference between the voltage applied to the third gate layer and the preset voltage is not greater than 8V.

[0044] In some embodiments, the first storage layer, the second storage layer, and the third storage layer each independently include one of the following structures:

[0045] The first stacked structure includes an oxide layer, a nitride layer, and an oxide layer stacked from bottom to top in a direction from near the common channel region to away from the common channel region;

[0046] The second stacked structure includes oxide layers, nitride layers, oxide layers, nitride layers and oxide layers stacked from bottom to top in a direction from near the common channel region to away from the common channel region;

[0047] as well as,

[0048] Floating gate.

[0049] The semiconductor structure and its operation method provided in this disclosure include: a substrate; a first transistor and a second transistor disposed adjacently, the first transistor and the second transistor being located on the substrate and having a common channel region, the common channel region extending along a first direction parallel to the surface of the substrate, the first transistor including at least a first gate layer and a first storage layer, the second transistor including at least a second gate layer and a second storage layer; a first extension and a second extension, respectively located at both ends of the common channel region in the first direction, the first extension being connected to the end of the common channel region adjacent to the second gate layer, and the second extension being connected to the end of the common channel region adjacent to the first gate layer; wherein the common channel region and the first extension have the same doping type, and the doping type of the second extension is opposite to that of the second extension; the voltage difference between the second extension and the first extension during operation is recorded as a reference voltage, data writing of the first storage layer is implemented based on the voltage difference between the first gate layer and the reference voltage within a first preset range, and data writing of the second storage layer is implemented based on the voltage difference between the second gate layer and the reference voltage within a second preset range.

[0050] Understandably, a memory cell structure can be obtained based on the first transistor and the second transistor. A memory cell containing two transistors offers increased operational stability compared to one containing only one transistor. Furthermore, during operation, the first extension can be supplied with a voltage from the bit line, and the second extension can be supplied with a voltage from the source line. In this embodiment, the first and second extensions have opposite doping types and share the same doping type as the first extension. This allows data to be written into the memory cell when appropriate voltages are applied to the first and second transistors, and the difference between the gate voltage and the reference voltage is within a preset range. During this process, latch-up can be triggered by setting operating conditions, significantly increasing the programming current to achieve high-speed data writing and providing stronger driving capability, even in miniaturized structures. Furthermore, in the embodiments of this disclosure, the common channel region of the two transistors contained in the memory cell is configured with a single doping type. Compared with the traditional method of controlling the doping of different physical junctions, which easily leads to greater process difficulty, the embodiments of this disclosure, in addition to the aforementioned advantages, also have the benefits of simple structure and ease of implementation. As the devices are miniaturized or stacked, the structure of the embodiments of this disclosure can achieve better performance and efficiency.

[0051] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the specification and drawings. Attached Figure Description

[0052] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0053] Figure 1 This is a schematic diagram of the semiconductor structure provided in the embodiments of this disclosure;

[0054] Figure 2 Schematic diagrams of the structure of the first storage layer, the second storage layer, and the third storage layer provided for different embodiments of this disclosure;

[0055] Figure 3 A three-dimensional structural diagram of the semiconductor structure provided in the embodiments of this disclosure;

[0056] Figure 4 This is one of the schematic diagrams of the semiconductor structure provided in the embodiments of this disclosure during the write operation process;

[0057] Figure 5 This is a second schematic diagram of the semiconductor structure provided in the embodiments of this disclosure during the write operation process;

[0058] Figure 6 A schematic diagram illustrating the band structure changes during a write operation of a semiconductor structure provided in this embodiment of the present disclosure;

[0059] Figure 7 A schematic diagram of the current path when latch-up occurs in a semiconductor structure provided in an embodiment of this disclosure;

[0060] Figure 8 This is a schematic diagram illustrating the changes in bit line voltage and bit line current during a write operation in a semiconductor structure provided in this embodiment of the disclosure. Detailed Implementation

[0061] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0062] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0063] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0064] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0065] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0066] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0067] Semiconductor devices, such as memory, typically contain various types of memory, including but not limited to volatile memory and non-volatile memory structures. Common volatile memory includes but is not limited to dynamic random access memory and static memory, while non-volatile memory includes but is not limited to flash memory and ferroelectric memory.

[0068] However, some memory systems still experience issues such as low read / write speeds and low programming current.

[0069] Based on this, the following technical solutions are proposed for embodiments of this disclosure:

[0070] This disclosure provides a semiconductor structure, which includes:

[0071] Substrate;

[0072] A first transistor and a second transistor are disposed adjacently, the first transistor and the second transistor are located on a substrate and have a common channel region, the common channel region extends along a first direction, the first direction is parallel to the surface of the substrate, the first transistor includes at least a first gate layer and a first storage layer, and the second transistor includes at least a second gate layer and a second storage layer.

[0073] The first extension and the second extension are respectively located at both ends of the common channel region in the first direction. The first extension is connected to the end of the common channel region adjacent to the second gate layer, and the second extension is connected to the end of the common channel region adjacent to the first gate layer.

[0074] The common channel region and the first extension have the same doping type, and the doping type is opposite to that of the second extension. The voltage difference between the second extension and the first extension during operation is recorded as the reference voltage. The data writing of the first storage layer is implemented based on the voltage difference between the first gate layer and the reference voltage within a first preset range, and the data writing of the second storage layer is implemented based on the voltage difference between the second gate layer and the reference voltage within a second preset range.

[0075] Understandably, a memory cell structure can be obtained based on the first transistor and the second transistor. A memory cell containing two transistors offers increased operational stability compared to one containing only one transistor. Furthermore, during operation, a voltage from the bit line can be applied to the first extension, and a voltage from the source line can be applied to the second extension. In this embodiment, the first and second extensions have opposite doping types, sharing the same doping type for the channel region and the first extension. This allows data to be written into the memory cell when appropriate voltages are applied to the first and second transistors, and the difference between the gate voltage and the reference voltage is within a preset range. During this process, latch-up can be triggered by setting operating conditions, significantly increasing the programming current to achieve high-speed data writing and providing stronger driving capability, even in miniaturized structures. Furthermore, in the embodiments of this disclosure, the common channel region of the two transistors contained in the memory cell is configured with a single doping type. Compared with the traditional method of controlling the doping of different physical junctions, which easily leads to greater process difficulty, the embodiments of this disclosure, in addition to the aforementioned advantages, also have the benefits of simple structure and ease of implementation. As the devices are miniaturized or stacked, the structure of the embodiments of this disclosure can achieve better performance and efficiency.

[0076] To make the above-mentioned objects, features, and advantages of this disclosure more apparent and understandable, the specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to general proportions, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure.

[0077] Figure 1 This is a schematic diagram of the semiconductor structure provided in the embodiments of this disclosure; Figure 2 Schematic diagrams of the structure of the first storage layer, the second storage layer, and the third storage layer provided for different embodiments of this disclosure; Figure 3 A three-dimensional structural diagram of the semiconductor structure provided in the embodiments of this disclosure; Figure 4 and Figure 5 This is a schematic diagram of the semiconductor structure provided in the embodiments of this disclosure during the write operation process; Figure 6 A schematic diagram illustrating the band structure changes during a write operation of a semiconductor structure provided in this embodiment of the present disclosure; Figure 7 A schematic diagram of the current path when latch-up occurs in a semiconductor structure provided in an embodiment of this disclosure; Figure 8 This is a schematic diagram illustrating the changes in bit line voltage and bit line current during a write operation in a semiconductor structure provided in this embodiment of the disclosure.

[0078] The semiconductor structure provided in the embodiments of this disclosure will now be described in further detail with reference to the accompanying drawings.

[0079] like Figure 1 and Figure 3 As shown, the semiconductor structure includes:

[0080] Substrate 10;

[0081] The first transistor T1 and the second transistor T2 are arranged adjacently. The first transistor T1 and the second transistor T2 are located on the substrate 10 and have a common channel region C. The common channel region C extends along a first direction, which is parallel to the surface of the substrate 10. The first transistor T1 includes at least a first gate layer G1 and a first storage layer 11, and the second transistor T2 includes at least a second gate layer G2 and a second storage layer 12.

[0082] The first extension 14 and the second extension 15 are respectively located at both ends of the common channel region C in the first direction. The first extension 14 is connected to the end of the common channel region C adjacent to the second gate layer G2, and the second extension 15 is connected to the end of the common channel region C adjacent to the first gate layer G1.

[0083] The common channel region C and the first extension 14 have the same doping type, and the doping type is opposite to that of the second extension 15. The voltage difference between the second extension 15 and the first extension 14 during operation is recorded as the reference voltage. The data writing of the first storage layer 11 is realized based on the voltage difference between the first gate layer G1 and the reference voltage within a first preset range. The data writing of the second storage layer 12 is realized based on the voltage difference between the second gate layer G2 and the reference voltage within a second preset range.

[0084] Here, substrate 10 can be a semiconductor substrate; the material of the semiconductor substrate specifically includes elemental semiconductor materials (e.g., silicon (Si) substrates, germanium (Ge) substrates, etc.), or III-V compound semiconductor materials (e.g., gallium nitride (GaN) substrates, gallium arsenide (GaAs) substrates, indium phosphide (InP) substrates, etc.), or II-VI compound semiconductor materials, or organic semiconductor materials, or other semiconductor materials known in the art. In a specific embodiment, substrate 10 is a silicon substrate.

[0085] In some embodiments, the common channel region C and the first extension 14 are P-type doped, and the second extension 15 is N-type doped.

[0086] In this embodiment of the disclosure, the method of having two transistor structures sharing a common channel region instead of having separate corresponding channel regions helps to simplify process steps and improve production efficiency.

[0087] In some embodiments, the doping concentration of the common channel region C ranges from 1 × 10⁻⁶.16 atoms / cm³ ~1×10 18 Between atoms / cm³ (including endpoint values), for example, 5 × 10 16 atoms / cm³, 8×10 16 atoms / cm³, 1×10 17 atoms / cm³, 5×10 17 atoms / cm³, 8×10 17 atoms / cm³, etc. The doping concentration range of the first extension 14 and the second extension 15 is 1×10⁻⁶. 19 atoms / cm³ ~1×10 20 Between atoms / cm³ (including endpoint values), for example, 2×10 19 atoms / cm³, 5×10 19 atoms / cm³, 8×10 19 atoms / cm³, etc.

[0088] In some embodiments, such as Figure 2 As shown, the first storage layer 11 and the second storage layer 12 each independently include one of the following structures:

[0089] like Figure 2 As shown in Figure (1), the first stacked structure ST1 includes an oxide layer, a nitride layer and an oxide layer stacked from bottom to top in a direction a from near the common channel region C to away from the common channel region C;

[0090] like Figure 2 As shown in Figure (2), the second stacked structure ST2 includes an oxide layer, a nitride layer, an oxide layer, a nitride layer and an oxide layer stacked from bottom to top in a direction a from near the common channel region C to away from the common channel region C;

[0091] as well as,

[0092] like Figure 2 As shown in Figure (3), the floating gate L.

[0093] In this embodiment, the first storage layer 11, the second storage layer 12, and the third storage layer 13 (which will be discussed later) are rechargeable thin films, rather than just gate oxide structures. Through programming, hole / electron traps can be formed in these multiple storage layers, creating a non-volatile structure similar to a PNPN thyristor. Furthermore, using the aforementioned materials in the first storage layer 11 and the second storage layer 12 helps improve the reliability of the semiconductor structure.

[0094] In some embodiments, when the materials of the first storage layer 11, the second storage layer 12, and the third storage layer 13 (which will be involved later) comprise the first stacked structure ST1, the thickness of the oxide layer disposed adjacent to the common channel region C ranges from 2 nm to 3 nm (inclusive), for example, 2.5 nm. The thickness of the oxide layer disposed away from the common channel region C ranges from 4 nm to 5 nm (inclusive), for example, 4.5 nm, and the thickness of the nitride layer ranges from 4 nm to 6 nm (inclusive), for example, 4.5 nm, 5 nm, 5.5 nm, etc.

[0095] In embodiments where the materials of the first storage layer 11, the second storage layer 12, and the third storage layer 13 (which will be discussed later) comprise the first stacked structure ST1, the thickness is set according to the magnitude of the gate voltage value that the storage cell A needs to apply during operation. The two complement each other and achieve mutual benefit.

[0096] In some embodiments, such as Figure 3 As shown, along the fourth direction, which is parallel to the second direction and perpendicular to the surface of the substrate 10, the semiconductor structure includes a multilayer memory cell A, and the memory cell A includes at least a first transistor T1 and a second transistor T2.

[0097] It is understood that in the embodiments of this disclosure, the memory cell A obtained based on the first transistor T1 and the second transistor T2 can be a non-volatile memory cell, which has the advantage of long data retention time.

[0098] In some embodiments, the semiconductor structure further includes: a source line SL and multiple bit lines BL, the source line SL extending along a second direction and a third direction and connected to a second extension 15, the multiple bit lines BL extending along the second direction and each bit line BL connected to a first extension 14 located in the same layer;

[0099] The third direction is parallel to the surface of the substrate 10 and intersects with the first direction.

[0100] In this embodiment, the common channel region C has a single doping type. During operation, memory cell A can write data by applying appropriate voltage values ​​to the first transistor T1 and the second transistor T2 at different stages. This process triggers a latch-up effect, which significantly increases the bit line current, providing a larger programming current for the memory cell's programming operations. This enables high-speed data writing and provides stronger driving capability, achieving good driving performance even in miniaturized structures. Furthermore, in this embodiment, the multiple transistors in memory cell A share a common channel region C with only one doping type. Compared to conventional structures where obtaining the channel regions corresponding to the first transistor T1 and the second transistor T2 requires two processes, and compared to methods requiring complex physical junction doping control for the channel regions corresponding to two transistors, the common channel region C in this embodiment can be obtained in a single doping operation. This reduces process complexity, saves process time, improves production efficiency, and lowers costs.

[0101] In the embodiments of this disclosure, the semiconductor structure including the arrangement of multiple layers of memory cells A stacked along a direction perpendicular to the plane of the substrate 10 helps to realize more memory cells A on the substrate 10 of the same area, which helps to improve storage capacity and integration.

[0102] The semiconductor structure provided in this disclosure can be a 3D stackable structure, which can further extend the original memory structure pattern beyond the planar structure to achieve the effect of high-density storage.

[0103] In some embodiments, the number of layers of memory cells A stacked on the substrate 10 can be multiple, such as 2, 3, 4, 5, 6, 7, 8, 9, 10, a dozen, several dozen, 100, several hundred or even more layers, which can be set according to needs and are not specifically limited here.

[0104] Continue to refer to Figure 3 It can be seen that the first extension 14 located on the same layer is connected by the connecting part 16, and a step structure 17 is provided to realize the connection between the first extension 14 located on the same layer and the corresponding bit line BL. That is to say, the first extension 14 adopts a layered setting in terms of connection relationship, and the first extension 14 of each layer is connected to a single bit line BL.

[0105] In this embodiment of the present disclosure, the first extension 14 can be used as a common source / drain region for the first transistor T1 and the second transistor T2, while the second extension 15 can be used as another common source / drain region for the first transistor T1 and the second transistor T2.

[0106] In some embodiments, the first extension 14 can be used as a common drain of the first transistor T1 and the second transistor T2, and is connected to the bit line BL, while the second extension 15 can be used as a common source of the first transistor T1 and the second transistor T2, and is connected to the source line SL.

[0107] In some embodiments, the semiconductor structure further includes:

[0108] The first word line WL1 is connected to the first gate layer G1 and extends along the second direction;

[0109] The second word line WL2 is connected to the second gate layer G2 and extends along the second direction;

[0110] The second direction is perpendicular to the surface of the substrate 10, and the third direction is parallel to the surface of the substrate 10 and intersects with the first direction.

[0111] In some embodiments, during a write operation, when the data to be written is "1", the operation on storage unit A may include at least the following stages:

[0112] 1. Charge injection stage:

[0113] like Figure 4 and Figure 5 As shown, through as Figure 4 The operations in Figures (1) and (2) apply suitable voltage values ​​to the gate layers of the first transistor T1 and the second transistor T2, and when the reference voltage is within a suitable range, the following can be obtained: Figure 5 The result shown is the injection of charge into the first storage layer 11 and the second storage layer 12.

[0114] 2. Latch-up triggering stage:

[0115] like Figure 6 and Figure 7 As shown, after the charge injection stage is completed, by applying a voltage lower than that of the charge injection stage to the gate layers of the first transistor T1 and the second transistor T2, and ensuring that the reference voltage is within a suitable range, a voltage can be established in memory cell A as shown in the diagram. Figure 7 The equivalent structure of the PNPN virtual junction shown in Figure (1) and Figure 7The current path diagram shown in Figure (2) can be used to obtain the result of the interaction between a PNP structure and an NPN structure, which is conducive to the establishment of a positive feedback mechanism, thereby realizing the latch-up effect triggering process. The band change process before and after the start of this process can be referred to as follows. Figure 6 The content shown in the figure indicates that the latch-up effect can be triggered by... Figure 6 The energy bands at the first region B1 of the shared channel region C, originally corresponding to the first transistor T1, and the energy bands at the second region B2 of the shared channel region C, originally corresponding to the second transistor T2, shown in the left-hand diagram, change from a more curved state to a state similar to the one shown in the diagram after receiving positive feedback. Figure 6 The band structure effect shown in the right-hand diagram can be understood as having a "flattening" effect on the band structure, which is beneficial for increasing the potential line current I. BL Thus, the data "1" was written. Furthermore, according to... Figure 8 As shown, in the content corresponding to 2-WL (which can be understood as an embodiment where the memory cell includes the first transistor T1 and the second transistor T2), at the same bit line voltage V BL For example, bit line voltage V BL At 1.2~1.5V, before the latch-up effect occurs, the bit line current I... BL The size is approximately 10 -12 The magnitude of A, and the bit line current I after the latch-up effect occurs. BL The size can be increased to 10 -5 The size of A. Increasing this current helps improve the write speed and enhance drive capability, achieving good drive performance even in miniaturized structures.

[0116] In some embodiments, the settings of the first preset range and the second preset range can correspond to the charge injection stage. The absolute values ​​of the first preset range and the second preset range are each independently 10V~12V, such as 10V, 11V, or 12V. Since charge or electron transitions only occur when the voltage difference between the gate layer voltage and the source / drain voltage (i.e., the reference voltage) of the corresponding transistor in the memory cell to be programmed is not less than 10V, setting a difference range of 10~12V in this embodiment helps to ensure the smooth progress of the charge injection stage and facilitates the data writing process. In addition, in the non-programming state, the difference between the gate and source / drain voltages is not greater than 8V.

[0117] In some embodiments, during a write operation, when the data to be written is "0", the voltage difference between the source and drain can be kept relatively low, for example, 0V~0.5V, after the "1" writing process is completed. This process discharges the charge in each storage layer of the memory cell A, putting the structure in a high-resistance state (HRS). During the "1" writing operation, the structure corresponds to a low-resistance state (LRS).

[0118] In some embodiments, during the charge injection phase of a write operation performed by memory cell A, the voltage direction applied to the first gate layer G1 may be opposite to the voltage direction applied to the second gate layer G2.

[0119] In some embodiments, during the charge injection phase of performing a write "1" operation, a positive voltage, such as 8V, can be applied to the first gate layer G1 of the first transistor T1, while the voltage difference between the source (second extension 15) and the drain (first extension 14) can be set to -2V. Conversely, a negative voltage, such as -8V, can be applied to the second gate layer G2 of the second transistor T2, while the voltage difference between the source (second extension 15) and the drain (first extension 14) can be set to 2V.

[0120] In some embodiments, refer to the appendix Figure 4 In this context, write operations for different transistor structures can be executed separately at different time periods. For example, the write operation can be executed first. Figure 4 The diagram in (1) illustrates the process of first writing to the hole h, and then executing the attached... Figure 4 The operation of writing electron e is shown in (2) above. However, it is not limited to this; the reverse order can also be used. The choice can be made according to the needs, and no specific restrictions are made here.

[0121] In some embodiments, when a read operation is required on memory cell A, the voltage difference between the source and drain can be between 1.2 and 1.5V. For example, at least a voltage is applied to the bit line BL (e.g., 1 to 1.5V), but no voltage is applied to the source line to read the data in memory cell A.

[0122] In this embodiment, the memory cell A includes two transistor structures, specifically a first transistor T1 and a second transistor T2. Based on the operation of injecting electrons into the first gate layer G1 in the first transistor T1 and injecting holes into the second gate layer G2 in the second transistor T2, a structure similar to a PNPN thyristor is formed. On this basis, a positive feedback mechanism is established through a structure similar to PNP and NPN bipolar devices to achieve the effect of reducing the energy barrier. The low resistance state and majority carriers can provide a larger current for programming the memory cell A.

[0123] In addition to the embodiments provided above, this disclosure also provides an embodiment in which the memory cell includes a three-transistor structure, which will be described below with reference to the accompanying drawings.

[0124] Continue to refer to Figure 1 and Figure 3 In some embodiments, the semiconductor structure further includes:

[0125] The third transistor T3 is located between the first transistor T1 and the second transistor T2, and the third transistor T3 shares a common channel region with the first transistor T1 and the second transistor T2; the third transistor T3 includes at least a third gate layer G3 and a third memory layer 13.

[0126] The data writing process of the third storage layer 13 is carried out simultaneously with the data writing process of the second storage layer 12, and the data writing of the third storage layer 13 is realized based on the voltage difference between the third gate layer G3 and the reference voltage within a third preset range.

[0127] In some embodiments, the material of the third storage layer 13 may be the same as the material of the first storage layer 11 and the second storage layer 12, such as the first stacked structure, the second stacked structure, or the floating gate mentioned above. The specific structure and material composition are the same as the materials of the first storage layer 11 and the second storage layer 12, and will not be described in detail here.

[0128] In some embodiments, such as Figure 1 and Figure 3 As shown, memory cell A also includes a third transistor T3.

[0129] In some embodiments, such as Figure 3 As shown, the semiconductor structure also includes:

[0130] The third word line WL3 is connected to the third gate layer G3 and extends along the second and third directions;

[0131] The second direction is perpendicular to the surface of the substrate 10, and the third direction is parallel to the surface of the substrate 10 and intersects with the first direction.

[0132] In some embodiments, the materials of the first word line WL1, the second word line WL2, and the third word line WL3 may include, but are not limited to, conductive materials such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), protactinium (Pa), platinum (Pt), silver (Ag), gold (Au), as well as Co-based alloys, Fe-based alloys, Ni-based alloys, FeNi-based alloys, CoNi-based alloys, FeCo-based alloys, Al-based alloys, Cu-based alloys, Mg-based alloys, Ti-based alloys, low-carbon steel, stainless steel, or conductive metal nitrides such as titanium nitride (TiN), conductive metal silicides, conductive metal carbides, conductive doped semiconductors such as doped polycrystalline silicon, conductive metal oxide semiconductors such as indium tin oxide, and other conductive materials.

[0133] In some embodiments, the materials of the first character line WL1, the second character line WL2, and the third character line WL3 may be the same or different, and no specific limitation is made here.

[0134] In some embodiments, the materials of bit line BL and source line SL may be the same as those of the first word line WL1, the second word line WL2 and the third word line WL3, but are not limited thereto, and may also be different, without specific limitation here.

[0135] In this embodiment of the present disclosure, the operation of applying voltage to the first gate layer G1 can be achieved by applying voltage to the first word line WL1, the operation of applying voltage to the second gate layer G2 can be achieved by applying voltage to the second word line WL2, and the operation of applying voltage to the third gate layer G3 can be achieved by applying voltage to the third word line WL3.

[0136] In some embodiments, during the read / write operation, the electrical signal applied to the third transistor T3, including but not limited to the timing, magnitude, and direction of the voltage applied to the third gate layer G3, can be the same as that applied to the second transistor T2, and will not be elaborated here.

[0137] In some embodiments, the third preset range may be the same as the first preset range and the second preset range, which will not be elaborated here. The settings for other information related to the third transistor T3 can be made with reference to the settings for the second transistor T2, and will not be described in detail here.

[0138] Furthermore, after adding the third transistor T3, the latch-up effect and other conditions that occur during read and write operations in the memory cell A, which originally consisted of two transistors, will not change and will still follow the original rules. Therefore, adding the third transistor T3 will not reduce the function of the original memory cell A.

[0139] Meanwhile, the introduction of the third transistor T3 enhances the control capability of the gate structure over the common channel region C in memory cell A, which helps improve stability during operation and increases the operating window, such as... Figure 8 Comparing the 3-WL curve with the 2-WL curve, we can see the increase in the operating window. In summary, regardless of whether the memory cell contains two or three transistors, data storage is based on the latch-up effect. This helps provide a larger programming current for the memory cell's programming operations, enabling high-speed data writing and stronger driving capability. Even in miniaturized structures, good driving performance can be achieved, which is beneficial for achieving good data storage performance in highly integrated structures. Furthermore, since the larger programming current is generated by the latch-up effect inside memory cell A, rather than being forcibly injected by external circuitry, the current driving capability requirements of peripheral driving circuits (such as write drivers) can be reduced, allowing these circuits to be made smaller and more energy-efficient.

[0140] Furthermore, as can be seen from the above, the semiconductor structure provided in this disclosure has studied the reduction of energy barrier, and in the multiple transistors corresponding to the memory cell, it can be obtained that G1-G2 or G1-G3 have different charge states.

[0141] This disclosure also provides an operation method for a semiconductor structure, such as... Figure 1 , Figure 3 as well as Figure 4 and Figure 5 As shown, the semiconductor structure includes:

[0142] A first transistor T1 and a second transistor T2 are disposed adjacently on a substrate 10. The first transistor T1 and the second transistor T2 have a common channel region C. The first transistor T1 includes at least a first gate layer G1 and a first storage layer 11, and the second transistor T2 includes at least a second gate layer G2 and a second storage layer 12. A first extension 14 and a second extension 15 are provided. The first extension 14 is connected to the end of the common channel region C adjacent to the second gate layer G2, and the second extension 15 is connected to the end of the common channel region C adjacent to the first gate layer G1.

[0143] The operation method includes performing a write operation, which includes: applying a first write voltage to the first gate layer G1, and using the voltage difference between the second extension 15 and the first extension 14 as a reference voltage; and writing data to the first memory layer 11 based on the voltage difference between the first write voltage and the reference voltage within a first preset range; and,

[0144] A second write voltage is applied to the second gate layer G2, and the voltage difference between the second extension 15 and the first extension 14 is used as a reference voltage. Data is written to the second memory layer 12 based on the voltage difference between the second write voltage and the reference voltage within a second preset range.

[0145] The common channel region C has the same doping type as the first extension 14 and the opposite doping type to the second extension 15.

[0146] In some embodiments, the common channel region C and the first extension 14 are both P-type doped, and the second extension 15 is N-type doped.

[0147] In some embodiments, the first extension 14 can be used as a common drain of the first transistor T1 and the second transistor T2, and is connected to the bit line BL, while the second extension 15 can be used as a common source of the first transistor T1 and the second transistor T2, and is connected to the source line SL.

[0148] In some embodiments, during a write operation, when the data to be written is "1", the operation on storage unit A may include at least the following stages:

[0149] 1. Charge injection stage:

[0150] In some embodiments, such as Figure 3 , Figure 4 As shown in Figures (1) and (2), this stage can be divided into two steps, for example:

[0151] First, such as Figure 4 As shown in Figure (1), a negative voltage is applied to the second gate layer G2 and a negative voltage is applied to the bit line BL, while no voltage is applied to the source line SL. Thus, the process of writing holes into the second storage layer 12 of the second transistor T2 is realized by the voltage difference between the second gate layer G2 and the reference voltage.

[0152] Next, as Figure 4 As shown in Figure (2), a positive voltage is applied to the first gate layer G1 and the bit line BL, and no voltage is applied to the source line SL. Thus, the process of writing electrons into the first storage layer 11 of the first transistor T1 is realized by the voltage difference between the first gate layer G1 and the reference voltage.

[0153] It should be noted that the order in which charge is written into the first transistor T1 and the second transistor T2 during this stage can be changed and the order can be set according to requirements. No specific limitation is made here.

[0154] In some embodiments, during the charge injection stage, the voltage applied to the first gate layer G1, i.e. the first write voltage, can be in the range of 7~10V, such as 8V, 9V, 10V, etc., and the voltage applied to the bit line BL is in the range of 0V~3V, such as 1V, 2V, or 3V, etc.

[0155] In some embodiments, during the charge injection stage, the voltage applied to the second gate layer G2, i.e. the second write voltage, can be in the range of -7 to -10V, such as -8V, -9V, -10V, etc., and the voltage applied to the bit line BL is in the range of -3V to 0V, such as -3V, -2V, -1V, etc.

[0156] In this way, one can obtain such Figure 5 The result shown is the injection of charge into the first storage layer 11 and the second storage layer 12.

[0157] 2. Latch-up triggering stage:

[0158] like Figure 6 and Figure 7 As shown, after the charge injection stage is completed, by applying a voltage lower than that of the charge injection stage to the gate layers of the first transistor T1 and the second transistor T2, and ensuring that the reference voltage is within a suitable range, a voltage can be established in memory cell A as shown in the diagram. Figure 7 The equivalent structure of the PNPN virtual junction shown in Figure (1) and Figure 7 The current path diagram shown in Figure (2) is similar to the result of the interaction between a PNP structure and an NPN structure, which is conducive to the establishment of a positive feedback mechanism, thereby realizing the latch-up effect triggering process. The corresponding band change process before and after the process is turned on can be referred to as follows. Figure 6 The content shown in the figure indicates that the latch-up effect can be triggered by... Figure 6 The energy bands at the first region B1 of the shared channel region C, originally corresponding to the first transistor T1, and the energy bands at the second region B2 of the shared channel region C, originally corresponding to the second transistor T2, shown in the left-hand diagram, change from a more curved state to a state similar to the one shown in the diagram after receiving positive feedback. Figure 6 The band structure effect shown in the right-hand diagram can be understood as having a "flattening" effect on the band structure, which is beneficial for increasing the potential line current I. BL Thus, the data "1" was written.

[0159] In some embodiments, during the latch-up triggering phase, the voltage applied to the gate layers of the first transistor T1 and the second transistor T2 can be between +1.5V and +2.5V (inclusive), for example, 2V, and can both be positive voltages. Alternatively, a voltage range of +3V to +5V (inclusive), such as +3.5V, +4V, +4.5V, can be applied to the bit line BL, while no voltage is applied to the source line SL.

[0160] In addition, according to such Figure 8 As shown, in the content corresponding to 2-WL (which can be understood as an embodiment where the memory cell includes the first transistor T1 and the second transistor T2), at the same bit line voltage V BL For example, bit line voltage V BL At 1.2~1.5V, before the latch-up effect occurs, the bit line current I... BL The size is approximately 10 -12 The magnitude of A, and the bit line current I after the latch-up effect occurs. BL The size can be increased to 10 -5 The size of A increases the current, which helps to improve the write speed and enhance the driving capability, so that good driving performance can be obtained even in miniaturized structures.

[0161] In some embodiments, the settings of the first preset range and the second preset range can correspond to the charge injection stage. The absolute values ​​of the first preset range and the second preset range are each independently 10V~12V, such as 10V, 11V, or 12V. Since charge or electron transitions only occur when the voltage difference between the gate layer voltage and the source / drain voltage (i.e., the reference voltage) of the corresponding transistor in the memory cell to be programmed is not less than 10V, setting a difference range of 10~12V in this embodiment helps to ensure the smooth progress of the charge injection stage and facilitates the data writing process. In addition, in the non-programming state, the difference between the gate and source / drain voltages is not greater than 8V.

[0162] In some embodiments, during a write operation, when the data to be written is "0", the data "0" can be written by applying a voltage of 0V~0.5V to the bit line BL (drain) without applying voltage to the first gate layer G1 and the second gate layer G2, and by setting the source line SL to be un-voltaged after the "1" writing process is completed. This process discharges the charge in each storage layer of the memory cell A, putting the structure in a high-resistance state (HRS). During the "1" writing operation, the structure corresponds to a low-resistance state (LRS).

[0163] In some embodiments, the operation method further includes performing a read operation, which includes applying a first read voltage to the first extension 14 to read data stored in the first storage layer 11 and the second storage layer 12;

[0164] or,

[0165] A first read voltage is applied to the first extension 14, a second read voltage is applied to the first gate layer G1, and a third read voltage is applied to the second gate layer G2 to read data stored in the first storage layer 11 and the second storage layer 12.

[0166] In some embodiments, during a read operation, the voltage difference between the source and drain ranges from 1.2 to 1.5V (including endpoint values), such as 1.1V, 1.2V, 1.3V, 1.4V, etc.

[0167] In some embodiments, during the read operation, a voltage application method may be used, wherein the first read voltage is in the range of 1 to 1.5V (including the endpoint value), such as 1.1V, 1.2V, 1.3V, 1.4V, etc. In this case, no voltage may be applied to the second extension 15.

[0168] In some embodiments, the second and third read voltages may have the same range, which is between 0 and 3V (inclusive), such as 1V, 2V, etc. The voltage directions of the two voltages may also be the same, but are not limited thereto, and may also be opposite, without specific limitation here.

[0169] In this embodiment, the memory cell A includes two transistor structures, specifically a first transistor T1 and a second transistor T2. Based on the operation of injecting electrons into the first gate layer G1 in the first transistor T1 and injecting holes into the second gate layer G2 in the second transistor T2, a structure similar to a PNPN thyristor is formed. On this basis, a positive feedback mechanism is established through bipolar devices similar to PNP and NPN to achieve the effect of reducing the energy barrier. The low resistance state and majority carriers can provide a larger current for programming the memory cell A.

[0170] In some embodiments, the semiconductor structure further includes a third transistor T3, which includes at least a third gate layer G3 and a third storage layer 13. The third transistor T3 is located between the first transistor T1 and the second transistor T2, and the third transistor T3 shares a common channel region C with the first transistor T1 and the second transistor T2. Performing a write operation further includes:

[0171] While applying a second write voltage to the second gate layer G2, a third write voltage is applied to the third gate layer G3. Data is written to the third storage layer 13 based on the voltage difference between the third write voltage and the reference voltage within a third preset range.

[0172] The third writing voltage has the same voltage direction as the second writing voltage.

[0173] In some embodiments, the method further includes performing a read operation, which includes:

[0174] A first read voltage is applied to the first extension 14 to read the data stored in the first storage layer 11, the second storage layer 12 and the third storage layer 13;

[0175] or,

[0176] A first read voltage is applied to the first extension 14, and a second read voltage is applied to the first gate layer G1, a third read voltage is applied to the second gate layer G2, and a fourth read voltage is applied to the third gate layer G3 to read the data stored in the first storage layer 11, the second storage layer 12, and the third storage layer 13.

[0177] In some embodiments, the absolute value of the third preset range is the same as that of the first preset range and the second preset range, and will not be described in detail.

[0178] In some embodiments, the operation method further includes: when no write operation is performed, recording the voltage difference between the second extension 15 and the first extension 14 as a preset voltage, and the absolute value of the difference between the voltage applied to the first gate layer G1 and the preset voltage is not greater than 8V; and / or, the absolute value of the difference between the voltage applied to the second gate layer G2 and the preset voltage is not greater than 8V; and / or, the absolute value of the difference between the voltage applied to the third gate layer G3 and the preset voltage is not greater than 8V.

[0179] In actual operation, the timing, magnitude, and direction of voltage application related to the third transistor T3 can all be set in the same way as the relevant information for the second transistor T2.

[0180] In this embodiment of the disclosure, the addition of a third transistor T3 is to increase the number of gate layers to enhance the control capability over the common channel region, thereby enhancing the stability of the operation process and helping to obtain an excellent operating window.

[0181] In some embodiments, such as Figure 2 As shown, the first storage layer 11, the second storage layer 12, and the third storage layer 13 each independently include one of the following structures:

[0182] like Figure 2 As shown in Figure (1), the first stacked structure ST1 includes an oxide layer, a nitride layer and an oxide layer stacked from bottom to top in a direction from near the common channel region C to away from the common channel region C;

[0183] like Figure 2 As shown in Figure (2), the second stacked structure ST2 includes an oxide layer, a nitride layer, an oxide layer, a nitride layer and an oxide layer stacked from bottom to top in a direction from near the common channel region C to away from the common channel region C;

[0184] as well as,

[0185] like Figure 2 As shown in Figure (3), the floating gate L.

[0186] The semiconductor structure and operation method provided in this disclosure are suitable for memory structures with a large number of stacked layers, such as 3D stacked structures with more than 100 or even more stacked layers, and can still achieve good performance. In these structures, capacitor-free non-volatile memory cells are constructed by using PNPN thyristors with ONO trapping layers. The first transistor T1, the second transistor T2, and the third transistor T3 all achieve electron / hole charge storage through the Fermi-Nordham tunneling effect, enabling the writing of "1" or "0" states in the hysteresis curve via bit lines, followed by the application of an appropriate bit line voltage to read the relevant data.

[0187] The technical features described in the embodiments provided in this disclosure can be arbitrarily combined without conflict.

[0188] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure includes: Substrate; A first transistor and a second transistor are disposed adjacently, the first transistor and the second transistor are located on the substrate and have a common channel region, the common channel region extending along a first direction, the first direction being parallel to the surface of the substrate, the first transistor including at least a first gate layer and a first storage layer, and the second transistor including at least a second gate layer and a second storage layer; The first extension and the second extension are respectively located at both ends of the common channel region in the first direction. The first extension is connected to the end of the common channel region adjacent to the second gate layer, and the second extension is connected to the end of the common channel region adjacent to the first gate layer. The source line extends along a second direction and a third direction and is connected to the second extension, and the bit line extends along the second direction and is connected to the first extension; wherein the second direction is perpendicular to the surface of the substrate, and the third direction is parallel to the surface of the substrate and intersects the first direction; The common channel region and the first extension have the same doping type, and the doping type is opposite to that of the second extension. The voltage difference between the second extension and the first extension during operation is recorded as the reference voltage. The data writing of the first storage layer is implemented based on the voltage difference between the first gate layer and the reference voltage within a first preset range, and the data writing of the second storage layer is implemented based on the voltage difference between the second gate layer and the reference voltage within a second preset range.

2. The semiconductor structure of claim 1, wherein, The semiconductor structure also includes: A third transistor is located between the first transistor and the second transistor, and the third transistor shares a common channel region with the first transistor and the second transistor; the third transistor includes at least a third gate layer and a third memory layer; The data writing process of the third storage layer is performed simultaneously with the data writing process of the second storage layer, and the data writing of the third storage layer is achieved based on the voltage difference between the third gate layer and the reference voltage within a third preset range.

3. The semiconductor structure of claim 1, wherein, The common channel region and the first extension are doped with P-type, and the second extension is doped with N-type.

4. The semiconductor structure according to claim 2, characterized in that, The first storage layer, the second storage layer, and the third storage layer each independently include one of the following structures: The first stacked structure includes an oxide layer, a nitride layer, and an oxide layer stacked from bottom to top in a direction from near the common channel region to away from the common channel region; The second stacked structure includes oxide layers, nitride layers, oxide layers, nitride layers and oxide layers stacked from bottom to top in a direction from near the common channel region to away from the common channel region; as well as, Floating gate.

5. The semiconductor structure according to claim 4, characterized in that, When the materials of the first storage layer, the second storage layer and the third storage layer contain the first stacked structure, the thickness of the oxide layer disposed adjacent to the common channel region is between 2nm and 3nm, the thickness of the oxide layer disposed away from the common channel region is between 4nm and 5nm, and the thickness of the nitride layer is between 4nm and 6nm.

6. The semiconductor structure according to claim 2, characterized in that, The semiconductor structure also includes: The first word line is connected to the first gate layer and extends along the second direction; The second word line is connected to the second gate layer and extends along the second direction; The third word line is connected to the third gate layer and extends along the second direction and the third direction; Wherein, the second direction is perpendicular to the surface of the substrate, and the third direction is parallel to the surface of the substrate and intersects the first direction.

7. The semiconductor structure of any of claims 1-6, wherein, The number of bit lines is multiple, and along the fourth direction, the semiconductor structure includes multiple layers of memory cells. Each memory cell includes at least the first transistor and the second transistor, wherein... The plurality of bit lines extend along the second direction and each bit line is connected to the first extension located in the same layer; The fourth direction is parallel to the second direction.

8. The semiconductor structure of any of claims 1-6, wherein, The doping concentration range of the common channel region is 1×10⁻⁶. 16 atoms / cm³ ~1×10 18 The doping concentrations of the first and second extensions are between atoms / cm³ and within the range of 1×10⁻⁶. 19 atoms / cm³ ~1×10 20 Between atoms / cm³.

9. A method of operating a semiconductor structure, the method comprising: The semiconductor structure includes: A first transistor and a second transistor are disposed adjacently on a substrate, the first transistor and the second transistor having a common channel region extending along a first direction, the first transistor including at least a first gate layer and a first memory layer, and the second transistor including at least a second gate layer and a second memory layer; a first extension and a second extension, the first extension being connected to an end of the common channel region adjacent to the second gate layer, and the second extension being connected to an end of the common channel region adjacent to the first gate layer; a source line and a bit line, the source line extending along a second direction and a third direction and connected to the second extension, and the bit line extending along the second direction and connected to the first extension; wherein the second direction is perpendicular to the surface of the substrate, and the third direction is parallel to the surface of the substrate and intersects the first direction; The operation method includes performing a write operation, which includes: applying a first write voltage to the first gate layer, and using the voltage difference between the second extension and the first extension as a reference voltage; and writing data to the first memory layer based on the voltage difference between the first write voltage and the reference voltage within a first preset range; and... A second write voltage is applied to the second gate layer, and the voltage difference between the second extension and the first extension is the reference voltage. Data is written to the second memory layer based on the voltage difference between the second write voltage and the reference voltage within a second preset range. The common channel region has the same doping type as the first extension and the opposite doping type to the second extension.

10. The method of claim 9, wherein, The semiconductor structure further includes a third transistor, which includes at least a third gate layer and a third memory layer. The third transistor is located between the first transistor and the second transistor, and the third transistor shares a common channel region with the first transistor and the second transistor. The write operation further includes: While applying the second write voltage to the second gate layer, a third write voltage is applied to the third gate layer, and data is written to the third memory layer based on the voltage difference between the third write voltage and the reference voltage within a third preset range; The third write voltage has the same voltage direction as the second write voltage.

11. The operating method according to claim 9, characterized in that, The operation method further includes performing a read operation, which includes applying a first read voltage to the first extension to read data stored in the first storage layer and the second storage layer; or, A first read voltage is applied to the first extension, a second read voltage is applied to the first gate layer, and a third read voltage is applied to the second gate layer to read data stored in the first memory layer and the second memory layer.

12. The operating method according to claim 10, characterized in that, The operation method further includes performing a read operation, wherein performing the read operation includes: A first read voltage is applied to the first extension to read the data stored in the first storage layer, the second storage layer, and the third storage layer; or, A first read voltage is applied to the first extension, and a second read voltage, a third read voltage, and a fourth read voltage are applied to the first gate layer, the second gate layer, and the third gate layer, respectively, to read data stored in the first memory layer, the second memory layer, and the third memory layer.

13. The method of claim 10, wherein, The absolute values ​​of the first preset range, the second preset range, and the third preset range are each independently 10V~12V.

14. The operating method according to claim 10, characterized in that, The operation method further includes: when no write operation is performed, recording the voltage difference between the second extension and the first extension as a preset voltage, and the absolute value of the difference between the voltage applied to the first gate layer and the preset voltage is not greater than 8V; and / or, the absolute value of the difference between the voltage applied to the second gate layer and the preset voltage is not greater than 8V; and / or, the absolute value of the difference between the voltage applied to the third gate layer and the preset voltage is not greater than 8V.

15. The method of operation according to any of claims 10, 12-14, wherein, The first storage layer, the second storage layer, and the third storage layer each independently include one of the following structures: The first stacked structure includes an oxide layer, a nitride layer, and an oxide layer stacked from bottom to top in a direction from near the common channel region to away from the common channel region; The second stacked structure includes oxide layers, nitride layers, oxide layers, nitride layers and oxide layers stacked from bottom to top in a direction from near the common channel region to away from the common channel region; as well as, Floating gate.

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