Semiconductor structure manufacturing method and semiconductor structure

Abstract

This application provides a method for manufacturing a semiconductor structure and a semiconductor structure. The method includes: providing a substrate including a substrate with a gate trench and a bottom gate portion; wherein the gate trench has a bottom surface and a side surface; the bottom gate portion is formed in a region near the bottom surface within the gate trench; a portion of the side surface of the gate trench is exposed; a trench filling portion is formed based on the exposed side surface of the gate trench using a lateral epitaxial process; a channel active structure is formed based on the trench filling portion; with the material growth direction of the lateral epitaxial process as the width direction, the width of the trench filling portion is equal to the width of the bottom gate portion and greater than the width of the channel active structure along the width direction; a top gate portion is formed covering the side surface of the channel active structure and the surface of the channel active structure away from the bottom gate portion, thereby obtaining a semiconductor structure including a fully surrounding gate. This application expands the effective channel width variation range of the fully surrounding gate structure.

Description

Technical Field

[0001] The embodiments in this application relate to the field of semiconductor technology, specifically to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Technology

[0002] As semiconductor devices continue to develop towards higher integration and higher performance, the structure of metal oxide semiconductor field-effect transistors (MOSFETs) has gradually evolved from the traditional two-dimensional planar structure to a three-dimensional structure, namely, the fin field-effect transistor (FinFET).

[0003] As semiconductor process nodes continue to shrink, the short-channel effect of fin field-effect transistors (FETs) limits their performance improvement. Therefore, in existing advanced semiconductor processes, FETs with a gate-all-around (GAA) structure are used to replace FETs in order to overcome the physical limitations of FETs.

[0004] Existing fabrication processes for all-around gate structures primarily involve nanosheet stacking. However, the effective channel width variation range of all-around gate structures fabricated using this process is insufficient to meet the design requirements of all-around gate structures. Summary of the Invention

[0005] In view of this, several embodiments of this application provide a method for manufacturing a semiconductor structure and a semiconductor structure to expand the range of variation of the effective channel width of the all-around gate structure.

[0006] In one aspect, one embodiment of this application provides a method for manufacturing a semiconductor structure, the method comprising: providing a substrate; the substrate including a substrate having a gate trench and a bottom gate portion; wherein the gate trench has a bottom surface and a side surface; the bottom gate portion is formed in a region of the gate trench near the bottom surface; a portion of the side surface of the gate trench is exposed; forming a trench filling portion based on the exposed side surface of the gate trench using a lateral epitaxial process; wherein, with the material growth direction of the lateral epitaxial process as the width direction, the width of the trench filling portion along the width direction is equal to the width of the bottom gate portion along the width direction; forming a channel active structure based on the trench filling portion; wherein the width of the trench filling portion along the width direction is greater than the width of the channel active structure along the width direction; forming a top gate portion covering the side surface of the channel active structure and the surface of the channel active structure away from the bottom gate portion, thereby obtaining the semiconductor structure; in the semiconductor structure, a gate composed of the bottom gate portion and the top gate portion surrounds the channel active structure.

[0007] Optionally, the step of providing a substrate includes: providing a transition substrate; the transition substrate includes a transition substrate and a first photolithographic functional layer formed on the surface of the transition substrate; etching the transition substrate based on the first photolithographic functional layer to obtain the substrate having a gate trench; wherein the bottom and side surfaces of the gate trench are exposed; performing surface oxidation on the substrate to form an isolation layer on the bottom and side surfaces of the gate trench; depositing gate material on the side of the isolation layer away from the substrate within the gate trench to form a gate material deposition portion; and etching the gate material deposition portion to form the bottom gate portion.

[0008] Optionally, the substrate further includes: a transition bottom gate oxide layer formed on the surface of the bottom gate portion away from the substrate; when the gate material is polysilicon, the step of etching the gate material deposition portion to form the bottom gate portion includes: etching the gate material deposition portion to form a transition gate portion; wherein, with the extension direction of the gate trench as the thickness direction, the thickness of the transition gate portion along the thickness direction is greater than a specified gate thickness; performing surface oxidation on the transition gate portion to form a first transition oxide layer on the surface of the transition gate portion away from the substrate, and using the unoxidized portion of the transition gate portion as the bottom gate portion; wherein, the thickness of the bottom gate portion along the thickness direction is equal to the specified gate thickness; correspondingly, the semiconductor structure manufacturing method further includes: removing a portion of the first transition oxide layer and a portion of the isolation layer formed on the side of the gate trench to obtain a transition bottom gate oxide layer, and exposing a portion of the side of the gate trench.

[0009] Optionally, when the gate material is metal, the step of etching the gate material deposition portion to form the bottom gate portion includes: etching the gate material deposition portion to form the bottom gate portion; wherein the thickness of the bottom gate portion along the thickness direction is equal to a specified gate thickness; correspondingly, the semiconductor structure manufacturing method further includes: forming an oxide on the surface of the bottom gate portion to obtain a transition bottom gate oxide layer; removing a portion of the isolation layer formed on the side of the gate trench, so that a portion of the side of the gate trench is exposed.

[0010] Optionally, the step of forming a channel active structure based on the trench filling portion includes: performing ion implantation on the trench filling portion to form a transition active structure; forming a second photolithographic functional layer on the surface of the transition active structure away from the bottom gate portion and a portion of the surface of the substrate; and etching the transition active structure and the substrate based on the second photolithographic functional layer to obtain a semiconductor substrate and a channel active structure protruding from the surface of the semiconductor substrate.

[0011] Optionally, the second photolithographic functional layer includes an oxide isolation layer; before forming a top gate portion covering the sidewalls of the channel active structure and the surface of the channel active structure away from the bottom gate portion, the method of manufacturing the semiconductor structure further includes: forming a side oxide layer covering the sidewalls of the channel active structure; using a self-aligned etching process to remove at least a portion of the transition bottom gate oxide layer to obtain a gate oxide layer, thereby exposing a portion of the semiconductor substrate and a portion of the bottom gate portion; wherein the remaining etch portions of the side oxide layer, the transition bottom gate oxide layer, and the remaining etch portions of the oxide isolation layer constitute the gate oxide layer; in the gate oxide layer, the portions covering different surfaces of the channel active structure have equal thickness.

[0012] Optionally, the step of forming a top gate portion covering the side of the channel active structure and the surface of the channel active structure away from the bottom gate portion to obtain the semiconductor structure includes: depositing a gate material on the surface of the semiconductor substrate and the surface of the gate oxide layer to obtain a gate material layer; forming a third photolithography functional layer on the side of the gate material layer away from the semiconductor substrate; and etching the gate material layer based on the third photolithography functional layer to form the top gate portion.

[0013] Optionally, the first photolithography functional layer includes a first photoresist layer, the material of which is negative photoresist; the second photolithography functional layer includes a second photoresist layer; the third photolithography functional layer includes a third photoresist layer; and the materials of the second photoresist layer and the third photoresist layer are positive photoresist.

[0014] Optionally, the semiconductor structure further includes an isolation structure formed on the surface of the semiconductor substrate and the gate side; the third photolithography functional layer includes a hard mask layer formed on the side of the top gate portion away from the bottom gate portion; after etching the gate material layer based on the third photolithography functional layer to form the top gate portion, the etching residue of the hard mask layer located on the side of the top gate portion away from the bottom gate portion is retained; before removing the etching residue of the hard mask layer, the method of manufacturing the semiconductor structure further includes: depositing an isolation material on the surface of the semiconductor substrate to obtain an isolation material layer; using the surface of the hard mask layer away from the semiconductor substrate as the grinding endpoint, planarizing the isolation material layer using a chemical mechanical polishing process; and removing the etching residue of the hard mask layer and part of the isolation material using a wet etching process to form the isolation structure.

[0015] In another aspect, one embodiment of this application provides a semiconductor structure manufactured by the semiconductor structure manufacturing method described in the above embodiments.

[0016] In several embodiments provided in this application, by providing a substrate including a substrate with a gate trench and a bottom gate portion, wherein a portion of the sidewalls of the gate trench are exposed, a trench filling portion is formed based on the exposed sidewalls of the gate trench using a lateral epitaxial process, such that the width of the trench filling portion along the material growth direction of the lateral epitaxial process is consistent with the width of the bottom gate portion along that direction, and then a channel active structure with a width smaller than the width of the trench filling portion is formed based on the trench filling portion, and a top gate portion is formed covering the sidewalls of the channel active structure and the surface away from the bottom gate portion, such that the gate surrounds the channel active structure, the unexpected effects achieved include: using a lateral epitaxial process to form a trench filling portion with a width dimension matching the width dimension of the bottom gate portion, and then forming a channel active structure based on the trench filling portion, the width of the trench active structure can be continuously varied within a range not greater than the width of the bottom gate portion, thereby enabling the effective channel width to be continuously varied, thus breaking through the limitation of the effective channel width variation range being restricted by the integer multiple of the number of nanosheet stacked layers in related technologies, and expanding the effective channel width variation range of the fully surrounding gate structure. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in describing the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1A schematic diagram of the structure of a two-dimensional planar field-effect transistor provided for related technologies.

[0019] Figure 2 A schematic diagram of the structure of a three-dimensional planar field-effect transistor provided for related technologies.

[0020] Figure 3 A schematic diagram of the structure of a three-dimensional vertical field-effect transistor provided for related technologies.

[0021] Figure 4 A schematic diagram of a fin field-effect transistor with a single fin, provided for related technologies.

[0022] Figure 5 A schematic diagram of a fin field-effect transistor with multiple fins, provided for related technologies.

[0023] Figure 6 A schematic diagram of multiple structural parameters in a fin field-effect transistor provided for related technologies.

[0024] Figure 7 This is a schematic flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this application.

[0025] Figure 8 This is a schematic diagram of the process for providing a substrate, as provided in an embodiment of this application.

[0026] Figure 9 This is a schematic diagram of the structure of the transition substrate provided in an embodiment of this application.

[0027] Figure 10 This is a schematic diagram of a substrate forming a gate trench, provided for an embodiment of this application.

[0028] Figure 11 This is a schematic diagram of an isolation layer formed on the bottom and side surfaces of a gate trench, provided as an embodiment of this application.

[0029] Figure 12 This is a schematic diagram of a gate material deposition portion formed on the surface of an isolation layer, provided in an embodiment of this application.

[0030] Figure 13 This is a schematic diagram of etching the gate material deposition portion to obtain the transition gate portion when the gate material is polysilicon, as provided in an embodiment of this application.

[0031] Figure 14 This is a schematic diagram showing the formation of a first transition oxide layer and a bottom gate portion when the gate material is polysilicon, as provided in an embodiment of this application.

[0032] Figure 15 This is a schematic diagram showing the removal of a portion of the first transition oxide layer and a portion of the isolation layer when the gate material is polysilicon, as provided in an embodiment of this application.

[0033] Figure 16 This is a schematic diagram of etching the gate material deposition portion to obtain the bottom gate portion when the gate material is metal, as provided in an embodiment of this application.

[0034] Figure 17 This is a schematic diagram of forming a transition bottom gate oxide layer when the gate material is metal, provided as an embodiment of this application.

[0035] Figure 18 This is a schematic diagram showing the removal of a portion of the isolation layer when the gate material is metal, as provided in an embodiment of this application.

[0036] Figure 19 This is a schematic diagram illustrating the formation of a trench filling portion based on the exposed side surface of a gate trench using a lateral epitaxial process, as provided in an embodiment of this application.

[0037] Figure 20 This is a schematic diagram illustrating the removal of the first oxide layer and the first nitride layer, provided in an embodiment of this application.

[0038] Figure 21 This is a schematic diagram of the process for forming an active channel structure based on the groove filling part, provided in an embodiment of this application.

[0039] Figure 22 This is a schematic diagram of performing ion implantation on the trench filling portion to form a transitional active structure, provided in an embodiment of this application.

[0040] Figure 23 This is a schematic diagram of forming a second photolithographic functional layer when the gate material is polysilicon, as provided in an embodiment of this application.

[0041] Figure 24 This is a schematic diagram of forming a second photolithographic functional layer when the gate material is metal, provided as an embodiment of this application.

[0042] Figure 25 This is a schematic diagram of a semiconductor substrate and a pre-channel structure obtained when the gate material is polycrystalline silicon, as provided in an embodiment of this application.

[0043] Figure 26 This is a schematic diagram of a semiconductor substrate and a channel active structure obtained when the gate material is metal, as provided in an embodiment of this application.

[0044] Figure 27 This is a schematic diagram of forming a channel active structure and a side oxide layer when the gate material is polysilicon, as provided in an embodiment of this application.

[0045] Figure 28 This is a schematic diagram of the formation of a side oxide layer when the gate material is metal, provided as an embodiment of this application.

[0046] Figure 29 This is a schematic diagram illustrating the removal of the remaining portion of the second nitride layer when the gate material is polysilicon, as provided in an embodiment of this application.

[0047] Figure 30 This is a schematic diagram illustrating the removal of the remaining portion of the second nitride layer when the gate material is metal, as provided in an embodiment of this application.

[0048] Figure 31 This is a schematic diagram of forming a gate oxide layer when the gate material is polysilicon, as provided in an embodiment of this application.

[0049] Figure 32 This is a schematic diagram of forming a gate oxide layer when the gate material is metal, provided as an embodiment of this application.

[0050] Figure 33 This is a schematic diagram of the process for forming the top gate portion provided in an embodiment of this application.

[0051] Figure 34 This is a schematic diagram of the formation of the gate material layer and the third photolithography functional layer provided in an embodiment of this application.

[0052] Figure 35 This is a schematic diagram of the formation of the top gate portion provided in an embodiment of this application.

[0053] Figure 36 This is a schematic diagram of the formation of an isolation material layer provided in an embodiment of this application.

[0054] Figure 37 This is a schematic diagram of the formation of an isolation structure provided in an embodiment of this application.

[0055] Structural designation explanation

[0056] 100. Transition substrate; 110. Transition substrate; 111. Substrate; 112. Gate trench; 113. Semiconductor substrate; 120. First photolithographic functional layer; 121. Oxide layer; 121a. Remaining etched portion of oxide layer; 122. First nitride layer; 122a. Remaining etched portion of first nitride layer; 123. First photoresist layer; 130. Isolation layer; 131. First etched portion of isolation layer; 132. Second etched portion of isolation layer; 140. Gate material deposition portion; 141. Transition gate portion; 142. Bottom gate portion; 150. First transition oxide layer; 151. Transition bottom gate oxide layer; 152. Remaining etched portion of transition bottom gate oxide layer; 210. Trench filling portion; 211. Transition active structure; 220. Second photolithography functional layer; 221. Oxide isolation layer; 221a. Remaining etched portion of the oxide isolation layer; 222. Second nitride layer; 223. Second photoresist layer; 230. Preparatory channel structure; 231. Channel active structure; 240. Side oxide layer; 241. Transition interface oxide layer; 242. Gate oxide layer; 250. Gate material layer; 260. Third photolithography functional layer; 261. Oxide mask layer; 261a. Remaining etched portion of the oxide mask layer; 262. Hard mask layer; 262a. Remaining etched portion of the hard mask layer; 263. Oxide dielectric layer; 264. Anti-reflective coating; 265. Bottom anti-reflective coating; 266. Third photoresist layer; 270. Top gate portion; 280. Isolation material layer; 281. Isolation structure. Detailed Implementation

[0057] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0058] The accompanying drawings provided in this application are only schematic illustrations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component may be changed, and the layout of the components may also be more complex.

[0059] In the description of the embodiments of this application, it should be understood that the terms "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," "center," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" and "second" may explicitly or implicitly include one or more of the stated features.

[0060] Please see Figure 1 As semiconductor process nodes shrink to 14nm, the channel length L is limited by the resolution of photolithography and the negative impact of short-channel effects. This is particularly relevant for two-dimensional planar field-effect transistors where the source, drain, and gate are all located on the same plane of the silicon substrate. g The size of these components has physical limitations, making it difficult to meet the current design requirements for miniaturization and high performance of semiconductor devices.

[0061] Please see Figures 2 to 4 Researchers have attempted to improve two-dimensional planar field-effect transistors (FETs) into three-dimensional FETs by vertically extending the channel length and width, thus overcoming the size limitations of two-dimensional planar FETs. They have fabricated three types of three-dimensional FETs: three-dimensional planar FETs, three-dimensional vertical FETs, and FinFETs (Fin Field-Effect Transistors). Comparing the manufacturing processes of these three types reveals that FinFETs are less complex and difficult to manufacture, and have a higher production yield than three-dimensional planar and three-dimensional vertical FETs. Therefore, FinFETs have found wider applications.

[0062] Please see Figure 5 and Figure 6 Based on the thickness of the dielectric layer between the top surface of the fin surrounded by the gate and the gate, the gate of a fin field-effect transistor can be divided into double-gate and triple-gate types. Specifically, it is determined by... Figure 6 As can be seen, in a fin field-effect transistor, the top surface and two side surfaces of the fin are surrounded by a gate, and a dielectric layer is disposed between each surface and the gate. The dielectric layer material is usually oxide. The dielectric layer between the two side surfaces of the fin and the gate is relatively thin; therefore, the two side surfaces serve as the front gate. Figure 6Middle gate (1) and back gate (Back Gate) Figure 6 (2) When the dielectric layer between the top surface of the fin and the gate is thick, the channel only includes the aforementioned front gate and rear gate. In this case, the gate of the fin field-effect transistor is a double-sided gate. When the dielectric layer between the top surface of the fin and the gate is thin, the channel may include the top surface of the fin in addition to the aforementioned front gate and rear gate. In this case, the gate of the fin field-effect transistor is a three-sided gate.

[0063] In a fin field-effect transistor, the channel length L g The length of the portion of the gate "sandwiched" between the source and drain along the source / drain distribution direction. This is due to the channel length L. g The saturation leakage current I of the field-effect transistor is determined dsat That is, the channel length L g The smaller the value, the shorter the carrier migration path, and the lower the saturation leakage current I. dsat The larger the current, the lower the saturation leakage current I of the fin field-effect transistor compared to a two-dimensional planar field-effect transistor. dsat Larger. For fin field-effect transistors with double-sided gates, the effective channel width W eff Fin height H fin Twice that, that is, W eff = 2 H fin For a fin field-effect transistor with three gate sides, the effective channel width W eff Fin height H fin Twice the width of the fin W fin The sum of, i.e., W eff =W fin +2 H fin Furthermore, researchers found through experiments that the suppression effect of drain-induced barrier lowing (DIBL) depends on the channel length Lg and the effective channel width W. eff The ratio of the channel length Lg to the effective channel width W eff Only when the ratio is greater than 1.5 can the leakage-induced barrier reduction effect be effectively suppressed.

[0064] In fin field-effect transistors, the dimension limited by the resolution of the photolithography process is the fin width W. fin To increase the saturation leakage current I of the field-effect transistor. dsat To improve the short-channel effect, researchers increased the number of fins in fin field-effect transistors to increase the effective channel width W. eff In a fin field-effect transistor with multiple fins, the distance between adjacent fins is the fin spacing P. finfin spacing P fin The value can be determined based on the requirement to suppress parasitic capacitance between fins.

[0065] As semiconductor process nodes shrink further to 7nm and below, channel length L g Further reduction, while the fin width W fin It is difficult to reduce the size accordingly to maintain the channel length L g With effective channel width W eff The ratio remains within the range that suppresses the drain-induced barrier reduction effect. Furthermore, compared to the fin field-effect transistor manufacturing process at the 14nm process node, the process complexity of fin field-effect transistor manufacturing processes at 7nm and below process nodes increases significantly. Therefore, to further increase the effective channel width W... eff To improve the control of the transistor gate over the channel, suppress the short-channel effect, reduce leakage current, reduce transistor power consumption, and improve transistor performance, researchers are trying to further increase the area of ​​the fin surrounded by the gate. That is, they are improving the double-sided or triple-sided gate of the fin field-effect transistor to a fully surrounding gate, so that the entire surface of the channel is surrounded by the gate.

[0066] In related technologies, the all-around gate structure is mainly fabricated using a nanosheet stacking process. The specific process includes: first, forming a multi-period stack by alternately depositing silicon and sacrificial materials (such as silicon-germanium). Then, selective etching is used to remove the sacrificial material, releasing individual suspended nanosheets. Next, a support material is filled into the gaps between the suspended nanosheets using a bonding process. Finally, gate material is deposited around the nanosheets, achieving a complete gate-to-channel surround.

[0067] However, the nanosheet stacking process requires multiple atomic layer deposition (ALD), sacrificial layer removal, and high-temperature annealing processes, resulting in high process complexity and cost. Among these, the selective etching process to remove the sacrificial material and release the suspended nanosheets is particularly challenging and yields low production rates. Furthermore, in the all-around gate structure fabricated using the nanosheet stacking process, the effective channel width W... eff The range of nanosheet stacking layers is limited to integer multiples, resulting in insufficient design flexibility for the above-mentioned all-around gate structure, making it difficult to meet the design requirements of the all-around gate structure.

[0068] Therefore, it is necessary to provide a method for manufacturing a semiconductor structure that allows the effective channel width of the all-around gate structure to be continuously varied.

[0069] Please see Figure 7 One embodiment of this application provides a method for manufacturing a semiconductor structure. The method may include steps S110, S130, S150, and S170.

[0070] S110: Provides a substrate.

[0071] In this embodiment, the substrate may include a substrate with a gate trench and a bottom gate portion. Specifically, the gate trench may have a bottom surface and side surfaces. The bottom gate portion may be formed in a region within the gate trench near the bottom surface, and a portion of the side surfaces of the gate trench may be exposed.

[0072] Please see Figure 8 In order to prepare a substrate including a substrate with a gate trench and a bottom gate portion, in this embodiment, the step of providing the substrate may include sub-steps S111, S112, S113, S114 and S115.

[0073] S111: Provides a transition substrate.

[0074] Please see Figure 9 In this embodiment, the transition substrate 100 may include a transition substrate 110 and a first photolithographic functional layer 120 formed on the surface of the transition substrate 110.

[0075] In this embodiment, the transition substrate 110 can serve as the basis for forming the semiconductor structure. Specifically, the transition substrate 110 can be constructed from semiconductor materials, insulating materials, conductive materials, or any combination thereof. For example, the transition substrate 110 can be made of materials such as silicon (Si), silicon-germanium (SiGe), silicon-germanium-carbon (SiGeC), or silicon carbide (SiC). The transition substrate 110 can be a single-layer structure or a multi-layer structure. In this embodiment, considering factors such as dielectric loss requirements, manufacturing process, manufacturing cost, and the convenience of subsequent lateral epitaxial processes, the transition substrate 110 can be a single-crystal silicon wafer.

[0076] In this embodiment, the first photolithography functional layer 120 can be used as a mask in the process of forming the gate trench. Specifically, the first photolithography functional layer 120 may include an oxide layer 121, a first nitride layer 122, and a first photoresist layer 123. The oxide layer 121 and the first nitride layer 122 can serve as hard masks in the photolithography process. The material of the oxide layer 121 can be silicon dioxide (SiO2), and the material of the first nitride layer 122 can be silicon nitride (SiN). To save process costs and simplify the process, in this embodiment, the process of forming the gate trench can share a photolithography mask with the process of manufacturing the polysilicon gate of a two-dimensional planar field-effect transistor in related technologies. Correspondingly, the first photoresist layer 123 can be a photolithographic pattern retained after exposure and development based on the shared photolithography mask, and the material of the first photoresist layer 123 can be a negative photoresist. To improve the manufacturing precision of the all-around gate, in some embodiments, a dedicated photomask can be designed and manufactured to form the gate trench 112. Correspondingly, the first photoresist layer 123 can be a photolithographic pattern retained after exposure and development based on the dedicated photomask. The material of the first photoresist layer 123 can be positive photoresist or negative photoresist.

[0077] S112: The transition substrate is etched based on the first photolithography functional layer to obtain a substrate with gate trenches.

[0078] To simplify the process of forming the all-around gate structure, a bottom gate portion surrounding the bottom surface of the channel active structure can be formed before forming the channel active structure. To provide space for forming the bottom gate portion, a gate trench for accommodating the bottom gate portion can be formed within the transition substrate.

[0079] Please refer to the following: Figure 9 and Figure 10 In this embodiment, the first nitride layer 122, oxide layer 121, and transition substrate 110 can be sequentially etched using a dry etching process based on the first photoresist layer 123. To ensure that the dimensions of the subsequently formed all-around gate meet the design requirements, the etching depth during the etching of the transition substrate 110 is not less than the sum of the subsequent ion implantation depth, the designed thickness of the all-around gate, and the designed thickness of the gate oxide layer. After etching the transition substrate 110 to form the gate trench 112, the first photoresist layer 123 can be removed using an asher process, followed by a wet cleaning process (WET) to remove the polymer remaining from the dry etching process, retaining the remaining etched portions 121a of the oxide layer and 122a of the first nitride layer, resulting in a substrate 111 with the gate trench 112 and the bottom and sides of the gate trench 112 exposed.

[0080] S113: Perform surface oxidation on the substrate to form an isolation layer on the bottom and side surfaces of the gate trench.

[0081] Please refer to the following: Figures 9 to 11 To repair the damage to the substrate 111 material caused during the dry etching process of forming the gate trench 112, and also to form an isolation layer between the bottom gate portion and the substrate 111, in this embodiment, the exposed bottom and side surfaces of the gate trench 112 can be oxidized using a furnace tube process or an in-situ steam generation (ISSG) method in a rapid thermal processing (RTP) process to form an isolation layer 130 for isolating the bottom gate portion and the substrate 111. Specifically, the material of the isolation layer 130 can be silicon dioxide. During the formation of the isolation layer 130, the ratio of the thickness of the substrate 111 material consumed to the thickness of the isolation layer 130 material generated along the growth direction of the isolation layer 130 typically falls within the range of 2:5 to 1:2. Taking the substrate 111 material as monocrystalline silicon and the isolation layer 130 material as silicon dioxide as an example, the thickness of monocrystalline silicon consumed for every 1 nm of silicon dioxide thickness generated falls between 0.4 nm and 0.5 nm. Since the etching of the gate trench 112 uses the etching opening of the oxide layer 121 as a mask, and the etching opening of the oxide layer 121 uses the etching opening of the first nitride layer 122 as a mask, the etching openings of the first nitride layer 122, the etching openings of the oxide layer 121, and the openings of the gate trench 112 along the etching opening direction are substantially the same size. The side surfaces of the etching openings of the first nitride layer 122 and the oxide layer 121 are coplanar with the side surfaces of the gate trench 112. Furthermore, the isolation layer 130 formed on the side surface of the gate trench 112 protrudes from this common plane. In this embodiment, since the portion of the isolation layer 130 formed on the side surface of the gate trench 112 will be removed in subsequent processes, its impact on subsequent processes is minimal. Therefore, the isolation layer 130 is not processed after its formation.

[0082] In some embodiments, in order to reduce the impact of the isolation layer 130 protruding from the common plane on subsequent processes, wet cleaning or other process steps can be added to remove part of the isolation layer 130 formed on the side of the gate trench 112.

[0083] S114: Deposit gate material on the side of the isolation layer away from the substrate within the gate trench to form a gate material deposition section.

[0084] To improve the design flexibility of gate thickness, the trench extension direction of the gate trench can be used as the thickness direction. First, the gate material is deposited in the gate trench, and then part of the gate material is removed so that the thickness of the bottom gate portion along the thickness direction meets the design requirements.

[0085] Please see Figure 12In this embodiment, the gate material can be polysilicon. Accordingly, the gate material can be deposited in the gate trench using a furnace tube process. The surface of the deposited gate material away from the substrate 111 can extend beyond the etch residue 122a of the first nitride layer away from the surface of the substrate 111. Subsequently, the deposited gate material is planarized using a chemical mechanical polishing (CMP) process. The polishing is stopped at the surface of the etch residue 122a of the first nitride layer away from the substrate 111 using an endpoint detection (EPD) method, resulting in the gate material deposition portion 140.

[0086] In some embodiments, the gate material can be a metal, such as tungsten (W), copper (Cu), aluminum (Al), etc. Accordingly, the gate material can be deposited in the gate trench using a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process, and then the deposited gate material can be planarized to obtain the gate material deposition portion 140.

[0087] S115: Etch the gate material deposition area to form the bottom gate area.

[0088] To achieve full-around gate isolation from the channel active structure, in this embodiment, the substrate may further include a transition bottom gate oxide layer formed on the surface of the bottom gate portion away from the substrate. Specifically, the transition bottom gate oxide layer can serve as the basis for the subsequent formation of a bottom gate oxide layer used to isolate the bottom gate portion and the channel active structure.

[0089] Please refer to the following: Figures 12 to 14 In this embodiment, when the gate material is polysilicon, the step of etching the gate material deposition portion to form the bottom gate portion may include: etching the gate material deposition portion 140 to form the transition gate portion 141; performing surface oxidation on the transition gate portion 141 to form a first transition oxide layer 150 on the surface of the transition gate portion 141 away from the substrate 111; and using the unoxidized portion of the transition gate portion 141 as the bottom gate portion 142.

[0090] Since the gate material is polycrystalline silicon, an oxide layer can be directly formed by oxidizing the surface of the polycrystalline silicon. Therefore, in order to ensure that the thickness of the polycrystalline silicon layer remaining after surface oxidation meets the design thickness requirements of the all-around gate, in this embodiment, a dry etching process can be used to remove part of the gate material deposition area to obtain the transition gate portion 141. Specifically, the thickness direction is taken as the extension direction of the gate trench, and the thickness of the transition gate portion 141 along the thickness direction is greater than the specified gate thickness. Specifically, the specified gate thickness can be the design thickness of the portion of the gate surrounding any side of the active structure of the channel in the all-around gate, and this design thickness can be determined according to the semiconductor manufacturing process node. For example, for the 7nm process node, the thickness of the transition gate portion 141 along the thickness direction can be 500Å to 800Å. For 5nm and below process nodes, the thickness of the transition gate portion 141 along the thickness direction can be 200Å to 500Å.

[0091] To simplify the gate oxide formation process and to repair damage to the gate material during dry etching to form the transition gate portion 141, in this embodiment, a rapid thermal processing method can be used to re-oxidize the transition gate portion 141, forming a first transition oxide layer 150 on the surface of the transition gate portion 141 away from the substrate 111, with the unoxidized portion serving as the bottom gate portion 142. The extension direction of the gate trench is still taken as the thickness direction, and the thickness of the bottom gate portion 142 along the thickness direction is equal to the specified gate thickness. Specifically, since the portion of the isolation layer 130 formed on the side of the gate trench will be removed in subsequent processes, and the isolation layer 130 is made of the same material as the first transition oxide layer 150, to ensure that the thickness of the subsequently formed transition bottom gate oxide layer along the thickness direction meets the design thickness requirements of the gate oxide layer, the extension direction of the gate trench is taken as the first thickness direction, and the opening direction of the gate trench is taken as the second thickness direction. The thickness of the first transition oxide layer 150 along the first thickness direction is not less than the sum of the thickness of the isolation layer 130 formed on the side of the gate trench along the second thickness direction and the design thickness of the gate oxide layer.

[0092] To simplify the process complexity of forming a channel active structure that is completely surrounded by the gate, a portion of the sidewalls of the gate trench can be exposed. Then, a trench filling portion can be formed based on the exposed sidewalls of the gate trench using a lateral epitaxial process, providing a foundation for the subsequent formation of the channel active structure.

[0093] In this embodiment, when the gate material is polysilicon, the semiconductor structure manufacturing method may further include, corresponding to the step of etching the gate material deposition portion to form the bottom gate portion, the step of etching the gate material deposition portion to form the bottom gate portion:

[0094] S120: Remove part of the first transition oxide layer and part of the isolation layer formed on the side of the gate trench to obtain the transition bottom gate oxide layer, and expose part of the side of the gate trench.

[0095] Please see Figure 15 To minimize damage to the substrate 111 and the bottom gate portion 142 during the removal of a portion of the isolation layer formed on the sidewall of the gate trench, in this embodiment, a wet etching process can be used to remove a portion of the isolation layer formed on the sidewall of the gate trench near the gate trench opening, obtaining the first etched residue 131 of the isolation layer. In the same process step, a portion of the first transition oxide layer is removed, and the portion of the first transition oxide layer remaining after wet etching is used as the transition bottom gate oxide layer 151. Using the trench extension direction of the gate trench as the thickness direction, the thickness of the transition bottom gate oxide layer 151 along the thickness direction can be equal to the designed thickness of the gate oxide layer. The etching solution can be diluted hydrofluoric acid (DHF).

[0096] Please refer to the following: Figure 12 and Figure 16 In some embodiments, when the gate material is metal, the step of etching the gate material deposition portion to form the bottom gate portion may include: etching the gate material deposition portion 140 to form the bottom gate portion 142.

[0097] Since the gate material is metal, the oxide layer needs to be formed on the surface of the gate material through a deposition process. Therefore, the bottom gate portion 142 can be directly obtained by etching the gate material deposition portion 140. In some embodiments, a dry etching process can be used to remove part of the gate material deposition portion 140 to form the bottom gate portion 142. Here, with the extension direction of the gate trench as the thickness direction, the thickness of the bottom gate portion 142 along the thickness direction is equal to a specified gate thickness, which can be the designed thickness of the portion of the gate surrounding any side of the channel active structure in the full-surround gate.

[0098] Similarly, in some embodiments, when the gate material is metal, the method for manufacturing a semiconductor structure may further include, corresponding to the step of etching the gate material deposition portion to form the bottom gate portion:

[0099] S121: An oxide is formed on the surface of the bottom gate portion to obtain a transition bottom gate oxide layer.

[0100] S122: Remove part of the isolation layer formed on the side of the gate trench, so that part of the side of the gate trench is exposed.

[0101] Please refer to the following: Figure 17 and Figure 18To achieve isolation between the channel active structure and the bottom gate portion 142, in some embodiments, a transition bottom gate oxide layer 151 can be formed on the surface of the bottom gate portion 142 away from the substrate 111 using a deposition process. Specifically, the transition bottom gate oxide layer 151 can be an interface oxide layer made of silicon dioxide. In this case, the transition bottom gate oxide layer 151 can be formed using chemical vapor deposition or physical vapor deposition processes.

[0102] To reduce leakage current and optimize device performance, in some embodiments, the transition bottom gate oxide layer 151 can be a high-k layer made of materials such as hafnium dioxide (HfO2), hafnium silicon oxynitride (HfSiON), or aluminum oxide (Al2O3), or it can be a composite layer formed by combining an interface oxide layer and a high-k layer (not shown in the figure). When the transition bottom gate oxide layer 151 is a high-k layer, it can be formed using atomic layer deposition (ALD). When the transition bottom gate oxide layer 151 is a composite layer, a high-k layer can first be formed on the surface of the bottom gate portion 142 away from the substrate 111 using atomic layer deposition, and then an interface oxide layer can be formed on the surface of the high-k layer away from the substrate 111 using chemical vapor deposition or physical vapor deposition. Taking the trench extension direction of the gate trench as the thickness direction, the thickness of the transition bottom gate oxide layer 151 along the thickness direction can be equal to the designed thickness of the gate oxide layer.

[0103] After the transition bottom gate oxide layer 151 is formed, a wet etching process can be used to remove the portion of the isolation layer near the gate trench opening formed on the side of the gate trench, obtaining the first etched remainder 131 of the isolation layer. Specifically, the etching solution can be diluted hydrofluoric acid.

[0104] S130: Using a lateral epitaxial process, a trench filling portion is formed based on the exposed side of the gate trench.

[0105] Please see Figure 19 After the bottom gate portion 142 is formed, a single-crystal silicon lateral epitaxial process can be performed on the exposed side of the gate trench to regenerate the portion of substrate material that was etched away to form the gate trench.

[0106] Since the material formed by the lateral epitaxial process grows gradually from the side of the gate trench towards the center of the gate trench, in order to improve the mechanical strength and reliability of the subsequent channel active structure, in this embodiment, the width direction of the trench filling portion 210 is equal to the width direction of the bottom gate portion 142, taking the material growth direction of the lateral epitaxial process as the width direction. Specifically, the material of the trench filling portion 210 can be single-crystal silicon or lightly doped silicon.

[0107] Please refer to the following: Figure 19 and Figure 20 To minimize interference from the remaining etching portions 121a of the oxide layer and 122a of the first nitride layer to subsequent processes, a wet etching process can be used to remove these portions after the trench filling portion 210 is formed. Specifically, the etching solution used to remove the remaining etching portions 121a of the oxide layer can be diluted hydrofluoric acid, and the etching solution used to remove the remaining etching portions 122a of the first nitride layer can be phosphoric acid (H3PO4).

[0108] S150: Active channel structure formed based on groove filling section.

[0109] Please see Figure 21 To simplify the process complexity of forming the channel active structure, the step of forming the channel active structure based on the trench filling part may include sub-steps S151, S152 and S153.

[0110] S151: Ion implantation is performed on the trench filling section to form a transitional active structure.

[0111] Please refer to the following: Figure 20 and Figure 22 To provide charge carriers in the channel active structure, in this embodiment, ion implantation can be performed on the trench filling portion 210, thereby transforming the trench filling portion 210, which is made of single-crystal silicon or lightly doped silicon, into a transition active structure 211 containing a certain concentration of charge carriers. Taking the material growth direction of the lateral epitaxial process as the width direction, the width of the trench filling portion 210 along the width direction is equal to the width of the transition active structure 211 along the width direction.

[0112] S152: A second photolithographic functional layer is formed on the surface of the transition active structure away from the bottom gate portion and on a portion of the substrate surface.

[0113] Please refer to the following: Figure 23 and Figure 24 To form a fully encircling gate structure, with the material growth direction of the lateral epitaxial process as the width direction, the width of the channel active structure along the width direction needs to be less than the width of the bottom gate portion 142 along the width direction. The width of the bottom gate portion 142 along the width direction is equal to the width of the trench filling portion along the width direction, and also equal to the width of the transition active structure 211 along the width direction. Therefore, the second photolithography functional layer 220 can be used as a mask to etch and remove part of the transition active structure 211, so that the width of the trench filling portion along the width direction is greater than the width of the channel active structure along the width direction.

[0114] In this embodiment, the second photolithography functional layer 220 may include an oxide isolation layer 221, a second nitride layer 222, and a second photoresist layer 223. The oxide isolation layer 221 and the second nitride layer 222 can serve as hard masks during the photolithography process. When the gate material is polysilicon, the oxide isolation layer 221 can be formed by surface oxidation of the transition active structure 211 and the substrate 111 using an in-situ vapor generation method. To reduce the negative impact of subsequent processes on the thickness of the gate oxide layer and to ensure uniform thickness of the subsequently formed gate oxide layer, the thickness of the oxide isolation layer 221 along the thickness direction, with the normal direction of the substrate as the thickness direction, is not less than twice the designed thickness of the gate oxide layer. The material of the oxide isolation layer 221 can be silicon dioxide. When the gate material is metal, to improve device performance, a high-dielectric material can be deposited on the surface of the substrate 111 using an atomic layer deposition process to form the oxide isolation layer 221. The material of the second nitride layer 222 can be silicon nitride. The second photoresist layer 223 can be a photolithographic pattern retained after exposure and development of a photolithographic mask corresponding to the channel active structure, and the material of the second photoresist layer 223 can be a positive photoresist.

[0115] In this embodiment, after the oxide isolation layer 221 is formed, a second nitride layer 222 and a positive photoresist can be deposited on the surface of the oxide isolation layer 221 away from the substrate 111. The positive photoresist is exposed and developed based on the photomask corresponding to the channel active structure to form a second photoresist layer 223, thereby obtaining a second photolithography functional layer 220.

[0116] S153: Based on the second photolithography functional layer, the transition active structure and the substrate are etched to obtain the semiconductor substrate and the channel active structure protruding from the surface of the semiconductor substrate.

[0117] Please refer to the following: Figure 23 and Figure 25 In this embodiment, when the gate material is polysilicon, the second nitride layer 222, the oxide isolation layer 221, the transition active structure 211, and the substrate 111 can be sequentially etched using a dry etching process based on the second photoresist layer 223 to form the pre-channel structure 230 and the semiconductor substrate 113. Subsequently, the second photoresist layer 223 can be removed, and then a wet cleaning process can be used to remove the polymer remaining from the dry etching process, retaining the remaining portion of the oxide isolation layer and the second nitride layer.

[0118] Please refer to the following: Figure 24 and Figure 26In some embodiments, when the gate material is metal, the second nitride layer 222, the oxide isolation layer 221, the transition active structure 211, and the substrate 111 can be sequentially etched using a dry etching process based on the second photoresist layer 223 to directly form the channel active structure 231 and the semiconductor substrate 113. Subsequently, the second photoresist layer 223 can be removed, and then a wet cleaning process can be used to remove the polymer remaining from the dry etching process, retaining the remaining portion of the oxide isolation layer and the second nitride layer.

[0119] In this embodiment, before forming the side portion covering the channel active structure and the top gate portion of the channel active structure away from the bottom gate portion, the method of manufacturing the semiconductor structure may further include:

[0120] S161: Forms a side oxide layer on the side of the active structure covering the channel.

[0121] To achieve isolation between the channel active structure and the all-around gate, and to improve the control capability of the all-around gate over the channel, a gate oxide layer of uniform thickness needs to be formed on each surface of the channel active structure before the all-around gate is formed.

[0122] Please refer to the following: Figure 25 and Figure 27 When the gate material is polycrystalline silicon, since the material of the pre-channel structure 230 is doped silicon, to simplify the process complexity of forming the gate oxide layer, an in-situ vapor generation method can be used to directly oxidize the exposed surface of the pre-channel structure, forming the channel active structure 231 and the side oxide layer 240 covering the sides of the trench active structure. The side oxide layer 240 can be combined with the remaining oxide isolation layer etched in subsequent process steps to jointly form the gate oxide layer surrounding the channel active structure. Correspondingly, since the semiconductor substrate 113 also has a partially exposed surface after the formation of the pre-channel structure 230, this part of the surface is oxidized together with the exposed surface of the pre-channel structure 230 during the surface oxidation process to form the transition interface oxide layer 241.

[0123] Please refer to the following: Figure 26 and Figure 28 When the gate material is metal, the gate oxide layer can be formed of a high-dielectric material. Accordingly, based on a deposition mask, a high-dielectric material can be deposited on the side of the channel active structure 231 to form a side oxide layer 240 covering the side of the channel active structure 231.

[0124] Please refer to the following: Figure 29 and Figure 30To form a gate oxide layer of uniform thickness, after the side oxide layer 240 is formed, a wet etching process can be used to remove the remaining portion of the second nitride layer to reduce its interference with subsequent etching processes. Specifically, the etching solution can be phosphoric acid. S162: A self-aligned etching process is used to remove at least a portion of the transition bottom gate oxide layer to obtain the gate oxide layer, thereby exposing a portion of the semiconductor substrate and a portion of the bottom gate portion.

[0125] Please refer to the following: Figure 29 and Figure 31 In this embodiment, when the gate material is polysilicon, only the oxide layer surrounding each surface of the channel active structure 231 can be retained. A self-aligned etching process is used to remove the transition interface oxide layer 241, a portion of the transition bottom gate oxide layer 151 covering a portion of the bottom gate portion 142, and a portion of the isolation layer formed on the side of the gate trench and located between the transition interface oxide layer 241 and the transition bottom gate oxide layer 151, resulting in a second etch residue 132 of the isolation layer and an etch residue 152 of the transition bottom gate oxide layer. Furthermore, during the self-aligned etching process to remove the above portions, some of the oxide isolation layer material is also removed, resulting in a gate oxide layer 242 with uniform thickness formed by the side oxide layer 240, the etch residue 152 of the transition bottom gate oxide layer, and the etch residue 221a of the oxide isolation layer. That is, in the gate oxide layer 242, the portions covering different surfaces of the channel active structure 231 have equal thickness.

[0126] Please refer to the following: Figure 30 and Figure 32 In some embodiments, when the gate material is metal, a self-aligned etching process can be used to remove a portion of the transition bottom gate oxide layer 151 covering a portion of the surface of the bottom gate portion 142, a portion of the isolation layer located between the semiconductor substrate 113 and the transition bottom gate oxide layer 151, and a portion of the semiconductor substrate 113, to obtain a second etch residue 132 of the isolation layer and an etch residue 152 of the transition bottom gate oxide layer, such that the side oxide layer 240, the etch residue 152 of the transition bottom gate oxide layer, and the oxide isolation layer 221 constitute a gate oxide layer 242 of uniform thickness, that is, in the gate oxide layer 242, the portions covering different surfaces of the channel active structure 231 have equal thickness.

[0127] S170: A semiconductor structure is obtained by forming a top gate portion covering the side surface of the active channel structure and the surface of the active channel structure away from the bottom gate portion.

[0128] Please see Figure 33 To simplify the process complexity of forming a fully surrounding gate structure, the step of forming the top gate portion may include sub-steps S171, S172, and S173.

[0129] S171: Deposit gate material on the surface of the semiconductor substrate and the surface of the gate oxide layer to obtain a gate material layer.

[0130] Since the semiconductor substrate and the bottom gate portion are partially exposed after the self-aligned etching process removes at least part of the transition bottom gate oxide layer, gate material can be directly deposited on the surface of the semiconductor substrate and the gate oxide layer, so that the deposited gate material is connected to the bottom gate portion.

[0131] Please see Figure 34 In this embodiment, a gate material identical to that of the bottom gate portion 142 can be deposited on the surface of the semiconductor substrate 113 and the gate oxide layer using chemical vapor deposition or physical vapor deposition processes. Then, chemical mechanical polishing is used to remove some of the deposited gate material, making the surface of the gate material layer 250 away from the semiconductor substrate 113 flat. To ensure that the thickness of the top gate portion meets the design thickness requirements for a fully encircling gate, the distance between the surface of the gate material layer 250 away from the semiconductor substrate 113 and the semiconductor substrate 113 is greater than the distance between the surface of the gate oxide layer away from the semiconductor substrate 113 and the semiconductor substrate 113, and the difference between the two distances is not less than the design thickness for a fully encircling gate.

[0132] S172: A third photolithographic functional layer is formed on the side of the gate material layer away from the semiconductor substrate.

[0133] In this embodiment, the third photolithography functional layer 260 may include an oxide mask layer 261, a hard mask layer 262, an oxide dielectric layer 263, an anti-reflection coating (ARC) 264, a bottom anti-reflection coating (BARC) 265, and a third photoresist layer 266. The oxide mask layer 261 and the hard mask layer 262 can serve as hard masks in the photolithography process. The oxide mask layer 261 can be made of silicon dioxide, and the hard mask layer 262 can be made of silicon nitride. The oxide dielectric layer 263 can be used to isolate the hard mask layer 262 and the anti-reflection coating 264; the oxide dielectric layer 263 can also be made of silicon dioxide. The anti-reflection coating 264 and the bottom anti-reflection coating 265 can reduce reflection from the photoresist surface and improve photolithography resolution. The anti-reflective coating 264 can be made of silicon oxynitride (SiON) and silicon dioxide, and the bottom anti-reflective coating 265 can be made of organic photopolymer, silicon nitride, or silicon oxynitride. The third photoresist layer 266 can be a photolithographic pattern retained after exposure and development of a photomask corresponding to the all-around gate structure, and the material of the third photoresist layer 266 can be positive photoresist.

[0134] In this embodiment, an oxide mask layer 261, a hard mask layer 262, an oxide dielectric layer 263, an anti-reflection coating 264, a bottom anti-reflection coating 265, and a positive photoresist can be sequentially deposited on the surface of the gate material layer 250 away from the semiconductor substrate 113 using chemical vapor deposition or physical vapor deposition processes. The deposited positive photoresist is then exposed and developed based on the photolithography mask corresponding to the all-around gate structure to form a third photoresist layer 266, resulting in a third photolithography functional layer 260.

[0135] S173: The gate material layer is etched based on the third photolithography functional layer to form the top gate portion.

[0136] Please refer to the following: Figure 34 and Figure 35 In this embodiment, based on the third photoresist layer 266, a dry etching process is used to sequentially etch the bottom anti-reflective coating 265, anti-reflective coating 264, oxide dielectric layer 263, hard mask layer 262, oxide mask layer 261, and gate material layer 250 to form a top gate portion 270 covering the side of the channel active structure 231 and the surface of the channel active structure 231 away from the bottom gate portion 142. After forming the top gate portion 270, the remaining etched portions of the third photoresist layer 266, the bottom anti-reflective coating, the anti-reflective coating, and the oxide dielectric layer can be removed sequentially. Then, a wet cleaning process is used to clean the remaining polymers from the dry etching process, retaining the remaining etched portions 261a of the oxide mask layer and 262a of the hard mask layer.

[0137] After the top gate portion 270 is formed, the bottom gate portion 142 and the top gate portion 270 form a full-around gate, which includes the entire surface of the channel active structure 231. At this time, the effective channel width W eff W is the sum of the lengths of the four sides of the channel active structure 231 that are completely surrounded by the gate. Since the side lengths of the channel active structure 231 can be continuously varied by controlling the mask parameters and etching parameters, the effective channel width W... eff It can also be continuously varied based on its relationship with the side length of the active channel structure 231, thereby expanding the effective channel width W. eff The range of variation. Furthermore, as future semiconductor process nodes shrink further, the all-around gate, consisting of the bottom gate portion 142 and the top gate portion 270, can also achieve performance improvements in smaller sizes by stacking multiple layers.

[0138] To improve the isolation between the all-around gate and other semiconductor components, and to enhance the overall performance of the semiconductor device, in some embodiments, the semiconductor structure may further include isolation structures formed on the surface of the semiconductor substrate and the gate side. Correspondingly, before removing the etching residue of the hard mask layer, the method for manufacturing the semiconductor structure may further include:

[0139] S181: Deposit an isolation material on the surface of a semiconductor substrate to obtain an isolation material layer.

[0140] Please see Figure 36 In this embodiment, an isolation material can be deposited on the surface of the semiconductor substrate 113 using a chemical vapor deposition process to obtain an isolation material layer 280. Specifically, the isolation material can be tetraethoxysilane (TEOS). To improve the isolation effect of the subsequent isolation structure, the distance between the surface of the isolation material layer 280 away from the semiconductor substrate 113 and the semiconductor substrate 113 can be greater than the distance between the surface of the etched remaining portion 262a of the hard mask layer away from the semiconductor substrate 113 and the semiconductor substrate 113.

[0141] S182: The isolation material layer is planarized using a chemical mechanical polishing process, with the surface of the hard mask layer far from the semiconductor substrate as the polishing endpoint.

[0142] After the isolation material layer 280 is formed, it can be planarized using a chemical mechanical polishing process. Polishing can be stopped when the etch residue 262a of the hard mask layer is away from the surface of the semiconductor substrate. After planarization, high-temperature annealing can be performed to make the planarized isolation material layer denser.

[0143] S183: The remaining part of the hard mask layer and part of the isolation material are removed by wet etching process to form an isolation structure.

[0144] Due to the limitations of chemical mechanical polishing (CMP) processes, the planarized isolation material layer may have discing defects. To reduce the impact of these defects on subsequent processes, some isolation material can be removed during the wet etching process to remove the remaining hard mask layer, thereby improving the flatness of the surface of the formed isolation structure away from the semiconductor substrate.

[0145] Please refer to the following: Figure 36 and Figure 37In this embodiment, a wet etching process can be used to remove the remaining etched portion 262a of the hard mask layer, the remaining etched portion 261a of the oxide mask layer, and part of the isolation material to obtain the isolation structure 281. Specifically, the etching solution for removing the remaining etched portion 261a of the oxide mask layer and part of the isolation material can be a diluted hydrofluoric acid solution, and the etching solution for removing the remaining etched portion 262a of the hard mask layer can be phosphoric acid.

[0146] Please refer to the following: Figure 35 and Figure 37 Another embodiment of this application provides a semiconductor structure that can be manufactured by the semiconductor structure manufacturing method described in the above embodiments.

[0147] For other technical effects of the semiconductor structure described in the above embodiments, please refer to other embodiments of this application for comparison and explanation, and they will not be repeated here.

[0148] In the semiconductor structure manufacturing method and semiconductor structure provided in this application embodiment, by providing a substrate including a substrate with a gate trench and a bottom gate portion, wherein a portion of the sidewalls of the gate trench are exposed, a trench filling portion is formed based on the exposed sidewalls of the gate trench using a lateral epitaxial process, such that the width of the trench filling portion along the material growth direction of the lateral epitaxial process is consistent with the width of the bottom gate portion, and then a channel active structure with a width smaller than the width of the trench filling portion is formed based on the trench filling portion, and a top gate portion is formed covering the sidewalls of the channel active structure and the surface away from the bottom gate portion, the bottom gate portion and the top gate portion together form a fully surrounding gate, achieving unexpected effects including... This involves using a lateral epitaxial process to form a trench filling portion whose width matches the width of the bottom gate portion, and then forming a channel active structure based on the trench filling portion. This achieves partial compatibility between the manufacturing process of the all-around gate structure and the manufacturing process of two-dimensional planar field-effect transistors in related technologies, simplifies the manufacturing process of the all-around gate structure, reduces the manufacturing cost of the all-around gate structure, and allows the width of the trench active structure to continuously vary within a range not exceeding the width of the bottom gate portion. This, in turn, allows the effective channel width to continuously vary, expands the range of variation of the effective channel width of the all-around gate structure, and improves the design flexibility of the all-around gate structure.

[0149] It is understood that the specific examples in this application are only intended to help those skilled in the art better understand the embodiments of this application, and are not intended to limit the scope of this application.

[0150] It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this application in any way.

[0151] It is understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited in this respect.

[0152] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0153] As should be understood from the several embodiments provided in this application, the disclosed semiconductor structure can be implemented in other ways. For example, the embodiments of the semiconductor structure described above are merely illustrative.

[0154] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, The method for manufacturing the semiconductor structure includes: A substrate is provided; the substrate includes a substrate having a gate trench and a bottom gate portion; wherein the gate trench has a bottom surface and a side surface; the bottom gate portion is formed in a region of the gate trench near the bottom surface; a portion of the side surface of the gate trench is exposed; Using a lateral epitaxial process, a trench filling portion is formed based on the exposed side surface of the gate trench; wherein, with the material growth direction of the lateral epitaxial process as the width direction, the width of the trench filling portion along the width direction matches the width of the bottom gate portion along the width direction. Ion implantation is performed on the trench filling portion to form a transitional active structure; The transition active structure is etched to form a channel active structure protruding from the surface of the semiconductor substrate; wherein the width of the channel active structure along the width direction is smaller than the width of the trench filling portion along the width direction and is determined based on the width of the bottom gate portion along the width direction and the portion of the transition active structure that is etched away, so that the width of the channel active structure can continuously vary within a range not greater than the width of the bottom gate portion; A semiconductor structure is obtained by forming a top gate portion that covers the side surface of the channel active structure and the surface of the channel active structure away from the bottom gate portion; in the semiconductor structure, a gate composed of the bottom gate portion and the top gate portion surrounds the channel active structure.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The steps for providing the substrate include: A transition substrate is provided; the transition substrate includes a transition substrate and a first photolithographic functional layer formed on the surface of the transition substrate; The transition substrate is etched based on the first photolithography functional layer to obtain the substrate with gate trenches; wherein the bottom and side surfaces of the gate trenches are exposed. The substrate is surface oxidized to form an isolation layer on the bottom and side surfaces of the gate trench; In the gate trench, gate material is deposited on the side of the isolation layer away from the substrate to form a gate material deposition area; The gate material deposition portion is etched to form the bottom gate portion.

3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, The substrate further includes: a transition bottom gate oxide layer formed on the surface of the bottom gate portion away from the substrate; and, when the gate material is polysilicon, the step of etching the gate material deposition portion to form the bottom gate portion includes: The gate material deposition portion is etched to form a transition gate portion; wherein, with the extension direction of the gate trench as the thickness direction, the thickness of the transition gate portion along the thickness direction is greater than a specified gate thickness; The transition gate portion is surface oxidized, and a first transition oxide layer is formed on the surface of the transition gate portion away from the substrate. The unoxidized portion of the transition gate portion is used as the bottom gate portion. The thickness of the bottom gate portion along the thickness direction is equal to a specified gate thickness. Accordingly, the method for manufacturing the semiconductor structure further includes: A portion of the first transition oxide layer and a portion of the isolation layer formed on the side of the gate trench are removed to obtain a transition bottom gate oxide layer, thereby exposing a portion of the side of the gate trench.

4. The method for manufacturing a semiconductor structure according to claim 3, characterized in that, When the gate material is metal, the step of etching the gate material deposition portion to form the bottom gate portion includes: The gate material deposition portion is etched to form a bottom gate portion; wherein the thickness of the bottom gate portion along the thickness direction is equal to a specified gate thickness; Accordingly, the method for manufacturing the semiconductor structure further includes: An oxide is formed on the surface of the bottom gate portion to obtain a transition bottom gate oxide layer; Remove a portion of the isolation layer formed on the side of the gate trench, thereby exposing a portion of the side of the gate trench.

5. The method for manufacturing a semiconductor structure according to claim 3 or 4, characterized in that, The step of etching the transition active structure to form a channel active structure protruding from the surface of the semiconductor substrate includes: A second photolithographic functional layer is formed on the surface of the transition active structure away from the bottom gate portion and on a portion of the surface of the substrate; Based on the second photolithography functional layer, the transition active structure and the substrate are etched to obtain a semiconductor substrate and a channel active structure protruding from the surface of the semiconductor substrate.

6. The method for manufacturing a semiconductor structure according to claim 5, characterized in that, The second photolithographic functional layer includes an oxide isolation layer; the method of manufacturing the semiconductor structure further includes, prior to forming a top gate portion covering the sidewalls of the channel active structure and the surface of the channel active structure away from the bottom gate portion: A side oxide layer is formed covering the sides of the active structure of the channel; A self-aligned etching process is used to remove at least a portion of the transition bottom gate oxide layer to obtain a gate oxide layer, thereby exposing a portion of the semiconductor substrate and a portion of the bottom gate portion; wherein the side oxide layer, the etch residue of the transition bottom gate oxide layer, and the etch residue of the oxide isolation layer constitute the gate oxide layer; in the gate oxide layer, the portions covering different surfaces of the channel active structure have equal thickness.

7. The method for manufacturing a semiconductor structure according to claim 6, characterized in that, The step of forming a top gate portion covering the side surface of the channel active structure and the surface of the channel active structure away from the bottom gate portion to obtain the semiconductor structure includes: A gate material is deposited on the surface of the semiconductor substrate and the surface of the gate oxide layer to obtain a gate material layer; A third photolithographic functional layer is formed on the side of the gate material layer away from the semiconductor substrate; The gate material layer is etched based on the third photolithography functional layer to form the top gate portion.

8. The method for manufacturing a semiconductor structure according to claim 7, characterized in that, The first photolithography functional layer includes a first photoresist layer, the material of which is negative photoresist; the second photolithography functional layer includes a second photoresist layer; the third photolithography functional layer includes a third photoresist layer; the materials of the second photoresist layer and the third photoresist layer are positive photoresist.

9. The method for manufacturing a semiconductor structure according to claim 7, characterized in that, The semiconductor structure further includes an isolation structure formed on the surface of the semiconductor substrate and the gate side of the top gate portion; the third photolithography functional layer includes a hard mask layer formed on the side of the top gate portion away from the bottom gate portion; after etching the gate material layer based on the third photolithography functional layer to form the top gate portion, the etching residue of the hard mask layer located on the side of the top gate portion away from the bottom gate portion is retained. The method for manufacturing the semiconductor structure further includes, before removing the etch residue of the hard mask layer: An isolation material is deposited on the surface of the semiconductor substrate to obtain an isolation material layer; The isolation material layer is planarized using a chemical mechanical polishing process, with the remaining etched portion of the hard mask layer away from the semiconductor substrate as the polishing endpoint; The remaining portion of the hard mask layer and part of the isolation material are removed using a wet etching process to form the isolation structure.

10. A semiconductor structure, characterized in that, The semiconductor structure is manufactured by the semiconductor structure manufacturing method as described in any one of claims 1 to 9.

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