Silicon carbide power device improving bv and ron and manufacturing method thereof, chip

Abstract

This application belongs to the field of power device technology and provides a silicon carbide power device with improved BV and Ron, as well as its fabrication method and chip. By setting a first P-type well region in the top epitaxial region, a heavily doped P-type region is formed on the first P-type well region, and adjacent second P-type well regions are isolated by the top epitaxial region. At least the second P-type well regions are symmetrically arranged with heavily doped P-type regions, and the depth of the second P-type well region is less than the depth of the first P-type well region. This allows the JFET region inside the device to have a higher doping concentration of donor doping. While ensuring the ideal BVDSS of the device, the on-resistance can be effectively reduced and the current density of the device can be increased.

Description

Technical Field

[0001] This application belongs to the field of power device technology, and in particular relates to a silicon carbide power device with improved BV and Ron, its fabrication method, and chip. Background Technology

[0002] Silicon carbide (SiC), as a new generation of wide bandgap semiconductor material, is widely used in electric vehicles, charging piles, and data electronics due to its advantages such as wide bandgap, high critical breakdown electric field, and high saturation drift velocity. Compared with traditional silicon-based metal-oxide-semiconductor (MOS) devices, SiC MOSFETs have better electrical performance, such as lower on-resistance, higher breakdown voltage, and better thermal stability.

[0003] However, the gate oxide of SiC MOSFET devices is prone to degradation under high electric fields, leading to excessively high electric field strength within the gate oxide layer and affecting device reliability. In traditional SiC MOSFET structures, the JFET region is often designed with a wide width to achieve low on-resistance, but this design may cause the gate oxide layer to withstand excessively high voltage under reverse bias, triggering premature device breakdown. On the other hand, while existing square, staggered square, and hexagonal layout structures optimize the electric field distribution to some extent, they still suffer from problems such as high on-resistance, low current density, and poor short-circuit characteristics. Summary of the Invention

[0004] To address the aforementioned technical problems, embodiments of this application provide a silicon carbide power device with improved BV and Ron, along with its fabrication method and chip. The aim is to simultaneously optimize the device's on-resistance and breakdown voltage, effectively compromising between breakdown voltage and on-resistance to improve the device's reliability and short-circuit characteristics.

[0005] The first aspect of this application provides a silicon carbide power device, the silicon carbide power device comprising:

[0006] A silicon carbide substrate and an N-type drift region formed on the front side of the silicon carbide substrate;

[0007] The top epitaxial region formed on the N-type drift region;

[0008] A first P-type well region is formed on the N-type drift region and in the top epitaxial region;

[0009] A heavily doped P-type region formed on the first P-type well region;

[0010] Multiple second P-type well regions are formed in the top epitaxial region, the depth of the second P-type well regions is less than the depth of the first P-type well region, adjacent second P-type well regions are isolated by the top epitaxial region, and at least two second P-type well regions are symmetrically arranged with respect to the P-type heavily doped region.

[0011] Multiple N-type heavily doped regions are formed on the second P-type well region; wherein the N-type heavily doped regions are located within the grooves of the second P-type well region;

[0012] A gate dielectric layer is formed on the top epitaxial region and the P-type heavily doped region, and the gate dielectric layer covers the second P-type well region;

[0013] A gate layer enclosed by the gate dielectric layer;

[0014] A first electrode covering the gate dielectric layer and the P-type heavily doped region;

[0015] A second electrode is formed on the back side of the silicon carbide substrate.

[0016] In some embodiments, the top epitaxial region between adjacent second P-type well regions is an N-type junction field-effect transistor region, the horizontal cross-sectional shape of the N-type junction field-effect transistor region is cross-shaped, and the first P-type well region and the heavily doped P-type region are located at the intersection of the N-type junction field-effect transistor region.

[0017] In some embodiments, the N-junction field-effect transistor region has a second P-type well region on each side of the first horizontal direction, and the N-junction field-effect transistor region has a first P-type well region and a heavily doped P-type region on each side of the second horizontal direction; wherein the first horizontal direction is perpendicular to the second horizontal direction.

[0018] In some embodiments, the width of the heavily doped P-type region is smaller than the width of the first P-type well region, the heavily doped P-type region is located within the groove of the first P-type well region, and the first P-type well region and the heavily doped P-type region are in contact with the gate dielectric layer.

[0019] In some embodiments, the second P-type well region has a stepped structure, the width of the second P-type well region gradually increases from the second electrode to the first electrode, and the heavily doped P-type region is formed between the second P-type well region and the gate dielectric layer.

[0020] In some embodiments, the silicon carbide power device further includes a P-type floating junction located at the interface region between the N-type drift region and the top epitaxial region, and grounded through the first P-type well region.

[0021] In some embodiments, the P-type heavily doped region has a concave structure, the first electrode has a convex structure, and the convex portion of the first electrode extends into the groove of the P-type heavily doped region.

[0022] In some embodiments, the silicon carbide substrate is a P-type substrate, and both the top epitaxial region and the N-type drift region are N-type doped;

[0023] The second electrode is the collector, and the first electrode is the emitter.

[0024] A second aspect of this application also provides a method for fabricating a silicon carbide power device as described in any of the above embodiments, the method comprising:

[0025] An N-type drift region and a top epitaxial region are sequentially formed on the front side of a silicon carbide substrate;

[0026] After depositing polycrystalline silicon material, the polycrystalline silicon material is etched to form a preset pattern, and a second P-type well region is formed in the top epitaxial region by ion implantation process;

[0027] A thermal oxide layer is formed, and an N-type heavily doped region is formed by ion implantation under the protection of the thermal oxide layer.

[0028] A junction field-effect transistor region extending into the N-type drift region is formed by ion implantation under the first mask coverage. Then, a first P-type well region and a heavily doped P-type region are formed by multiple ion implantation processes under the second mask coverage. The depth of the second P-type well region is less than the depth of the first P-type well region. Adjacent second P-type well regions are isolated by the top epitaxial region. At least two second P-type well regions are symmetrically arranged with respect to the heavily doped P-type region.

[0029] Remove the second mask and form a gate dielectric layer covering the P-type well region and the junction field-effect transistor region, as well as a gate layer included by the gate dielectric layer;

[0030] A first electrode is formed covering the gate dielectric layer and the P-type heavily doped region, and a second electrode is formed on the back side of the silicon carbide substrate.

[0031] A third aspect of this application also provides a chip including a silicon carbide power device as described in any of the above embodiments.

[0032] The beneficial effects of the embodiments of this application are as follows: by setting a first P-type well region formed in the top epitaxial region, a heavily doped P-type region formed on the first P-type well region, and the adjacent second P-type well regions being isolated by the top epitaxial region, at least the second P-type well regions are symmetrically arranged with heavily doped P-type regions, and the depth of the second P-type well region is less than the depth of the first P-type well region, the JFET region inside the device can have a higher doping concentration of donor doping, which can effectively reduce the on-resistance and increase the current density of the device while ensuring the ideal BVDSS of the device. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of a silicon carbide power device provided in an embodiment of this application;

[0034] Figure 2 This is another schematic diagram of the silicon carbide power device provided in the embodiments of this application;

[0035] Figure 3 This is another schematic diagram of the silicon carbide power device provided in the embodiments of this application;

[0036] Figure 4 This is another schematic diagram of the silicon carbide power device provided in the embodiments of this application;

[0037] Figure 5 This is another schematic diagram of the silicon carbide power device provided in the embodiments of this application;

[0038] Figure 6 This is another schematic diagram of the silicon carbide power device provided in the embodiments of this application;

[0039] Figure 7a This is a partial cross-sectional schematic diagram of the silicon carbide power device provided in the embodiments of this application;

[0040] Figure 7b This is a partial cross-sectional schematic diagram of the silicon carbide power device provided in the embodiments of this application;

[0041] Figure 7c This is a partial cross-sectional schematic diagram of the silicon carbide power device provided in the embodiments of this application;

[0042] Figure 7d This is a partial cross-sectional schematic diagram of the silicon carbide power device provided in the embodiments of this application;

[0043] Figure 7e This is a partial cross-sectional schematic diagram of the silicon carbide power device provided in the embodiments of this application;

[0044] Figure 7f This is a partial cross-sectional schematic diagram of the silicon carbide power device provided in the embodiments of this application;

[0045] Figure 7g This is a partial cross-sectional schematic diagram of the silicon carbide power device provided in the embodiments of this application;

[0046] Figure 8 This is a schematic flowchart of the method for fabricating silicon carbide power devices provided in the embodiments of this application;

[0047] Figure 9 This is a partial schematic diagram of the method for fabricating silicon carbide power devices provided in the embodiments of this application;

[0048] Figure 10 This is a partial schematic diagram of the method for fabricating silicon carbide power devices provided in the embodiments of this application;

[0049] Figure 11 This is a partial schematic diagram of the method for fabricating silicon carbide power devices provided in the embodiments of this application;

[0050] Figure 12a , 12b 12c is a partial schematic diagram of the method for fabricating silicon carbide power devices provided in the embodiments of this application;

[0051] Figure 13 This is a partial schematic diagram of the method for fabricating silicon carbide power devices provided in the embodiments of this application;

[0052] Figure 14 This is a partial schematic diagram of the method for fabricating silicon carbide power devices provided in the embodiments of this application. Detailed Implementation

[0053] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0054] The gate oxide of SiC MOSFET devices is prone to degradation under high electric fields, leading to excessively high electric field strength within the gate oxide layer and affecting device reliability. In traditional SiC MOSFET structures, the JFET region is often designed with a wide width to achieve low on-resistance, but this design may cause the gate oxide layer to withstand excessively high voltage under reverse bias, triggering premature device breakdown. On the other hand, while existing square, staggered square, and hexagonal layout structures optimize the electric field distribution to some extent, they still suffer from problems such as high on-resistance, low current density, and poor short-circuit characteristics.

[0055] To address the aforementioned technical problems, embodiments of this application provide a silicon carbide power device with improved breakdown voltage (BV) and on-resistance (Ron). See [link to relevant documentation]. Figure 1 As shown, Figure 1The schematic diagram (a) shows a horizontal cross-section of a silicon carbide power device. Figure 1 The schematic diagram (b) shows a cross-section A of the silicon carbide power device. Figure 1 The schematic diagram (c) shows a cross-sectional view of the silicon carbide power device, B. Figure 1 The schematic diagram (d) shows a cross-sectional view of the silicon carbide power device. The silicon carbide power device in this embodiment includes: a silicon carbide substrate 210, an N-type drift region 220, a top epitaxial region 230, a first P-type well region 240, a second P-type well region 261, a heavily doped P-type region 250, a heavily doped N-type region 262, a gate dielectric layer 320, a gate layer 310, a first electrode 110, and a second electrode 120.

[0056] Combination Figure 1 As shown, an N-type drift region 220 is formed on the front side of the silicon carbide substrate 210, a second P-type well region 261 is formed on the N-type drift region 220, and a top epitaxial region 230 is formed on the N-type drift region 220, which is isolated by a first P-type well region 240. A heavily doped P-type region 250 is formed on the first P-type well region 240, and is isolated from adjacent heavily doped P-type regions 250 by the top epitaxial region 230. Multiple heavily doped N-type regions 262 are formed on multiple second P-type well regions 261, and are isolated from adjacent top epitaxial regions 230 by the second P-type well regions 261. The thickness of the heavily doped N-type regions 262 is less than the thickness of the second P-type well regions 261. A gate dielectric layer 320 is formed on the top epitaxial region 230 and the second P-type well region 261, and the gate dielectric layer 320 covers the second P-type well region 261. The gate layer 310 is wrapped by the gate dielectric layer 320, the first electrode 110 covers the gate dielectric layer 320 and the heavily doped P-type region 250, and the second electrode 120 is formed on the back side of the silicon carbide substrate 210.

[0057] In this embodiment, the N-type heavily doped region 262 is isolated from the adjacent top epitaxial region 230 by a second P-type well region 261. In vertical section A, the P-type heavily doped region 250 is disposed opposite to the gate layer 310, and the P-type heavily doped region 250 and the gate layer 310 are isolated by a gate dielectric layer 320. In vertical section B, the adjacent P-type heavily doped regions 250 form an N-type JFET region. In vertical section B, the adjacent top epitaxial regions 230 are isolated by the second P-type well region 261 and the P-type heavily doped region 250. The P-type heavily doped region 250 is connected to the first electrode 110, and the first electrode 110 and the second electrode 120 form a reverse PN junction formed by the first P-type well region 240 and the N-type drift region 220. Within the vertical section C, the N-type JFET region and the second P-type well region 261 form a planar gate MOS structure. The N-type JFET region is surrounded by the second P-type well region 261 and the first P-type well region 240, thus forming a PN junction-like superjunction pillar structure. This allows the top epitaxial region 230 to have a higher doping concentration of donor doping. Under the condition of ensuring the ideal BVDSS of the device, the on-resistance can be effectively reduced, the current density of the device can be increased, and the reliability of the device can be improved.

[0058] In this embodiment, a first P-type well region 240 with a deep well structure is formed below the heavily doped P-type region 250. The doping concentration of the heavily doped P-type region 250 is greater than that of the first P-type well region 240. The first P-type well region 240 extends into the surface of the N-type drift region 220. The top epitaxial regions 230 on both sides of the heavily doped P-type region 250 serve as JFET regions. Each JFET region has an independent gate, which is wrapped by a gate dielectric layer. The first electrode 110 is connected to the heavily doped N-type region 262 through a via between the gate dielectric layers 320. When the control voltage connected to the gate layer 310 is 0V, the gate-drain capacitance Cgd of the device is reduced and the gate-source capacitance Cgs is increased through the first P-type well region 240 with the deep well structure. This achieves higher high-frequency performance while reducing the displacement current generated by the gate-drain capacitance Cgd and increasing the gate-source capacitance Cgs, thus playing a role in current shunting and voltage regulation. This reduces the risk of gate mis-turn-on, facilitates 0-voltage turn-off, and improves the reliability of the device.

[0059] In some embodiments, the top epitaxial region 230 between adjacent second P-type well regions 261 is an N-type junction field-effect transistor region (N-type JFET region), the horizontal cross-sectional shape of the N-type junction field-effect transistor region is cross-shaped, and the first P-type well region 240 and the P-type heavily doped region 250 are located in the intersection region of the N-type junction field-effect transistor region.

[0060] In some embodiments, the N-type junction field-effect transistor region has a second P-type well region 261 on both sides of the horizontal first direction, and the N-type junction field-effect transistor region has a first P-type well region 240 and a P-type heavily doped region 250 on both sides of the horizontal second direction; wherein the horizontal first direction is perpendicular to the horizontal second direction.

[0061] In some embodiments, combined with Figure 1 As shown, the cross-shaped area of ​​the JFET region is filled with a small P-type shielding area (i.e., the block area).

[0062] In some embodiments, the P-type shielding region (block region) and the second P-type trap region 261 can be integrally formed.

[0063] In some embodiments, the second P-type well region 261 is square or rectangular, and the second P-type well region 261 surrounds the N-type heavily doped region 262. The area between adjacent second P-type well regions 261 is an N-type JFET region. The cross intersection of the JFET regions is a shielding region (Block). The shielding region can be formed by high-energy P-type ion implantation to form a double-layer structure of the first P-type well region 240 and the P-type heavily doped region 250.

[0064] In some embodiments, the N-type JFET region is rectangular in shape within a horizontal cross section. The rectangular JFET region has a second P-type well region 261 on both sides in the first direction and a first P-type well region 240 on both sides in the second direction, as shown in sections A and B. The first P-type well region 240 and the JFET region form a PN alternating structure, as shown in section C. The JFET region and the second P-type well region 261 form a planar gate MOS structure, that is, the JFET region is surrounded by the second P-type well region 261 and the first P-type well region 240, forming a PN-type superjunction pillar structure. The first direction and the second direction are perpendicular to each other, and the angle between the first direction and the second direction is 90°.

[0065] In some embodiments, the top epitaxial region 230 and the second P-type well region 261 form a lateral PN junction structure, that is, a superjunction-like structure in which the second P-type well region 261 surrounds the N-type JFET region.

[0066] In this embodiment, the superjunction-like structure allows for higher donor impurity doping in the JFET region, thus effectively reducing on-resistance while maintaining ideal BVDSS. The novel structure exhibits 40-50% higher current density than the strip layout and 10-20% higher current density than the square / staggered square / hexagonal layout.

[0067] In some embodiments, the corner of the second P-type well region 261 of the novel structure in this embodiment has a shielded area, from which the electric field peak moves to the bottom of the first P-type well region 240, improving reliability. At the same time, the depletion region can be completely closed, so its IDSS is lower (two orders of magnitude lower than the conventional one) and BVDSS is higher.

[0068] In some embodiments, combined with Figure 1 As shown, the width of the first P-type well region 240 is the same as the width of the heavily doped P-type region 250. The heavily doped P-type region 250 and the first P-type well region 240 can use the same photomask, saving production costs.

[0069] In some embodiments, the width of the top epitaxial region 230 is 1.0-2.4 μm, the depth of the top epitaxial region 230 is 1.0-1.4 μm, and the total doping dose of the top epitaxial region 230 is 2E12-8E12 cm⁻¹. -2 .

[0070] In some embodiments, the top epitaxial region 230 between adjacent second P-type well regions 261 is set as a JFET region, and the doping concentrations of the second P-type well region 261, the JFET region, and the heavily doped P-type region 250 are all approximately box-shaped.

[0071] In some embodiments, the width of the JFET region is 0.6-2.4 μm.

[0072] In some embodiments, the depth of the JFET region is 1.0-4.0 μm.

[0073] In some embodiments, the doping dose of the JFET region is 1E12-1E14 cm⁻¹. -2 .

[0074] In some embodiments, the depth of the second P-type well region 261 is 0.6-0.7 μm, and the doping dose of the second P-type well region 261 is 2E12-2E13 cm⁻¹. -2 .

[0075] In some embodiments, the depth of the first P-type well region 240 is 1.0-4.0 μm, and the doping dose of the first P-type well region 240 is 8E12-1E14 cm⁻¹. -2 .

[0076] In some embodiments, the depth of the heavily doped P-type region 250 is 1 μm, and the doping dose of the heavily doped P-type region 250 is 3E15-8E15cm. -2 .

[0077] In some embodiments, combined with Figure 2 As shown, Figure 2 The schematic structure (b) is a cross-sectional view of the horizontal schematic structure (a). Figure 2 The schematic diagram (c) shows a cross-sectional view of the silicon carbide power device, B. Figure 2The schematic structure (d) is a cross-sectional view of the silicon carbide power device. The width of the heavily doped P-type region 250 is smaller than the width of the first P-type well region 240. The heavily doped P-type region 250 is located in the groove of the first P-type well region 240, and the first P-type well region 240 and the heavily doped P-type region 250 are in contact with the gate dielectric layer 320.

[0078] In this embodiment, the first P-type well region 240 has a concave structure, and the heavily doped P-type region 250 is located in the groove of the first P-type well region 240. The doping concentration of the heavily doped P-type region 250 is greater than that of the first P-type well region 240. The heavily doped P-type region 250 is connected to the first electrode 110. The heavily doped P-type region 250 is isolated from the JFET regions on both sides by the first P-type well region 240. The area of ​​the second P-type well region 261 is increased, and the depth of the first P-type well region 240 is also increased, which increases the depletion region capacitance, reduces the gate drain charge Qgd of the new structure, and speeds up the switching speed of the device.

[0079] In some embodiments, combined with Figure 1 As shown in the schematic structure (d), the second P-type well region 261 is square or rectangular, and an N-type JFET region is provided between adjacent second P-type well regions 261. The N-type JFET region is disposed opposite to the gate layer 310 and is isolated by the gate dielectric layer 320.

[0080] In some embodiments, the surrounding second P-type well region 261 and the first P-type well region 240 have a stronger depletion effect than other layouts, thus causing the device to enter the saturation region earlier, clamping the saturation current, and optimizing the short-circuit characteristics of the device.

[0081] In some embodiments, see Figure 3 As shown, Figure 3 The schematic structure (b) is a cross-sectional view of the horizontal schematic structure (a). Figure 3 The schematic diagram (c) shows a cross-sectional view of the silicon carbide power device, B. Figure 3 The schematic structure (d) is a cross-sectional view of the silicon carbide power device. The second P-type well region 261 has a stepped structure, and the width of the second P-type well region 261 gradually increases from the second electrode 120 to the first electrode 110. The heavily doped P-type region 250 is formed between the second P-type well region 261 and the gate dielectric layer 320.

[0082] In this embodiment, the first P-type well region 240 can be formed by multiple ion implantations to create an ultra-deep junction with progressively varying doping concentration and width. By setting the width of the first P-type well region 240 to gradually increase from the interface region between the N-type drift region 220 and the top epitaxial region 230 toward the first electrode 110, the electric field of the JFET region can be adjusted, allowing for higher donor impurity doping within the JFET region. This is beneficial for reducing its on-resistance (Ron) and increasing the current density of the device. Furthermore, the width and doping concentration of the first P-type well region 240 closer to the N-type drift region 220 are smaller, which is beneficial for increasing the breakdown voltage (BV) of the device. By adjusting the width and doping concentration of each step in the stepped structure of the first P-type well region 240, a trade-off between Ron and BV can be achieved.

[0083] In some embodiments, see Figure 4 As shown, Figure 4 The schematic structure (b) is a cross-sectional view of the horizontal schematic structure (a). Figure 4 The schematic diagram (c) shows a cross-sectional view of the silicon carbide power device, B. Figure 4 The schematic diagram (d) shows a cross-sectional view of the silicon carbide power device. The silicon carbide power device also includes a P-type floating junction, which is located at the interface between the N-type drift region 220 and the top epitaxial region 230, and is grounded through the first P-type well region 240.

[0084] In this embodiment, the P-type levitated junction is connected to the first P-type well region 240. Within section A, the P-type levitated junction extends below the adjacent first P-type well region 240, and within section A, the N-type drift region 220 and the top epitaxial region 230 are isolated. Within section B, the heavily doped P-type region 250 is connected to the first electrode 110. The first P-type well region 240 is formed between the heavily doped P-type region 250 and the P-type levitated junction. The width of the P-type doped region between the P-type levitated junction and the first P-type well region 240 is smaller than the width of the first P-type well region 240. Within section C, the P-type levitated junction is disposed opposite to the gate layer 310, allowing an NPN structure to be formed below the gate layer 310. This disperses the electric field between the first electrode 110 and the second electrode 120, which is beneficial for improving the device's breakdown voltage and has a smaller impact on the device's on-resistance.

[0085] In some embodiments, see Figure 5 As shown, Figure 5 The schematic structure (b) is a cross-sectional view of the horizontal schematic structure (a). Figure 5 The schematic diagram (c) shows a cross-sectional view of the silicon carbide power device, B. Figure 5The schematic structure (d) is a cross-sectional view of the silicon carbide power device. The P-type heavily doped region 250 is a concave structure, the first electrode 110 is a convex structure, and the convex part of the first electrode 110 extends into the groove of the P-type heavily doped region 250.

[0086] In this embodiment, the protrusion of the first electrode 110 extends into the groove of the heavily doped P-type region 250. The protrusion of the first electrode 110 is surrounded by the heavily doped P-type region 250 in the horizontal cross section. The heavily doped P-type region 250 is annular in the horizontal cross section, which can increase the distance between the first electrode 110 and the N-type JFET regions on both sides of the heavily doped P-type region 250. Compared with other layouts, it has a stronger depletion effect, which is beneficial for the device to enter the saturation region, clamp the saturation current, and optimize the short-circuit characteristics of the device.

[0087] In some embodiments, the silicon carbide substrate 210 can be N-type doped, in which case the silicon carbide power device can be a MOS structure, with the first electrode 110 as the source and the second electrode 120 as the drain.

[0088] In some embodiments, see Figure 6 As shown, Figure 6 The schematic structure (b) is a cross-sectional view of the horizontal schematic structure (a). Figure 6 The schematic diagram (c) shows a cross-sectional view of the silicon carbide power device, B. Figure 6 The schematic diagram (d) shows a cross-sectional view of the silicon carbide power device. The silicon carbide substrate 210 can be P-type doped, in which case the silicon carbide power device can be an IGBT structure, with the first electrode 110 as the emitter and the second electrode 120 as the collector.

[0089] In some embodiments, the P-type heavily doped region 250 and the N-type heavily doped region 262 are arranged in a single direction, that is, they can be arranged in the following layout: N-type heavily doped region 262 / P-type heavily doped region 250 / N-type heavily doped region 262.

[0090] In this embodiment, compared to square, staggered square or hexagonal layouts, the second P-type well region 261 of the silicon carbide power device in this embodiment has no corners, and the depletion region can be completely closed. Therefore, its IDSS is lower (two orders of magnitude lower than conventional), BVDSS is higher, and its reliability at room temperature / high temperature is better.

[0091] In some embodiments, combined with Figure 1As shown, in this embodiment, the area of ​​the second P-type well region 261 of the silicon carbide power device is increased, resulting in increased depletion region capacitance. Compared to a square structure layout, its Qgd is reduced, and switching is faster. The P-type shielding region (block region) and the second P-type well region 261 enclose the JFET region, exhibiting a stronger depletion effect than other layouts. This reduces reverse leakage current IDSS. Additionally, the device can enter the saturation region earlier upon power-on, clamping the saturation current and optimizing the device's short-circuit characteristics. Furthermore, in the fabrication process, the heavily doped P-type region 250 and the first P-type well region 240 use the same photomask, requiring no additional cost.

[0092] In some embodiments, combined with Figure 7a As shown, each top epitaxial region 230 has a P-type heavily doped region 250 on both sides, and each P-type heavily doped region 250 has an N-type heavily doped region 262 on both sides.

[0093] In this embodiment, the first direction is perpendicular to the second direction, and a second P-type well region 261 is provided at the intersection of the top epitaxial region JFET arranged along the first direction and the top epitaxial region JFET arranged along the second direction.

[0094] In some embodiments, combined with Figure 7b As shown, the N-type heavily doped region 262 has an annular cross-sectional shape and is arranged around the P-type heavily doped region 250 in the horizontal cross-section.

[0095] In this embodiment, the N-type heavily doped region 262 has a ring-shaped square structure in the horizontal cross-section.

[0096] In some embodiments, combined with Figure 7c As shown, the intersection area of ​​the top epitaxial region JFETs arranged along the first direction and the top epitaxial region JFETs arranged along the second direction is the P-type shielding area (block area).

[0097] In some embodiments, the P-type shielding area (block area) has a hollow square structure.

[0098] In some embodiments, a smaller second JFET region 211 is also provided in the central region within the P-type shielding area (block area).

[0099] In some embodiments, combined with Figure 7d As shown, the N-type heavily doped region 262 and the P-type heavily doped region 250 are located on both sides of the top epitaxial region JFET, respectively. The intersection of the line connecting two adjacent N-type heavily doped regions 262 and the line connecting two adjacent P-type heavily doped regions 250 is located in the region between adjacent top epitaxial regions JFETs.

[0100] In this embodiment, the top epitaxial region JFET has a rectangular shape in horizontal cross-section. The long sides of the plurality of top epitaxial region JFETs arranged along a first direction are parallel to the first direction, and the long sides of the plurality of top epitaxial region JFETs arranged along a second direction are perpendicular to the second direction. A P-type heavily doped region 250 is disposed on one long side of the top epitaxial region JFET, and an N-type heavily doped region 262 is disposed on the other long side of the top epitaxial region JFET. Thus, the N-type heavily doped region 262 and the P-type heavily doped region 250 are arranged diagonally opposite each other.

[0101] In some embodiments, such as Figure 7e As shown, the cell can be a rectangular structure. Three top epitaxial region JFETs are arranged in the second direction. The long side of the three top epitaxial region JFETs is parallel to the second direction. Each top epitaxial region JFET in the second direction has an N-type heavily doped region 262 / P-type heavily doped region 250 / N-type heavily doped region 262 structure on both sides. A top epitaxial region JFET arranged in the first direction is also arranged between each adjacent N-type heavily doped region 262 / P-type heavily doped region 250 / N-type heavily doped region 262 structure on each side.

[0102] In some embodiments, such as Figure 7f As shown, the horizontal cross-section of the P-type heavily doped region 250 can be hexagonal, and the N-type heavily doped region 262 is also a hexagonal structure.

[0103] In some embodiments, a plurality of top epitaxial region JFETs are arranged sequentially in a first direction, a second direction and a third direction on a horizontal cross section, wherein the angle between the first direction and the second direction is 120° and the angle between the first direction and the third direction is 120°.

[0104] In some embodiments, a plurality of top epitaxial region JFETs are arranged in a plurality of directions, and a top epitaxial region JFET is provided at the intersection of the plurality of directions.

[0105] In some embodiments, the cross-sectional shape of the top epitaxial region JFET in the intersection region of multiple directions is square or triangular.

[0106] In some embodiments, such as Figure 7g As shown, in the case of a hexagonal cell layout, the block region is a hollow triangle, that is, the intersection area of ​​the first direction, the second direction and the third direction is filled by the top epitaxial region JFET of the triangle.

[0107] In some embodiments, combined with Figure 7cAs shown, multiple top epitaxial region JFETs are arranged sequentially in a first direction and a second direction on a horizontal cross section. The first direction and the second direction are perpendicular. A square top epitaxial region JFET is provided in the intersection area between the multiple top epitaxial region JFETs arranged in the first direction and the multiple top epitaxial region JFETs arranged in the second direction. The area of ​​the square top epitaxial region JFET is smaller than the area of ​​the adjacent top epitaxial region JFET, and the width of the square top epitaxial region JFET is smaller than the width of the adjacent top epitaxial region JFET.

[0108] In some embodiments, combined with Figure 7c As shown, the P-type heavily doped region 250 has a square shape in the horizontal cross-section, the N-type heavily doped region 262 has a rectangular shape in the horizontal cross-section, and the top epitaxial region JFET has a rectangular shape in the horizontal cross-section. The long sides of the P-type heavily doped region 250, the N-type heavily doped region 262, and the top epitaxial region JFET are arranged in parallel. An N-type heavily doped region 262 is provided on each of the two long sides of the P-type heavily doped region 250.

[0109] This application also provides a method for fabricating the silicon carbide power device in any of the above embodiments, see [link to documentation]. Figure 8 As shown, the preparation method includes steps S100 to S600.

[0110] In step S100, an N-type drift region 220 and a top epitaxial region are sequentially formed on the front side of the silicon carbide substrate 210.

[0111] In this embodiment, combined with Figure 9 As shown, the top epitaxial region is integrally formed with the silicon carbide substrate 210.

[0112] In some embodiments, the silicon carbide substrate 210 can be a highly doped substrate, and a double lightly doped epitaxial layer is formed on the silicon carbide substrate 210. The first lightly doped epitaxial layer can serve as an N-type drift region 220, and the second lightly doped epitaxial layer can serve as a top epitaxial region.

[0113] In some embodiments, the doping concentration of the top epitaxial region is 1.3-3E16 cm⁻¹. -3 The thickness of the top epitaxial region is 1-3 μm.

[0114] In some embodiments, the doping concentration of the N-type drift region 220 is 3E15-1.5E16 cm⁻¹. -3 The thickness and concentration of the N-type drift region 220 depend on the device's voltage rating.

[0115] In step S200, after depositing polysilicon material, the polysilicon material 501 is etched to form a preset pattern, and a second P-type well region 261 is formed in the top epitaxial region by ion implantation.

[0116] In this embodiment, combined with Figure 10 As shown, the implantation energy for forming the second P-type well region 261 and the block region by ion implantation decreases sequentially, with doping concentrations ranging from 1E16 to 2E18 cm⁻¹. -3 Within the range.

[0117] In some embodiments, the implantation depth of the second P-type well region 261 is 0.6-0.8 μm, which is 0.3-0.4 μm shallower than that of the conventional structure. The number of implantations is 3-5 times, with the energy decreasing sequentially. The doping concentration is distributed in a box-like pattern.

[0118] In step S300, a thermal oxide layer 502 is formed, and an N-type heavily doped region 262 is formed by ion implantation under the protection of the thermal oxide layer 502.

[0119] In this embodiment, combined with Figure 11 As shown, by widening the hard mask through oxidation, the channel is masked, and an N-type heavily doped region 262 is formed through ion implantation.

[0120] A self-aligned process is employed to deposit polycrystalline silicon as a hard mask, thereby masking the channel. An N-type heavily doped region 262 is formed via ion implantation to a depth of 1.0-4.0 μm, achieving charge balance with the first P-type well region 240 / second P-type well region 261. The implantation process involves 4-6 implantations with decreasing energy, resulting in a doping concentration of 2E16-2E18 cm⁻¹. -3 The overall structure is box-shaped.

[0121] In some embodiments, if the silicon carbide substrate 210 is P-type doped, the silicon carbide power device is an IGBT structure. In the fabrication process of the IGBT structure, a hard mask can be formed by isotropic CVD deposition of silicon oxide, followed by anisotropic dry etching of the silicon oxide hard mask. The silicon oxide on the SiC surface is etched away, leaving the silicon oxide hard masks on both sides of the hard mask. The silicon oxide hard masks on both sides of the hard mask effectively mask the channel, and ion implantation forms an N-type heavily doped region 262.

[0122] In step S400, combined Figure 12a , Figure 12b , Figure 12c Under the cover of the first mask 503, the first JFET region 221 extending into the N-type drift region 220 is formed by ion implantation. Then, under the cover of the second mask 505, the first P-type well region 240 and the P-type heavily doped region 250 are formed by ion implantation.

[0123] In this embodiment, combined with Figure 12b As shown, the conductivity of the first JFET region 221 can be improved by N-type doping under the cover of the first mask 503.

[0124] In some embodiments, in step S400, the implantation depth of the ion implantation process is approximately 1.0-1.4 μm.

[0125] In some embodiments, in step S400, the ion implantation process is performed 4-6 times, the implantation energy decreases sequentially, and the doping concentration of the first JFET region 221 is 2E16-2E17 cm⁻¹. -3 The overall distribution is in the shape of a box.

[0126] In this embodiment, combined with Figure 12c As shown, after removing the first mask 503, a second mask 505 is formed. Under the coverage of the second mask 505, a P-type heavily doped region 250 is formed by ion implantation. The P-type heavily doped region 250 and the first JFET region 221 are isolated by a second P-type well region 261.

[0127] In some embodiments, in step S400, P-type ion implantation forms a heavily doped P-type region 250. The implantation depth of the P-type ions is approximately 1.0-1.5 μm, the number of P-type ion implantations is 3-5 times, the P-type ion implantation energy decreases sequentially, and the doping concentration of the heavily doped P-type region 250 is greater than 1E19 cm⁻¹. -3 The P-type heavily doped region 250 is distributed in a box pattern. After P-type ion implantation, the device is annealed at 1600-1800℃.

[0128] In step S500, combined Figure 13 As shown, the second mask 505 is removed, and a gate dielectric layer 320 covering the second P-type well region 261 and the first JFET region 221 and a gate layer 310 included by the gate dielectric layer 320 are formed.

[0129] In this embodiment, see Figure 13 As shown, the implantation process ends with annealing and activation at 1600-1800℃, sacrificial oxidation to form the gate dielectric layer 320, and deposition of polysilicon material to form the gate layer 310.

[0130] In step S600, a first electrode 110 is formed covering the gate dielectric layer 320 and the P-type heavily doped region 250, and a second electrode 120 is formed on the back side of the silicon carbide substrate 210.

[0131] In this embodiment, see Figure 14 As shown, the first electrode 110 and the second electrode 120 are formed by depositing metallic materials.

[0132] In some embodiments, if the silicon carbide substrate 210 in step S100 can be N-type doped, then the silicon carbide power device can be a MOS structure.

[0133] In some embodiments, if the silicon carbide substrate 210 in step S100 can be P-type doped, then the silicon carbide power device can be an IGBT structure.

[0134] This application also provides a chip including a silicon carbide power device as described in any of the above embodiments.

[0135] In some embodiments, the chip includes a chip substrate on which one or more silicon carbide power devices are disposed, the silicon carbide power devices including those described in any of the above embodiments.

[0136] In one specific application embodiment, when the silicon carbide substrate 210 is N-type doped, the silicon carbide power device can be a MOS structure, with the first electrode 110 as the source and the second electrode 120 as the drain. When the silicon carbide substrate 210 is P-type doped, the silicon carbide power device can be an IGBT structure, with the first electrode 110 as the emitter and the second electrode 120 as the collector.

[0137] Other related semiconductor devices, as well as MOSFETs, can be integrated on the chip substrate to form an integrated circuit.

[0138] In one specific application embodiment, the chip can be a switch chip or a driver chip.

[0139] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of doped regions and devices is used as an example. In practical applications, the above functions can be assigned to different doped regions and devices as needed, that is, the internal structure of the device can be divided into different doped regions to complete all or part of the functions described above. In the embodiments, the doped regions and devices can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0140] Furthermore, the specific names of each doped region and device are only for the purpose of distinguishing them from each other and are not intended to limit the scope of protection of this application.

[0141] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0142] In addition, in the various embodiments of this application, each doped region can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0143] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A silicon carbide power device with improved breakdown voltage and on-resistance, characterized in that, The silicon carbide power device includes: A silicon carbide substrate and an N-type drift region formed on the front side of the silicon carbide substrate; The top epitaxial region formed on the N-type drift region; A first P-type well region is formed on the N-type drift region and in the top epitaxial region; A heavily doped P-type region formed on the first P-type well region; Multiple second P-type well regions are formed in the top epitaxial region, the depth of the second P-type well regions is less than the depth of the first P-type well region, adjacent second P-type well regions are isolated by the top epitaxial region, and at least two second P-type well regions are symmetrically arranged with respect to the P-type heavily doped region. Multiple N-type heavily doped regions are formed on the second P-type well region; wherein the N-type heavily doped regions are located within the grooves of the second P-type well region; A gate dielectric layer is formed on the top epitaxial region and the heavily doped P-type region, and the gate dielectric layer covers the second P-type well region; the top epitaxial region between adjacent second P-type well regions is an N-type junction field-effect transistor region, the horizontal cross-sectional shape of the N-type junction field-effect transistor region is cross-shaped, the first P-type well region and the heavily doped P-type region are located at the intersection of the N-type junction field-effect transistor region, the N-type junction field-effect transistor region is also formed between adjacent heavily doped P-type regions, and the N-type junction field-effect transistor region is surrounded by the second P-type well region and the first P-type well region to form a PN junction-like superjunction pillar structure; The P-type levitated junction is located at the interface region between the N-type drift region and the top epitaxial region, and is grounded through the first P-type well region; A gate layer enclosed by the gate dielectric layer; A first electrode covers the gate dielectric layer and the P-type heavily doped region, and the first electrode is electrically connected to the P-type heavily doped region and the N-type heavily doped region; A second electrode is formed on the back side of the silicon carbide substrate.

2. The silicon carbide power device as described in claim 1, characterized in that, The N-type junction field-effect transistor region has a second P-type well region on each side of the first horizontal direction, and a first P-type well region and a heavily doped P-type region on each side of the second horizontal direction; wherein the first horizontal direction is perpendicular to the second horizontal direction.

3. The silicon carbide power device as described in claim 1, characterized in that, The width of the heavily doped P-type region is smaller than the width of the first P-type well region. The heavily doped P-type region is located within the groove of the first P-type well region, and the first P-type well region and the heavily doped P-type region are in contact with the gate dielectric layer.

4. The silicon carbide power device as described in claim 1, characterized in that, The second P-type well region has a stepped structure, and the width of the second P-type well region gradually increases from the second electrode to the first electrode. The heavily doped P-type region is formed between the second P-type well region and the gate dielectric layer.

5. The silicon carbide power device as described in claim 1, characterized in that, The P-type heavily doped region has a concave structure, the first electrode has a convex structure, and the convex portion of the first electrode extends into the groove of the P-type heavily doped region.

6. The silicon carbide power device as described in claim 1, characterized in that, The silicon carbide substrate is a P-type substrate, and both the top epitaxial region and the N-type drift region are N-type doped. The second electrode is the collector, and the first electrode is the emitter.

7. A method for fabricating a silicon carbide power device as described in any one of claims 1-6, characterized in that, The preparation method includes: An N-type drift region and a top epitaxial region are sequentially formed on the front side of a silicon carbide substrate; After depositing polycrystalline silicon material, the polycrystalline silicon material is etched to form a preset pattern, and a second P-type well region is formed in the top epitaxial region by ion implantation process; A thermal oxide layer is formed, and an N-type heavily doped region is formed by ion implantation under the protection of the thermal oxide layer. A junction field-effect transistor region extending into the N-type drift region is formed by ion implantation under the first mask coverage. Then, a first P-type well region and a heavily doped P-type region are formed by multiple ion implantation processes under the second mask coverage. The depth of the second P-type well region is less than the depth of the first P-type well region. Adjacent second P-type well regions are isolated by the top epitaxial region. At least two second P-type well regions are symmetrically arranged with respect to the heavily doped P-type region. Remove the second mask and form a gate dielectric layer covering the P-type well region and the junction field-effect transistor region, as well as a gate layer included by the gate dielectric layer; A first electrode is formed covering the gate dielectric layer and the P-type heavily doped region, and a second electrode is formed on the back side of the silicon carbide substrate.

8. A chip, characterized in that, Including the silicon carbide power device as described in any one of claims 1-6.

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