Silicon substrate electrical property detection link structure and test method

Abstract

The invention relates to a silicon substrate electrical property detection link structure and a test method, the silicon substrate electrical property detection link structure comprises an interconnection substrate, the interconnection substrate comprises a plurality of photomask areas arranged in an array along a first direction and a second direction, each photomask area comprises four corner areas, and the first direction is perpendicular to the second direction; a plurality of discrete test links, each test link spanning the plurality of photomask areas distributed along the third direction, and each test link comprises at least one test interconnection line, and each test interconnection line comprises a plurality of discrete corner connection lines, each corner connecting line stretches across the corresponding three corner areas in the three adjacent photomask areas in a stepped mode, and the third direction intersects with the first direction and the second direction. The method simplifies the test process, supports the cross-photomask long-link test, and is wide in coverage range and high in universality.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging, and in particular to a silicon substrate electrical detection link structure and testing method. Background Technology

[0002] As the size of interposers continues to increase, the overall pattern size exceeds the exposure range of a single photomask, necessitating the creation of the entire pattern through multiple photomask stitching operations. This technology typically employs a boundary alignment target and local exposure overlap strategy during wafer fabrication to achieve precise stitching of multiple photomask patterns on the interposer.

[0003] Wafer-level electrical testing is a core component for evaluating the yield, interconnect integrity, and functional consistency of interconnect boards, and it is especially important in the pre-bond stage before entering the packaging process.

[0004] Existing methods for electrical performance testing of large-size adapter boards require temporary bonding of a test board with a test structure to the adapter board under test, making the testing process complex. Furthermore, this test focuses on short-range electrical connectivity verification with through-silicon via (TSV) interconnect structures, does not support long-link testing across photomasks, has limited coverage, and lacks versatility. Summary of the Invention

[0005] Based on this, this application provides a silicon substrate electrical detection link structure and testing method, which simplifies the testing process, supports long link testing across photomasks, has a wide coverage, and is highly versatile.

[0006] In a first aspect, embodiments of this application provide a silicon substrate electrical detection link structure, including:

[0007] The interconnect substrate includes a plurality of photomask regions arranged in an array along a first direction and a second direction, each photomask region including four corner regions, the first direction being perpendicular to the second direction;

[0008] Multiple separate test links, each test link spans multiple photomask areas distributed along a third direction, and each test link includes at least one test interconnect line. Each test interconnect line includes multiple separate corner connection lines. Each corner connection line spans three corresponding corner areas in three adjacent photomask areas in a "step" manner. The third direction intersects with the first direction and the second direction.

[0009] In some embodiments of this application, multiple separate test links are configured in parallel.

[0010] In some embodiments of this application, each test link includes one or more test interconnects.

[0011] In some embodiments of this application, each photomask area further includes a functional area and an edge area surrounding the functional area;

[0012] The functional area contains functional connecting metal wires.

[0013] In some embodiments of this application, each test interconnect further includes multiple discrete intermediate connection lines, with each end of the intermediate connection line connected to one end of a corresponding corner connection line, and the intermediate connection lines and corner connection lines of each test interconnect line are distributed alternately.

[0014] The middle connecting line is located in the edge area.

[0015] In some embodiments of this application, the interconnect substrate includes a silicon substrate and a dielectric layer located on the top surface of the silicon substrate;

[0016] The test interconnect is located in the dielectric layer;

[0017] The functional connection wires are located in the dielectric layer.

[0018] In some embodiments of this application, the dielectric layer has multiple layers;

[0019] The functional connecting metal wires have multiple layers;

[0020] The number of layers in the test interconnect is multi-layered, and the number of layers in the test interconnect is equal to or less than the number of layers in the functional connection metal wire.

[0021] In some embodiments of this application, it further includes: a plurality of test pads, the test pads being electrically connected to corner interconnects in corner areas, the test pads being used as contact points for current injection and voltage sampling by the test probes of the test machine when performing electrical performance testing on the test interconnects, the electrical performance testing including continuity testing, resistance testing and short circuit testing;

[0022] The top surface of the dielectric layer exposes the test pads.

[0023] In some embodiments of this application, in the three corner areas of three adjacent photomask areas, each corner area has a test pad that is electrically connected to the corresponding corner connection line.

[0024] In some embodiments of this application, the silicon substrate has a plurality of through-hole interconnect structures penetrating the top and bottom surfaces of the silicon substrate, and the through-hole interconnect structures are electrically connected to functional connection metal lines.

[0025] Each photomask area represents the exposure range corresponding to a photomask during the patterning process, and different photomask areas are exposed using different photomasks.

[0026] Secondly, embodiments of this application provide a testing method, including:

[0027] Provides the aforementioned silicon substrate electrical detection link structure;

[0028] Perform electrical performance tests on one or more test interconnects.

[0029] The embodiments of this application may have, or at least have, the following advantages:

[0030] The embodiment of this application describes a silicon substrate electrical testing link structure and testing method. The silicon substrate electrical testing link structure includes: an interconnect substrate, which includes multiple photomask areas arranged in an array along a first direction and a second direction, each photomask area including four corner areas, and the first direction being perpendicular to the second direction; multiple discrete test links, each test link spanning multiple photomask areas distributed along a third direction, and each test link including at least one test interconnect line, each test interconnect line including multiple discrete corner connection lines, each corner connection line spanning three adjacent photomask areas in a "stepped" manner, the third direction intersecting with the first and second directions. Because the interconnect substrate in this application includes multiple discrete test links, each spanning multiple photomask areas distributed along a third direction, it enables long-link electrical performance testing across photomask areas, increasing the detection range of the interconnect substrate; furthermore, since the test links are multiple discrete links, each spanning multiple photomask areas distributed along a third direction, multiple test links can cover different positions of the interconnect substrate, resulting in a wide coverage of the test links;

[0031] Furthermore, each test interconnect includes multiple discrete corner connection lines. Each corner connection line spans three adjacent photomask areas in a "stepped" manner. On the one hand, this avoids the impact of the test interconnect layout on the functional area routing. On the other hand, it allows the layout positions and structures of different corner connection lines to be the same or similar, reducing the design difficulty of test interconnects when laying them across photomask areas (when designing the layout, the corner connection line designs in the corner areas of three adjacent photomask areas at different positions can be directly reused without redesigning each position). This makes the test interconnects (or test links) of this application applicable to different chip layouts and different sizes of interconnect substrates, without the need for "starting from scratch" to reconstruct the overall layout, and has good structural compatibility and versatility.

[0032] Furthermore, the interconnect substrate of this application can directly test the electrical performance of the test link without temporarily bonding a test board with a test structure, thus realizing cross-photomask area testing and simplifying the testing process.

[0033] Details of one or more embodiments of this application are set forth in the following drawings and description. Other features, objects, and advantages of this application will become apparent from the specification, drawings, and claims. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a top view schematic diagram of the electrical detection link structure of a silicon substrate provided in some embodiments of this application;

[0036] Figure 2 This is a cross-sectional schematic diagram of a portion of the test interconnects in a silicon substrate electrical detection link structure provided in some embodiments of this application.

[0037] Explanation of reference numerals in the attached figures:

[0038] Interconnect substrate 101; Test link 102; Test pad 103; Silicon substrate 104; Dielectric layer 105;

[0039] Test interconnect 12; corner connector 12a; middle connector 12b; photomask area 21; corner area 22; edge area 23. Detailed Implementation

[0040] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be more thorough and complete.

[0041] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0042] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, part, region, layer, doping type, or portion discussed below may be referred to as a second element, part, region, layer, or portion.

[0043] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0044] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or several, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or several. Meanwhile, in this application, the term “and / or” includes any and all combinations of the associated listed items.

[0045] The structure of the embodiments of this application should not be limited to the specific shape shown in the accompanying drawings, but includes shape deviations due to, for example, manufacturing techniques.

[0046] It is understood that in the accompanying drawings of this application, some adjacent membrane layers with the same processed membrane material are drawn as connected to make them resemble the actual structure.

[0047] This application first provides a silicon substrate electrical detection link structure. Figure 1 This is a top view schematic diagram of the electrical detection link structure of a silicon substrate provided in some embodiments of this application;

[0048] Figure 2 This is a cross-sectional schematic diagram of a portion of the test interconnects in a silicon substrate electrical detection link structure provided in some embodiments of this application.

[0049] refer to Figure 1 and Figure 2 The silicon substrate electrical detection link structure includes:

[0050] Interconnect substrate 101 includes a plurality of photomask regions 21 arranged in an array along a first direction D1 and a second direction D2. Each photomask region 21 includes four corner regions 22. The first direction D1 is perpendicular to the second direction D2.

[0051] Multiple separate test links 102, each test link 102 spans multiple photomask areas 21 distributed along the third direction D3, and each test link 102 includes at least one test interconnect line 12, each test interconnect line 12 includes multiple separate corner connection lines 12a, each corner connection line 12a spans three corresponding corner areas 22 of three adjacent photomask areas 21 in a "step" manner, and the third direction D3 intersects with the first direction D1 and the second direction D2.

[0052] Because the interconnect substrate 101 is relatively large, during patterning processes (such as photolithography and etching processes for forming functional connection metal lines on the interconnect substrate 101), the overall pattern size exceeds the exposure range of a single photomask. Therefore, the entire pattern must be fabricated through multiple photomask stitching operations. Photomask stitching can employ alignment target technology, partial exposure technology, magnification photomask technology, multi-segment micro-shift alignment technology, or sacrificial pattern-assisted technology. Consequently, in this application, the interconnect substrate 101 includes multiple photomask regions 21 arranged in an array. Specifically, these multiple photomask regions are arranged in rows along the first direction D1 and in columns along the second direction D2.

[0053] Each photomask area 21 represents the exposure range corresponding to one photomask during the patterning process. In one specific example, different photomask areas 21 are exposed using different photomasks. In another specific example, a portion of the photomask areas 21 may be exposed using the same photomask, while other portions of the photomask areas 21 are exposed using different photomasks.

[0054] Each photomask area 21 is rectangular or square, and multiple photomask areas 21 are of the same size. Each photomask area 21 also includes four corner areas 22, which are the top corners of the photomask area 21. The corner areas 22 can overlap with some edge areas. The corner areas 22 are also used to lay out some test interconnects 12. Specifically, one corner area 22 of a photomask area 21 serves as the corner connecting line 12a in the test interconnect 12, which crosses to the starting point of the adjacent photomask area 21. On the one hand, this avoids the impact of the test interconnect layout on the functional area routing. On the other hand, it allows the layout position and layout structure of several corner connecting lines 12a to be the same or similar, reducing the design difficulty when laying out the test interconnect 12 across photomask areas 21.

[0055] There is no electrical connection between the multiple discrete test links 102. Each test link 102 spans multiple photomask areas 21 distributed along a third direction D3, and the spanning positions of different test links 102 are different. Each test link 102 includes at least one test interconnect line 12, and each test interconnect line 12 includes multiple discrete corner connecting lines 12a. Each corner connecting line 12a spans three corresponding corner areas 22 of three adjacent photomask areas 21 in a "stepped" manner, and the third direction D3 intersects with the first direction D1 and the second direction D2. In a specific example, when the photomask area 21 is square, the angle between the third direction D3 and the first direction D1 is 45°, and the angle between the third direction D3 and the second direction D2 is 45°. In another specific example, when the photomask area 21 is rectangular, the angle between the third direction D3 and the first direction D1 can be other angles, and the angle between the third direction D3 and the second direction D2 can also be other angles. The angle between the third direction D3 and the first direction D1 is equal to or approximately equal to the angle between the diagonal and the base of the rectangle, and the angle between the third direction D3 and the second direction D2 is equal to or approximately equal to the angle between the diagonal and the side of the rectangle. In this application, since the test link 102 on the interconnect substrate 101 spans multiple photomask areas 21 distributed along the third direction D3, the detection range of the interconnect substrate 101 is increased by realizing long-link electrical performance testing across photomask areas 21.

[0056] Furthermore, the test links 102 are multiple separate links, each of which spans multiple photomask areas 21 distributed along the third direction D3. In other words, multiple test links 102 can cover different positions of the interconnect substrate 101, resulting in a wide coverage of the test links 102.

[0057] Furthermore, each test interconnect 12 includes multiple discrete corner connection lines 12a. Each corner connection line 12a spans the corresponding three corner areas 22 of the three adjacent photomask areas 21 in a "stepped" manner. On the one hand, this avoids the impact of the test interconnect line 12 layout on the functional area routing. On the other hand, it allows the layout positions and layout structures of different corner connection lines 12a to be the same or similar, reducing the design difficulty of the test interconnect line 12 when laying it across photomask areas 21 (when designing the layout, the design of the corner connection lines 12a in the corner areas 22 of the three adjacent photomask areas 21 at different positions can be directly reused without redesigning each position). This makes the test interconnect line 12 (or test link 102) of this application applicable in different chip layouts and different sized interconnect substrates, without the need for "starting from scratch" to reconstruct the overall layout, and has good structural compatibility and versatility.

[0058] Furthermore, the interconnect substrate of this application can directly test the electrical performance of the test link 102 without temporarily bonding a test board with a test structure, thus achieving cross-photomask area 21 testing while simplifying the testing process.

[0059] In some embodiments, such as Figure 1 As shown, multiple separate test links 102 are arranged in parallel, which allows the test links 102 to better and more evenly cover different positions of the interconnect substrate 101, so as to better monitor the electrical performance of different positions of the interconnect substrate 101.

[0060] In some embodiments, each test link 102 includes one or more test interconnects 12. Each test link 102 includes multiple test interconnects 12, and the number of test interconnects 12 can be two, three or more.

[0061] In some embodiments, each photomask area 21 further includes a functional area (not shown) and an edge area (not shown) surrounding the functional area. The functional area is used to lay out functional connection metal lines (not shown). The functional connection metal lines in adjacent photomask areas 21 are electrically connected. The functional connection metal lines serve as the main wiring of the interconnect substrate. When the interconnect substrate is bonded between two other devices (e.g., between an interconnect substrate and a semiconductor chip), the functional connection metal lines are used for electrical signal transmission between the two devices. The edge area is a non-functional area, which is the surrounding edge region of the photomask area 21. Each test interconnect line 12 also includes a plurality of discrete intermediate connection lines 12b. The two ends of the intermediate connection lines 12b are respectively connected to the corresponding ends of two corner connection lines 12a. The intermediate connection lines 12b and corner connection lines 12a are alternately distributed in each test interconnect line 12; the intermediate connection lines 12b are located in the edge area. On the one hand, it further avoids the impact of the test interconnect 12 layout on the functional area routing. On the other hand, it allows the layout position and layout structure of the test interconnect 12 in different photomask areas 21 to be the same or similar, further reducing the design difficulty of the test interconnect 12 when laid out across photomask areas 21 (when designing the layout, the design of the test interconnect 12 in different photomask areas 21 can be directly reused without redesigning each position). This makes the test interconnect 12 of this application applicable in different chip layouts and interconnect substrates of different sizes, without the need to "start from scratch" to reconstruct the overall layout, and has good structural compatibility and versatility.

[0062] In some embodiments, reference Figure 2 The interconnect substrate 101 includes a silicon substrate 104 and a dielectric layer 105 located on the top surface of the silicon substrate 104; the test interconnect 12 is located in the dielectric layer 105; and the functional connection metal line (not shown in the figure) is located in the dielectric layer 105 on the functional area.

[0063] In some embodiments, the silicon substrate 104 has a plurality of through-hole interconnect structures penetrating the top and bottom surfaces of the silicon substrate 104, and the through-hole interconnect structures are electrically connected to functional connection metal lines.

[0064] In some embodiments, the test interconnect 12 is located in the dielectric layer 105 on the edge region 23 and the corner region 22. Specifically, the test interconnect 12 includes an intermediate connection line 12b and a corner connection line 12a connected to the intermediate connection line 12b, wherein the intermediate connection line 12b is located in the dielectric layer 105 on the edge region 23 and the corner connection line 12a is located in the dielectric layer 105 on the corner region 22.

[0065] In some embodiments, the dielectric layer 105 has multiple layers. In one example, the dielectric layer 105 comprises a stacked structure formed by two or more of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, FSG (fluorine-doped silicon dioxide), BSG (boron-doped silicon dioxide), PSG (phosphorus-doped silicon dioxide) or BPSG (boron-phosphorus-doped silicon dioxide), and a low dielectric constant material (K less than 2.5).

[0066] Correspondingly, the functional connection metal wire has multiple layers. The number of functional metal layers can be the same as the number of dielectric layers 105. That is, each dielectric layer has a corresponding functional metal layer, and adjacent functional metal layers can be electrically connected through metal plugs.

[0067] The test interconnect 12 has multiple layers, and the number of layers of the test interconnect 12 is equal to or less than the number of layers of the functional connection metal wire. In one example, such as... Figure 2 As shown, the test interconnect 12 has four layers, and the test interconnects of adjacent layers are electrically connected through metal plugs. When the number of layers of the test interconnect 12 is the same as the number of layers of the functional connection metal lines, the interlayer connectivity of the functional connection metal lines on the functional area, the quality of the metal plugs, and the resistance uniformity of the cross-mask splice section can be monitored synchronously under the same process stack and density environment.

[0068] In some embodiments, when a corner connector 12a crosses from a corner area 22 of one photomask area 21 to a corner area 22 of an adjacent photomask area 21, the corner connector 12a in the two corner areas 22 can be located on the same layer (e.g., ...). Figure 2 As shown, the corner connectors 12a in the two corner areas 22 can be located on the same layer, which can be the top layer or any other layer below the top layer. In other embodiments, when the corner connector 12a crosses from a corner area 22 of one photomask area 21 to a corner area 22 of another adjacent photomask area 21, the corner connectors 12a in the two corner areas 22 can be located on different layers and interconnected by metal plugs.

[0069] In some embodiments, when each test link 102 includes multiple test interconnects 12, the number of layers of the multiple test interconnects 12 can be different, and the multiple test interconnects 12 can be laid on different metal layers to expand the sampling coverage of different layer processes and splicing quality. In some embodiments, the multiple test interconnects 12 can also be routed on the same metal layer, but spacing and coupling control must be met.

[0070] In some embodiments, continue to refer to Figure 1 and Figure 2It also includes: several test pads 103, which are electrically connected to the corner connection lines 12a of the corner area 22. The test pads 103 are used as contact points for the test probes of the test machine to inject current and sample voltage when performing electrical performance tests on the test interconnects 12. The electrical performance tests include continuity tests, resistance tests, and short-circuit tests. The top surface of the dielectric layer 105 exposes the test pads 103. When the test pads 103 are electrically connected to the corner connection lines 12a of the corner area 22, on the one hand, it facilitates the design of the test pads 103, so that the layout of the test pads 103 will not affect the wiring of the functional area. On the other hand, since the corner areas 22 of the adjacent photomask areas 21 are adjacent, the corner connection lines 12a in the two corner areas 22 are relatively short. When performing electrical performance tests on the corner connection lines 12a in the two corner areas 22, the test error can be reduced, thereby improving the monitoring accuracy of the splicing quality between the two photomask areas 21.

[0071] One or more test points are selected on the test interconnect 12. The test probes of the test equipment apply test current or test voltage to the test interconnect 12 through the corresponding test pads 103. The test equipment receives the feedback test current or test voltage from the corresponding test pads 103, processes the feedback test current or test voltage to obtain the resistance (test resistance) of the test interconnect 12, thereby realizing the electrical performance test of the test interconnect 12 in the test link 102. The electrical performance test includes continuity test, resistance test and short circuit test. The continuity test is based on the measured electrical... The resistance magnitude and trend of resistance variation are used to determine the continuity performance of the interconnect 12. The resistance test measures the resistance of the interconnect 12, and the short-circuit test determines whether there is a short circuit in the interconnect 12 based on the measured resistance magnitude and trend of resistance variation. The test results can reflect the metallic connectivity between the splicing area (or contact area) of two adjacent photomask areas 21, to evaluate the alignment of different photomasks during the patterning process and the splicing quality or yield between adjacent photomask areas. The test results can also reflect the metallic connectivity within the photomask area 21, to evaluate the patterning process quality within the photomask area 21. Furthermore, each set of test points corresponds one-to-one with the coordinates of the photomask area 21 or the chip coordinates (each photomask area 21 can be divided into multiple chip areas, which are subsequently used to bond semiconductor chips). Therefore, after completing the test, the defective area can be directly located based on the resistance abnormal area (excessive resistance or open circuit), and the yield distribution can be deduced from the resistance abnormal area, thus revealing the relationship between the splicing yield and the chip position, assisting the production line in optimizing photomask alignment and mask manufacturing processes.

[0072] In some embodiments, in the three corner areas 22 of the three adjacent photomask areas 21, each corner area 22 has a test pad 103 electrically connected to the corresponding corner interconnect line 12a. When electrical performance testing is required, a test voltage or test current can be applied to any two test pads 103 on the test interconnect line 12.

[0073] Some embodiments of this application also provide a testing method, including:

[0074] Provides the aforementioned silicon substrate electrical detection link structure;

[0075] Perform electrical performance tests on one or more test interconnects.

[0076] During testing, one or more test points are selected on the test interconnect 12. The test probes of the test machine apply test current or test voltage to the test interconnect 12, and the test machine receives the feedback test current or test voltage. The feedback test current or test voltage is processed to obtain the resistance (test resistance) of the test interconnect 12.

[0077] In the description of this application, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this application, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0078] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0079] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A silicon substrate electrical detection link structure, characterized in that, include: An interconnect substrate includes a plurality of photomask regions arranged in an array along a first direction and a second direction, each photomask region including four corner regions, the first direction being perpendicular to the second direction; Multiple separate test links, each test link spanning multiple photomask areas distributed along a third direction, and each test link including at least one test interconnect line, each test interconnect line including multiple separate corner connection lines, each corner connection line spanning three adjacent photomask areas in a "step" manner, the third direction intersecting with the first direction and the second direction.

2. The silicon substrate electrical detection link structure according to claim 1, characterized in that, Multiple separate test links are set up in parallel.

3. The silicon substrate electrical detection link structure according to claim 1 or 2, characterized in that, Each of the test links includes one or more test interconnects.

4. The silicon substrate electrical detection link structure according to claim 3, characterized in that, Each of the photomask areas further includes a functional area and an edge area surrounding the functional area; The functional area contains functional connecting metal wires.

5. The silicon substrate electrical detection link structure according to claim 4, characterized in that, Each of the test interconnects also includes multiple discrete intermediate connecting lines, the two ends of which are respectively connected to one end of two corner connecting lines, and the intermediate connecting lines and the corner connecting lines are alternately distributed in each of the test interconnects; The intermediate connecting line is located in the edge area.

6. The silicon substrate electrical detection link structure according to claim 4, characterized in that, The interconnect substrate includes a silicon substrate and a dielectric layer located on the top surface of the silicon substrate; The test interconnect is located in the dielectric layer; The functional connection metal wire is located in the dielectric layer; The silicon substrate has a plurality of through-hole interconnect structures penetrating the top and bottom surfaces of the silicon substrate, and the through-hole interconnect structures are electrically connected to the functional connection metal lines. Each of the aforementioned photomask areas represents the exposure range corresponding to a photomask during the patterning process, and different photomask areas are exposed using different photomasks.

7. The silicon substrate electrical detection link structure according to claim 6, characterized in that, The dielectric layer has multiple layers; The functional connecting metal wire has multiple layers; The test interconnect has multiple layers, and the number of layers of the test interconnect is equal to or less than the number of layers of the functional connection metal wire.

8. The silicon substrate electrical detection link structure according to claim 6, characterized in that, Also includes: A plurality of test pads are provided, which are electrically connected to the corner interconnects of the corner area. The test pads are used as contact points for the test probes of the test machine to inject current and sample voltage when the test interconnects are subjected to electrical performance testing. The electrical performance testing includes continuity testing, resistance testing and short circuit testing. The top surface of the dielectric layer exposes the test pad.

9. The silicon substrate electrical detection link structure according to claim 8, characterized in that, In the three adjacent photomask areas, each of the three corresponding corner areas has a test pad that is electrically connected to the corresponding corner connection line.

10. A testing method, characterized in that, include: Provides the silicon substrate electrical detection link structure as described in any one of claims 1-9; Perform electrical performance tests on one or more of the test interconnects.

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