Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor manufacturing method comprises the following steps: forming a first etching barrier layer on a semiconductor substrate, and enabling a connecting metal structure of the semiconductor substrate to be in contact with the first etching barrier layer; forming a first groove in the first etching barrier layer and exposing the connecting metal structure; forming a sacrificial structure covering the connecting metal structure in the first groove; then forming a laminated structure and forming a third groove, so that the sacrificial structure is exposed through the third groove; and removing the sacrificial structure to form a connecting hole, so that the connecting metal structure is exposed through the connecting hole. According to the semiconductor device and the manufacturing method thereof provided by the invention, the sacrificial structure covers the connecting metal structure, and then the sacrificial structure is removed, so that the size of the bottom of the connecting hole is ensured, and the influence on the reliability and performance of the semiconductor device due to insufficient critical size of the bottom of the deep hole of the semiconductor device is avoided; and the manufacturing yield of the semiconductor device is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor device and a manufacturing method thereof. BACKGROUND With the continuous reduction of the size of semiconductor devices, when etching to a deep hole, due to the micro-etching load effect, the critical dimension at the bottom of the deep hole is often insufficient, causing the resistance value to be too large, and even causing the phenomenon of open circuit or fuse, thereby affecting the reliability and performance of the semiconductor device.

[0002] Therefore, how to avoid the insufficient critical dimension at the bottom of the deep hole of the semiconductor device from affecting the reliability and performance of the semiconductor device, thereby improving the production yield of the semiconductor device, is a technical problem to be solved at present. SUMMARY

[0003] Therefore, the present application provides a semiconductor device and a manufacturing method thereof, aiming at solving the technical problem of the insufficient critical dimension at the bottom of the deep hole of the semiconductor device affecting the reliability and performance of the semiconductor device, thereby improving the production yield of the semiconductor device.

[0004] In one aspect of the embodiments of the present application, a manufacturing method of a semiconductor device is provided, comprising the following steps: forming a first etching stop layer on a semiconductor substrate, the semiconductor substrate comprising a plurality of connection metal structures, the connection metal structures being in contact with the first etching stop layer; forming a first groove in the first etching stop layer, so that the connection metal structures are exposed through the first groove; forming a sacrificial structure in the first groove, the sacrificial structure covering the connection metal structures; forming a laminated structure on the first etching stop layer and the sacrificial structure; forming a third groove in the laminated structure, so that the sacrificial structure is exposed through the third groove; removing the sacrificial structure to form a connection hole, so that the connection metal structures are exposed through the connection hole.

[0005] Further, in the manufacturing method of the semiconductor device, the semiconductor device comprises a first region and a second region, the first region forms the connection hole, and the second region does not form the connection hole; and the step of forming a first groove in the first etching stop layer comprises: coating a photoresist material on the first etching stop layer to form a first photoresist layer; forming a first notch in the first photoresist layer, the first notch being located above the connection metal structures in the first region, so that the first etching stop layer above the connection metal structures in the first region is exposed through the first notch; etching the first etching stop layer through the first gap, to form the first trench in the first region.

[0006] Further, the method for manufacturing the semiconductor device, wherein forming the first gap in the first photoresist layer comprises: exposing the first photoresist layer through a first mask, wherein the first mask is transparent in the region of the first region corresponding to the connection metal structure and opaque in other regions; developing the exposed first photoresist layer to form the first gap, wherein the first gap is above the connection metal structure in the first region; Further, the method for manufacturing the semiconductor device, wherein forming the third trench in the stack structure comprises: applying a photoresist material to the stack structure to form a third photoresist layer; exposing the third photoresist layer through a third mask, wherein the third mask is transparent in the region of the first region corresponding to the connection metal structure and opaque in other regions; and wherein the pattern of the third mask is the same as or different from the pattern of the first mask; developing the exposed third photoresist layer to form a third gap, wherein the third gap is above the connection metal structure in the first region; etching the stack structure through the third gap using the third photoresist layer as a mask, to form the third trench in the stack structure, wherein the third trench is above the connection metal structure in the first region, and the sacrificial structure is exposed through the third trench.

[0007] Further, the method for manufacturing the semiconductor device, wherein the first gap is also above the connection metal structure in a second region; and wherein the first etching stop layer in the second region also forms the first trench, and the connection metal structure in the second region is exposed through the first trench in the second region.

[0008] Further, the method for manufacturing the semiconductor device, wherein forming the first gap in the first photoresist layer comprises: exposing the first photoresist layer through a fourth mask, wherein the fourth mask is transparent in the region of the first region and the second region corresponding to the connection metal structure and opaque in other regions; developing the first photoresist layer after exposure to form the first gap, the first gap being located above the connection metal structure of the first region and the second region, so that the first etching stop layer above the connection metal structure of the first region and the second region is exposed through the first gap.

[0009] Further, in the method for manufacturing the semiconductor device, the stack structure includes an auxiliary layer, and the forming the stack structure on the first etching stop layer and the sacrificial structure includes: coating a photoresist material on the auxiliary layer to form a second photoresist layer; exposing the second photoresist layer through a fifth mask, the fifth mask being a light-transmitting region corresponding to the region of the connection metal structure of the first region and the second region and being a light-blocking region in other regions; the pattern of the fifth mask is the same as that of the fourth mask or different from that of the fourth mask; developing the second photoresist layer after exposure to form a second gap, the second gap being located above the connection metal structure of the first region and the second region; etching the auxiliary layer through the second gap to form a second trench in the auxiliary layer, the second trench being located above the connection metal structure of the first region and the second region.

[0010] Further, in the method for manufacturing the semiconductor device, the forming the sacrificial structure in the first trench includes: forming a sacrificial layer on the first etching stop layer and the connection metal structure, the sacrificial layer covering the first etching stop layer and filling the first trench; etching the sacrificial layer to remove the sacrificial layer covering the first etching stop layer and to retain the sacrificial layer in the first trench to form the sacrificial structure; the sacrificial structure fills the first trench and covers the connection metal structure.

[0011] Further, in the method for manufacturing the semiconductor device, the sacrificial layer is made of amorphous material or low-dielectric material.

[0012] Further, in the method for manufacturing the semiconductor device, the sacrificial layer is made of amorphous carbon. The forming the sacrificial layer includes using propylene (C3H6) as a carbon source and forming the sacrificial layer by a chemical vapor deposition method, the deposition temperature being 400°C to 600°C, the deposition pressure being 1 Torr to 10 Torr, and the deposition time being 5 to 20 minutes. The etching of the sacrifice layer comprises: etching the sacrifice layer by using oxygen plasma etching combined with argon physical etching, the oxygen flow rate is 100-300sccm, the argon flow rate is 30-80sccm, the power is 500-1000W, and the etching time is 30-90s.

[0013] Further, in the manufacturing method of the semiconductor device, the stack structure further comprises a second etching stop layer, and the forming of the stack structure on the first etching stop layer and the sacrifice structure comprises: The second etching stop layer is formed on the first etching stop layer and the sacrifice structure and is in contact with the first etching stop layer and the sacrifice structure.

[0014] Further, in the manufacturing method of the semiconductor device, the removing of the sacrifice structure comprises: performing oxygen plasma ashing, the oxygen flow rate is 200-400sccm, the power is 1000-1300W, and the ashing time is 150-190s.

[0015] In another aspect of the embodiments of the present application, a semiconductor device is provided, which is manufactured according to the above-mentioned manufacturing method of the semiconductor device, and comprises a substrate and a connection hole, the substrate comprises a plurality of connection metal structures, and the connection metal structures are exposed through the connection hole.

[0016] Further, in the semiconductor device, the semiconductor device further comprises a sacrifice structure, and the semiconductor device comprises a first region and a second region, the connection hole exposes the connection metal structure in the first region, and the sacrifice structure covers the connection metal structure in the second region.

[0017] The semiconductor device and the manufacturing method thereof provided by the present application, when manufacturing the connection hole, the sacrifice structure is covered on the connection metal structure, and then the sacrifice structure is removed, because the material of the sacrifice structure is different from that of the first etching stop layer, the sacrifice structure in the position corresponding to the connection hole can be completely removed, the size of the bottom of the connection hole is ensured, and thus the reliability and performance of the semiconductor device are not affected by the insufficient key size of the bottom of the deep hole of the semiconductor device, and the manufacturing yield of the semiconductor device is improved. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the following will briefly introduce the drawings needed to be used in the embodiments or the related art description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0019] Figure 1 A flow chart of a method for fabricating a semiconductor device in some embodiments; Figure 2 A cross-sectional view after forming a first etching stop layer in some embodiments; Figure 3 A cross-sectional view after forming a photoresist layer in some embodiments; Figure 4 A cross-sectional view after forming a first opening in some embodiments; Figure 5 A cross-sectional view after forming a trench structure in some embodiments; Figure 6 A cross-sectional view after forming a sacrificial layer in some embodiments; Figure 7 A cross-sectional view after forming a sacrificial structure in some embodiments; Figure 8 A cross-sectional view after forming a second photoresist layer on the stack structure in some embodiments; Figure 9 A cross-sectional view after etching the stack structure in some embodiments; Figure 10 A cross-sectional view of a semiconductor device in some embodiments; Figure 11 A cross-sectional view after forming a first etching stop layer in other embodiments; Figure 12 A cross-sectional view after forming a photoresist layer in other embodiments; Figure 13 A cross-sectional view after forming a first opening in other embodiments; Figure 14 A cross-sectional view after forming a trench structure in other embodiments; Figure 15 A cross-sectional view after forming a sacrificial layer in other embodiments; Figure 16 A cross-sectional view after forming a sacrificial structure in other embodiments; Figure 17 A cross-sectional view after forming a second photoresist layer on the stack structure in other embodiments; Figure 18 A cross-sectional view after etching the stack structure in other embodiments; Figure 19 A cross-sectional view of a semiconductor device in other embodiments. DETAILED DESCRIPTION

[0020] For the purpose of clarity, detailed descriptions of embodiments of the present application will be provided with reference to the accompanying drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the present application to those skilled in the art.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments of the present application belong. The terminology used in the description of the embodiments of the present application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of embodiments of the present application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0022] In the description of embodiments of the present application, it should be understood that the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", and the like, indicate an orientation or positional relationship based on the method or position shown in the drawings, and are only for the purpose of facilitating the description of embodiments of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of embodiments of the present application.

[0023] It can be understood that the terms "first region", "second region", etc. used in the present application can be used herein to describe different structural ranges, but these structural ranges are not limited by these terms. These terms are only used to distinguish the first structural range from another structural range. For example, without departing from the scope of the present application, the first region can be referred to as the second region, and similarly, the second region can be referred to as the first region. Both the first region and the second region belong to the structure of describing the present application, but they are not the same range.

[0024] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality of" is at least two, such as two, three, etc., unless otherwise specifically limited. In the description of the present application, the meaning of "several" is at least one, such as one, two, etc., unless otherwise specifically limited.

[0025] As used herein, the terms "substrate" and "base" mean and include a base material or construction of the materials of the transistor described herein. The substrate can be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures or regions formed thereon. The substrate can be a conventional silicon substrate or other bulk substrate including a layer of semiconductor material.

[0026] In this document, the term "comprising" is intended to mean that the compositions and methods include the recited elements, but not excluding others. "Consisting essentially of" when used herein in relation to a composition, means including the recited elements plus those that do not materially affect the basic and novel characteristic of the compositions or methods. "Consisting of" when used herein in relation to a composition, means including only the recited elements.

[0027] In this document, reference can be made to numerical intervals (i.e., numerical ranges), which, unless otherwise specifically stated, are considered to be continuous intervals of values, and include the two numerical endpoints (i.e., the minimum and maximum values) of the numerical interval, as well as every numerical value between the two numerical endpoints. Unless otherwise specifically stated, when a numerical interval is stated to refer only to integers within the numerical interval, this is equivalent to directly listing each integer within the numerical interval, including the two numerical endpoints, and every integer between the two numerical endpoints. When multiple numerical ranges are provided to describe a characteristic or property, these numerical ranges can be combined. In other words, unless otherwise specifically stated, numerical ranges disclosed herein are to be understood to include any and all sub-ranges of values falling within the indicated ranges. A "value" in a numerical interval can be any quantitative value, such as a number, a percentage, a ratio, etc. A "numerical interval" is intended to broadly include numerical interval types such as percentage intervals, ratio intervals, value intervals, etc.

[0028] In this document, when a method flow includes multiple steps, unless otherwise specifically stated, the execution of these steps is not strictly limited in order, and can be executed in other orders than described. Also, any step can include multiple sub-steps or stages, which do not necessarily have to be executed at the same time, but can be executed at different times, and the execution order does not necessarily have to be sequential, but can be executed in rotation or alternation or simultaneously with other steps or sub-steps or stages of other steps.

[0029] With the continuous reduction of the size of semiconductor devices, when etching into a deep hole, due to the micro-etching load effect, the critical dimension at the bottom of the deep hole is often insufficient, thereby causing the resistance value to be too large, or causing a broken circuit or a fuse phenomenon, affecting the reliability and performance of the semiconductor device. How to avoid the influence of the insufficient critical dimension at the bottom of the deep hole of the semiconductor device on the reliability and performance of the semiconductor device, thereby improving the yield of the manufacturing of the semiconductor device, is a technical problem to be solved at present.

[0030] In view of the above-mentioned technical problems, the present invention provides a semiconductor device and a method for manufacturing the same, which avoids the impact of insufficient critical dimensions at the bottom of deep holes on the reliability and performance of the semiconductor device, thereby improving the yield of semiconductor production.

[0031] The semiconductor devices and manufacturing methods of the present invention will be described below with reference to the accompanying drawings.

[0032] Please see Figure 1 , Figure 1 This is a schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. The method for manufacturing a semiconductor device includes: S1: A first etch barrier layer is formed on a semiconductor substrate, the semiconductor substrate including a plurality of interconnecting metal structures, the interconnecting metal structures being in contact with the first etch barrier layer.

[0033] Specifically, such as Figure 2 As shown, in this embodiment, the semiconductor substrate 300 includes a substrate (not shown), a transistor (not shown), and a plurality of interconnecting metal structures 310, which are spaced apart. The semiconductor device includes a first region I and a second region II, both of which have interconnecting metal structures 310 formed thereon. The first region I is the region where the interconnecting metal structures 310 are connected to other circuits, and the second region II is the region where the interconnecting metal structures 310 are not connected to other circuits. A first etch barrier layer 301 covers the semiconductor substrate 300 and is in contact with the interconnecting metal structures 310. The first etch barrier layer 301 is a carbon-doped silicon dioxide layer, with a carbon doping concentration between 5% and 20%. Carbon doping can reduce the dielectric constant of the silicon dioxide layer and improve the performance of the semiconductor device. In this embodiment, the thickness of the first etch barrier layer 301 can be between 50 nm and 300 nm, and it can be formed by chemical vapor deposition, for example, using tetraethoxysilane (TEOS) and methane (CH4) as precursors, and deposited at a temperature of 300°C to 400°C to form the first etch barrier layer 301.

[0034] S2: A first trench is formed in the first etch barrier layer, so that the connecting metal structure is exposed through the first trench.

[0035] Specifically, in one embodiment of the present invention, forming a first trench in the first etch barrier layer includes: S21: Coating a photoresist material onto the first etch barrier layer to form a first photoresist layer.

[0036] like Figure 3As shown, a first photoresist layer 302 is formed by coating a photoresist material onto the first etch barrier layer 301. The photoresist material can be either positive or negative, and the choice can be made according to specific process requirements. In this embodiment, the photoresist material forming the first photoresist layer 302 is a negative photoresist material, and the thickness of the first photoresist layer 302 is 0.5 μm to 1.5 μm. The photoresist material is coated onto the first etch barrier layer 301 by spin coating at a speed of 2000 rpm to 4000 rpm for 30 to 60 seconds. The photoresist material completely covers the first etch barrier layer 301, thereby forming the first photoresist layer 302 on the first etch barrier layer 301.

[0037] S22: A first notch is formed in the first photoresist layer, the first notch being located above the connecting metal structure in the first region I, so that the first etch barrier layer located above the connecting metal structure in the first region I is exposed through the first notch.

[0038] Specifically, such as Figure 4 As shown, the first photoresist layer 302 is exposed by the first photomask. The area of ​​the first photomask corresponding to the connecting metal structure 310 in the first region I is the light-transmitting area, and the remaining areas are the light-shielding areas.

[0039] The first photoresist layer 302 is exposed using a first photomask. The light source for exposure is an i-ray or deep ultraviolet light source, and the exposure dose is 20 mJ / cm² to 60 mJ / cm². Then, the exposed first photoresist layer 302 is developed to form the first notch 312, which is located above the connecting metal structure 310 in the first region I. Specifically, in this example, the photoresist material forming the first photoresist layer 302 is a negative photoresist material. The exposed first photoresist layer 302 is developed using a developing solution, which is a liquid that can remove the first photoresist layer 302 irradiated by the light source during the exposure process, such as tetramethylammonium hydroxide solution. The development time is 30 seconds to 90 seconds. Furthermore, the area of ​​the first photomask corresponding to the connecting metal structure 310 of the first region I is a light-transmitting area, and the remaining areas are light-shielding areas. Therefore, during the exposure process, the light source only shines through the light-transmitting area of ​​the first photomask onto the first photoresist layer 302 located above the connecting metal structure 310 of the first region I. After development, the first photoresist layer 302 located above the connecting metal structure 310 of the first region I is removed, thereby forming a first notch 312, so that the first etching barrier layer 301 located above the connecting metal structure 310 of the first region I is exposed through the first notch 312.

[0040] S23: Using the first photoresist layer as a shield, the first etching barrier layer is etched through the first notch to form the first trench located in the first region I.

[0041] Specifically, such as Figure 4 and Figure 5 As shown, the first photoresist layer 302 after development is used as a shield to etch the first etch barrier layer 301 through the first notch 312. Since the first etch barrier layer 301 below the first notch 312 is not shielded by the first photoresist layer 302, the part of the first etch barrier layer 301 exposed to the first notch 312 is etched away to form the first trench 311, thereby exposing the connecting metal structure 310 below the first trench 311.

[0042] In this embodiment, since the area of ​​the first photomask corresponding to the connecting metal structure 310 in the first region I is a light-transmitting area and the remaining areas are light-shielding areas, after exposure and development, only the first photoresist layer 302 located above the connecting metal structure 310 in the first region I is removed to form a first notch 312. Furthermore, after etching, the portion of the first etch barrier layer 301 located above the connecting metal structure 310 in the first region I is removed to form a first trench 311, thereby exposing the connecting metal structure 310 below the first trench 311. Further, in this embodiment, two first trenches 311 are formed in the first region I. Of course, in other embodiments, the number of first trenches 311 can be adjusted according to actual needs; for example, the number of first trenches 311 may be one or more.

[0043] Furthermore, the first etch barrier layer 301 can be etched using either dry etching or wet etching processes. In some embodiments of the present invention, reactive ion etching or inductively coupled plasma etching equipment is used to etch the first etch barrier layer 301; the etching gas can be a fluorine-containing gas, such as a mixture of CF4, CHF3, or C4F8 with oxygen; the chamber pressure of the etching equipment is maintained at 10 mTorr to 50 mTorr; the radio frequency power is 500 W to 1500 W; and the etching time is adjusted according to the thickness of the barrier layer, for example, 30 seconds to 120 seconds.

[0044] After the first trench 311 is formed, the first photoresist layer 302 is removed. Specifically, the first photoresist layer 302 is removed by oxygen plasma ashing or wet adhesive removal. In some embodiments, oxygen plasma ashing is used to remove the first photoresist layer 302, with an oxygen flow rate of 50 sccm to 200 sccm, a power of 300 W to 800 W, and a processing time of 60 seconds to 180 seconds.

[0045] S3: A sacrificial structure is formed in the first trench, the sacrificial structure covering the connecting metal structure.

[0046] Specifically, such as Figure 6As shown, a sacrificial layer 303a is formed on the first etching stop layer 301 and the connection metal structure 310, and fills the first trench 311. The material of the sacrificial layer 303a is amorphous material or other low dielectric material, such as SiC(OH)3. In some embodiments of the present application, the material of the sacrificial layer 303a is amorphous carbon, and the sacrificial layer 303a is formed by low pressure chemical vapor deposition method. In some embodiments of the present application, propylene (C3H6) is used as carbon source, the deposition temperature is 400-600°C, the deposition pressure is 1-10 Torr, and the deposition time is 5-20 minutes, so as to ensure that the first trench 311 is completely filled with the sacrificial layer 303a.

[0047] Further, the sacrificial layer 303a is etched to remove the sacrificial layer 303a covering the first etching stop layer 301, and the sacrificial layer 303a in the first trench 311 is reserved, so as to form a sacrificial structure 303. The sacrificial structure 303 fills the first trench 311 and covers the connection metal structure 310, as shown. Figure 7 Specifically, in some embodiments of the present application, when the sacrificial layer 303a is etched, the oxygen plasma etching combined with argon physical etching is used to etch the sacrificial layer 303a, the oxygen flow is 100-300 sccm, the argon flow is 30-80 sccm, the power is 500-1000 W, and the etching time is 30-90 seconds. The combination of oxygen plasma etching and argon physical etching can improve the anisotropy of etching, so that the sacrificial layer 303a except in the first trench 311 is more uniformly etched and removed.

[0048] S4: forming a stack structure on the first etching stop layer and the sacrificial structure.

[0049] The stack structure includes multiple low dielectric layers, which are used to meet the requirements of semiconductor devices on reducing the capacitance of interconnection layer, improving the signal transmission speed and reliability. Specifically, in some embodiments of the present application, as shown, Figure 8 As shown, the stack structure includes a second etching stop layer 313. After the formation of the sacrificial structure 303, the second etching stop layer 313 covering the first etching stop layer 301 and the sacrificial structure 303 is formed on the first etching stop layer 301 and the sacrificial structure 303, and the formation material of the second etching stop layer 313 is the same as that of the first etching stop layer 301. Of course, in some other embodiments of the present application, the second etching stop layer can also not be provided.

[0050] Further, the stack structure includes a first dielectric layer 304. In some embodiments of the present application, as shown, Figure 8As shown, the first dielectric layer 304 is formed on the second etch stop layer 313. Since the first dielectric layer 304 is formed on the second etch stop layer 313 which is formed of the same material, the uniformity of the first dielectric layer 304 can be further improved. Of course, in other embodiments of the present application, the first dielectric layer can also be formed directly on the first etch stop layer and the sacrificial structure. The first dielectric layer 304 is a TEOS layer formed by chemical vapor deposition (CVD) at a temperature between 500°C and 700°C. An organic silicon source material, such as tetraethylorthosilicate (TEOS), is delivered in a gaseous form to a CVD reaction chamber. The TEOS molecules undergo thermal decomposition and redox reactions and deposit a TEOS layer on the second etch stop layer 313.

[0051] Further, the stack structure further includes a second dielectric layer 305, a third etch stop layer 314, and a first anti-reflective coating 306. The second dielectric layer 305 is an ultra-low-k (ULK) layer. The third etch stop layer 314 is formed of the same material system (e.g., silicon nitride SiN or silicon oxynitride SiON) as the first etch stop layer 301 to provide effective diffusion barrier and etch selectivity. The first anti-reflective coating 306 is formed by a chemical vapor deposition technique. The first anti-reflective coating 306 is a silicon nitride-based anti-reflective coating.

[0052] Further, the stack structure further comprises an auxiliary layer, which is formed on the first anti-reflective coating 306. Specifically, in some embodiments of the present application, a photoresist material is coated on the auxiliary layer to form a second photoresist layer (not shown); the second photoresist layer is exposed through a second mask, the second mask has a light-transmitting area corresponding to the connecting metal structure 310 of the first region I and the second region II and a light-blocking area corresponding to other areas; the exposed second photoresist layer is developed to form a second gap (not shown), which is located above the connecting metal structure 310 of the first region I and the second region II; the auxiliary layer is etched through the second gap with the second photoresist layer as a shield to form a second groove 319 in the auxiliary layer, which is located above the connecting metal structure 310 of the first region I and the second region II. Specifically, in the present example, the photoresist material used to form the second photoresist layer is a negative photoresist material, and a developing solution is used to develop the exposed second photoresist layer. The developing solution is a liquid that can remove the second photoresist layer irradiated by a light source during the exposure process. Further, the second mask has a light-transmitting area corresponding to the connecting metal structure 310 of the first region I and the second region II and a light-blocking area corresponding to other areas. Therefore, during the exposure process, the light source irradiates the second photoresist layer located above the connecting metal structure 310 of the first region I and the second region II through the light-transmitting area of the second mask, and the second photoresist layer located above the connecting metal structure 310 of the first region I and the second region II is removed after development to form the second gap.

[0053] Further, the auxiliary layer comprises a first auxiliary layer 307 and a second auxiliary layer 315. Specifically, the first auxiliary layer 307 is formed on the first anti-reflective coating 306, and the first auxiliary layer 307 can be a titanium nitride (TiN) layer formed by a physical vapor deposition method. Then, the second auxiliary layer 315 is formed on the first auxiliary layer 307, and the second auxiliary layer 315 can be an anti-reflective layer to further reduce the influence of light reflection on the semiconductor device process. The material of the second auxiliary layer 315 can be the same as that of the first anti-reflective coating 306.

[0054] Specifically, coating a photoresist material on the auxiliary layer to form a second photoresist layer comprises coating a photoresist material on the second auxiliary layer 315 to form a second photoresist layer.

[0055] Specifically, etching the auxiliary layer through the second notch while using the second photoresist layer as a shield to form the second trench includes: sequentially etching the second auxiliary layer 315 and the first auxiliary layer 307 through the second notch while using the second photoresist layer as a shield to form a second trench 319 penetrating the second auxiliary layer 315 and the first auxiliary layer 307. After forming the second trench 319, the second photoresist layer is removed by oxygen plasma ashing.

[0056] Furthermore, the laminated structure also includes a filler layer 308 and a second antireflective coating 309. The filler layer 308 covers the second auxiliary layer 315 and the first antireflective coating 306, and the second antireflective coating 309 covers the filler layer 308. The filler layer 308 can be a carbon coating, such as SOC (spin-on-carbon), and the second antireflective coating 309 can be a silicon-containing antireflective coating. The constituent material of the second antireflective coating 309 can also be the same as that of the first antireflective coating 306.

[0057] S5, a third trench is formed in the stacked structure, so that the sacrificial structure is exposed through the third trench.

[0058] Specifically, forming the third trench in the stacked structure includes: S51: A third photoresist layer 316 is formed by coating a photoresist material onto the laminated structure. In some embodiments of the present invention, the third photoresist layer 316 is formed on and covers the second anti-reflective coating 309. The photoresist material forming the third photoresist layer 316 can be either positive or negative photoresist, selected according to specific process requirements. In this embodiment, the photoresist material forming the third photoresist layer 316 is a negative photoresist material.

[0059] S52: Expose the third photoresist layer using a third photomask.

[0060] Specifically, such as Figure 8 As shown, the third photoresist layer 316 is exposed using a third photomask. The area of ​​the third photomask corresponding to the connecting metal structure 310 in the first region I is a light-transmitting area, and the remaining areas are light-shielding areas. Furthermore, the pattern of the third photomask is the same as the pattern of the first photomask, or the pattern of the third photomask is different from the pattern of the first photomask. When the pattern of the third photomask is the same as the pattern of the first photomask, the third photomask and the first photomask are the same photomask, which further reduces the manufacturing cost of semiconductor devices.

[0061] S53: Develop the exposed third photoresist layer to form a third notch, the third notch being located above the connecting metal structure in the first region I.

[0062] Specifically, the third photoresist layer 316 after exposure is developed. Since the third mask corresponds to the transparent area of the connecting metal structure 310 in the first area I, and the rest is the light shielding area, the exposed third photoresist layer 316 is removed, forming a third gap 317, and the third gap 317 is located above the connecting metal structure in the first area I. The second anti-reflective coating 309 is exposed through the third gap 317.

[0063] S54: etching the stack structure through the third gap with the third photoresist layer as a shield, and forming the third trench in the stack structure.

[0064] Specifically, etching the stack structure through the third gap with the third photoresist layer as a shield, and forming the third trench in the stack structure includes: etching the second anti-reflective coating 309, the filling layer 308, the auxiliary layer, the first anti-reflective coating 306, the third etching stop layer 314, the second dielectric layer 305, the first dielectric layer 304 and the second etching stop layer 313 in turn through the third gap 317 with the third photoresist layer 316 as a shield. Since the stack structure below the third gap 317 is not shielded by the third photoresist layer 316, the part of the stack structure exposed to the third gap 317 is etched and removed, forming a third trench 320, and the third trench 320 is located above the connecting metal structure 310 in the first area I, so that the sacrificial structure 303 is exposed through the third trench 320, and the second area II does not form a third trench, and the connecting metal structure 310 in the second area II is covered with a stack structure.

[0065] Further, as shown in Figure 9 , after forming the third trench, it further includes: removing the third photoresist layer 316 and the etched second anti-reflective coating 309, filling layer 308, second auxiliary layer 315.

[0066] S6, removing the sacrificial structure to form a connecting hole, so that the connecting metal structure is exposed through the connecting hole.

[0067] Specifically, as shown in Figure 10 , the sacrificial structure 303 is removed to form a connecting hole 318 by connecting the first trench 311 and the third trench 320. Since the sacrificial structure 303 covers the connecting metal structure 310, after removing the sacrificial structure 303, the connecting metal structure 310 is exposed through the connecting hole 318.

[0068] Further, the first region I forms a connection hole 318 after the removal of the sacrificial structure 303, thus the connection hole 318 only exposes the connection metal structure 310 in the first region I, and the connection metal structure 310 in the first region I can be connected with other lines through the connection hole 318; the second region II does not form a third trench, and the second region II does not form a connection hole, and the connection metal structure 310 in the second region II is covered by the stack structure, thus the connection metal structure 310 in the second region II is not connected with other lines.

[0069] Further, the removal of the sacrificial structure 303 includes: firstly, oxygen plasma ashing is performed, the oxygen flow is 200-400sccm, the power is 1000-1300W, and the processing time is 150-190 seconds; then, wet cleaning is performed, a mixed solution of sulfuric acid and hydrogen peroxide (SPM, H2SO4:H2O2=3:1-8:1) is used to clean at 80-150℃ for tens of minutes to remove the residues of the sacrificial structure 303.

[0070] In the manufacturing method of the semiconductor device, when the connection hole is made, the sacrificial structure is covered on the connection metal structure, and then the sacrificial structure is removed, because the material of the sacrificial structure is different from the first etching stop layer, thus the sacrificial structure at the position corresponding to the connection hole can be completely removed, the size of the bottom of the connection hole is ensured, thus the insufficient key size of the deep hole bottom of the semiconductor device is avoided, the reliability and performance of the semiconductor device are affected, and the production yield of the semiconductor device is improved.

[0071] Please refer to Figures 11 to 19 , Figures 11 to 19 the manufacturing method of the semiconductor device of another embodiment of the present application, in the embodiment, the manufacturing method of the semiconductor device includes: S1: forming a first etching stop layer on a semiconductor substrate, the semiconductor substrate includes a plurality of connection metal structures, and the connection metal structures are in contact with the first etching stop layer.

[0072] Specifically, as Figure 11As shown, in this embodiment, the semiconductor substrate 400 includes a substrate (not shown), a transistor (not shown), and a plurality of interconnecting metal structures 410, which are spaced apart. The semiconductor device includes a first region I and a second region II, both of which have interconnecting metal structures 410 formed thereon. The first region I is the region where the interconnecting metal structures 410 are connected to other circuits, and the second region II is the region where the interconnecting metal structures 410 are not connected to other circuits. A first etch barrier layer 401 covers the semiconductor substrate 400 and is in contact with the interconnecting metal structures 410. The first etch barrier layer 401 is a carbon-doped silicon dioxide layer, with a carbon doping concentration between 5% and 20%. Carbon doping can reduce the dielectric constant of the silicon dioxide layer and improve the performance of the semiconductor device. In this embodiment, the thickness of the first etch barrier layer 401 can be between 50 nm and 300 nm, and it can be formed by chemical vapor deposition, for example, using tetraethoxysilane (TEOS) and methane (CH4) as precursors, and deposited at a temperature of 300°C to 400°C to form the first etch barrier layer 401.

[0073] S2: A first trench is formed in the first etch barrier layer, so that the connecting metal structure is exposed through the first trench.

[0074] Specifically, in one embodiment of the present invention, forming a first trench in the first etch barrier layer includes: S21: Coating a photoresist material onto the first etch barrier layer to form a first photoresist layer.

[0075] like Figure 12 As shown, a first photoresist layer 402 is formed by coating a photoresist material onto the first etch barrier layer 401. The photoresist material can be either positive or negative, and the choice can be made according to specific process requirements. In this embodiment, the photoresist material forming the first photoresist layer 402 is a negative photoresist material, and the thickness of the first photoresist layer 402 is 0.5 μm to 1.5 μm. The photoresist material is coated onto the first etch barrier layer 401 by spin coating at a speed of 2000 rpm to 4000 rpm for 30 to 60 seconds. The photoresist material completely covers the first etch barrier layer 401, thereby forming the first photoresist layer 402 on the first etch barrier layer 401.

[0076] S22: A first notch is formed in the first photoresist layer, the first notch being located above the connecting metal structure of the first region I and the second region II, so that the first etch barrier layer located above the connecting metal structure of the first region I and the second region II is exposed through the first notch.

[0077] Specifically, such as Figure 13As shown, the first photoresist layer 402 is exposed by a fourth mask, the fourth mask has a transparent region corresponding to the region of the connecting metal structure 410 in the first region I and the second region II, and has a shielding region corresponding to the other region. The light source for exposure is i-line or deep ultraviolet light source, and the exposure dose is 20 mJ / cm2to 60 mJ / cm2. Then, the first photoresist layer 402 after exposure is developed to form the first gap 412, and the first gap 412 is located above the connecting metal structure 410 in the first region I and the second region II. Specifically, in this example, the photoresist material forming the first photoresist layer 402 is negative photoresist material, and the first photoresist layer 402 after exposure is developed using a developing solution, such as tetramethylammonium hydroxide solution, and the developing time is 30 seconds to 90 seconds. Further, the fourth mask has a transparent region corresponding to the region of the connecting metal structure 410 in the first region I and the second region II, and has a shielding region corresponding to the other region. Therefore, in the exposure process, the light source transmits through the transparent region of the fourth mask to irradiate the first photoresist layer 402 above the connecting metal structure 410 in the first region I and the second region II, and the first photoresist layer 402 above the connecting metal structure 410 in the first region I and the second region II is removed after development, thereby forming the first gap 412, and the first etching stop layer 401 above the connecting metal structure 410 in the first region I and the second region II is exposed through the first gap 412.

[0078] S23: etching the first etching stop layer through the first gap with the first photoresist layer as a shield to form the first groove in the first region I and the second region II.

[0079] Specifically, as shown in Figure 13 and 14 the first etching stop layer 401 is etched through the first gap 412 with the developed first photoresist layer 402 as a shield. Since the first etching stop layer 401 below the first gap 412 is not shielded by the first photoresist layer 402, the part of the first etching stop layer 401 exposed to the first gap 412 is etched and removed, thereby forming the first groove 411 and exposing the connecting metal structure 410 below the first groove 411.

[0080] In the embodiment, since the fourth mask corresponds to the region of the connecting metal structure 410 in the first region I and the second region II as the light-transmitting region and the other regions as the light-blocking region, after exposure and development, the first photoresist layer 402 above the connecting metal structure 410 in the first region I and the second region II is removed to form the first gap 412; then, after etching, the part of the first etching stop layer 401 above the connecting metal structure 410 in the first region I and the second region II is removed, and the first groove 411 is formed in the first region I and the second region II, and the connecting metal structure 410 in the first region I and the second region II is exposed through the first groove 411 in the first region I and the second region II. Further, in the embodiment, two first grooves 411 are formed in the first region I, and one first groove 411 is formed in the second region II. Of course, in other embodiments, the number of the first grooves 411 can be adjusted according to actual needs, for example, one or three or more grooves are formed in the first region I, and two or more grooves are formed in the second region II.

[0081] Further, the first etching stop layer 401 can be etched by dry etching or wet etching process. In some embodiments of the present application, the first etching stop layer 401 is etched by a reactive ion etching or an inductively coupled plasma etching device; the etching gas can be selected from fluorine-containing gas, such as CF4, CHF3 or C4F8 mixed with oxygen, the cavity pressure of the etching device is maintained at 10 mTorr to 50 mTorr, the radio frequency power is 500 W to 1500 W, and the etching time is adjusted according to the thickness of the stop layer, for example, 30 seconds to 120 seconds.

[0082] After the first groove 411 is formed, the first photoresist layer 402 is removed. Specifically, the remaining first photoresist layer 402 is removed by oxygen plasma ashing or wet adhesive remover. In some embodiments, the remaining first photoresist layer 402 is removed by oxygen plasma ashing, the oxygen flow is 50 sccm to 200 sccm, the power is 300 W to 800 W, and the processing time is 60 seconds to 180 seconds.

[0083] S3: forming a sacrificial structure in the first groove, the sacrificial structure covering the connecting metal structure.

[0084] Specifically, as shown in FIG. 4c, the first groove 411 is formed in the first region I and the second region II, and the connecting metal structure 410 in the first region I and the second region II is exposed through the first groove 411 in the first region I and the second region II. Figure 15As shown, a sacrificial layer 403a is formed on the first etch barrier layer 401 and the connecting metal structure 410. The sacrificial layer 403a covers the first etch barrier layer 401 and the connecting metal structure 410 and fills the first trench 411. The sacrificial layer 403a is composed of an amorphous material or a low-dielectric material, such as SiC(OH)3. Further, the material of the sacrificial layer 403a is amorphous carbon. The sacrificial layer 403a is formed by a low-pressure chemical vapor deposition method. In some embodiments of the present invention, propylene (C3H6) is used as the carbon source, the deposition temperature is 400°C to 600°C, the deposition pressure is 1 Torr to 10 Torr, and the deposition time is 5 to 20 minutes to ensure that the first trench 411 is completely filled by the sacrificial layer 403a.

[0085] Further, the sacrificial layer 403a is etched to remove the sacrificial layer 403a covering the first etch barrier layer 401, while retaining the sacrificial layer 403a within the first trench 411, thereby forming a sacrificial structure 403. The sacrificial structure 403 fills the first trench 411 and covers the connecting metal structure 410; since both the first region I and the second region II form the first trench 411, the connecting metal structures 410 located in the first region I and the second region II are covered with sacrificial structures 403, such as... Figure 16 As shown. Specifically, in some embodiments of the present invention, when etching the sacrificial layer 403a, oxygen plasma etching combined with argon physical etching is used to etch the sacrificial layer 403a. The oxygen flow rate is 100 to 300 sccm, the argon flow rate is 30 to 80 sccm, the power is 500 to 1000 W, and the etching time is 30 to 90 seconds. The combined etching method of oxygen plasma etching and argon physical etching can improve the anisotropy of etching, so that the sacrificial layer 403a, except for the area located in the first trench 411, is etched away more uniformly.

[0086] S4: A stacked structure is formed on the first etch barrier layer and the sacrificial structure.

[0087] The stacked structure includes multiple low-dielectric layers to meet the requirements of semiconductor devices for reduced interconnect layer capacitance, increased signal transmission speed, and improved reliability. Specifically, in some embodiments of the present invention, such as... Figure 17 As shown, the stacked structure includes a second etch barrier layer 413. After the sacrificial structure 403 is formed, a second etch barrier layer 413 is formed on the first etch barrier layer 401 and the sacrificial structure 403, covering the first etch barrier layer 401 and the sacrificial structure 403. The forming material of the second etch barrier layer 413 is the same as the forming material of the first etch barrier layer 401. Of course, in some other embodiments of the present invention, the second etch barrier layer may not be provided.

[0088] Furthermore, the stacked structure includes a first dielectric layer 404. In some embodiments of the present invention, such as... Figure 17 As shown, the first dielectric layer 404 is formed on the second etch barrier layer 413. Since the first dielectric layer 404 is formed on the second etch barrier layer 413 made of the same material, the uniformity of the first dielectric layer 404 can be further improved. Of course, in other embodiments of the present invention, the first dielectric layer can also be directly formed on the first etch barrier layer and the sacrificial structure. The first dielectric layer 404 is a TEOS layer, formed by chemical vapor deposition (CVD) at a temperature between 500°C and 700°C. An organosilicon source material, such as tetraethoxysilane (TEOS), is transported in gaseous form to the CVD reaction chamber, where TEOS molecules undergo thermal decomposition and redox reactions, and a TEOS layer is deposited on the second etch barrier layer 413.

[0089] Furthermore, the stacked structure also includes a second dielectric layer 405, a third etch barrier layer 414, and a first anti-reflective coating 406. The second dielectric layer 405 is an ultra-low dielectric constant (Ultra-Low-K, ULK) layer. The third etch barrier layer 414 uses the same material system as the first etch barrier layer 401 (such as silicon nitride SiN or silicon oxynitride SiON) to provide effective diffusion blocking and etch selectivity. The first anti-reflective coating 406 is formed by chemical vapor deposition and is a silicon nitride-based anti-reflective coating.

[0090] Further, the stack structure further comprises an auxiliary layer, which is formed on the first anti-reflective coating 406. Specifically, in some embodiments of the present application, a photoresist material is coated on the auxiliary layer to form a second photoresist layer (not shown); the second photoresist layer is exposed through a fifth mask, the fifth mask has a light-transmitting area corresponding to the area of the connecting metal structure 410 of the first region I and the second region II and a light-blocking area corresponding to the other areas; the exposed second photoresist layer is developed to form a second gap (not shown), which is located above the connecting metal structure 410 of the first region I and the second region II; the auxiliary layer is etched through the second gap with the second photoresist layer as a shield to form a second groove 419 above the connecting metal structure 410 of the first region I and the second region II. Specifically, in the present example, the photoresist material used to form the second photoresist layer is a negative photoresist material, and a developing solution is used to develop the exposed second photoresist layer. Further, the fifth mask has a light-transmitting area corresponding to the area of the connecting metal structure 410 of the first region I and the second region II and a light-blocking area corresponding to the other areas. Therefore, during the exposure process, the light source transmits through the light-transmitting area of the fifth mask to irradiate the second photoresist layer above the connecting metal structure 410 of the first region I and the second region II, and the second photoresist layer above the connecting metal structure 410 of the first region I and the second region II is removed after development to form the second gap.

[0091] Further, the pattern of the fifth mask is the same as or different from the pattern of the fourth mask. When the pattern of the fifth mask is the same as the pattern of the fourth mask, the fifth mask is the same as the fourth mask, further reducing the manufacturing cost of the semiconductor device.

[0092] Further, the auxiliary layer comprises a first auxiliary layer 407 and a second auxiliary layer 415. Specifically, the first auxiliary layer 407 is formed on the first anti-reflective coating 406, and the first auxiliary layer 407 can be a titanium nitride (TiN) layer formed by a physical vapor deposition method. Then, the second auxiliary layer 415 is formed on the first auxiliary layer 407, and the second auxiliary layer 415 can be an anti-reflective layer, further reducing the influence of light reflection on the semiconductor device process. The material constituting the second auxiliary layer 415 can be the same as the material constituting the first anti-reflective coating 406.

[0093] Specifically, coating a photoresist material on the auxiliary layer to form a second photoresist layer comprises coating a photoresist material on the second auxiliary layer 415 to form a second photoresist layer.

[0094] Specifically, etching the auxiliary layer through the second notch while using the second photoresist layer as a shield to form the second trench includes: sequentially etching the second auxiliary layer 415 and the first auxiliary layer 407 through the second notch while using the second photoresist layer as a shield to form a second trench 419 penetrating the second auxiliary layer 415 and the first auxiliary layer 407. After forming the second trench 419, the second photoresist layer is removed by oxygen plasma ashing.

[0095] Furthermore, the laminated structure also includes a filler layer 408 and a second antireflective coating 409. The filler layer 408 covers the second auxiliary layer 415 and the first antireflective coating 406, and the second antireflective coating 409 covers the filler layer 408. The filler layer 408 can be a carbon coating, such as SOC (spin-on-carbon), and the second antireflective coating 409 can be a silicon-containing antireflective coating. The constituent material of the second antireflective coating 409 can also be the same as that of the first antireflective coating 406.

[0096] S5, a third trench is formed in the stacked structure, so that the sacrificial structure is exposed through the third trench.

[0097] Specifically, forming the third trench in the stacked structure includes: S51: A third photoresist layer 416 is formed by coating a photoresist material onto the stacked structure. In some embodiments of the present invention, the third photoresist layer 416 is formed on and covers the second anti-reflective coating 409. The photoresist material forming the third photoresist layer 416 can be either positive or negative photoresist, selected according to specific process requirements. In this embodiment, the photoresist material forming the third photoresist layer 416 is a negative photoresist material.

[0098] S52: Expose the third photoresist layer using a third photomask.

[0099] Specifically, such as Figure 17 As shown, the third photoresist layer 416 is exposed by the sixth photomask. The area of ​​the sixth photomask corresponding to the connecting metal structure 410 of the first region I is the light-transmitting area, and the remaining areas are the light-shielding areas.

[0100] S53: Develop the exposed third photoresist layer to form a third notch, the third notch being located above the connecting metal structure in the first region I.

[0101] Specifically, the third photoresist layer 416 after exposure is developed. Since the sixth mask corresponds to the transparent area of the connecting metal structure 410 in the first area I, and the rest is the light shielding area, the exposed third photoresist layer 416 is removed, forming a third gap 417, and the third gap 417 is located above the connecting metal structure in the first area I. The second anti-reflective coating 409 is exposed through the third gap 417.

[0102] S54: etching the stack structure through the third gap with the third photoresist layer as a shield, and forming the third trench in the stack structure.

[0103] Specifically, etching the stack structure through the third gap with the third photoresist layer as a shield, and forming the third trench in the stack structure includes: etching the second anti-reflective coating 409, the filling layer 408, the auxiliary layer, the first anti-reflective coating 406, the third etching stop layer 414, the second dielectric layer 405, the first dielectric layer 404 and the second etching stop layer 413 in sequence through the third gap 417 with the third photoresist layer 416 as a shield. Since the stack structure below the third gap 417 is not shielded by the third photoresist layer 416, the part of the stack structure exposed to the third gap 417 is etched and removed, forming a third trench 420 above the connecting metal structure 410 in the first area I, so that the sacrificial structure 403 is exposed through the third trench 420, and the second area II does not form a third trench, and the connecting metal structure 410 in the second area II is covered by the stack structure and the sacrificial structure 403.

[0104] Further, as shown in Figure 18 , after etching the stack structure, it further includes: removing the third photoresist layer 416 and the etched second anti-reflective coating 409, filling layer 408 and second auxiliary layer 415.

[0105] S6, removing the sacrificial structure to form a connecting hole, so that the connecting metal structure is exposed through the connecting hole.

[0106] Specifically, as shown in Figure 19 , the sacrificial structure 403 is removed to form a connecting hole 418 in communication with the first trench 411 and the third trench 420. Since the sacrificial structure 403 covers the connecting metal structure 410, after removing the sacrificial structure 403, the connecting metal structure 410 is exposed through the connecting hole 418.

[0107] Further, the first region I forms a connection hole 418 after the sacrifice structure 403 is removed, and thus the connection hole 418 exposes only the connection metal structure 410 in the first region I, and the connection metal structure 410 in the first region I can be connected to other lines through the connection hole 418; the second region II does not form a third groove, and thus the second region II does not form a connection hole, and the connection metal structure 410 in the second region II is covered by the sacrifice structure 403 and the stack structure, and thus the connection metal structure 410 in the second region II is not connected to other lines.

[0108] Further, the removing of the sacrifice layer 403 includes: first, oxygen plasma ashing is performed, the oxygen flow is 200-400sccm, the power is 1000-1300W, and the processing time is 150-190 seconds; then, wet cleaning is performed, a mixed solution of sulfuric acid and hydrogen peroxide (SPM, H2SO4:H2O2=3:1-8:1) is used to clean at 80-150℃ for tens of minutes to remove the residue of the sacrifice structure 403.

[0109] In the manufacturing method of the semiconductor device, when the connection hole is made, the sacrifice structure is covered on the connection metal structure, and then the sacrifice structure is removed, and thus the sacrifice structure at the position corresponding to the connection hole can be completely removed due to the difference between the material of the sacrifice structure and the first etching stop layer, and the size of the bottom of the connection hole is ensured, so that the insufficient key size of the deep hole bottom of the semiconductor device is avoided, and the reliability and performance of the semiconductor device are affected, and the production yield of the semiconductor device is improved.

[0110] The application also provides a semiconductor device manufactured by the manufacturing method of the semiconductor device, and the same or corresponding parts in the manufacturing method of the semiconductor device will not be described here.

[0111] The application provides a semiconductor device, which comprises a semiconductor substrate, the semiconductor substrate comprises a substrate (not shown), a transistor (not shown) and a plurality of connection metal structures, a connection hole is formed on the semiconductor substrate, and the connection metal structure is exposed through the connection hole. The first region I is a connection region of the connection metal structure and other lines, and the second region II is a connection region of the connection metal structure and other lines. The connection metal structure is exposed through the connection hole.

[0112] For details, please refer to Figure 10In an embodiment of the present application, the semiconductor device includes a semiconductor substrate 300 and a connection hole 318, the semiconductor substrate 300 includes a substrate (not shown), a transistor (not shown) and a plurality of connection metal structures 310, the connection metal structures 310 are exposed through the connection hole 318. Further, the semiconductor device includes a first region I and a second region II, the first region I is formed with the connection hole 318, the connection metal structures 310 in the first region I are exposed through the connection hole 318, and the connection metal structures 310 in the first region I are connected with other circuits through the connection hole 318; the second region II is not formed with the connection hole, and the connection metal structures 310 in the second region II are not connected with other circuits.

[0113] Further, please refer to Figure 19 In another embodiment of the present application, the semiconductor device includes a semiconductor substrate 400, a connection hole 418 and a sacrificial structure 403, the semiconductor substrate 400 includes a substrate (not shown), a transistor (not shown) and a plurality of connection metal structures 410, the semiconductor device includes a first region I and a second region II, the first region I is formed with the connection hole 418, the connection metal structures 410 in the first region I are exposed through the connection hole 418, and the connection metal structures 410 in the first region I are connected with other circuits through the connection hole 418; the second region II is not formed with the connection hole, and the connection metal structures 410 in the second region II are covered with the sacrificial structure 403, and the connection metal structures 410 in the second region II are not connected with other circuits. The sacrificial structure 403 is made of amorphous material or other low dielectric material, such as SiC(OH)3.

[0114] In the above semiconductor device, when the connection hole is made, the sacrificial structure is covered on the connection metal structure, and then the sacrificial structure is removed, because the material of the sacrificial structure is different from the first etching stop layer, thus the sacrificial structure in the position corresponding to the connection hole can be completely removed, and the size of the bottom of the connection hole is ensured, thus the insufficient key size of the bottom of the deep connection hole of the semiconductor device is avoided, and the reliability and performance of the semiconductor device are affected, and the yield of the semiconductor device is improved.

[0115] In some embodiments, the semiconductor device is made by the above method for making the semiconductor device.

[0116] It should be pointed out finally that the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit the same; and although the present application has been described in detail with reference to the foregoing embodiments, it should be appreciated by those skilled in the art that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features thereof can be replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The manufacturing method comprises: forming a first etching stop layer on a semiconductor substrate, the semiconductor substrate comprising a plurality of connecting metal structures, the connecting metal structures being in contact with the first etching stop layer; forming a first trench in the first etching stop layer, so that the connecting metal structures are exposed through the first trench; forming a sacrificial structure in the first trench, the sacrificial structure covering the connecting metal structures; forming a stack structure on the first etching stop layer and the sacrificial structure; forming a third trench in the stack structure, so that the sacrificial structure is exposed through the third trench; removing the sacrificial structure, forming a connecting hole, so that the connecting metal structures are exposed through the connecting hole.

2. The method of manufacturing a semiconductor device according to claim 1, wherein The semiconductor device comprises a first region and a second region, the first region forming the connecting hole, and the second region not forming the connecting hole; the forming of the first trench in the first etching stop layer comprises: coating a photoresist material on the first etching stop layer to form a first photoresist layer; forming a first gap in the first photoresist layer, the first gap being above the connecting metal structures in the first region, so that the first etching stop layer above the connecting metal structures in the first region is exposed through the first gap; etching the first etching stop layer through the first gap with the first photoresist layer as a shield, so that the first trench in the first region is formed.

3. The method of manufacturing a semiconductor device according to claim 2, wherein The forming of the first gap in the first photoresist layer comprises: exposing the first photoresist layer through a first mask, the region corresponding to the connecting metal structures in the first region of the first mask being a light-transmitting region, and the remaining region being a light-shielding region; developing the exposed first photoresist layer to form the first gap, the first gap being above the connecting metal structures in the first region.

4. The method of manufacturing a semiconductor device according to claim 3, wherein The forming of the third trench in the stack structure comprises: coating a photoresist material on the stack structure to form a third photoresist layer; exposing the third photoresist layer through a third mask, the region corresponding to the connecting metal structures in the first region of the third mask being a light-transmitting region, and the remaining region being a light-shielding region; the pattern of the third mask is the same as that of the first mask or different from that of the first mask; developing the exposed third photoresist layer to form a third gap, the third gap being above the connecting metal structures in the first region; etching the stack structure through the third gap with the third photoresist layer as a shield, so that the third trench in the stack structure is formed, the third trench being above the connecting metal structures in the first region, so that the sacrificial structure is exposed through the third trench.

5. The manufacturing method of the semiconductor device according to claim 2, wherein: the first gap is also above the connecting metal structures in the second region; the first etching stop layer in the second region also forms the first trench, so that the connecting metal structures in the second region are exposed through the first trench in the second region.

6. The method of manufacturing a semiconductor device according to claim 5, wherein The forming the first gap in the first photoresist layer comprises: exposing the first photoresist layer by a fourth mask, wherein the fourth mask is a light-transmitting mask corresponding to the region of the connecting metal structure in the first region and the second region, and a light-blocking mask corresponding to the other regions; developing the exposed first photoresist layer to form the first gap, wherein the first gap is located above the connecting metal structure in the first region and the second region, and the first etching stop layer above the connecting metal structure in the first region and the second region is exposed through the first gap.

7. The method of manufacturing a semiconductor device according to claim 6, wherein The stack structure comprises an auxiliary layer, and the forming the stack structure on the first etching stop layer and the sacrificial structure comprises: coating a photoresist material on the auxiliary layer to form a second photoresist layer; exposing the second photoresist layer by a fifth mask, wherein the fifth mask is a light-transmitting mask corresponding to the region of the connecting metal structure in the first region and the second region, and a light-blocking mask corresponding to the other regions; the pattern of the fifth mask is the same as that of the fourth mask or different from that of the fourth mask; developing the exposed second photoresist layer to form a second gap, wherein the second gap is located above the connecting metal structure in the first region and the second region; etching the auxiliary layer through the second gap with the second photoresist layer as a shield to form a second trench in the auxiliary layer, wherein the second trench is located above the connecting metal structure in the first region and the second region.

8. The method of manufacturing a semiconductor device according to Claim 1, wherein The forming the sacrificial structure in the first trench, wherein the sacrificial structure covers the connecting metal structure comprises: forming a sacrificial layer on the first etching stop layer and the connecting metal structure, wherein the sacrificial layer covers the first etching stop layer and fills the first trench; etching the sacrificial layer to remove the sacrificial layer covering the first etching stop layer, and retaining the sacrificial layer in the first trench to form the sacrificial structure, wherein the sacrificial structure fills the first trench and covers the connecting metal structure.

9. The method of manufacturing a semiconductor device according to claim 8, wherein The material of the sacrificial layer is amorphous material or low dielectric material.

10. The method of manufacturing a semiconductor device according to claim 8 or 9, wherein The material of the sacrificial layer is amorphous carbon. The forming the sacrificial layer comprises: using propylene (C3H6) as a carbon source and forming the sacrificial layer by a chemical vapor deposition method, wherein the deposition temperature is 400-600°C, the deposition pressure is 1-10 Torr, and the deposition time is 5-20 minutes. The etching the sacrificial layer comprises: etching the sacrificial layer by oxygen plasma etching combined with argon physical etching, wherein the oxygen flow rate is 100-300 sccm, the argon flow rate is 30-80 sccm, the power is 500-1000 W, and the etching time is 30-90 seconds.

11. The method of manufacturing a semiconductor device according to Claim 1, wherein The stack structure further comprises a second etching stop layer, and the forming the stack structure on the first etching stop layer and the sacrificial structure comprises: The second etching stop layer is formed on the first etching stop layer and the sacrificial structure, and is in contact with the first etching stop layer and the sacrificial structure.

12. The method of manufacturing a semiconductor device according to Claim 1, wherein The removing the sacrificial structure includes: performing oxygen plasma ashing, oxygen flow rate is 200-400sccm, power is 1000-1300W, ashing time is 150-190 seconds.

13. A semiconductor device, characterized by comprising: The semiconductor device is manufactured according to the manufacturing method of the semiconductor device of any one of claims 1-12, the semiconductor device includes a semiconductor substrate and a connection hole, the semiconductor substrate includes a plurality of connection metal structures, the connection metal structures are exposed through the connection hole.

14. The semiconductor device of claim 13, wherein, The semiconductor device further includes a sacrificial structure, the semiconductor device includes a first region and a second region, the connection metal structures located in the first region are exposed through the connection hole, and the sacrificial structure covers the connection metal structures located in the second region.

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