Redistribution structure and forming method thereof

Abstract

The invention discloses a redistribution structure and a forming method thereof. The redistribution structure comprises at least one redistribution layer; the rewiring layer comprises a plurality of signal lines and a plurality of grounding lines which extend along a first direction; the signal lines and the grounding lines are alternately distributed along a second direction, and the first direction is perpendicular to the second direction. The signal lines and the grounding lines in the re-wiring layers are alternately distributed in the second direction, so that the adjacent signal lines in the same re-wiring layer can be isolated through the grounding lines, the signal isolation quality between the adjacent signal lines is improved, crosstalk between the adjacent signal lines is reduced, and then the signal transmission quality and the chip performance are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, in particular to a rewiring structure and a forming method thereof. BACKGROUND

[0002] The package structure is a complete system for connecting chips and external circuits to realize signal transmission function.

[0003] In the field of advanced packaging technology, the 2.5D package structure refers to inserting a rewiring layer between the chip and the package substrate for connection, realizing three-dimensional high-performance integration in two-dimensional plane.

[0004] However, in the current 2.5D package structure, there is signal crosstalk in the rewiring layer, which leads to low signal transmission quality between the chip and the package substrate, and it is difficult to meet the performance requirements of the chip. SUMMARY

[0005] The technical problem solved by the present application is how to reduce the signal crosstalk in the rewiring layer.

[0006] To solve the above technical problem, the present application provides a rewiring structure, comprising: at least one rewiring layer; the rewiring layer comprises: a plurality of signal lines and a plurality of ground lines extending along a first direction; the signal lines and the ground lines are alternately distributed along a second direction, and the first direction is perpendicular to the second direction.

[0007] Optionally, the size of the ground line along the second direction is greater than the size of the signal line along the second direction; along the second direction, the spacing between adjacent ground lines and signal lines is greater than the size of the signal line along the second direction.

[0008] Optionally, the size of the ground line along the second direction is twice the size of the signal line along the second direction.

[0009] Optionally, the rewiring structure comprises two or more rewiring layers; the signal lines and the ground lines in the two or more rewiring layers are alternately distributed along a third direction, and the third direction is perpendicular to the plane in which the second direction and the first direction lie.

[0010] Optionally, the size of the ground line along the third direction is greater than the size of the signal line along the third direction; along the third direction, the spacing between adjacent ground lines and signal lines is greater than the size of the signal line along the third direction.

[0011] Optionally, the size of the ground line along the third direction is twice the size of the signal line along the third direction.

[0012] Optionally, it further comprises: a plurality of connecting columns, the connecting columns are used to connect two adjacent ground lines in the third direction.

[0013] Optionally, two adjacent connecting columns in the third direction are staggered.

[0014] Correspondingly, the application further provides a forming method of the rewiring structure, comprising: forming at least one rewiring layer; the forming of the at least one rewiring layer comprises: forming a dielectric layer; forming a plurality of signal lines and a plurality of ground lines extending in a first direction in the dielectric layer; the signal lines and the ground lines are alternately distributed in a second direction, and the first direction is perpendicular to the second direction.

[0015] Optionally, the rewiring structure comprises two or more rewiring layers; the signal lines and the ground lines in the two or more rewiring layers are alternately distributed in a third direction, and the third direction is perpendicular to a plane in which the second direction and the first direction are located.

[0016] Compared with the prior art, the technical scheme of the embodiment of the application has the following beneficial effects:

[0017] In the technical scheme of the application, the signal lines and the ground lines in the rewiring layer are alternately distributed in the second direction, so that the adjacent signal lines in the same rewiring layer can be isolated by the ground lines, the signal isolation quality between the adjacent signal lines is improved, the crosstalk between the adjacent signal lines is reduced, and the signal transmission quality and the performance of the chip are improved.

[0018] Further, in the second direction, the size of the ground line is greater than the size of the signal line, the size of the ground line is increased, the isolation effect of the ground line is enhanced, the signal isolation quality between the adjacent signal lines is improved, and the crosstalk between the adjacent signal lines is reduced.

[0019] Further, in the second direction, the spacing between the ground line and the signal line is greater than the size of the signal line, the spacing between the signal lines is increased, the signal isolation quality between the adjacent signal lines is improved, and the crosstalk between the adjacent signal lines is reduced.

[0020] Further, in the technical scheme of the application, the signal lines and the ground lines between adjacent rewiring layers are alternately distributed in the third direction, so that the adjacent signal lines in different rewiring layers can be isolated by the ground lines, the signal isolation quality between the adjacent signal lines is improved, the crosstalk between the adjacent signal lines is reduced, and the signal transmission quality and the performance of the chip are improved.

[0021] Further, in the third direction, the size of the ground line is greater than the size of the signal line, the size of the ground line is increased, the isolation effect of the ground line is improved, the signal isolation quality between the adjacent signal lines is improved, and the crosstalk between the adjacent signal lines is reduced.

[0022] Further, along the third direction, the spacing between the ground lines and the signal lines is greater than the size of the signal lines, the spacing between the signal lines is increased, and the signal isolation quality between adjacent signal lines is improved, and crosstalk between adjacent signal lines is reduced.

[0023] Further, the adjacent ground lines are connected through the connecting columns, and the connecting columns are staggered along the third direction between two adjacent connecting columns, so that the wiring space is saved, the wiring density is improved, and the signal transmission quality requirement can be met in high-speed interconnection. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 is a structural schematic diagram of a semiconductor packaging structure;

[0025] Figure 2 in the curve is Figure 1 is a curve diagram of the crosstalk value of the signal line in the redistribution layer in the change with frequency in the

[0026] Figure 3 in the curve is Figure 1 is a curve diagram of the voltage density of the signal line in the redistribution layer in the change with time in the

[0027] Figures 4 to 9 is a schematic diagram of the forming process of the redistribution structure in an embodiment of the application;

[0028] Figures 10 to 13 is a schematic diagram of the forming process of the redistribution structure in another embodiment of the application;

[0029] Figure 14 in the curve is Figure 8 is a curve diagram of the crosstalk value of the signal line in the redistribution layer in the change with frequency in the

[0030] Figure 15 in the curve is Figure 8 is a curve diagram of the voltage density of the signal line in the redistribution layer in the change with time in the

[0031] Figure 16 is a structural schematic diagram of a semiconductor packaging structure in an embodiment of the application. DETAILED DESCRIPTION

[0032] It should be noted that the "surface", "upper", in the specification, is used to describe the relative position relationship in space, and is not limited to whether it is in direct contact.

[0033] In the current semiconductor packaging structure, signal crosstalk exists in the redistribution layer, which leads to low signal transmission quality between the chip and the packaging substrate, and it is difficult to achieve the performance index of the chip. The reasons for the existing deficiencies are analyzed as follows:

[0034] Further, along the third direction, the spacing between the ground lines and the signal lines is greater than the size of the signal lines, the spacing between the signal lines is increased, and the signal isolation quality between adjacent signal lines is improved, and crosstalk between adjacent signal lines is reduced.Figure 1 is a structural schematic diagram of a semiconductor package structure. Referring to Figure 1 , the semiconductor package structure has a redistribution structure therein, the redistribution structure includes a plurality of redistribution layers, the same redistribution layer includes a plurality of signal lines 101 or a plurality of ground lines 102 extending along a first direction Y, the plurality of signal lines 101 are arranged along a second direction X, the plurality of ground lines 102 are arranged along the second direction X, and the signal lines 101 and the ground lines 102 in adjacent redistribution layers are alternately distributed along a third direction Z.

[0035] The redistribution structure includes a first redistribution layer M1, a second redistribution layer M2, a third redistribution layer M3, a fourth redistribution layer M4, and a fifth redistribution layer M5.

[0036] When the semiconductor package structure is formed by using the above redistribution structure, all the signal lines 101 in the same redistribution layer (such as the first redistribution layer M1, the third redistribution layer M3, and the fifth redistribution layer M5) have no isolation between adjacent signal lines 101, so that signal crosstalk occurs between the signal lines 101 in the same redistribution layer, affecting the signal transmission quality.

[0037] The signal in the redistribution structure in Figure 1 is simulated and tested, and a curve diagram of the crosstalk value changing with frequency is obtained as shown in Figure 2 , and a curve diagram of the voltage density changing with time is obtained as shown in Figure 3 .

[0038] The signal crosstalk problem between the signal lines 101 in the same redistribution layer in Figure 2 and Figure 3 is described below: Figure 1

[0039] Figure 2 The curve in Figure 1 is a curve diagram of the crosstalk value of the signal line 101 in the redistribution layer in Figure 2 changing with frequency, wherein the abscissa is the frequency of the signal applied to the signal line 101, the ordinate is the crosstalk value of the signal in the redistribution layer, and m1 is a measurement mark.

[0040] Specifically, the type of the crosstalk value includes a near-end crosstalk value XTL and a far-end crosstalk value XTF.

[0041] As shown in Figure 2 ​As shown, the intersection of the curve and the measurement mark m1 is the key characteristic point of crosstalk. The frequency corresponding to this intersection is 16GHz. The near-end crosstalk value XTL at the intersection is -24 dB and the far-end crosstalk value XTF is -36.125 dB. It can be seen that at the key characteristic point of crosstalk, the near-end crosstalk value XTL and the far-end crosstalk value XTF are still in a large value state, that is, there is a crosstalk problem in the same redistribution layer.

[0042] Figure 3 The middle curve is Figure 1 The graph shows the voltage density of signal line 101 within the redistribution layer over time. Figure 3 The horizontal axis represents the time when the signal is applied to signal line 101, and the vertical axis represents the voltage density value of the signal within the redistribution layer.

[0043] Specifically, in Figure 3 The parameter that reflects the effect of signal noise is eye height H1, which is... Figure 3 The voltage difference between the lowest point of the "1" level and the highest point of the "0" level at the middle position (i.e., the middle position of the sampling time).

[0044] like Figure 3 As shown, Figure 3 The highest voltage of the "0" level is 0.8V, and the lowest voltage of the "1" level is 0.2V, that is... Figure 3 The eye height H1 is 0.6V, which is visible. Figure 3 The eye height H1 is still at a relatively small value, indicating that there is a noise problem within the same rewiring layer.

[0045] To address the aforementioned technical problems, this invention provides a redistribution structure. A ground wire is placed before adjacent signal lines within the same redistribution layer of the redistribution structure, enabling the signal lines and ground wires to be alternately distributed in the second direction. The ground wire isolates adjacent signal lines, improving the signal isolation quality between adjacent signal lines, reducing crosstalk between adjacent signal lines, and thereby improving signal transmission quality and chip performance.

[0046] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0047] This invention provides a method for forming a redistribution structure, the method including the following steps: forming at least one redistribution layer; forming at least one redistribution layer includes: forming a dielectric layer; forming a plurality of signal lines and a plurality of ground lines extending along a first direction in the dielectric layer; the signal lines and the ground lines are alternately distributed along a second direction, the first direction being perpendicular to the second direction.

[0048] The rewiring structure is used to redistribute and connect the internal signals of the chip to the substrate after bonding with the chip and the substrate, and realizes high-density interconnection.

[0049] The signal lines are used to establish electrical connection between the chip and the substrate, and between different chips, to transmit digital signals, analog signals, clock signals, etc.

[0050] The ground lines are used to isolate the electric field coupling between the signal lines and reduce the crosstalk between the signal lines.

[0051] The dielectric layer is used to fill between adjacent signal lines and ground lines to avoid short circuit caused by the contact between the signal lines and the ground lines, and to play the role of interlayer isolation.

[0052] The material of the dielectric layer includes low-K dielectric material.

[0053] In the above scheme, the signal lines and the ground lines are alternately distributed along the second direction, so that the adjacent signal lines in the same layer of the rewiring layer can be isolated by the ground lines, the signal isolation quality between the adjacent signal lines is improved, the crosstalk between the adjacent signal lines is reduced, and the signal transmission quality and the performance of the chip are improved.

[0054] In some embodiments of the present application, the rewiring structure includes two or more rewiring layers; the signal lines and the ground lines in the two or more rewiring layers are alternately distributed along a third direction, and the third direction is perpendicular to the plane where the second direction and the first direction are located.

[0055] For example, the number of rewiring layers in the rewiring structure is three, four or five.

[0056] In some embodiments, the step of forming the dielectric layer includes: forming a first sub-dielectric layer; forming a plurality of signal lines and a plurality of ground lines extending along the first direction in the first sub-dielectric layer to form a first rewiring layer; forming a second sub-dielectric layer on the first rewiring layer; etching the second sub-dielectric layer to expose the surface of the first rewiring layer to form a plurality of connection holes; filling the plurality of connection holes to form a plurality of connection columns; forming a third sub-dielectric layer on the connection columns; forming a plurality of signal lines and a plurality of ground lines extending along the first direction in the third sub-dielectric layer to form a second rewiring layer, and the connection columns are used to connect two adjacent ground lines in the first rewiring layer and the second rewiring layer along the third direction.

[0057] The connection columns are used to electrically connect the adjacent ground lines, and the material of the connection columns includes copper.

[0058] For example, the two adjacent connection columns along the third direction are staggered to save the wiring space and improve the wiring density, which can meet the signal transmission quality requirements in high-speed interconnection.

[0059] The following description refers to Figures 4 to 9 The forming process of the redistribution structure in an embodiment is described in detail.

[0060] It should be noted that, Figures 4 to 9 The redistribution layer in the redistribution structure formed in the embodiment is three layers, and the forming process of other layers is the same as that of the three-layer redistribution layer, which is not described here.

[0061] As Figure 4 shown, a first sub dielectric layer 2031 is formed; a plurality of first signal lines 201 and a plurality of first ground lines 202 extending along a first direction Y are formed in the first sub dielectric layer 2031, and a first redistribution layer M1 is formed.

[0062] For example, in the step of forming a plurality of first signal lines 201 and a plurality of first ground lines 202 extending along a first direction Y in the first sub dielectric layer 2031, the first signal lines 201 and the first ground lines 202 are alternately distributed along a second direction X, and the first direction Y is perpendicular to the second direction X.

[0063] By alternately distributing the first signal lines 201 and the first ground lines 202 in the first redistribution layer M1 along the second direction X, the adjacent first signal lines 201 in the same layer of the redistribution layer can be isolated by the first ground lines 202, the signal isolation quality between the adjacent first signal lines 201 is improved, the crosstalk between the adjacent first signal lines 201 is reduced, and the signal transmission quality and the performance of the chip are improved.

[0064] In some embodiments, the size W1 of the first ground line 202 along the second direction X is greater than the size W2 of the first signal line 201 along the second direction X, and the spacing W3 between the adjacent first ground line 202 and the first signal line 201 along the second direction X is greater than the size W2 of the first signal line 201 along the second direction X.

[0065] In the embodiment, along the second direction X, the size W1 of the first ground line 202 is greater than the size W2 of the signal line 201, the size W1 of the first ground line 202 is increased, the isolation effect of the first ground line 202 is improved, and the signal isolation quality between the adjacent first signal lines 201 is improved, and the crosstalk between the adjacent signal lines 201 is reduced.

[0066] Specifically, the dimension W1 of the first grounding wire 202 along the second direction X is twice the dimension W2 of the first signal line 201 along the second direction X, which further increases the dimension W1 of the first grounding wire 202, improves the isolation effect of the first grounding wire 202, improves the signal isolation quality between adjacent first signal lines 201, and reduces crosstalk between adjacent signal lines 201.

[0067] In this embodiment, along the second direction X, the spacing W3 between the first grounding wire 202 and the first signal line 201 is greater than the size W2 of the first signal line 201, which increases the spacing W3 between the first signal lines 201, thereby improving the signal isolation quality between adjacent first signal lines 201 and reducing crosstalk between the first adjacent signal lines 201.

[0068] In other embodiments, a plurality of signal lines 201 and a plurality of ground lines 202 are formed before the formation of the first sub-dielectric layer 2031; and after the formation of the plurality of signal lines 201 and the plurality of ground lines 202, a first sub-dielectric layer 2031 filled with the plurality of signal lines 201 and the plurality of ground lines 202 is formed.

[0069] The material of the first sub-dielectric layer 2031 includes a low-k dielectric material, and the materials of the signal line 201 and the ground line 202 include copper.

[0070] In this embodiment, the first sub-dielectric layer 2031 is formed using a chemical vapor deposition process or a physical vapor deposition process.

[0071] like Figure 5 As shown, a second sub-dielectric layer 2032 is formed on the first redistribution layer M1; the second sub-dielectric layer 2032 is etched to expose the surface of the first redistribution layer M1 to form a plurality of first connection holes (not shown in the figure); the plurality of first connection holes are filled to form a plurality of first connection posts 204.

[0072] The first connection hole is used to provide a receiving space for the first connection post 204, which is used to electrically connect to the adjacent first ground wire 202. The material of the first connection post 204 includes copper.

[0073] For example, the step of etching the second sub-dielectric layer 2032 to expose the surface of the first redistribution layer M1 to form a plurality of first interconnect holes includes: a hard mask layer (not shown in the figure) having a first interconnect hole pattern on the second sub-dielectric layer 2032; using the hard mask layer having the first interconnect hole pattern as a mask, etching the second sub-dielectric layer to expose the surface of the first redistribution layer M1 to form a plurality of first interconnect holes.

[0074] In the embodiment, the process of etching the second sub dielectric layer 2032 is dry etching, and process parameters of the dry etching include that the pressure of the chamber is 20 mT to 100 mT, the source power is 500 W to 2800 W, the bias power is 30 W to 2800 W, the gas flow is 20 sccm to 200 sccm, and the etching time is 8 s to 20 s.

[0075] For example, the step of filling the first connection holes to form the connection columns 204 includes filling the first connection holes with conductive material, and planarizing the conductive material in the first connection holes to expose the surface of the second sub dielectric layer 2032 to form the first connection columns 204.

[0076] In the embodiment, the first connection columns 204 are formed by electroplating.

[0077] As shown in FIG. 2, the second sub dielectric layer 2032 is formed on the first sub dielectric layer 2031, and a plurality of first signal lines 201 and a plurality of first ground lines 202 are formed in the second sub dielectric layer 2032 along the first direction Y to form a first redistribution layer M1. Figure 6 As shown in FIG. 2, the third sub dielectric layer 2033 is formed on the second sub dielectric layer 2032, and a plurality of second signal lines 205 and a plurality of second ground lines 206 are formed in the third sub dielectric layer 2033 along the first direction Y to form a second redistribution layer M2.

[0078] The second signal lines 205 and the second ground lines 206 in the second redistribution layer M2 are alternately distributed along the second direction X, so that the adjacent second signal lines 205 in the same redistribution layer can be isolated by the second ground lines 206, the signal isolation quality between the adjacent second signal lines 205 is improved, the crosstalk between the adjacent second signal lines 205 is reduced, and the signal transmission quality and the performance of the chip are improved.

[0079] The size of the second signal lines 205 and the second ground lines 206 in the second redistribution layer M2 and the spacing between the second signal lines 205 and the second ground lines 206 are the same as the size of the first signal lines 201 and the first ground lines 202 in the first redistribution layer M1 and the spacing between the first signal lines 201 and the first ground lines 202, which will not be described here.

[0080] For example, in the step of forming the plurality of second signal lines 205 and the plurality of second ground lines 206 in the third sub dielectric layer 2033 along the first direction Y, the second signal lines 205 and the second ground lines 206 are alternately distributed along the second direction X, and the first direction Y is perpendicular to the second direction X.

[0081] In other embodiments, a plurality of second signal lines 205 and a plurality of second ground lines 206 are formed before the third sub-dielectric layer 2033 is formed; after the plurality of second signal lines 205 and a plurality of second ground lines 206 are formed, a third sub-dielectric layer 2033 is formed that fills the plurality of second signal lines 205 and a plurality of second ground lines 206.

[0082] The material of the third sub-dielectric layer 2033 includes a low-k dielectric material, and the materials of the second signal line 205 and the second ground line 206 include copper.

[0083] In this embodiment, the first sub-dielectric layer 2031 is formed using a chemical vapor deposition process or a physical vapor deposition process.

[0084] like Figure 7 As shown, a fourth sub-dielectric layer 2034 is formed on the second redistribution layer M2; the fourth sub-dielectric layer 2034 is etched to expose the surface of the second redistribution layer M2 to form a plurality of connection holes (not shown in the figure); the plurality of second connection holes are filled to form a plurality of second connection posts 204.

[0085] The second connection hole is used to provide a receiving space for the second connection post 207, which is used to electrically connect to the adjacent second grounding wire 206. The material of the second connection post 207 includes copper.

[0086] For example, the step of etching the fourth sub-dielectric layer 2034 to expose the surface of the first redistribution layer M1 and forming a plurality of second interconnect holes includes: a hard mask layer (not shown in the figure) having an interconnect hole pattern on the fourth sub-dielectric layer 2034; using the hard mask layer having the second interconnect hole pattern as a mask, etching the fourth sub-dielectric layer to expose the surface of the second redistribution layer M2 and forming a plurality of second interconnect holes.

[0087] In this embodiment, the etching process of the fourth sub-dielectric layer 2034 is dry etching. The process parameters of the dry etching include: chamber pressure of 20mT to 100mT, source power of 500W to 2800W, bias power of 30W to 2800W, gas flow rate of 20sccm to 200sccm, and etching time of 8s to 20s.

[0088] For example, the step of filling a plurality of second connection holes to form a plurality of second connection posts 207 includes: filling the second connection holes with conductive material; planarizing the conductive material in the second connection holes to expose the surface of the fourth sub-dielectric layer 2034, thereby forming a plurality of second connection posts 207.

[0089] In this embodiment, the second connecting post 207 is formed by electroplating.

[0090] Specifically, the two adjacent first connecting posts 204 and the second connecting posts 207 in the second sub-dielectric layer 2032 within the fourth sub-dielectric layer 2034 are staggered.

[0091] Among them, the two adjacent first connecting posts 204 and the second connecting post 207 are staggered along the third direction Z.

[0092] The staggered distribution refers to the fact that the projected areas of two adjacent first connecting columns 204 and second connecting columns 207 on the third direction Z have no overlap.

[0093] In this embodiment, adjacent grounding wires are connected by connecting posts, and the connecting posts 204 are staggered along the third direction Z, which saves wiring space, increases wiring density, and can meet the signal transmission quality requirements in high-speed interconnection.

[0094] like Figure 8 as well as Figure 9 As shown, Figure 9 This is a top view of each rewiring layer within the rewiring structure. Figure 8 Each rewiring layer is Figure 9 A cross-sectional schematic diagram of each rewiring layer along the AA1 direction is shown. A fifth sub-dielectric layer 2035 is formed on the fourth sub-dielectric layer 2034. A plurality of third signal lines 208 and a plurality of third ground lines 209 extending along the first direction Y are formed in the fifth sub-dielectric layer 2035 to form a third rewiring layer M3. The second connecting post 207 is used to connect two adjacent second ground lines 206 and third ground lines 209 in the second rewiring layer M2 and the third rewiring layer M3 along the third direction Z.

[0095] For example, in the step of forming a plurality of third signal lines 208 and a plurality of third ground lines 209 extending along a first direction Y within the fifth sub-dielectric layer 2035, the third signal lines 208 and the third ground lines 209 are alternately distributed along a second direction X, wherein the first direction Y is perpendicular to the second direction X.

[0096] The third signal line 208 and the third ground line 209 in the third redistribution layer M3 are alternately distributed along the second direction X, so that adjacent third signal lines 208 in the same redistribution layer can be isolated by the third ground line 209, thereby improving the signal isolation quality between adjacent third signal lines 208, reducing crosstalk between adjacent third signal lines 208, and thus improving signal transmission quality and chip performance.

[0097] In other embodiments, before forming the fifth sub-intermediate layer 2035, a plurality of third signal lines 208 and a plurality of third ground lines 209 are formed; after forming the plurality of third signal lines 208 and the plurality of third ground lines 209, the fifth sub-intermediate layer 2035 is formed to fill the plurality of third signal lines 208 and the plurality of third ground lines 209.

[0098] The material of the fifth sub-intermediate layer 2035 includes a low-K dielectric material, and the material of the third signal lines 208 and the third ground lines 209 includes copper.

[0099] In the present embodiment, the fifth sub-intermediate layer 2035 is formed by a chemical vapor deposition process or a physical vapor deposition process.

[0100] Reference will be made to the drawings below Figures 10 to 13 The process of forming the rewiring structure in another embodiment will be described in detail. The same as the previous embodiment, the same will not be described here, and the difference from the previous embodiment is that the signal lines 301 and the ground lines 302 in the two or more rewiring layers are alternately distributed along the third direction Z, and the third direction Z is perpendicular to the plane where the second direction X and the first direction Y are located.

[0101] It should be noted that Figures 10 to 13 The number of rewiring layers in the rewiring structure formed in the present embodiment is four, and the forming process of other numbers of layers is the same as that of the four rewiring layers, which will not be described here.

[0102] As shown in the drawings, Figure 10 A plurality of signal lines 301 and a plurality of ground lines 302 extending along the first direction Y are formed in the first sub-intermediate layer 3031 to form a first rewiring layer M1; a second sub-intermediate layer 3032 is formed on the first rewiring layer M1; a plurality of signal lines 301 and a plurality of ground lines 302 extending along the first direction Y are formed in the third sub-intermediate layer 3033 to form a second rewiring layer M2; a fourth sub-intermediate layer 3034 is formed on the second rewiring layer M2; the fourth sub-intermediate layer 3034, the third sub-intermediate layer 3033 and the second sub-intermediate layer 3032 are etched in turn to expose the surface of the ground line 302 in the first rewiring layer M1 to form a plurality of connection holes; and a plurality of connection columns are formed by filling a plurality of the connection holes.

[0103] Among them, the first rewiring layer M1 and the second rewiring layer M2 are arranged along the third direction Z, and the third direction Z is perpendicular to the plane where the second direction X and the first direction Y are located.

[0104] In this embodiment, the signal lines 301 and the ground lines 302 between adjacent redistribution layers are alternately distributed along the third direction Z, so that adjacent signal lines 301 in different redistribution layers can be isolated by the ground lines 302, thereby improving the signal isolation quality between adjacent signal lines 301, reducing crosstalk between adjacent signal lines 301, and thus improving signal transmission quality and chip performance.

[0105] In an embodiment not shown, the dimension of the grounding wire 302 along the third direction Z is greater than the dimension of the signal line 301 along the third direction Z, and the spacing between adjacent grounding wires 302 and signal lines 301 along the third direction Z is greater than the dimension of the signal line 301 along the third direction Z.

[0106] Specifically, the Z-dimensional dimension of the grounding wire 302 along the third direction is twice that of the Z-dimensional dimension of the signal line 301 along the third direction.

[0107] Along the third direction Z, the size of the grounding wire 302 is larger than the size of the signal wire 301, which increases the size of the grounding wire 302, improves the isolation effect of the grounding wire 302, and thus improves the signal isolation quality between adjacent signal lines 301 and reduces crosstalk between adjacent signal lines 301.

[0108] Along the third direction Z, the spacing between the grounding wire 302 and the signal line 301 is greater than the size of the signal line 301, which increases the spacing between the signal lines 301, thereby improving the signal isolation quality between adjacent signal lines 301 and reducing crosstalk between adjacent signal lines 301.

[0109] like Figure 11 As shown, a third sub-dielectric layer M3 is formed on the fourth sub-dielectric layer 3034, and the third sub-dielectric layer M3 is located within the fifth sub-dielectric layer 3035; a sixth sub-dielectric layer 3036 is formed on the third sub-dielectric layer M3; the sixth sub-dielectric layer 3036, the fifth sub-dielectric layer 3035 and the fourth sub-dielectric layer 3034 are etched sequentially until the surface of the ground wire 302 in the second sub-dielectric layer M2 is exposed, forming a plurality of connection holes; the plurality of connection holes are filled to form a plurality of connection posts.

[0110] In this configuration, adjacent connecting columns are staggered along the third direction Z.

[0111] The staggered distribution of two adjacent connecting columns along the third direction Z means that the projected areas of the two adjacent connecting columns in the third direction Z have no overlap.

[0112] The adjacent ground lines 302 are connected by connecting columns, and the connecting columns are staggered between the adjacent two connecting columns along a third direction Z, so that wiring space is saved, wiring density is improved, and the signal transmission quality requirement can be met in high-speed interconnection.

[0113] As shown in Figure 12 and Figure 13 , Figure 13 is a top view of each redistribution layer of the redistribution structure, Figure 12 each redistribution layer in the redistribution structure is Figure 13 The cross-sectional view of each redistribution layer along the BB1 direction is shown in the sixth sub-intermediate layer 3036, and the fourth redistribution layer M4 is located in the seventh sub-intermediate layer 3037.

[0114] Correspondingly, please refer to Figure 8 The application also provides a redistribution structure, comprising: at least one redistribution layer; the redistribution layer comprises: a plurality of signal lines 201 and a plurality of ground lines 202 extending along a first direction Y; the signal lines 201 and the ground lines 202 are alternately distributed along a second direction X, and the first direction Y is perpendicular to the second direction X.

[0115] In some embodiments, the size of the ground line 202 along the second direction X is greater than the size of the signal line 201 along the second direction X.

[0116] In some embodiments, the size of the ground line 202 along the second direction X is twice the size of the signal line 201 along the second direction X.

[0117] In some embodiments, the distance between adjacent ground lines 202 and signal lines 201 along the second direction X is greater than the size of the signal line 201 along the second direction X.

[0118] In some embodiments, the redistribution structure comprises two or more redistribution layers; the signal lines 201 and the ground lines 202 in the two or more redistribution layers are alternately distributed along a third direction Z, and the third direction Z is perpendicular to the plane in which the second direction X and the first direction Y are located.

[0119] In some embodiments, the size of the ground line 202 along the third direction Z is greater than the size of the signal line 201 along the third direction Z.

[0120] In some embodiments, the size of the ground line 202 along the third direction Z is twice the size of the signal line 201 along the third direction Z.

[0121] In some embodiments, the spacing between adjacent ground lines 202 and signal lines 201 along the third direction Z is greater than the dimension of the signal lines 201 along the third direction Z.

[0122] In some embodiments, further comprising: a plurality of connecting columns 204 for connecting two adjacent ground lines 202 along the third direction Z.

[0123] In some embodiments, the two adjacent connecting columns 204 along the third direction Z are staggered.

[0124] The following describes the signal crosstalk between the signal lines in the redistribution layer in the embodiments of the present application: Figures 14 to 15 The signal crosstalk between the signal lines in the redistribution layer in the embodiments of the present application is described as follows:

[0125] Figure 14 The curve in FIG. 6 is a variation curve diagram of the crosstalk value of the signal lines in the redistribution layer in the embodiments of the present application with the change of frequency, wherein, Figure 8 the abscissa of FIG. 6 is the frequency of the signal applied to the signal line, and the ordinate is the crosstalk value of the signal in the redistribution layer, and m1 is a measurement mark. Figure 14

[0126] Specifically, the type of the crosstalk value includes a near-end crosstalk value XTL and a far-end crosstalk value XTF.

[0127] As shown in FIG. 7, the intersection of the curve and the measurement mark m1 is a key feature point of crosstalk, the frequency corresponding to the intersection is 16 GHz, the near-end crosstalk value XTL at the intersection is -24 dB, and the far-end crosstalk value XTF at the intersection is -46.425 dB. It can be seen that the far-end crosstalk value XTF at the key feature point of crosstalk is reduced compared with the crosstalk value in the prior art of the present application, the crosstalk index is improved by 30%, and the crosstalk between adjacent signal lines is reduced. Figure 14 Figure 2

[0128] Figure 15 The curve in FIG. 8 is a variation curve diagram of the voltage density of the signal lines in the redistribution layer in the embodiments of the present application with the change of time, wherein, Figure 8 the abscissa of FIG. 8 is the time of the signal applied to the signal line, and the ordinate is the voltage density value of the signal in the redistribution layer. Figure 15

[0129] Specifically, the parameter reflecting the influence of signal noise in the embodiments of the present application is the eye height H2, that is, the voltage difference between the lowest point of the “1” level and the highest point of the “0” level at the middle position (i.e., the middle position of the sampling time) in the embodiments of the present application. Figure 15 Figure 15 As shown in FIG. 9, the intersection of the curve and the measurement mark m1 is a key feature point of crosstalk, the frequency corresponding to the intersection is 16 GHz, the near-end crosstalk value XTL at the intersection is -24 dB, and the far-end crosstalk value XTF at the intersection is -46.425 dB. It can be seen that the far-end crosstalk value XTF at the key feature point of crosstalk is reduced compared with the crosstalk value in the prior art of the present application, the crosstalk index is improved by 30%, and the crosstalk between adjacent signal lines is reduced.

[0130] As shown in FIG. 9, the intersection of the curve and the measurement mark m1 is a key feature point of crosstalk, the frequency corresponding to the intersection is 16 GHz, the near-end crosstalk value XTL at the intersection is -24 dB, and the far-end crosstalk value XTF at the intersection is -46.425 dB. It can be seen that the far-end crosstalk value XTF at the key feature point of crosstalk is reduced compared with the crosstalk value in the prior art of the present application, the crosstalk index is improved by 30%, and the crosstalk between adjacent signal lines is reduced. Figure 15 Figure 15 ​​​​​​The highest voltage of the "0" level is 0.9V, and the lowest voltage of the "1" level is 0.1V. Figure 15 The eye height H2 in it is 0.8V, and it can be seen that Figure 15 The eye height H2 in Figure 3 is increased compared with the eye height H1 in the prior art of

[0131] Correspondingly, the present invention further provides a packaging method for a semiconductor structure, including: providing a carrier 501 and a substrate 701, on which a plurality of discrete chips are formed; forming the above-mentioned redistribution structure on the carrier 501; and bonding the redistribution structure to the substrate 701.

[0132] The carrier 501 is used to provide a structural basis for the chips. In this embodiment, the material of the carrier 501 is epoxy resin.

[0133] In some embodiments of the present invention, the number of chips is two, and the substrate 701 is an organic substrate 701.

[0134] Next, in combination with Figure 16 and Figure 8 a detailed description of the formation process of the packaging method for the semiconductor structure in an embodiment will be given.

[0135] It should be noted that in this embodiment, based on Figure 8 the redistribution structure in, a detailed description of the formation process of the packaging method for the semiconductor structure will be given. The packaging methods based on the redistribution structures in other embodiments are the same as this embodiment and will not be elaborated here.

[0136] On the basis of Figure 8 referring to Figure 16 a carrier 501 and a substrate 701 are provided, on which a first chip 401 and a second chip 402 are formed; a redistribution structure is formed on the carrier 501; and the redistribution structure is bonded to the substrate 701.

[0137] For example, the first chip 401 and the second chip 402 have signal input / output pads 2011 and ground pads 2012. When forming the redistribution structure on the carrier 501, the signal input / output pads 2011 are connected to the signal lines 201 in the redistribution layer, and the ground pads 2012 are connected to the ground lines 202 in the redistribution layer to achieve the transmission of different signals.

[0138] For example, the redistribution structure is bonded to the substrate 701 through solder balls 601.

[0139] In specific embodiments, the semiconductor package structure of the present application establishes electrical connections between the chips and the substrate 701 and between different chips through the redistribution structure to transmit digital signals, analog signals, clock signals, etc.

[0140] Accordingly, the present application also provides a semiconductor package structure, comprising: the above-mentioned redistribution structure, the redistribution structure having opposite first face a and second face b; a plurality of chips, the plurality of chips being separated on the first face a; a substrate 701, the substrate 701 being located on the second face b.

[0141] In some embodiments, the chip has signal input / output pads 2011 and ground pads 2012, the ground lines 202 in the redistribution layer on the first face a are connected to the ground pads 2012, and the signal lines 201 in the redistribution layer on the first face a are connected to the signal input / output pads 2011.

[0142] In some embodiments, the substrate 701 is an organic substrate.

[0143] In some embodiments, the number of redistribution layers in the redistribution structure is three.

[0144] In summary, in the technical scheme of the present application, the signal lines and the ground lines in the redistribution layer are alternately distributed along the second direction, so that adjacent signal lines in the same redistribution layer can be isolated by the ground lines, the signal isolation quality between adjacent signal lines is improved, the crosstalk between adjacent signal lines is reduced, and the signal transmission quality and the performance of the chip are improved.

[0145] Although the present application is disclosed as above, the present application is not limited to this. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A rewiring structure, characterized in that, Comprising: at least one heavy wiring layer; the heavy wiring layer comprises a plurality of signal lines and a plurality of ground lines extending along a first direction; the signal lines and the ground lines are alternately distributed along a second direction, the first direction being perpendicular to the second direction.

2. The rewiring structure according to claim 1, wherein the ground lines have a dimension along the second direction that is greater than a dimension of the signal lines along the second direction; along the second direction, a spacing between adjacent ground lines and signal lines is greater than the dimension of the signal lines along the second direction.

3. The rewiring structure according to claim 2, wherein the ground lines have a dimension along the second direction that is twice the dimension of the signal lines along the second direction.

4. The re-wiring structure according to any one of claims 1 to 3, wherein the heavy wiring structure comprises two or more heavy wiring layers; in the two or more heavy wiring layers, the signal lines and the ground lines are alternately distributed along a third direction, the third direction being perpendicular to a plane in which the second direction and the first direction lie.

5. The rewiring structure according to claim 4, wherein the ground lines have a dimension along the third direction that is greater than a dimension of the signal lines along the third direction; along the third direction, a spacing between adjacent ground lines and signal lines is greater than the dimension of the signal lines along the third direction.

6. The rewiring structure according to claim 5, wherein the ground lines have a dimension along the third direction that is twice the dimension of the signal lines along the third direction.

7. The rewiring structure according to claim 4, wherein Further comprising: a plurality of connecting columns, the connecting columns being used to connect two adjacent ground lines in the third direction.

8. The rewiring structure according to claim 7, wherein two adjacent connecting columns in the third direction are staggered.

9. A method of forming a rewiring structure, characterized by, Comprising: forming at least one heavy wiring layer; the forming at least one heavy wiring layer comprises: forming a dielectric layer; forming a plurality of signal lines and a plurality of ground lines extending along a first direction in the dielectric layer; the signal lines and the ground lines are alternately distributed along a second direction, the first direction being perpendicular to the second direction.

10. The method of forming a rewiring structure according to Claim 9, wherein the heavy wiring structure comprises two or more heavy wiring layers; in the two or more heavy wiring layers, the signal lines and the ground lines are alternately distributed along a third direction, the third direction being perpendicular to a plane in which the second direction and the first direction lie.

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