Hot-pressing jig, chip packaging body partition heating packaging system and packaging method

Abstract

The embodiment of the invention provides a hot-pressing jig, a chip packaging body partition heating packaging system and a packaging method, the hot-pressing jig comprises a first heating pressing plate and a second heating pressing plate, and a chip packaging body is clamped between the first heating pressing plate and the second heating pressing plate; wherein each of the first heating pressing plate and the second heating pressing plate comprises a heating area and a cooling area so as to realize zoned temperature control of the chip packaging body. When the FCBGA chip packaging body is pressurized and heated by adopting the hot-pressing jig, the temperature rising area corresponds to the adhesive layer, the temperature rising area heats the adhesive layer so as to cure the adhesive layer, and then the heat dissipation cover is fixed on the substrate; the cooling area corresponds to the chip area, and the cooling area cools the chip area, so that the chip area is in a non-heating state, the possibility that the chip area, especially the center and the edge of a chip, warps due to high temperature is reduced, and the phenomenon that the coverage rate of a thermal interface material layer is reduced due to product warping is reduced.

Description

TECHNICAL FIELD

[0001] The embodiment of the present disclosure belongs to the technical field of semiconductor packaging, and particularly relates to a hot-pressing jig, a chip package partition heating packaging system and a packaging method. BACKGROUND

[0002] As a mainstream solution for high-performance chip packaging, FCBGA packaging technology is widely used in the packaging of high-power integrated circuits such as CPUs, GPUs, FPGAs and ASICs. Its typical structure includes: the chip is connected to the organic substrate through solder balls, the TIM is filled between the chip and the metal heat sink cover, the heat sink cover is fixed to the substrate through the AD glue, and a complete packaging structure is formed. The main heat dissipation path of this structure is: the heat generated by the chip is conducted to the heat sink cover through the TIM, and then dissipated to the environment through the heat sink, and about 90% of the heat is dissipated through this path.

[0003] In the prior art, TIM materials are mainly divided into two categories: organic TIM (such as thermal conductive gel, phase change material) and graphite TIM. Organic TIM has good adhesion and filling performance, but the thermal conductivity is relatively low; although the thermal conductivity of graphite TIM is high, the adhesion performance is poor, and delamination is easy to occur at the interface. In order to ensure the good thermal conduction performance of the TIM, the industry usually adopts the method of heating and pressing in the adhesive dispensing and bonding (ASA) process to make the TIM fully wet the surfaces of the chip and the heat sink cover, and at the same time solidify the AD glue to realize mechanical fixation.

[0004] The existing technology mainly focuses on material optimization and structure design to improve the TIM coverage: 1) develop composite materials with high thermal conductivity and good adhesion, such as thermal conductive gel or phase change material with nano filler; 2) adopt heat sink groove design (such as the boss structure in patent CN220106500U) to increase the mechanical interlocking of TIM, or use reinforced AD glue to form a rectangular frame structure around the TIM area (such as patent CN202311442131), to reduce delamination through mechanical constraint.

[0005] Although the existing technology has made certain progress, there are still the following key problems in actual application: 1) TIM coverage reduction due to CTE mismatch: In FCBGA packaging, there is a significant difference in the coefficient of thermal expansion between the organic substrate, silicon chip, and metal heat spreader. During the heating process of the ASA process (usually 150-180°C), this difference will cause uneven thermal stress in the packaging structure, causing warping deformation. Test data shows that this warping will reduce the contact area of the TIM with the chip / heat spreader, especially in the edge area of the chip, and the TIM coverage can be reduced to 84.69%. The root cause is that global heating causes the overall structure to expand synchronously, which cannot alleviate the local stress concentration caused by CTE difference; the rigid connection of the heat spreader and the chip limits the free compensation of thermal deformation, and the stress is concentrated at the TIM interface.

[0006] 2) Process control limitations: The existing ASA process uses global heating, which cannot differentiate control for different areas of thermal demand. This leads to two contradictions: ADH glue needs high temperature (usually above 150°C) to fully cure, while the chip-TIM-heat spreader area will produce greater warping due to CTE mismatch at high temperature; if the overall temperature is reduced to ensure the integrity of the TIM interface, it will also cause the ADH glue to cure insufficiently, affecting the mechanical strength of the package.

[0007] 3) Structural reliability challenges: Long-term temperature cycle tests show that the existing structure is prone to the following failure modes after 300-500 cycles: TIM delamination from the edge of the heat spreader (especially more likely for graphite TIM); cracks in low dielectric constant dielectric layers at the edge of the chip; broken contacts of stacked vias. The root cause of these failures is still thermal stress accumulation, and existing solutions (such as strengthening AD glue) can improve coverage to 91.09%-96.83%, but cannot fundamentally solve the thermal stress generation mechanism.

[0008] 4) Inherent contradictions in material performance: TIM materials have a performance contradiction between "high thermal conductivity" and "high adhesion": thermal conductive gel has good adhesion but low thermal conductivity (usually <10 W / mK); graphite gasket has high thermal conductivity (up to 1000 W / mK or more) but poor adhesion, and is more prone to delamination. Existing technologies partially alleviate this contradiction through structural design (such as grooves, bosses), but increase manufacturing costs and process complexity.

[0009] In summary, the core problem faced by existing FCBGA packaging technology is that under the condition of global heating in the ASA process, the thermal stress caused by CTE mismatch cannot be effectively controlled, which affects the integrity of the TIM interface.

[0010] In view of the above problems, it is necessary to propose a hot-pressing jig, a chip packaging body partition heating packaging system and a packaging method which are reasonably designed and effectively solve the above problems. SUMMARY

[0011] Embodiments of the present disclosure aim to at least solve one of the problems existing in the prior art, and provide a hot-pressing jig, a chip package partition heating packaging system and a packaging method.

[0012] An aspect of the embodiments of the present disclosure provides a hot-pressing jig for pressurizing and partition temperature controlling a chip package, comprising a first heating press plate and a second heating press plate, and the chip package is clamped between the first heating press plate and the second heating press plate; wherein, The first heating press plate and the second heating press plate both comprise a heating area and a cooling area to realize partition temperature controlling of the chip package.

[0013] Optionally, a heat insulation area is arranged between the heating area and the cooling area, and a heat insulation member is arranged in the heat insulation area, and the heat insulation member is used to block heat transfer between the heating area and the cooling area.

[0014] Optionally, the heating area comprises a heating member, and the heating member is used to heat a high-temperature area of the chip package to a preset heating temperature.

[0015] Optionally, the heating area further comprises a first temperature sensor, and the first temperature sensor is used to monitor and regulate the temperature of the heating area in real time.

[0016] Optionally, the cooling area comprises a cooling member, and the cooling member is used to cool a low-temperature area of the chip package to a preset cooling temperature.

[0017] Optionally, the cooling area further comprises a second temperature sensor, and the second temperature sensor is used to monitor and regulate the temperature of the cooling area in real time.

[0018] Another aspect of the embodiments of the present disclosure provides a chip package partition heating packaging system, comprising a chip package, a hot-pressing jig and a controller; wherein the hot-pressing jig is the hot-pressing jig described above. The chip package comprises a substrate, a chip flip-chip mounted on the substrate, a thermal interface material layer arranged on the chip, and a heat dissipation cover fixed to the edge of the substrate through an adhesive layer; The first heating press plate is arranged on the heat dissipation cover, and the second heating press plate is arranged opposite to the first heating press plate and bears the substrate; wherein the first heating press plate and the second heating press plate are respectively provided with a heating area and a cooling area corresponding to the adhesive layer area and the chip area; The controller is used to control the hot-pressing jig to pressurize the chip package; and, The controller is further used to control the heating area to heat the adhesive layer area, and control the cooling area to cool the chip area.

[0019] Optionally, the controller is further configured to control the heating member to heat the adhesive layer region to a preset heating temperature, so as to solidify the adhesive layer, and thereby fix the heat dissipation cover to the substrate. The controller is further configured to control the cooling member to cool the chip region to a preset cooling temperature, so as to maintain the interface integrity of the thermal interface material layer.

[0020] Optionally, the controller is further configured to control the hot-pressing jig to apply a first preset pressure and a second preset pressure to the chip region and the adhesive layer region, respectively; and the first preset pressure is greater than the second preset pressure.

[0021] Another aspect of the embodiments of the present disclosure provides a chip package partition heating packaging method, which adopts the chip package partition heating packaging system described above, and the method comprises the following steps: flip-chip mounting a chip on a substrate, and forming an adhesive layer on an edge region of the substrate; forming a thermal interface material layer on a side of the chip away from the substrate; placing the substrate on a second heating platen, and fixing a heat dissipation cover to the substrate through the adhesive layer, so as to form a chip package; covering a first heating platen on the heat dissipation cover, and connecting the first heating platen with the second heating platen; lifting the second heating platen upward, and fixing the first heating platen, so as to provide a preset pressure to the chip package; The controller controls the heating region and the cooling region to heat the adhesive layer region and cool the chip region, respectively.

[0022] The hot-pressing jig, the chip package partition heating packaging system and the packaging method of the embodiments of the present disclosure, the first heating platen and the second heating platen of the hot-pressing jig both comprise a heating region and a cooling region, so as to control the temperature in different regions according to the heating requirement of the chip package. When the hot-pressing jig is used to press and heat the FCBGA chip package, the heating region corresponds to the adhesive layer, the heating region heats the adhesive layer to solidify the adhesive layer, and thereby fix the heat dissipation cover to the substrate; the cooling region corresponds to the chip region, the cooling region cools the chip region, so that the chip region is in a non-heating state, which reduces the possibility of warping of the chip region, especially the center and the edge of the chip, due to high temperature, thereby reducing the phenomenon of reduced coverage of the thermal interface material layer caused by product warping; the edge coverage of the thermal interface material layer is improved to ≥97%, and the warping amount is reduced to ≤40 μm (the existing value is ≥120 μm); the hot-pressing jig fundamentally solves the TIM interface failure problem caused by CTE mismatch without changing the existing FCBGA packaging structure and increasing the material cost, by innovatively controlling the temperature in different regions of the heating platen. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 A structure schematic diagram of a hot-pressing jig for an embodiment of the present disclosure; Figure 2 A structure schematic diagram of a second heating platen for another embodiment of the present disclosure; Figure 3 A structure schematic diagram of a heating zone and a cooling zone for another embodiment of the present disclosure; Figure 4 A distribution diagram of a heating element and a cooling element for another embodiment of the present disclosure; Figure 5 A distribution diagram of a heating element and a cooling element for another embodiment of the present disclosure; Figure 6 A structure schematic diagram of a chip package partition heating packaging system for another embodiment of the present disclosure; Figure 7 A flow schematic diagram of a chip package partition heating packaging method for another embodiment of the present disclosure; Figures 8 to 13 A process schematic diagram of a chip package partition heating packaging method for another embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] In order for those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the embodiments of the present disclosure are further described in detail below with reference to the drawings and specific embodiments.

[0025] The existing ASA method and principle: after the semi-finished chip unit is coated with adhesive and TIM or attached, it will enter the ASA station. The normal process of the station is as follows: the semi-finished chip unit coated with TIM or attached with graphite sheet and adhesive is placed on the lower heating platen, the lower heating platen can provide overall heating effect under normal circumstances, then the device sucks the heat dissipation cover and places it on the semi-finished chip unit, then the lower heating platen moves upward to press and provide heating like the upper heating platen, so as to achieve the purpose of adhesive curing and forming the adhesion of the chip semi-finished product and the heat dissipation cover (the curing time and curing temperature provided by the upper and lower heating platens at this time are generally determined by the material properties of the adhesive), after the curing of the ASA machine is completed, the finished chip unit is sent into the oven for drying and secondary full curing (this step is mainly to further ensure the full curing of the glue).

[0026] Therefore, the existing FCBGA packaging technology faces the following technical problems: 1) TIM interface integrity damage due to CTE mismatch: During the global heating process of traditional ASA process, the difference in thermal expansion coefficient between the substrate (CTE 16 ppm / ℃), the chip (2.6 ppm / ℃) and the heat sink cover (17 ppm / ℃) leads to uncontrollable composite warping of the packaging structure (including substrate dominated "smile" deformation and local "cry" deformation at the edge of the chip). This thermal mechanical stress makes the TIM interface contact pressure distribution seriously uneven, especially in the chip edge area, the contact pressure drops by >60%, resulting in the TIM effective coverage rate from the designed value of 98% to 82-85%.

[0027] 2) Inherent contradiction of process temperature requirements: The existing technology cannot meet the following requirements at the same time: the adhesive glue curing requires high temperature conditions of ≥150℃ (the epoxy resin Tg is usually 130-150℃); the TIM interface stability requires a low temperature environment of ≤120℃ (the viscosity of organic TIM decreases by 3 orders of magnitude when the temperature exceeds this value, and the interface stress of graphite TIM increases by 300%) 3) Defects of insufficient long-term reliability: The existing scheme shows the following problems in temperature cycle test (-55℃~125℃): the edge delamination rate reaches 38.7-52.3% after 500 cycles; the thermal resistance increases by more than 200%. These failures are caused by interface fatigue due to thermal stress accumulation.

[0028] 4) Limitations of material performance and structure design: The current improvement scheme has an irreconcilable contradiction: the boss design increases the processing cost of the heat sink cover by 30% and is ineffective for small chips; the double glue system narrows the process window by 50%; the reinforced frame violates the thin trend (increases the thickness by 0.2mm).

[0029] 5) Precise regulation requirements of thermal-mechanical coupling field: The existing technology lacks coordinated control of multiple physical fields in the ASA process. Temperature field: global uniform distribution cannot match the regionalized requirements; stress field: uniform pressure leads to edge stress concentration; rheological field: TIM viscosity is strongly related to temperature but cannot be adjusted in different zones.

[0030] In view of the technical problems of the existing FCBGA packaging technology, as shown in Figure 1 An aspect of the embodiments of the present disclosure provides a hot-pressing jig 100 for pressurizing and partition temperature control of a chip package 200.

[0031] The hot-pressing jig 100 comprises a first heating platen 110 and a second heating platen 120, and the chip package is clamped between the first heating platen 110 and the second heating platen 120; wherein the first heating platen 110 and the second heating platen 120 each comprise a heating zone 130 and a cooling zone 140 to realize partition temperature control of the chip package through the heating zone 130 and the cooling zone 140. AsFigure 2 As shown, taking the first heating plate 110 as an example, the heating zone 130 is located in the edge region of the first heating plate 110, and the cooling zone 140 is located in the central region of the first heating plate 110. The structure of the second heating plate 120 is similar to that of the first heating plate 110.

[0032] like Figure 1 As shown, in this embodiment, the chip package 200 is described using an FCBGA chip package as an example. The chip package 200 includes a substrate 210, a chip 220 flip-chip disposed on the substrate 210, a thermal interface material layer 230 disposed on the chip 220, and a heat dissipation cap 250 fixed to the edge of the substrate 210 by an adhesive layer 240. The heating zones 130 in the first heating platen 110 and the second heating platen 120 correspond to the adhesive layer area, and the cooling zones 140 in the first heating platen 110 and the second heating platen 120 correspond to the chip area.

[0033] During the heating and pressurization of the chip package 200, the heating zone 130 heats the adhesive layer area to cure the adhesive layer 240, thereby fixing the heat sink 250 to the substrate 210; the cooling zone 140 cools the chip area, so that the chip area is in a non-heated state, reducing the possibility of warping of the chip area, especially the chip center and edges, due to high temperature, thereby reducing the phenomenon of reduced thermal interface material layer coverage caused by product warping.

[0034] The hot pressing fixture of this disclosure provides heating and cooling zones on both the first and second heating plates to achieve zoned temperature control according to the heating requirements of the chip package. By establishing an active thermal stress regulation mechanism, a high temperature of 150°C to 180°C is maintained in the adhesive curing zone to ensure full cross-linking of the adhesive, while the chip-TIM-heat sink interface zone is controlled within a suitable relatively low temperature range. This decouples the CTE mismatch effect from a thermodynamic perspective, increasing the TIM edge coverage to ≥97% and reducing warpage to ≤40μm (compared to the existing ≥120μm), fundamentally suppressing interface failure caused by CTE mismatch. This achieves coordinated control of the adhesive curing zone (high temperature) and the TIM interface zone (low temperature), meeting the different temperature requirements of the chip package. It does not increase any material cost or structural complexity, saving costs.

[0035] For example, such as Figure 1 and Figure 2As shown, a heat insulation area 150 is arranged between the heating area 130 and the cooling area 140. The heat insulation area 150 is provided with a heat insulation member for blocking heat transfer between the heating area 130 and the cooling area 140, so as to better ensure the heating effect of the heating area 130 and the cooling effect of the cooling area 140.

[0036] The heat insulation member can be composed of a heat blocking material, and heat transfer is blocked by a material with low thermal conductivity or air / inert gas in a closed pore. For example, aerogel with a thermal conductivity of 0.013 W / (m•K)~0.025 W / (m•K), glass wool / rock wool, foamed ceramic / foamed glass, etc. can be used. The material of the heat insulation member is not limited in the embodiment, and can be selected according to actual needs.

[0037] As shown in the figure, Figure 3 The heating area 130 includes a heating member 131 for heating the high-temperature area of the chip package 200 to a preset heating temperature.

[0038] Specifically, in the embodiment, the heating member 131 is used to heat the bonding adhesive layer area of the chip package 200 to 150°C or above, so as to cure the bonding adhesive layer 240, and then fix the heat dissipation cover 250 to the substrate 210.

[0039] In the embodiment, the area of the heating area 130 covers the area of the bonding adhesive layer 240, so as to better heat and cure the bonding adhesive layer 240. Specifically, the width of the heating area 130 ranges from 0.5 mm to 15 mm.

[0040] As shown in the figure, Figure 4 The heating member 131 can be in a S-shaped distribution with the head connected to the tail; as shown in the figure, Figure 5 The heating member 131 can be in a grid distribution. The distribution of the heating member 131 is not limited in the embodiment, and can be selected according to actual needs.

[0041] It should be noted that in the embodiment, the heating member 131 can be a thermocouple, and the material of the heating area 130 can be tungsten-rhenium alloy (temperature resistance > 300°C). The specific structure of the heating member 131 is not limited in the embodiment, and can be selected according to actual needs.

[0042] As shown in the figure, Figure 3 The heating area 130 further includes a first temperature sensor 132 for monitoring and regulating the temperature of the heating area 130 in real time. Specifically, when the temperature of the heating area 130 is less than the preset heating temperature, the heating member 131 continues to heat until the preset heating temperature is reached.

[0043] In the embodiment, the temperature of the heating area can be dynamically adjusted by the cooperation of the heating element and the first temperature sensor, so that the high temperature area of the chip package can be better heated.

[0044] As shown in the figure, Figure 3 The cooling area 140 includes a cooling element 141 for cooling the low temperature area of the chip package 200 to a preset cooling temperature.

[0045] Specifically, in the embodiment, the cooling element 141 is used to cool the chip area of the chip package 200 to room temperature, avoiding the heat energy conducted from the heating area 130 from heating the chip area, so that the chip area is in a non-heating state, reducing the possibility of warping of the chip area, especially the center and edges of the chip, due to high temperature, thereby reducing the phenomenon of reduced coverage of the thermal interface material layer due to product warping.

[0046] It should be noted that in the embodiment, the cooling element 141 can adopt a thermoelectric refrigeration array or a micro-channel liquid cooling auxiliary, for example: loading an aluminum nitride ceramic substrate embedded with a micro-sized Peltier element, and realizing refrigeration through thermoelectric conversion of semiconductor materials. The structure of the cooling element 141 is not specifically limited and can be selected according to actual needs.

[0047] As shown in the figure, Figure 4 The cooling element 141 can be in an S-shaped distribution connected head to tail; as shown in the figure, Figure 5 The cooling element 141 can be in a grid-shaped distribution. The distribution of the heating element 131 is not specifically limited in the embodiment and can be selected according to actual needs.

[0048] As shown in the figure, Figure 3 The cooling area 140 further includes a second temperature sensor 142 for real-time monitoring and regulating the temperature of the cooling area 140. Specifically, when the heat of the heating area 130 is conducted to the cooling area 140, the temperature of the cooling area 140 is higher than the preset cooling temperature, and the cooling element 141 continues to cool to the preset cooling temperature.

[0049] In the embodiment, the temperature of the cooling area can be dynamically adjusted by the cooperation of the cooling element and the second temperature sensor, so that the low temperature area of the chip package can be better cooled.

[0050] It should be noted that in the embodiment, the partition temperature control accuracy of the heating area and the cooling area is ±1.5℃ (traditional overall heating ±5℃), and the temperature fluctuation of the gradient transition zone is <3℃ / mm.

[0051] As shown in the figure, Figure 6As shown, another aspect of the present disclosure provides a chip package partition heating packaging system, which comprises a chip package 200, a hot-pressing jig 100 and a controller; wherein the hot-pressing jig is the hot-pressing jig 100 described above. The structure of the hot-pressing jig 100 has been described in detail above, and will not be described here again.

[0052] The chip package 200 comprises a substrate 210, a chip 220 flip-chip mounted on the substrate 210, a thermal interface material layer 230 mounted on the chip 220, and a heat dissipation cover 250 fixed to the edge of the substrate 210 through an adhesive layer 240.

[0053] The first heating platen 110 is arranged on the heat dissipation cover 250, and the second heating platen 120 is arranged opposite to the first heating platen 110 and bears the substrate 210. That is, the substrate 210 is arranged on the second heating platen 120, and the first heating platen 110 is arranged on the heat dissipation cover 250. The first heating platen 110 and the second heating platen 120 sandwich the chip package 200. The first heating platen 110 and the second heating platen 120 are respectively provided with a heating zone 130 and a cooling zone 140 corresponding to the adhesive layer region and the chip region.

[0054] The controller is configured to control the hot-pressing jig 100 to pressurize the chip package 200. In addition, the controller is further configured to control the heating zone 130 to heat the adhesive layer region, and control the cooling zone 140 to cool the chip region, thereby realizing partition temperature control of the chip package 200.

[0055] For example, the controller is further configured to control the heating member 131 to heat the adhesive layer region to a preset heating temperature, so as to solidify the adhesive layer 240, thereby fixing the heat dissipation cover 250 to the substrate.

[0056] Specifically, in the present embodiment, the heating member 131 is configured to heat the adhesive layer region of the chip package 200 to 150°C or higher, so as to solidify the adhesive layer 240, thereby fixing the heat dissipation cover 250 to the substrate 210 and improving the reliability of the chip package.

[0057] For example, the controller is further configured to control the cooling member 141 to cool the chip region to a preset cooling temperature, so as to maintain the interface integrity of the thermal interface material layer 230.

[0058] Specifically, in the present embodiment, the cooling member 141 is used to cool the chip region of the chip package 200 to room temperature, avoiding the heat energy conducted from the heating area 130 from heating the chip region, so that the chip region is in a non-heating state, reducing the possibility of warping of the chip region, especially the center and edges of the chip, due to high temperature, thereby reducing the phenomenon of reduced coverage of the thermal interface material layer due to product warping, and further improving the reliability of the chip package.

[0059] For example, the controller is further configured to control the hot-pressing jig 100 to apply a first preset pressure to the chip region, and control the hot-pressing jig 100 to apply a second preset pressure to the adhesive layer region; wherein the first preset pressure is greater than the second preset pressure.

[0060] Specifically, in the present embodiment, the controller controls the hot-pressing jig 100 to apply a pressure of 0.3 MPa to 0.5 MPa to the chip region, and a pressure of 0.1 MPa to 0.2 MPa to the adhesive layer region, achieving pixel-level regulation of the thermal-mechanical coupling parameters. Wherein the pressure application repeatability is ±0.01 MPa (traditional ±0.05 MPa).

[0061] The chip package partition heating packaging system of the present embodiment has significant advantages in packaging quality, production efficiency, energy consumption, etc., which are specifically as follows: 1. The packaging quality is significantly improved: 1) TIM coverage optimization, TIM edge coverage is significantly improved, TIM interface thermal resistance is reduced; chip region TIM contact pressure uniformity is improved (traditional process <40%); 2) warpage control breakthrough, chip region maximum warpage is reduced (traditional process ≥80μm, improvement amplitude >68%); delamination rate after temperature cycling (-55℃~125℃) is reduced (traditional process 38.7-52.3%); 3) mechanical performance is enhanced, adhesive layer solidification strength is maintained >15MPa (ASTM D1002 standard), interface peel strength is improved.

[0062] 2. Production efficiency and cost advantage: 1) Process cycle is shortened, secondary baking step can be cancelled, single solidification time is shortened from traditional 180s+60min oven to 180s, UPH is improved by 33% (from 4.5 minutes / unit to 3 minutes / unit); 2) Energy consumption is reduced, only 15-20% effective area is heated, energy consumption is reduced by 40%, cooling water consumption is reduced (central chip area uses precise temperature control instead of overall cooling); 3) Material cost is saved, TIM material waste is reduced (edge overflow is reduced from 5% to <1%), adhesive usage is accurately controlled (tolerance is reduced from ±10mg to ±3mg).

[0063] 3. Process control advancement: 1) Temperature control accuracy, sub-zone temperature control accuracy ±1.5℃ (traditional overall heating ±5℃), gradient transition zone temperature fluctuation <3℃ / mm; 2) Pressure regulation capability: realize differential pressure control of 0.4MPa in the bonding adhesive layer area and 0.15MPa in the chip area, pressure application repeatability ±0.01MPa (traditional ±0.05MPa).

[0064] 4. Technological innovation advantage: 1) Strong process compatibility, suitable for various chip sizes from 3x3mm to 60x60mm, supporting multiple materials such as organic TIM (45-80℃) and graphite TIM (<150℃); 2) Reliability improvement: the chip package body heated and pressurized by the chip package body sub-zone heating packaging system will have a significant improvement in performance under reliability test environments such as uhast (accelerated humidity resistance test), TCT (cold thermal shock test), HTSL (high temperature storage test), etc., improving reliability.

[0065] The chip package body sub-zone heating packaging system of the embodiments of the present disclosure, without changing the existing FCBGA packaging structure and without increasing the cost of materials, establishes an active thermal stress regulation mechanism through innovative chip package body sub-zone temperature control technology, fundamentally solving the TIM interface failure problem caused by CTE mismatch. Compared with the traditional scheme, it realizes the technical leap from "passive bearing warping" to "active control deformation", providing a breakthrough solution for the reliable packaging of high-performance chips such as 5G, AI (PKG size is larger, chip warping is larger, chip power consumption is higher, etc.).

[0066] As shown in Figure 7 Another aspect of the embodiments of the present disclosure provides a chip package body sub-zone heating packaging method S100, which adopts the chip package body sub-zone heating packaging system described above. The structure of the chip package body sub-zone heating packaging system has been described in detail above, and will not be repeated here. The chip package body sub-zone heating packaging method S100 of the embodiments of the present disclosure can specifically include: S110, flip-chip mounting a chip on a substrate, and forming a bonding adhesive layer in the edge area of the substrate.

[0067] Specifically, as shown in Figure 8 The chip 220 is flip-chip mounted on the substrate 210. The bonding agent is coated in the edge area of the substrate 210 to form the bonding adhesive layer 240.

[0068] S120, forming a thermal interface material layer on the side of the chip away from the substrate.

[0069] Specifically, as shown in Figure 9 The thermal interface material layer 230 is formed by coating the thermal interface material on the back of the chip.

[0070] S130, placing the substrate on the second heating platen and fixing the heat dissipation cover on the substrate through the adhesive layer to form a chip package.

[0071] Specifically, as shown in FIG. 1 1, the substrate 210 is placed on the second heating platen 120, the heat dissipation cover 250 is adsorbed by the vacuum suction head, and the heat dissipation cover 250 is fixed on the edge region of the substrate 210 through the adhesive layer 240 to form a chip package. Figure 10

[0072] S140, placing the first heating platen cover on the heat dissipation cover and placing the second heating platen opposite to each other.

[0073] Specifically, as shown in FIG. 1 1, the first heating platen 110 is placed on the heat dissipation cover 250, and the second heating platen 120 is placed opposite to each other to form a cavity between them for clamping the chip package. Figure 11

[0074] S150, the second heating platen is lifted upward, and the first heating platen is fixed to provide a preset pressure on the chip package.

[0075] Specifically, as shown in FIG. 1 1, the second heating platen 120 is lifted upward, and the first heating platen 110 is fixed to provide a preset pressure on the chip package. In this embodiment, the controller controls the hot-pressing jig 100 to apply a pressure of 0.3 MPa~0.5 MPa on the chip region and a pressure of 0.1 MPa~0.2 MPa on the adhesive layer region, realizing pixel-level regulation of the thermal-mechanical coupling parameters. The pressure application repeatability is ±0.01 MPa (traditional ±0.05 MPa). Figure 12

[0076] S160, the controller controls the heating zone and the cooling zone to heat the adhesive layer region and cool the chip region, respectively.

[0077] Specifically, as shown in FIG. 1 1, the controller controls the heating member 131 to heat the adhesive layer region to a preset heating temperature to solidify the adhesive layer 240 and fix the heat dissipation cover 250 on the substrate. Figure 13 In this embodiment, the heating member 131 is used to heat the adhesive layer region of the chip package 200 to 150°C or above to solidify the adhesive layer 240 and fix the heat dissipation cover 250 on the substrate 210, thereby improving the reliability of the chip package.

[0078]

[0079] ​​​​The controller also controls the temperature reducing element 141 to reduce the temperature of the chip region to a preset temperature, so as to maintain the interface integrity of the thermal interface material layer 230.

[0080] In the embodiment, the temperature reducing element 141 is used to reduce the temperature of the chip region of the chip package 200 to room temperature, so as to avoid the heat energy conducted by the heating area 130 from heating the chip region, so that the chip region is in a non-heating state, and the possibility of warping of the chip region, especially the center and edges of the chip, due to high temperature is reduced, thereby reducing the phenomenon of reduction of the coverage of the thermal interface material layer due to warping of the product, and further improving the reliability of the chip package.

[0081] The chip package partition heating packaging method of the embodiment of the present disclosure fundamentally solves the TIM interface failure problem caused by CTE mismatch and improves the reliability of the chip package without changing the structure of the existing chip package and increasing the material cost.

[0082] It can be understood that the above embodiments are only exemplary embodiments for illustrating the principles of the embodiments of the present disclosure, and the embodiments of the present disclosure are not limited thereto. Various modifications and improvements can be made by those skilled in the art without departing from the spirit and essence of the embodiments of the present disclosure, and these modifications and improvements are also considered to be within the protection scope of the embodiments of the present disclosure.

Claims

1. A hot-pressing jig for pressurizing and partition temperature control of a chip package, characterized by, The hot-pressing jig comprises a first heating pressing plate and a second heating pressing plate, and the chip package is clamped between the first heating pressing plate and the second heating pressing plate. The first heating pressing plate and the second heating pressing plate each comprise a heating area and a cooling area to realize partitioned temperature control of the chip package.

2. The hot press tooling fixture of claim 1, wherein, A heat insulation area is arranged between the heating area and the cooling area, and a heat insulation member is arranged in the heat insulation area to block heat transfer between the heating area and the cooling area.

3. The hot press tooling fixture of claim 1, wherein, The heating area comprises a heating member for heating a high-temperature area of the chip package to a preset heating temperature.

4. The hot press tooling fixture of claim 3, wherein, The heating area further comprises a first temperature sensor for monitoring and regulating the temperature of the heating area in real time.

5. The hot press tooling fixture of any one of claims 1 to 4, wherein, The cooling area comprises a cooling member for cooling a low-temperature area of the chip package to a preset cooling temperature.

6. The hot press tooling fixture of claim 5, wherein, The cooling area further comprises a second temperature sensor for monitoring and regulating the temperature of the cooling area in real time.

7. A chip package partitioned heating package system, comprising: The chip package, the hot-pressing jig and a controller are provided, wherein the hot-pressing jig is the hot-pressing jig according to any one of claims 1 to 6. The chip package comprises a substrate, a chip flip-chip mounted on the substrate, a thermal interface material layer arranged on the chip, and a heat dissipation cover fixed to the edge of the substrate through an adhesive layer. The first heating pressing plate is arranged on the heat dissipation cover, and the second heating pressing plate is arranged opposite to the first heating pressing plate and bears the substrate, wherein the first heating pressing plate and the second heating pressing plate are respectively provided with a heating area and a cooling area corresponding to the adhesive layer area and the chip area. The controller is configured to control the hot-pressing jig to pressurize the chip package, and The controller is further configured to control the heating area to heat the adhesive layer area and control the cooling area to cool the chip area.

8. The system of claim 7, wherein, The controller is further configured to control the heating member to heat the adhesive layer area to a preset heating temperature, so as to solidify the adhesive layer and fix the heat dissipation cover to the substrate. The controller is further configured to control the cooling member to cool the chip area to a preset cooling temperature, so as to maintain the interface integrity of the thermal interface material layer.

9. The system of claim 7, wherein, The controller is further configured to control the hot-pressing jig to apply a first preset pressure and a second preset pressure to the chip area and the adhesive layer area respectively, wherein the first preset pressure is greater than the second preset pressure.

10. A method for partitioned heating of a chip package, comprising: The chip package partitioned heating packaging system according to any one of claims 7 to 9 comprises the following steps: A chip is flip-chip mounted on a substrate, and an adhesive layer is formed on the edge area of the substrate; A thermal interface material layer is formed on the side of the chip away from the substrate; The substrate is placed on a second heating pressing plate, and a heat dissipation cover is fixed to the substrate through the adhesive layer to form a chip package; A first heating pressing plate is arranged on the heat dissipation cover and placed opposite to the second heating pressing plate; The second heating pressing plate is lifted upward, and the first heating pressing plate is fixed to provide a preset pressure to the chip package; The controller controls the heating of the adhesive layer region by the heating zone and the cooling of the chip region by the cooling zone. The controller controls the heating of the adhesive layer region by the heating zone and the cooling of the chip region by the cooling zone.

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