Six-surface sealing method for 3D integrated chip

Abstract

The invention belongs to the technical field of packaging integrated chips, and relates to a six-surface packaging method for a 3D integrated chip. The method comprises the following steps: mounting a plurality of 3D integrated chips on a first wafer substrate; carrying out five-surface plastic package on the plurality of 3D integrated chips, thinning the plastic package of one side, far away from the first wafer substrate, of the plastic package wafer, and exposing the chips; etching a micro-channel and manifold channel structure on the back surface of the exposed chip; bonding a second wafer substrate on one side of the exposed chip of the plastic package wafer; performing pressed film encapsulation on one side of the plastic package wafer, which is provided with the external interconnection structure, and partially removing encapsulation on the external interconnection structure by adopting an ultrafast laser technology to expose the external interconnection structure; a heat dissipation cover plate is bonded and sealed on one side, provided with the micro-channel and manifold channel structure, of the chip; and preparing a solder ball connected with the external interconnection structure on the plastic package wafer. The external interconnection structure of the integrated chip is simplified, and the packaging process efficiency and reliability are improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of packaging integrated chips, and relates to a six-surface packaging method for a 3D integrated chip. BACKGROUND

[0002] Breakthroughs in disruptive technologies such as unmanned technology, artificial intelligence technology, and big data technology have led to an urgent demand for smaller, faster, and more intelligent high-end chips. Through 3D integrated chips, multiple functions can be integrated in a system at high density to comprehensively improve system performance, which has become an important development path for high-end chips. In order to reduce the damage to the chips caused by clamping and external environment during subsequent assembly and testing of the 3D integrated chips, and to consider the reliability of the chips in subsequent applications, the 3D integrated chips often need to be packaged. Currently, epoxy molding compound (EMC) is mainly used to package the 3D integrated chips at the wafer level in five or six surfaces. For the chips packaged in five surfaces, the surface with the pads and wiring layers is not wrapped with epoxy molding compound, so there is still a possibility of damage to this surface in subsequent processes. For the six-surface packaging technology, a copper pillar, a solder ball or other lead-out structures are prepared on the sixth surface, and then two five-surface packaging technologies are used in sequence, and the sixth surface is thinned to expose the interconnection structure. The existing six-surface packaging technology needs to prepare relatively complex lead-out structures, and the interconnection structure is prone to stress concentration during preparation and subsequent work, which may cause cracking, open circuit and other problems. On the other hand, the existing six-surface packaging technology does not consider the heat dissipation problem of high-power chips, and the heat dissipation is mainly achieved by using traditional cold plates or external jet cooling schemes, which have problems such as high peak temperature and poor temperature uniformity. SUMMARY

[0003] The purpose of the present application is to provide a six-surface packaging method for a 3D integrated chip to solve the technical problems that the surface with pads and wiring layers of a five-surface packaged chip is prone to damage in subsequent processes, the six-surface packaging technology needs to prepare complex lead-out structures and the interconnection structure is prone to cracking, and the six-surface packaging of high-power chips has poor temperature uniformity.

[0004] In order to achieve the above-mentioned purpose, the present application adopts the following technical solutions: The present application provides a six-surface packaging method for a 3D integrated chip, the 3D integrated chip comprising an external interconnection structure and a plurality of chips, comprising the following steps: S1, a plurality of the 3D integrated chips having the external interconnection structure are attached to a first wafer substrate; S2, the plurality of 3D integrated chips are packaged in five surfaces to obtain a packaged wafer, and the packaged wafer is thinned on the side away from the first wafer substrate to expose the chips; S3, etching micro-channel and manifold channel structure on the exposed back of the chip; S4, removing the first wafer substrate of the plastic package wafer, and bonding a second wafer substrate on the side of the plastic package wafer exposed to the chip; S5, film encapsulation on the side of the plastic package wafer with external interconnection structure, using ultrafast laser technology to partially remove the encapsulation on the external interconnection structure to expose the external interconnection structure; S6, removing the second wafer substrate of the plastic package wafer, and bonding a sealing heat dissipation cover plate on the side of the chip with the micro-channel and manifold channel structure; S7, preparing solder balls connected with the external interconnection structure on the plastic package wafer, and cutting the plastic package wafer with the 3D integrated chip as a basic unit.

[0005] Further, the said several 3D integrated chips with the external interconnection structure on one side are attached to the first wafer substrate, including: Several 3D integrated chips with the external interconnection structure on one side are attached to the first wafer substrate by adhesive; The adhesive uses thermal glass adhesive film, laser temporary bonding glue or hydrolysis glue.

[0006] Further, the said several 3D integrated chips are five-side plastic packaged to obtain a plastic package wafer, and the plastic package on the side of the plastic package wafer away from the first wafer substrate is thinned and exposed to the chip, including: Several 3D integrated chips are five-side plastic packaged to obtain a plastic package wafer, and the plastic package material forms a plastic package shell wrapping the 3D integrated chip; The said plastic package shell on the side of the plastic package wafer away from the first wafer substrate is mechanically thinned by the method of rough thinning first and then fine grinding to expose the chip away from the first wafer substrate.

[0007] Further, the said several 3D integrated chips are five-side plastic packaged to obtain a plastic package wafer, including: Liquid or powder plastic package material is used to plastic package the remaining five sides of several 3D integrated chips and fill the interlayer gap of 3D integrated chips to obtain a plastic package wafer; The thickness of the plastic package shell covering the top surface of the 3D integrated chip is 200um-500um.

[0008] Further, the said etching micro-channel and manifold channel structure on the exposed back of the chip, including: A multilayer mask is prepared on the exposed back surface of the chip by lithography, specifically: a low-pressure chemical vapor deposition silicon dioxide with a thickness of 50 nm is used as a protective film, a physical vapor deposition aluminum layer with a thickness of 100 nm is used as a hard mask, and a photoresist with a thickness of 10 μm is used as an etching mask; After the multilayer mask is prepared by lithography, the aluminum layer in the etching area is etched using a chemical reagent; After the aluminum layer is etched, an embedded microchannel and manifold channel structure is prepared using deep silicon etching technology; After the microchannel and manifold channel structure is prepared, the multilayer mask is removed using a chemical cleaning and plasma cleaning process.

[0009] Further, the method for removing the first wafer substrate of the plastic package wafer comprises: The first wafer substrate of the plastic package wafer is removed by heating, laser irradiation, and water washing; The method for removing the first wafer substrate of the plastic package wafer is the same as the method for removing the second wafer substrate of the plastic package wafer Further, the method for performing film pressing and encapsulation on the side of the plastic package wafer having external interconnection structures and partially removing the encapsulation on the external interconnection structures to expose the external interconnection structures using ultrafast laser technology comprises: Positioning marks are prepared on the side of the plastic package wafer having external interconnection structures; Film pressing and encapsulation are performed on the side of the plastic package wafer having external interconnection structures, and a plastic package material forms an encapsulation film layer; The encapsulation film layer is thinned to a target thickness, and the positioning marks are exposed; The encapsulation film layer and the corresponding part of the external interconnection structures are removed using ultrafast laser technology, and the external interconnection structures are exposed.

[0010] Further, the method for preparing positioning marks on the side of the plastic package wafer having external interconnection structures comprises: On the side of the plastic package wafer having external interconnection structures, positioning marks are prepared using a semi-additive wiring process, and the height of the positioning marks is greater than the target thickness; The method for performing film pressing and encapsulation on the side of the plastic package wafer having external interconnection structures, and a plastic package material forms an encapsulation film layer, comprises: A plastic package material is used to perform sixth face film pressing and encapsulation on the side of the plastic package wafer having external interconnection structures by vacuum hot pressing film technology, the plastic package material forms an encapsulation film layer, and the encapsulation film layer is baked and solidified; The method for thinning the encapsulation film layer to a target thickness to expose the positioning marks comprises: The encapsulation film layer is thinned to a target thickness by mechanical thinning or polishing technology, and the positioning mark is exposed; The part of the encapsulation film layer corresponding to the external interconnection structure is removed by using the ultrafast laser technology to expose the external interconnection structure, and the method comprises the following steps: The positioning mark is positioned, the part of the encapsulation film layer corresponding to the external interconnection structure is removed by using the ultrafast laser technology according to the relative position between the positioning mark and the external interconnection structure to expose the external interconnection structure.

[0011] Further, the sealing and heat-dissipating cover plate is bonded on the side of the chip with the microchannel and manifold channel structure, and the method comprises the following steps: On the side of the chip with the microchannel and manifold channel structure, a gold bonding layer, a tin bonding layer and an indium bonding layer are prepared by using a patterned thin film growth process, and the pattern transfer is performed by using a peeling method to complete the bonding of the sealing and heat-dissipating cover plate.

[0012] Further, the solder balls connected with the external interconnection structure are prepared on the plastic package wafer, and the method comprises the following steps: The organic material remaining on the surface of the external interconnection structure is removed by using a plasma dry etching method; The metal oxide on the surface of the external interconnection structure is removed by using a chemical etching method; Nickel and gold are prepared on the surface of the external interconnection structure by using a chemical plating method; The solder balls connected with the external interconnection structure are prepared on the surface of the plastic package wafer after the plastic package wafer is pressed and encapsulated by using a screen printing or laser ball planting method.

[0013] Compared with the prior art, the present application has the following beneficial effects: The present application attaches several 3D integrated chips on the first wafer substrate, avoids affecting the face of the 3D integrated chip having the external interconnection structure when the other five faces are molded. The five faces of the several 3D integrated chips are molded to prevent external mechanical damage and environmental corrosion, and at the same time, the existing 2.5D / 3D / fan-out packaging process can be compatible. The molded wafer far from the first wafer substrate is thinned and the chip is exposed to provide operating space for subsequent micro-channel etching, and at the same time, it is beneficial to reduce the thermal resistance. The micro-channel and manifold channel structure are etched on the back of the exposed chip, which is used to introduce high heat transfer coefficient fluid near the chip junction area to form an "embedded micro-fluid cooling" architecture, which is beneficial to eliminate local hot spots and improve system-level temperature uniformity. At the same time, the heat conduction path is significantly shortened, the peak temperature is significantly reduced, and the temperature uniformity is improved. The second wafer substrate is bonded on one side of the molded wafer having the exposed chip, and the second wafer substrate provides reverse support for the molded wafer, which is beneficial to reduce the warpage of the molded wafer and improve the packaging quality. The side of the molded wafer having the external interconnection structure is subjected to film pressing encapsulation to avoid the complexity of the traditional two five-face encapsulation process. The encapsulation on the external interconnection structure is partially removed by using ultrafast laser technology to expose the external interconnection structure. The low heat effect of ultrafast laser can reduce the stress change of the molded wafer, which is beneficial to reduce the warpage of the wafer. The sealing heat dissipation cover plate is bonded on the side of the chip having the micro-channel and manifold channel structure, and the heat dissipation cover plate and the micro-channel on the back of the chip form a closed cavity to prevent the leakage of the cooling fluid, while providing mechanical protection. The present application avoids the preparation of complex lead-out structures such as copper pillars / welding balls in the traditional six-face encapsulation, reduces the risk of cracking caused by stress concentration, significantly improves the reliability of the interconnection structure, and is compatible with 2.5D / 3D / fan-out packaging, which is beneficial to improve the encapsulation efficiency. Through the design of the micro-channel and manifold channel structure on the back of the chip, the heat conduction path is significantly shortened, which is beneficial to reduce the peak temperature and improve the temperature uniformity. The present application realizes full encapsulation protection by five-face molding and the sixth film pressing encapsulation. On the basis of five-face molding, the top chip is thinned to expose the sixth face, and the sixth face is subjected to film pressing encapsulation combined with laser removal method, which not only simplifies the external interconnection structure of the integrated chip, but also is beneficial to improve the packaging process efficiency and application reliability. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 The method flowchart of the embodiment of the present application is shown in the figure; Figure 2 The 3D integrated chip structure diagram of the embodiment of the present application is shown in the figure; Figure 3 The structure diagram of the embodiment of the present application is shown in the figure, in which the 3D integrated chip is attached to the wafer substrate by adhesive; Figure 4Structure diagram of the 3D integrated chip wafer after five-face plastic packaging of the embodiment of the present application; Figure 5 Structure diagram of the plastic packaged wafer after thinning of the embodiment of the present application; Figure 6 Structure diagram of the embodiment of the present application after etching of the micro-channel and manifold channel structure on the back of the chip; Figure 7 Structure diagram of the first wafer substrate after debonding of the embodiment of the present application; Figure 8 Structure diagram of the embodiment of the present application after preparation of the positioning mark; Figure 9 Structure diagram of the plastic packaged wafer after film coating on the sixth face of the embodiment of the present application; Figure 10 Structure diagram of the embodiment of the present application after thinning of the film layer on the sixth face; Figure 11 Structure diagram of the plastic packaged wafer after exposure of the external interconnection structure of the embodiment of the present application; Figure 12 Structure diagram of the plastic packaged wafer after bonding of the heat dissipation cover plate of the embodiment of the present application; Figure 13 Structure diagram of the embodiment of the present application after preparation of the solder ball on the external interconnection structure; Figure 14 Mechanical cutting effect diagram of the plastic packaged wafer of the embodiment of the present application; Figure 15 Method flow chart of another embodiment of the present application; Figure 16 Structure diagram of the 3D integrated chip after six-face packaging of the embodiment of the present application welded on the interconnection board; Figure 17 The diagram of the embodiment of the present application, wherein, diagram (a) is an electron microscope photo of the micro-channel etching result, and diagram (b) is a depth test result.

[0015] Wherein: 100, 3D integrated chip; 101, chip; 102, re-wiring layer; 103, interconnection bump; 104, fan-out substrate; 105, interconnection via structure; 106, external interconnection structure; 201, adhesive; 202, first wafer substrate; 203, second wafer substrate; 301, plastic package shell; 401, micro-channel and manifold channel structure; 501, positioning mark; 601, film layer; 701, heat dissipation cover plate; 801, solder ball; 901, interconnection board; 902, filler. DETAILED DESCRIPTION

[0016] In the following, the technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative effort should fall within the protection scope of the present application.

[0017] It should be noted that the terms "first", "second" and the like in the specification of the present application and the above-described accompanying drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0018] It should be noted that 2.5D packaging is an advanced technology between traditional 2D planar packaging and 3D vertical stacked packaging, the core of which is to realize high-density interconnection of multiple chips through an interposer, while maintaining the horizontal layout of the chips on the substrate. 3D integrated chip is a semiconductor technology that realizes higher integration by vertically stacking multiple chip layers. 3D packaging integrates multiple chips or wafers directly in the vertical direction (Z-axis) through chip stacking or package stacking.

[0019] The present application will be described in further detail below in conjunction with the accompanying drawings: Embodiment 1 Referring to Figure 1 The present embodiment discloses a six-sided packaging method for a 3D integrated chip, referring to Figure 2 The 3D integrated chip 100 includes a plurality of chips 101 and an external interconnection structure 106, comprising the following steps: S1, referring to Figure 3 A plurality of 3D integrated chips 100 having the external interconnection structure 106 are attached to one side of a first wafer substrate 202. The first wafer substrate 202 can provide stable mechanical support to avoid affecting the side of the 3D integrated chip 100 having the external interconnection structure 106 when the other five sides are molded. The S1 is specifically as follows: Several of the 3D integrated chips 100 with the external interconnection structure 106 on one side are attached to the first wafer substrate 202 by adhesive 201.

[0020] The adhesive 201 is a thermal glass film, a laser temporary bonding glue or a hydrolysis glue.

[0021] S2, see Figure 4 Several of the 3D integrated chips 100 are five-side molded to obtain a molded wafer, forming a physical protection layer to prevent external mechanical damage and environmental corrosion, and at the same time, being compatible with existing 2.5D / 3D / fan-out packaging processes, which is conducive to reducing the cost of technology migration. See Figure 5 The molded wafer far from the first wafer substrate 202 is thinned and the chip 101 is exposed, providing operating space for subsequent micro-channel etching, and at the same time, being conducive to reducing thermal resistance. The S2 is as follows: Several of the 3D integrated chips 100 are five-side molded to obtain a molded wafer, and the molding material forms a molded shell 301 wrapping the 3D integrated chip 100, including: Liquid or powdered molding material is used to mold the remaining five sides of the 3D integrated chip 100 and fill the interlayer gap of the 3D integrated chip 100 to obtain a molded wafer. At this time, the thickness of the molding shell 301 covering the top surface of the 3D integrated chip 100 is 200um-500um.

[0022] The molding shell 301 on the side of the molded wafer far from the first wafer substrate 202 is mechanically thinned by a rough thinning and then a fine grinding method to expose the chip 101 far from the first wafer substrate 202.

[0023] S3, see Figure 6 The micro-channel and manifold channel structure 401 are etched on the back of the exposed chip 101 to introduce a high heat transfer coefficient fluid near the chip junction region to form an "embedded micro-fluid cooling" architecture, which is conducive to eliminating local hot spots and improving system-level temperature uniformity. Avoiding the series thermal resistance problem caused by the multi-layer thermal interface material and thick metal cover plate in the traditional scheme, significantly reducing the peak temperature of the chip. At the same time, significantly shortening the heat conduction path, significantly reducing the peak temperature and improving the temperature uniformity, and having higher energy efficiency under the same pump power. The S3 is as follows: A multi-layer mask is prepared on the back of the exposed chip 101 by photolithography, and the multi-layer mask is specifically: a low-pressure chemical vapor deposition silicon dioxide with a thickness of 50nm is used as a protective film, a physical vapor deposition aluminum layer with a thickness of 100nm is used as a hard mask, and a photoresist with a thickness of 10μm is used as an etching mask.

[0024] After photolithography is used to prepare multilayer masks, the aluminum layer in the etched area is etched using chemical reagents.

[0025] After the aluminum layer is etched, the embedded microchannel and manifold channel structure 401 is prepared using deep silicon etching technology.

[0026] After the embedded microchannel and manifold channel structure 401 is fabricated, the multilayer mask is removed by chemical cleaning and plasma cleaning processes.

[0027] S4, see S4 Figure 7 The first wafer substrate 202 of the plastic-encapsulated wafer is removed, and a second wafer substrate 203 is bonded to one side of the exposed chip 101 of the plastic-encapsulated wafer. The second wafer substrate 203 provides reverse support for the plastic-encapsulated wafer, which helps to reduce the warpage of the plastic-encapsulated wafer and improve the packaging quality.

[0028] In this embodiment of the invention, the method for removing the first wafer substrate 202 from the molded wafer includes: The first wafer substrate 202 of the molded wafer is removed by heating, laser irradiation and water washing; S5, see S5. Figure 9 A lamination encapsulation process is performed on one side of the molded wafer with the external interconnect structure 106, avoiding the complexity of the traditional two-stage five-sided encapsulation process. Ultrafast laser technology is used to partially remove the encapsulation on the external interconnect structure 106, exposing the external interconnect structure 106. The low thermal effect of ultrafast lasers reduces stress changes on the molded wafer, which helps to reduce wafer warpage. S5 is specifically as follows: S51, see S51. Figure 8 A positioning mark 501 is prepared on one side of the molded wafer having the external interconnect structure 106, including: On one side of the molded wafer with the external interconnect structure 106, a positioning mark 501 is prepared using a semi-additive wiring process, wherein the height of the positioning mark 501 is greater than the target thickness.

[0029] S52, see S52. Figure 9 A molding compound is applied to one side of the molded wafer having the external interconnect structure 106, and the molding compound forms an encapsulation film layer 601, comprising: Using molding compound material, a sixth-side encapsulation is performed on one side of the molding wafer with the external interconnect structure 106 through vacuum hot pressing technology. The molding compound material forms an encapsulation film layer 601, which is then baked and cured.

[0030] S53, see also Figure 10 Thinning the encapsulation film layer 601 to the target thickness to expose the positioning mark 501 includes: The encapsulation film layer 601 is thinned to a target thickness by mechanical thinning or polishing techniques, exposing the positioning mark 501.

[0031] S54, see Figure 11 The portion of the encapsulation film layer 601 corresponding to the external interconnection structure 106 is removed by ultrafast laser technology, exposing the external interconnection structure 106, including: The positioning mark 501 is used for positioning, and the portion of the encapsulation film layer 601 corresponding to the external interconnection structure 106 is removed by ultrafast laser technology according to the relative position between the positioning mark 501 and the external interconnection structure 106, exposing the external interconnection structure 106.

[0032] S6, see Figure 12 The second wafer substrate 203 of the plastic encapsulation wafer is removed, and a sealing heat dissipation cover plate 701 is bonded on the side of the chip 101 having the microchannel and manifold channel structure 401. The heat dissipation cover plate 701 forms a closed cavity with the microchannel on the back of the chip, preventing leakage of the cooling fluid and providing mechanical protection. The S6 is as follows: On the side of the chip 101 having the microchannel and manifold channel structure 401, a gold bonding layer, a tin bonding layer, and an indium bonding layer are prepared by a patterned thin film growth process, and a pattern transfer is performed by a lift-off method to complete the bonding of the sealing heat dissipation cover plate 701.

[0033] The method of removing the first wafer substrate 202 of the plastic encapsulation wafer is the same as the method of removing the second wafer substrate 203 of the plastic encapsulation wafer.

[0034] S7, see Figure 13 Solder balls 801 connected to the external interconnection structure 106 are prepared on the plastic encapsulation wafer, and electrical connection between the chip and external circuit is established through the solder balls 801 to meet the system-level integration requirements, including: The residual organic material on the surface of the external interconnection structure 106 is removed by plasma dry etching.

[0035] The metal oxide on the surface of the external interconnection structure 106 is removed by chemical etching.

[0036] Nickel and gold are prepared on the surface of the external interconnection structure 106 by chemical plating.

[0037] Solder balls 801 connected to the external interconnection structure 106 are prepared on the surface of the plastic encapsulation wafer after pressure film encapsulation by screen printing or laser ball planting.

[0038] See Figure 14The plastic-encapsulated wafer is cut using the 3D integrated chip 100 as the basic unit, and a single 3D integrated chip 100 module is obtained after cutting, which is convenient for subsequent assembly and application.

[0039] This invention avoids the complex fabrication of copper pillars / solder balls 801 in traditional six-sided encapsulation, reducing the risk of cracking due to stress concentration and significantly improving the reliability of the interconnect structure. It is compatible with 2.5D / 3D / fan-out packaging, which is beneficial for improving encapsulation efficiency. The design of the microchannel and manifold channel structure 401 on the back of the chip significantly shortens the heat conduction path, which helps reduce peak temperature and improve temperature uniformity. This invention achieves fully enclosed protection by adding a sixth-sided lamination to the five-sided plastic encapsulation. Based on the five-sided plastic encapsulation, the top chip is further thinned and exposed. The sixth side is encapsulated using lamination and laser removal methods. While achieving the sixth-sided encapsulation, it avoids the fabrication of copper pillars, solder balls 801, and other lead-out structures, simplifying the external interconnect structure 106 of the integrated chip and improving packaging process efficiency and application reliability.

[0040] Example 2: See Figure 15 This embodiment proposes a six-sided encapsulation method for 3D integrated chips. It employs top-surface EMC thinning and exposure, deep silicon etching of flow channels and manifolds, EMC lamination, laser EMC removal, and wafer-level bonding to achieve efficient and reliable six-sided encapsulation of the 3D integrated chip 100, while also addressing the heat dissipation requirements of high-performance chips. The encapsulated 3D integrated chip 100 can be soldered to adapter boards, packaging carriers, and other structures to form more complex and multifunctional integrated microsystems.

[0041] See Figure 2 An example is shown of a three-layer stacked 3D integrated chip 100, but the present invention is not limited to this. Figure 2 The three-layer structure is shown. The 3D integrated chip 100 includes multiple chips 101. Chips 101 can be 3D integrated by fabricating a redistribution layer 102 and interconnect bumps 103 on their surfaces and then using flip-chip bonding. One or more chips 101 can also be embedded in a fan-out substrate 104 and 3D integrated by fabricating a redistribution layer 102, interconnect bumps 103, and interconnect via structures 105, using flip-chip bonding. The fan-out substrate 104 can be made of silicon, glass, or organic materials, etc. The bottom layer of the 3D integrated chip 100 should have external interconnect structures 106.

[0042] See Figure 15 The present invention provides a six-sided encapsulation method for 3D integrated chips, as detailed below: S10, Temporary mounting of 3D integrated chips 100. Multiple 3D integrated chips 100 are mounted onto a first wafer substrate 202 using adhesive 201 to form a 3D micro-module, such as... Figure 3As shown. The adhesive 201 can be a thermally bonded glass film, laser temporary bonding adhesive, or hydrolyzed adhesive, etc., which can be used to remove the encapsulated 3D integrated chip 100 from the first wafer substrate 202 through methods such as heating, laser irradiation, and washing, without leaving any adhesive residue. The material of the first wafer substrate 202 includes, but is not limited to, silicon and glass.

[0043] S20, 3D integrated chip 100 wafer-level molding. Using wafer-level molding technology, the 3D micro-module is molded to obtain a molded wafer. The molding material forms a molding shell 301 that encapsulates the five sides of the 3D integrated chip 100, such as... Figure 4 As shown. Preferably, liquid or powdered molding compound can be used to fill the interlayer gaps of the 3D integrated chip 100. The thickness after molding should be 200um to 500um higher than the top surface of the 3D integrated chip 100 to reduce molding voids.

[0044] S30, Molded Wafer Thinning. The molded wafer is mechanically thinned to expose the top chip 101, such as... Figure 5 As shown. Exposing chip 101 facilitates heat dissipation of the 3D integrated chip 100. Mechanical thinning can be performed by first coarse thinning and then fine grinding to reduce damage at the interface between chip 101 and plastic casing 301.

[0045] S40, heat dissipation structure fabrication. Microchannels and manifold channel structures 401 with different morphologies and sizes are etched on the back side of the exposed chip 101, such as... Figure 6 As shown, a multilayer mask was used during the etching process. This multilayer mask consisted of a 50nm thick low-pressure chemical vapor deposition (LPCVD) silicon dioxide layer as a protective film, a 100nm thick physical vapor deposition (PVD) aluminum layer as a hard mask, and a 10μm thick photoresist layer as an etching mask. The purpose of using a multilayer mask was to protect the non-etched areas of the bonding surface from etching. After photolithography to prepare the multilayer mask, the aluminum layer in the etchable area was etched using chemical reagents. Subsequently, deep reactive ion etching (DRIE) technology was used to fabricate the embedded microchannel and manifold channel structure 401. Finally, chemical cleaning and plasma cleaning processes were used to remove the multilayer mask.

[0046] S50, wafer substrate debonding. The encapsulated 3D integrated chip 100 is removed from the first wafer substrate 202 by means of heating, laser irradiation, water washing, etc. Optionally, a second wafer substrate 203 is temporarily bonded to the side of the chip 101 that exposes the top chip, such as... Figure 7 As shown, this can effectively reduce the warpage of molded wafers, facilitating subsequent wiring processes.

[0047] S60, preparation of positioning mark 501. On the side with external interconnection structure 106, positioning mark 501 is prepared by using a semi-additive wiring process, as shown in FIG. 6A. The height of positioning mark 501 should be higher than the target thickness of the sixth side encapsulation, and 20-50 μιη higher. Figure 8

[0048] S70, film encapsulation of the sixth side of the plastic-encapsulated wafer. Dry film adhesive is used to perform film encapsulation of the sixth side of the plastic-encapsulated wafer containing positioning mark 501 by vacuum hot-pressing film technology, and the plastic-encapsulated material forms encapsulation film layer 601, which is baked and cured, as shown in FIG. 6B. Figure 9

[0049] S80, thinning of the sixth side of the plastic-encapsulated wafer. Mechanical thinning or polishing technology is used to thin encapsulation film layer 601 to the target thickness of the sixth side encapsulation, while exposing positioning mark 501, as shown in FIG. 6C. Figure 10

[0050] S90, exposure of the external interconnection structure. According to the relative position between positioning mark 501 and external interconnection structure 106, the encapsulation film layer 601 on the external interconnection structure 106 is removed by using ultrafast laser, as shown in FIG. 6D. Figure 11

[0051] S100, surface treatment of external interconnection structure 106. Plasma dry etching is used to remove the organic material remaining on the surface of external interconnection structure 106, and chemical etching is used to remove the metal oxide on the surface. Finally, nickel, gold and other materials are prepared on the surface of external interconnection structure 106 by chemical plating, which is convenient for the preparation of solder balls 801. Alternatively, for the second wafer substrate 203 temporarily bonded on the side of the plastic-encapsulated wafer exposing top chip 101 in S5, the encapsulated 3D integrated chip 100 wafer can be removed from the second wafer substrate 203 by heating, laser irradiation and water washing.

[0052] ​​​​S110, bonding sealing heat dissipation cover plate 701. Gold bonding layer, tin bonding layer and indium bonding layer required for wafer level bonding are usually prepared by using a patterned thin film growth process, and pattern transfer is realized by using a lift-off method. The gold bonding layer is prepared by using a double-gun electron beam evaporation, and the thickness is usually 300-600 nm. The tin bonding layer and the indium bonding layer are prepared by using thermal evaporation, and the thickness is usually 4-6 μm. Different low-temperature eutectic bonding technologies such as (gold-tin, tin-tin, indium-indium) are usually used to bond the sealing heat dissipation cover plate 701 on the chip 101 with the microchannel and manifold channel structure 401, as shown in Figure 12 The method reduces the stress concentration phenomenon caused by bonding, relies on the thermal expansion coefficient matching between silicon-silicon / silicon-metal materials to realize airtight packaging, and greatly improves the thermal cycle reliability and anti-leakage performance of the device.

[0053] S120, ball planting on the sixth surface of the plastic encapsulated wafer. The solder balls 801 are prepared on the external interconnection structure 106 by using screen printing, laser ball planting and the like, as shown in Figure 13 for reflow soldering of the 3D integrated chip 100 and the packaging board after packaging.

[0054] S130, mechanical cutting of the plastic encapsulated wafer. The plastic encapsulated wafer after six surface packaging is cut and diced by using mechanical cutting, and finally the single six surface packaged 3D integrated chip 100 is obtained, as shown in Figure 14

[0055] For S12 and S13, the two processes can be interchanged as needed.

[0056] The process of the present application is compatible with 2.5D / 3D / fan-out and other advanced packaging forms. On the one hand, based on wafer level five surface plastic packaging, the top chip is further thinned to expose the EMC, and the sixth surface is thinned by EMC film pressing, laser EMC removal and the like, which realizes the sixth surface packaging while avoiding the preparation of copper pillars, solder balls 801 and the like. This not only simplifies the external interconnection structure 106 of the integrated chip, but also improves the packaging process efficiency and application reliability. On the other hand, for the thermal management problem of high-power microsystems, the microchannel and manifold channel structure 401 is integrated in the silicon cover plate, the high heat transfer coefficient fluid is introduced into the vicinity of the chip 101 junction, and the series thermal resistance caused by the multi-layer thermal interface material and thick metal cover plate is completely eliminated. Compared with the traditional cold plate or external jet cooling scheme, the system-level embedded microfluid of the present application can establish the shortest heat conduction path, significantly reduce the peak temperature and improve the temperature uniformity, and has higher energy efficiency under the same pump power.

[0057] Referring to Figure 16 ​The six-side packaged 3D integrated chip 100 formed by the present application can be directly welded on an interconnection substrate 901, which includes but is not limited to a transition board, an organic substrate, a ceramic substrate, a PCB and the like, and a gap is filled with a filler 902. The packaged 3D integrated chip 100 is electrically interconnected with an external electronic system through the interconnection substrate 901, thereby realizing a high-performance microsystem. A heat dissipation system on the surface of the 3D integrated chip 100 is composed of a cooling liquid, a microchannel and a manifold channel structure 401. The cooling liquid is introduced into a plurality of microchannels through a manifold, and then flows through the entire surface of the microchannels. The high surface area of the microchannels is in contact with the cooling liquid, so that the heat dissipation is more rapid and effective. The design of the manifold can ensure that the cooling liquid is uniformly distributed in each channel, avoiding uneven flow and local overheating, ensuring uniform temperature distribution and reducing local hot spots. In order to minimize thermal resistance, a multi-physical field numerical simulation software is used to optimize the flow channel size of the heat source area. A deep silicon etching process is used to prepare embedded microchannels, as shown in Figure 17 (a) is a microchannel etching result electron microscope photo, and (b) is a depth test result.

[0058] The above is only to illustrate the technical idea of the present application, and cannot limit the protection scope of the present application. Any modification made according to the technical idea of the present application on the basis of the technical scheme falls within the protection scope of the present application.

Claims

1. A six-sided encapsulation method for a 3D integrated chip, the 3D integrated chip (100) comprising an external interconnect structure (106) and a plurality of chips (101), characterized in that, Includes the following steps: S1, a plurality of the 3D integrated chips (100) having one side of the external interconnection structure (106) are mounted on a first wafer substrate (202); S2, the 3D integrated chips (100) are encapsulated on five sides to obtain a plastic-encapsulated wafer. The plastic encapsulation on the side of the plastic-encapsulated wafer away from the first wafer substrate (202) is thinned to expose the chip (101). S3, etching microchannel and manifold channel structures (401) on the exposed back side of the chip (101). S4, remove the first wafer substrate (202) of the plastic-encapsulated wafer, and bond the second wafer substrate (203) to one side of the exposed chip (101) of the plastic-encapsulated wafer. S5, a lamination is applied to one side of the molded wafer with the external interconnect structure (106), and the encapsulation on the external interconnect structure (106) is partially removed using ultrafast laser technology to expose the external interconnect structure (106). S6, remove the second wafer substrate (203) of the plastic-encapsulated wafer, and bond a sealing heat dissipation cover plate (701) to the side of the chip (101) having the microchannel and manifold channel structure (401). S7, solder balls (801) connected to the external interconnect structure (106) are prepared on the plastic-encapsulated wafer, and the plastic-encapsulated wafer is cut with the 3D integrated chip (100) as the basic unit.

2. The six-sided encapsulation method for 3D integrated chips according to claim 1, characterized in that, The step of mounting one side of the plurality of 3D integrated chips (100) having the external interconnect structure (106) onto the first wafer substrate (202) includes: One side of the plurality of 3D integrated chips (100) having the external interconnection structure (106) is attached to the first wafer substrate (202) by adhesive (201); The adhesive (201) is a hot glass film, a laser temporary bonding adhesive, or a hydrolyzed adhesive.

3. The six-sided encapsulation method for 3D integrated chips according to claim 1, characterized in that, The step of performing five-sided molding on a plurality of the 3D integrated chips (100) to obtain a molded wafer, and thinning the molding on the side of the molded wafer away from the first wafer substrate (202) to expose the chip (101), includes: A plastic-encapsulated wafer is obtained by five-sided plastic encapsulation of several 3D integrated chips (100), and the plastic encapsulation material forms a plastic encapsulation shell (301) that encapsulates the 3D integrated chips (100). The plastic casing (301) on the side of the plastic-encapsulated wafer away from the first wafer substrate (202) is mechanically thinned by first coarse thinning and then fine grinding to expose the chip (101) away from the first wafer substrate (202).

4. The six-sided encapsulation method for 3D integrated chips according to claim 3, characterized in that, The process of performing five-sided molding of a plurality of the 3D integrated chips (100) to obtain a molded wafer includes: Using liquid or powdered molding compound, the remaining five sides of several 3D integrated chips (100) are molded and the interlayer gaps of the 3D integrated chips (100) are filled to obtain a molded wafer; The thickness of the plastic encapsulation shell (301) covering the top surface of the 3D integrated chip (100) is 200um~500um.

5. A six-sided encapsulation method for 3D integrated chips according to claim 1, characterized in that, The etching of microchannel and manifold channel structures (401) on the exposed back side of the chip (101) includes: A multilayer mask is photolithographically prepared on the back side of the exposed chip (101). Specifically, the multilayer mask is prepared by using a 50nm thick low-pressure chemical vapor deposition silicon dioxide as a protective film, a 100nm thick physical vapor deposition aluminum layer as a hard mask, and a 10μm thick photoresist as an etching mask. After photolithography is used to prepare multilayer masks, chemical reagents are used to etch the aluminum layer in the etched area; After the aluminum layer is etched, the embedded microchannel and manifold channel structure is prepared using deep silicon etching technology (401). After the microchannel and manifold channel structure (401) is prepared, the multilayer mask is removed by chemical cleaning and plasma cleaning processes.

6. The six-sided encapsulation method for 3D integrated chips according to claim 1, characterized in that, The method for removing the first wafer substrate (202) from the molded wafer includes: The first wafer substrate (202) of the molded wafer is removed by heating, laser irradiation and water washing. The method for removing the first wafer substrate (202) of the molded wafer is the same as the method for removing the second wafer substrate (203) of the molded wafer.

7. The six-sided encapsulation method for 3D integrated chips according to claim 1, characterized in that, The step of laminating and encapsulating one side of the molded wafer with the external interconnect structure (106) and partially removing the encapsulation on the external interconnect structure (106) using ultrafast laser technology to expose the external interconnect structure (106) includes: A positioning mark (501) is prepared on one side of the molded wafer having an external interconnect structure (106). A molding encapsulation is performed on one side of the molded wafer that has an external interconnect structure (106), and the molding material forms an encapsulation film layer (601). The encapsulation film layer (601) is thinned to the target thickness to expose the positioning mark (501). Ultrafast laser technology is used to remove the portion of the encapsulation layer (601) corresponding to the external interconnect structure (106), exposing the external interconnect structure (106).

8. A six-sided encapsulation method for 3D integrated chips according to claim 7, characterized in that, The step of fabricating a positioning mark (501) on one side of the molded wafer having an external interconnect structure (106) includes: On one side of the molded wafer with an external interconnect structure (106), a positioning mark (501) is prepared using a semi-additive wiring process, wherein the height of the positioning mark (501) is greater than the target thickness; The process of laminating and encapsulating the molded wafer on one side having the external interconnect structure (106), wherein the molding material forms an encapsulation film layer (601), includes: Using molding compound, a sixth-side encapsulation is performed on the side of the molding wafer with external interconnect structure (106) by vacuum hot pressing film technology. The molding compound forms an encapsulation film layer (601), and the encapsulation film layer (601) is baked and cured. The step of thinning the encapsulation film layer (601) to the target thickness to expose the positioning mark (501) includes: The encapsulation film layer (601) is thinned to the target thickness using mechanical thinning or polishing techniques, exposing the positioning mark (501). The step of using ultrafast laser technology to remove the portion of the encapsulation layer (601) corresponding to the external interconnect structure (106) to expose the external interconnect structure (106) includes: Positioning is performed using the positioning mark (501). Based on the relative position between the positioning mark (501) and the external interconnection structure (106), ultrafast laser technology is used to remove the portion of the encapsulation layer (601) corresponding to the external interconnection structure (106), exposing the external interconnection structure (106).

9. A six-sided encapsulation method for 3D integrated chips according to claim 1, characterized in that, The bonding and sealing heat dissipation cover plate (701) on one side of the chip (101) having the microchannel and manifold channel structure (401) includes: On the side of the chip (101) having the microchannel and manifold channel structure (401), a gold bonding layer, a tin bonding layer and an indium bonding layer are prepared using a patterned thin film growth process, and a pattern transfer is performed using a stripping method to complete the bonding of the sealed heat dissipation cover plate (701).

10. A six-sided encapsulation method for 3D integrated chips according to claim 1, characterized in that, The fabrication of solder balls (801) on the molded wafer and connected to the external interconnect structure (106) includes: The residual organic material on the surface of the external interconnect structure (106) was removed by plasma dry etching; The metal oxides on the surface of the external interconnect structure (106) are removed by chemical etching. Nickel and gold were prepared on the surface of the external interconnect structure (106) by chemical electroplating; Solder balls (801) that are connected to the external interconnect structure (106) are prepared on the surface of the plastic-encapsulated wafer after lamination and encapsulation by means of screen printing or laser ball placement.

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