Packaging structure and method of manufacturing the same

Abstract

Provided are a packaging structure and a preparation method thereof. The packaging structure comprises a packaging substrate, a plurality of chips, a filling layer, a conductive column and a rewiring layer. The packaging substrate has at least one mounting groove. A plurality of chips are arranged in the mounting groove. The filling layer is arranged between the chips. A plurality of first through holes are formed through the filling layer and the bottom of the mounting groove. The conductive column is arranged in the first through hole and electrically connected to the chip. The rewiring layer is arranged on the surface of the packaging substrate and electrically connected to the conductive column. The packaging structure integrates a plurality of chips in the same packaging substrate to form a large array planar packaging structure, which can significantly increase the throughput of biochemical substance analysis, improve the accuracy of biochemical substance analysis, reduce labor costs, and reduce the risk of line corrosion by reagents, line short circuit and chip failure.

Description

Technical Field

[0001] This application relates to the field of biochemical analysis technology, and in particular to an encapsulation structure and its preparation method. Background Technology

[0002] With the development of sequencing technology, the demands for the efficiency and functional versatility of sequencing chips are increasing. Currently, commonly used low-throughput targeted sequencing chips typically employ traditional soldering methods to connect the chip to the circuit board, then encapsulate and protect the solder wires with glue, and finally fix a cover plate on top of the chip. Sequencing samples enter the sequencing chip through small holes in the cover plate. This encapsulation method for low-throughput targeted sequencing chips limits the sequencing rate and accuracy, and also suffers from problems such as solder wires being easily corroded by reagents and the chip being easily contaminated by glue. Therefore, this type of low-throughput targeted sequencing chip is far from meeting the needs of the public and urgently requires improvement. Summary of the Invention

[0003] To address at least one of the above-mentioned shortcomings, it is necessary to propose a packaging structure, which is a large-array planar packaging structure, that can effectively improve the throughput and accuracy of biochemical analysis.

[0004] In addition, this application also provides a method for preparing the aforementioned packaging structure.

[0005] In a first aspect, embodiments of this application provide a packaging structure, the packaging structure comprising: a packaging substrate, a plurality of chips, a filler layer, conductive pillars, and a redistribution layer, wherein the packaging substrate has at least one mounting slot; a plurality of chips are spaced apart in each mounting slot; a first gap is formed between two adjacent chips, and a second gap is formed between the chips and the sidewall of the mounting slot; the filler layer is located in the first gap and the second gap, and a plurality of first through holes are formed through the filler layer and the bottom of the mounting slot, the first through holes being located around each chip; the conductive pillars are located in the first through holes, and the conductive pillars are electrically connected to the chips; the redistribution layer is located on the surface of the packaging substrate away from the opening of the mounting slot, and the redistribution layer is electrically connected to the conductive pillars.

[0006] In some possible embodiments, the package structure further includes a connection pad located on the end face of the conductive post near the opening of the mounting slot, the connection pad extending to the surface of the filler layer and the chip, and the conductive post being electrically connected to the chip through the connection pad.

[0007] In some possible embodiments, the chip is a biochip, the surface of the chip near the opening of the mounting slot is the front side, the front side is provided with a biofunctional layer and pins located around the periphery of the biofunctional layer, the biofunctional layer is exposed from the encapsulation substrate, and the connecting pad extends to the surface of the pins.

[0008] In some possible embodiments, the packaging structure further includes an insulating layer on the surface of the redistribution layer and a connection portion on the insulating layer, the connection portion being electrically connected to the redistribution layer.

[0009] In some possible embodiments, the packaging substrate is a monolithic substrate with a plurality of second through holes formed through the bottom of the mounting groove, the second through holes being located around each of the chips, and the filler layer extending to the second through holes.

[0010] In some possible embodiments, the encapsulation substrate includes a substrate and an encapsulation layer stacked along the thickness direction. The substrate has at least one opening, and the encapsulation layer includes a first portion, a second portion, and a third portion that are interconnected. The first portion is located on the surface of the substrate, the second portion corresponds to the opening, the substrate and the second portion form the mounting groove, and the third portion is located within the mounting groove and within the first gap and the second gap. The third portion constitutes the filler layer.

[0011] Secondly, embodiments of this application provide a method for preparing a packaging structure, including: At least one mounting groove is formed on the packaging substrate; Multiple chips are spaced apart in each of the mounting slots, with a first gap between two adjacent chips and a second gap between the chips and the sidewall of the mounting slot. A plurality of second through holes are formed through the bottom of the mounting groove, and the second through holes are located around each of the chips; A filling layer is formed within the first gap and the second gap, and the filling layer extends into the second through hole; A first through-hole is formed by penetrating the filler layer; A conductive post is formed in each of the first vias, and the conductive post is electrically connected to the chip; and A redistribution layer is formed on the surface of the encapsulation substrate opposite to the opening of the mounting groove. The redistribution layer is electrically connected to the conductive pillar, thereby obtaining the encapsulation structure.

[0012] In some possible embodiments, the step of forming a conductive post in each of the first vias and electrically connecting the conductive post to the chip includes: A dielectric layer is formed on the surface of the filling layer near the opening of the mounting groove, and the dielectric layer extends to the surface of the chip; Pattern the dielectric layer to expose the first via and the pins on the chip; and The conductive post is formed in the first through hole, and a connecting pad is formed on the surface of the filling layer. The connecting pad electrically connects the conductive post and the pin.

[0013] In some possible embodiments, after the step of forming the redistribution layer, the fabrication method further includes: An insulating layer is formed on the surface of the redistribution layer, and a connection portion is formed on the surface of the insulating layer, the connection portion being electrically connected to the redistribution layer.

[0014] Thirdly, embodiments of this application provide another method for preparing a packaging structure, including: At least one groove is formed on the substrate; Multiple chips are spaced apart in each of the grooves, with a first gap between two adjacent chips and a second gap between the chips and the sidewall of the groove. An encapsulation layer is formed on the surface of the substrate, the encapsulation layer extends into the groove, the encapsulation layer includes a first portion on the substrate, a second portion corresponding to the groove, and a third portion extending into the groove, the third portion constituting a filling layer located in the first gap and the second gap; A portion of the substrate is removed to expose the surface of the chip, and the remaining substrate and the second portion form a mounting groove; A first through-hole is formed by penetrating the filler layer and the corresponding second portion; A conductive post is formed in each of the first vias, and the conductive post is electrically connected to the chip; and A redistribution layer is formed on the surface of the encapsulation layer away from the substrate, and the redistribution layer is electrically connected to the conductive pillars to obtain the encapsulation structure.

[0015] The packaging structure and its preparation method provided in this application integrate multiple chips (e.g., sequencing chips) into the same packaging substrate to form a large array planar packaging structure. This significantly increases the throughput of biochemical analysis, improves the accuracy of biochemical analysis, and reduces labor costs. Furthermore, multiple chips within the same mounting slot can have multiple functions, enhancing the versatility of the chips in the packaging structure. Electrical lead-out of the chips is achieved by forming a first through-hole and a conductive pillar within it within the packaging substrate. Therefore, the electrical lead-out lines are not exposed, effectively reducing the risks of reagent corrosion, short circuits, and chip failure. The electrical lead-out method eliminates the need for wire bonding, thus avoiding the use of adhesive and preventing the influence of adhesive on chip performance, thereby improving the accuracy of biochemical analysis. Additionally, multiple chips in the packaging structure can be independently controlled, and the failure of a few chips will not affect the use of the entire large array. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the packaging structure according to an embodiment of this application.

[0018] Figure 2 This is a schematic flowchart illustrating a method for fabricating a packaging structure according to an embodiment of this application.

[0019] Figures 3A to 3J for Figure 1 A schematic diagram of the fabrication process of the encapsulated structure.

[0020] Figure 4 This is a schematic diagram of the packaging structure according to another embodiment of this application.

[0021] Figure 5 This is a schematic flowchart illustrating a method for preparing a packaging structure according to another embodiment of this application.

[0022] Figures 6A to 6F for Figure 4 A schematic diagram of the fabrication process of the encapsulation structure.

[0023] Explanation of main component symbols The following detailed description, in conjunction with the accompanying drawings, will further illustrate this application. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0025] It should be noted that when a component is described as "fixed to" or "mounted to" another component, it can be directly on the other component or may be interspersed with an intermediate component. When a component is described as "set to" another component, it can be directly set on the other component or may be interspersed with an intermediate component. The term "and / or" as used herein includes all and any combination of one or more of the associated listed items.

[0026] Please see Figure 1 As shown in the figure, this application embodiment provides a packaging structure 100, which includes: a packaging substrate 1, a plurality of chips 2, a filling layer 3, conductive pillars 4, and a redistribution layer 5. The packaging substrate 1 has at least one mounting groove 11, and a plurality of chips 2 are spaced apart in each mounting groove 11. The filling layer 3 is located between two adjacent chips 2 and between the chips 2 and the sidewalls of the mounting groove 11, that is, the filling layer 3 can fill the first gap 12 formed between two adjacent chips 2, or fill the second gap 13 between the chips 2 and the sidewalls of the mounting groove 11, thereby fixing the chips 2 in the mounting groove 11. A plurality of first through holes 31 are formed through the filling layer 3 and the bottom of the mounting groove 11, and the first through holes 31 are located around each chip 2. The conductive pillars 4 are located in the first through holes 31 and are electrically connected to the chips 2. Specifically, the conductive pillars 4 may include a first end face 41 and a second end face 42 disposed opposite to each other, and the first end face 41 is close to the opening of the mounting groove 11. The redistribution layer 5 is located on the surface of the package substrate 1 opposite to the opening of the mounting groove 11, and is electrically connected to the conductive pillar 4, further enabling the electrical lead-out of the chip 2. The redistribution layer 5 can be used to achieve electrical connection between the package structure 100 and other functional components (e.g., circuit boards). The electrical lead-out of the chip 2 is achieved through the conductive pillar 4 and the redistribution layer 5. Specifically, this package structure 100 can be used in the field of biochemical analysis (e.g., gene sequencing).

[0027] The encapsulation substrate 1 may include a first surface 101 and a second surface 102 disposed opposite to each other, wherein the first surface 101 is recessed towards the second surface 102 to form a mounting groove 11. By forming one or more mounting grooves 11 on the encapsulation substrate 1, multiple chips 2 can be mounted in each mounting groove 11, effectively improving the throughput and efficiency of biochemical analysis (e.g., sequencing throughput and sequencing efficiency). In addition, embedding multiple chips 2 within the encapsulation substrate 1 helps to reduce the thickness of the encapsulation structure 100 and improves the connection stability of the chips 2. The multiple chips 2 described in this application may be gene sequencing chips or other IC chips (such as electronic components such as microphones or speakers). The use of various different chip combinations can expand the application scenarios of the encapsulation structure 100.

[0028] In some embodiments, the package substrate 1 may be a monolithic silicon substrate, such as a 12-inch package silicon wafer. A plurality of second vias 14 are formed through the bottom of the mounting groove 11, with the second vias 14 located around each chip 2, and the filler layer 3 extending to the second vias 14. Second vias 14 may be provided around each chip 2 near the pins 23, further penetrating the package substrate 1 to electrically lead the chip 2 out from the back side of the package structure 100.

[0029] In some embodiments, the surface of the chip 2, the surface of the filling layer 3, and the first end face 41 of the conductive pillar 4 are all substantially flush with the first surface 101 to facilitate the electrical connection between the chip 2 and the conductive pillar 4.

[0030] Chip 2 may include a front side 21 and a back side 22 that are arranged opposite to each other. The front side 21 of chip 2 is close to the opening of the mounting groove 11, and the back side 22 is close to the bottom of the mounting groove 11. This facilitates the formation of a redistribution layer 5 on the front side 21 of chip 2 to realize the electrical lead-out of chip 2.

[0031] In some embodiments, the chip 2 has pins 23 on its surface near the opening of the mounting groove 11, a redistribution layer 5 extends to the pins 23, and conductive posts 4 are electrically connected to the pins 23 through the redistribution layer 5, thereby realizing the electrical lead-out of the chip 2. The surface of the chip 2 with the pins 23 is the front surface 21, which is the working surface of the chip 2, while the back surface 22 is usually the non-working surface of the chip 2.

[0032] In some embodiments, chip 2 can have different functions according to actual needs. Chip 2 with multiple functions effectively improves the diversity of chip functions in the packaging structure 100. For example, this method can also be used for chip packaging in applications such as optical imaging, nanopore sequencing, and sensors to improve product performance. Specifically, depending on the function, chip 2 may include sensor chips, processor chips, micro-electro-mechanical system (MEMS) chips, etc. In the field of biochemical analysis, chip 2 may also include biochips for biochemical analysis, such as sequencing chips. The front side 21 of chip 2, as a biochip, also has a biological functional layer (not shown), and the biological functional layer needs to be exposed to facilitate the loading of samples into the biological functional layer, so that biochemical substances can undergo biochemical reactions on the biological functional layer, and at the same time, it is convenient to capture the light signals generated after the reaction.

[0033] In some embodiments, when chip 2 is a biochip, pin 23 is located outside the biofunctional layer, and redistribution layer 5 is electrically connected to pin 23 to avoid affecting the biochemical performance of the biofunctional layer during the molding process and to improve the accuracy of biochemical reactions.

[0034] In some embodiments, multiple chips 2 within the same mounting slot 11 can be arranged in an array. When multiple mounting slots 11 are present on the same packaging substrate 1, the multiple mounting slots 11 can also be arranged in an array. Encapsulating multiple chips 2 within the packaging substrate 1 constitutes a large-array planar packaging structure 100, which significantly improves the throughput of biochemical analysis (e.g., sequencing throughput), improves the accuracy of biochemical analysis, and reduces labor costs, making it applicable to more application scenarios.

[0035] The filling layer 3 can be made of inorganic insulating materials (such as semiconductor materials) or resin. In this embodiment, the filling layer 3 is made of resin. The filling layer 3 can fix the chip 2, and forming the first through-hole 31 on the resin filling layer 3 is easier than forming a hole directly on the packaging substrate 1, reducing the difficulty of hole formation and facilitating the electrical lead-out of the chip 2. In addition, the filling layer 3 is only located within the first gap 12 of the chip 2 and will not affect the working surface of the chip 2, thereby further improving the accuracy of biochemical analysis.

[0036] In some embodiments, the material of the filler layer 3 may include resins such as ABS resin, epoxy resin, polyphenylene oxyide (PPO), polyimide (PI), polyethylene terephthalate (PET), and polyethylene naphthalate (PEN).

[0037] The conductive posts 4 connecting different chips 2 are electrically isolated from each other. That is, during the process of setting the electrical connection between the conductive post 4 and the chip 2, a single conductive post 4 is electrically connected to a pin 23 on the corresponding chip 2. A chip 2 has conductive posts 4 around it corresponding to the number of pins 23. The conductive posts 4 connecting different chips 2 are independent of each other, that is, the chips 2 are electrically isolated from each other. This can prevent multiple chips 2 from interfering with each other, and thus enable independent control of multiple chips 2.

[0038] In some embodiments, the conductive post 4 can be made of metal (e.g., copper plating) or conductive paste. The conductive post 4 can be formed in the first through hole 31 by electroplating metal, or by filling and curing conductive paste.

[0039] In some embodiments, the second end face 42 of the conductive post 4 may be substantially flush with the second surface 102.

[0040] The package structure 100 may also include a connection pad 6, which is located on the first end face 41 of the conductive post 4 and extends to the fill layer 3 and the pin 23 of the chip 2 to achieve an electrical connection between the conductive post 4 and the pin 23.

[0041] The encapsulation structure 100 may also include a protective layer 8 covering the surface of the connector pad 6. By adding a protective layer 8 locally, the connector pad 6 can be protected, preventing it from being corroded by reagents during use and avoiding risks such as short circuits. Understandably, if the connector pad 6 does not completely cover the pin 23 during electrical connection, the protective layer 8 can also cover the pin 23 to prevent it from being corroded by reagents and avoiding risks such as short circuits.

[0042] The package structure 100 also includes an insulating layer 9 located on the surface of the redistribution layer 5. The insulating layer 9 has a connection portion 7, which may be a conductive protrusion formed on the second end face 42 of the conductive post 4, for subsequent electrical connection with other functional components.

[0043] In some embodiments, the connecting portion 7 may be a solder ball.

[0044] The packaging structure 100 provided in this application integrates multiple chips 2 (e.g., sequencing chips) into the same packaging substrate 1 to form a large-array planar packaging structure 100, which can significantly increase the throughput of biochemical analysis, improve the accuracy of biochemical analysis, and reduce labor costs. Electrical lead-out of the chip 2 is achieved by forming a first through-hole 31 through the bottom of the filling layer 3 and the mounting groove 11, and forming a conductive post 4 within the first through-hole 31. Therefore, the electrical lead-out lines of the chip 2 are not exposed, effectively reducing the risk of reagent corrosion, short circuits, and chip failure. The electrical lead-out method of the chip 2 does not require wire bonding, thus eliminating the need for adhesive to protect the wires and avoiding the influence of adhesive on the biochemical performance of the chip 2, improving the accuracy of biochemical analysis. Multiple chips 2 in the packaging structure 100 can be independently led out, and the circuit connections will not affect each other; the failure of a few chips 2 will not affect the use of the entire large array. Furthermore, multiple chips 2 in the packaging structure 100 can be independently controlled to meet the needs of different reaction processes.

[0045] Please see Figure 2 As shown, please refer to the following: Figure 1 and Figures 3A to 3H This application embodiment also provides a method for preparing the aforementioned packaging structure 100, including the following steps: Step S11, as follows Figure 3A As shown, at least one mounting groove 11 is formed on the packaging substrate 1.

[0046] Specifically, the package substrate 1 can be a monolithic structure, such as a 12-inch package silicon wafer. Mounting grooves 11 can be fabricated on the package substrate 1 using an etching process. Figure 3B As shown, the thickness of the packaging substrate 1 can be selected according to the thickness of the chip 2 to be packaged, so that the depth of the mounting groove 11 is approximately equal to the thickness of the chip 2.

[0047] Step S12, as follows Figure 3B and Figure 3C As shown, multiple chips 2 are spaced apart in each mounting slot 11, with the front side 21 of the chip 2 close to the opening of the mounting slot 11.

[0048] like Figure 3B As shown, the surface of wafer 10 is covered with photoresist 20. Wafer 10 can be cut into chips 2 by means of outer circle cutting, inner circle cutting, wire cutting and laser wire cutting. The photoresist 20 is retained on the front side 21 of chip 2, which can protect chip 2 in subsequent packaging process.

[0049] like Figure 3C As shown, multiple chips 2 can be installed in a mounting slot 11. The chips 2 are spaced apart to form a first gap 12, and the chips 2 are spaced apart from the sidewall of the mounting slot 11 to form a second gap 13. Specifically, when installing the chips 2, an adhesive layer (not shown) can be provided between the back surface 22 of the chips 2 and the bottom of the mounting slot 11 to improve the installation stability of the chips 2.

[0050] In some embodiments, the thickness of the chip 2 is approximately equal to the thickness of the mounting groove 11, so that the front side 21 of the chip 2 is approximately flush with the first surface 101 of the package substrate 1. This allows the front side of the chip 2 to be exposed through the mounting groove 11, and also facilitates the subsequent formation of a flat connection pad.

[0051] In some embodiments, the chips 2 within the same mounting slot 11 may have different functions, such as sensor chips, processor chips, MEMS chips, microphone chips, speaker chips, and biochips.

[0052] In some embodiments, chips 2 with different functions are mounted in the mounting slots 11 according to a certain pattern. For example, multiple chips 2 in the same mounting slot 11 can be arranged in an array. In addition, when multiple mounting slots 11 are provided on the package substrate 1, the multiple mounting slots 11 can also be arranged in an array to form a large array package.

[0053] Step S13, as follows Figure 3D As shown, a plurality of second through holes 14 are formed through the bottom of the mounting groove 11, and the second through holes 14 are located around each chip 2.

[0054] Specifically, by further etching, the bottom of the mounting groove 11 is etched through to form a hole that penetrates the packaging substrate 1. By using a step-by-step etching process to first etch the mounting groove 11 and then etch the second via 14, the difficulty of directly forming vias on a thick silicon substrate is reduced. In addition, the second via 14 is distributed around the chip 2, generally located near the pin 23 of the chip 2, to facilitate the electrical lead-out of the pin 23.

[0055] Step S14, as follows Figure 3E As shown, a filling layer 3 is provided in the second through hole 14, and the filling layer 3 extends between two adjacent chips 2 and between the chip 2 and the side wall of the mounting groove 11.

[0056] A filling layer 3 is provided in the first gap 12, the second gap 13 and the corresponding second through hole 14, so that the chip 2 can be stably encapsulated in the mounting groove 11.

[0057] In some embodiments, the filler layer 3 is formed by physical vapor deposition, chemical vapor deposition, lamination, or other methods. The filler layer 3 can be made of inorganic insulating material or resin material. By providing the filler layer 3, the chip 2 can be encapsulated within the encapsulation substrate 1 to form an embedded structure.

[0058] In some embodiments, the filler layer 3 may be made of resin materials, specifically including ABS resin, epoxy resin, polyphenylene oxyide (PPO), polyimide (PI), polyethylene terephthalate (PET), and polyethylene naphthalate (PEN), etc.

[0059] Step S15, as follows Figure 3F As shown, a first through-hole 31 is formed through the filling layer 3.

[0060] The first through-hole 31 can be formed on the filler layer 3 by mechanical drilling, laser drilling, or etching, so that the first through-hole 31 penetrates the entire filler layer 3. When resin material is used to form the filler layer 3, the forming difficulty of the first through-hole 31 is reduced compared to directly forming a through-hole on the thicker encapsulation substrate 1.

[0061] Step S16, as follows Figure 3G and Figure 3H As shown, a conductive post 4 is formed in each first through hole 31, and the conductive post 4 is electrically connected to the chip 2.

[0062] Specifically, the conductive post 4 includes a first end face 41 and a second end face 42 disposed opposite to each other, with the first end face 41 close to the opening of the mounting groove 11.

[0063] A first through-hole 31 is formed on the filler layer 3, and a conductive post 4 is formed within the first through-hole 31. The hole wall of the first through-hole 31 is flat, providing a smooth surface for the forming of the conductive post 4. Specifically, the conductive post 4 can be formed using conventional conductive post forming methods in circuit board design, such as physical vapor deposition, chemical vapor deposition, electroplating, etc.

[0064] The first end face 41 of the conductive post 4 is approximately flush with the first surface 101 of the package substrate 1, that is, the first end face 41 can be approximately flush with the front surface 21 of the chip 2, so as to facilitate the subsequent electrical connection between the conductive post 4 and the chip 2. The second end face 42 of the conductive post 4 is approximately flush with the second surface 102 of the package substrate 1, which is beneficial for the electrical lead-out of the chip 2.

[0065] Specifically, the electrical connection method between the conductive post 4 and the chip 2 includes the following steps: Step 1, as follows Figure 3G As shown, a conductive post 4 is formed inside the first through hole 31.

[0066] The conductive pillar 4 can be formed within the first through-hole 31 by methods such as physical vapor deposition, chemical vapor deposition, or electroplating. Alternatively, the conductive pillar 4 can also be formed by filling the first through-hole 31 with conductive paste.

[0067] In some embodiments, before forming the conductive post 4, a seed layer may be formed on the inner wall of the first through hole 31 to improve the bonding force between the conductive post 4 and the filling layer 3.

[0068] Step 2, as follows Figure 3H As shown, the photoresist 20 on the surface of chip 2 is removed, and a dielectric layer 30 is formed.

[0069] Step 3, as follows Figure 3H As shown, the dielectric layer 30 is patterned to form an opening 40, through which the conductive pillar 4, the filling layer 3, and the pin 23 of the chip 2 are exposed.

[0070] Step 4, as follows Figure 1 As shown, a connecting pad 6 is formed within the opening 40, and the connecting pad 6 is electrically connected to the conductive post 4 and the pin 23 of the chip 2.

[0071] Step 5, as follows Figure 1 As shown, a protective layer 8 is formed on the surface of the connecting pad 6.

[0072] A protective layer 8 is formed within the opening 40 to cover the connector pad 6, thereby reducing the risk of the connector pad 6 being corroded by reagents. Understandably, the protective layer 8 can also cover the exposed pin 23.

[0073] Step 6, remove the medium layer 30.

[0074] Removing the dielectric layer 30 exposes the front side 21 of the chip 2. Alternatively, the dielectric layer 30 can be removed after subsequent steps.

[0075] Understandably, in other embodiments, the conductive post 4 and the connecting pad 6 can also be formed simultaneously, specifically including the following steps: Step 1a, as follows Figure 3I As shown, a dielectric layer 30 is formed on the surface of the filling layer 3 near the opening of the mounting groove 11, and the dielectric layer 30 extends to the front side 21 of the chip 2.

[0076] First, the photoresist 20 on the front side 21 of chip 2 is removed, and then a dielectric layer 30 is applied to the front side 21 of chip 2. Extending the dielectric layer 30 to the front side 21 of chip 2 provides protection, preventing damage to the working surface of chip 2 during subsequent patterning and electroplating processes.

[0077] Step 2a, as follows Figure 3I As shown, the patterned dielectric layer 30 exposes the first via 31 and the pins 23 of the chip 2.

[0078] Specifically, an opening 40 is formed in the dielectric layer 30 at the position corresponding to the first through hole 31, so that the first through hole 31, the end face of the filling layer 3 and the pin 23 of the chip 2 are exposed through the opening 40.

[0079] The patterning of the dielectric layer 30 may include steps such as coating, exposure and development, and etching.

[0080] Step 3a, as follows Figure 3J As shown, a conductive post 4 is formed in the first through hole 31, and a connecting pad 6 is formed on the surface of the filling layer 3. The connecting pad 6 electrically connects the conductive post 4 and the pin 23.

[0081] Step 4a, as follows Figure 1 As shown, a protective layer 8 is formed on the surface of the connecting pad 6.

[0082] Step 5a, remove the dielectric layer 30.

[0083] Step S17, as follows Figure 1 As shown, a redistribution layer 5 is formed on the surface of the encapsulation substrate 1 away from the opening of the mounting groove 11. The redistribution layer 5 is electrically connected to the conductive pillar 4, thereby obtaining the encapsulation structure 100.

[0084] The redistribution layer 5 may include one layer of wiring or multiple layers of wiring, and the specific wiring method can be formed using traditional additive or subtractive methods. The redistribution layer 5 can also be formed by printing.

[0085] After the redistribution layer 5 is formed, an insulating layer 9 can be formed on the surface of the redistribution layer 5, and a connecting portion 7 can be formed on the surface of the insulating layer 9. The connecting portion 7 is electrically connected to the redistribution layer 5. The connecting portion 7 can be a solder ball, which can be used to make electrical connections with other functional components (such as a motherboard circuit board).

[0086] The method for fabricating the encapsulation structure 100 provided in this application encapsulates multiple chips 2 within the encapsulation substrate 1, which helps reduce the overall thickness of the encapsulation structure 100 and achieves a large-array planar encapsulation, effectively improving the throughput and accuracy of biochemical analysis. Furthermore, by forming a first through-hole 31 within the filling layer 3 and placing the conductive posts 4 for electrical lead-out of the chip 2 within the first through-hole 31, corrosion of the conductive posts 4 by reagents and short circuits can be avoided, reducing the risk of chip 2 failure. The electrical lead-out method of the chip 2 does not require wire bonding, thus eliminating the need for adhesive to protect the wires and avoiding the influence of adhesive on the performance of the chip 2, thereby improving the accuracy of biochemical analysis. In addition, the fabrication process of this encapsulation structure 100 is simple, improving the yield of the encapsulation structure 100 and reducing labor costs.

[0087] Please see Figure 4 This application also provides a packaging structure 200, which is basically the same as the packaging structure 100 in the previous embodiment. The main difference is that the structure of the packaging substrate 1a in the packaging structure 200 is different from that in the previous embodiment.

[0088] In this embodiment, the encapsulation substrate 1a includes a substrate 1b and an encapsulation layer 1c stacked along the thickness direction a. The substrate 1b has at least one opening 11b, and the encapsulation layer 1c includes a first portion 11c, a second portion 12c, and a third portion 13c that are interconnected. The first portion 11c is located on the surface of the substrate 1b, and the first portion 11c and the second portion 12c are interconnected along the extension direction b of the encapsulation substrate 1a. The opening 11b corresponds to the second portion 12c, thereby forming a mounting groove 11a between the substrate 1b and the second portion 12c. A plurality of chips 2 are spaced apart in the mounting groove 11a, with the front surface 21 of the chips 2 close to the opening of the mounting groove 11a. The third portion 13c is located in the mounting groove 11a, between two adjacent chips 2 and between the chips 2 and the sidewall of the mounting groove 11a, thereby forming a filling layer 3. A first through-hole 31 is provided through the third portion 13c and the corresponding second portion 12c, and a conductive post 4 is located in the first through-hole 31 to achieve electrical connection with the chips 2. The redistribution layer 5 is located on the surface of the encapsulation layer 1c opposite to the mounting groove 11a and is electrically connected to the conductive post 4, thereby realizing the electrical lead-out of the chip 2. The surface of the substrate 1b opposite to the encapsulation layer 1c forms the first surface 101, and the surface of the encapsulation layer 1c opposite to the substrate 1b forms the second surface 102.

[0089] In some embodiments, substrate 1b may be a silicon substrate.

[0090] In some embodiments, the encapsulation layer 1c may be a resin encapsulation layer. Specifically, the material of the encapsulation layer 1c may include resins such as ABS resin, epoxy resin, polyphenylene oxyether (PPO), polyimide (PI), polyethylene terephthalate (PET), and polyethylene naphthalate (PEN). It is understood that the encapsulation layer 1c may also be an inorganic insulating material (e.g., a semiconductor material).

[0091] Please see Figure 5 Please refer to both together. Figure 4 and Figures 6A to 6F This application provides a method for fabricating the encapsulation structure 200, which specifically includes the following steps: Step S21, as follows Figure 6A As shown, at least one groove 12b is formed on the substrate 1b.

[0092] Specifically, substrate 1b can be a silicon substrate, such as a 12-inch packaging silicon wafer. Recesses 12b can be fabricated on substrate 1b using an etching process. Figure 3B As shown, the depth of the groove 12b is approximately equal to the thickness of the chip 2.

[0093] Step S22, as follows Figure 6B As shown, multiple chips 2 are spaced apart in each groove 12b, with the front side 21 of the chip 2 close to the bottom of the groove 12b.

[0094] The structure and molding method of chip 2 are detailed in the aforementioned embodiments and will not be elaborated further here.

[0095] Step S23, as Figure 6C As shown, an encapsulation layer 1c is formed on the surface of substrate 1b and extends into the groove 12b. The encapsulation layer 1c includes a first portion 11c located on substrate 1b, a second portion 12c corresponding to the groove 12b, and a third portion 13c extending into the groove 12b. The third portion 13c is located between two adjacent chips 2 and between the chip 2 and the sidewall of the groove 12b. The third portion 13c constitutes a filling layer 3.

[0096] Step S24, as Figure 6D As shown, a portion of the substrate 1b is removed to expose the front side 21 of the chip 2, and the remaining substrate 1b and the second portion 12c form a mounting groove 11a.

[0097] Remove the substrate 1b corresponding to the bottom of the groove 12b to form an opening 11b in the groove 12b, thereby thinning the substrate 1b so that the front side 21 of the chip 2 is exposed.

[0098] Step S25, as Figure 6E As shown, a first through hole 31 is formed by penetrating the filling layer 3 and the corresponding second part 12c.

[0099] The specific molding method of this step is basically the same as step S15 of the aforementioned embodiment. Please refer to step S15 of the aforementioned embodiment. It will not be described in detail here.

[0100] Step S26, as follows Figure 6F As shown, a conductive post 4 is formed in each first through hole 31, and the conductive post 4 is electrically connected to the chip 2.

[0101] The specific forming method of this step is basically the same as step S16 in the aforementioned embodiment. Please refer to step S16 in the aforementioned embodiment. It will not be described in detail here.

[0102] Step S27, as Figure 4 As shown, a redistribution layer 5 is formed on the surface of the encapsulation layer 1c away from the substrate 1b. The redistribution layer 5 is electrically connected to the conductive pillar 4, thereby obtaining the encapsulation structure 200.

[0103] The specific forming method of this step is basically the same as step S17 of the aforementioned embodiment. Please refer to step S17 of the aforementioned embodiment. It will not be described in detail here.

[0104] Compared to the aforementioned embodiments, the packaging structure 200 and its fabrication method provided in this embodiment offer another implementation approach for large array planar packaging. By combining the substrate 1b and the packaging layer 1c to form the packaging substrate 1a, the bonding area between the packaging layer 1c and the substrate 1b is increased, improving bonding stability and thus enhancing the packaging stability of the chip 2. Furthermore, the second part 12c and the third part 13c in the packaging layer 1c are an integral structure, allowing the filling layer 3 to be directly formed without the need for separately forming a second via for filling. This reduces the steps of forming and filling vias on the silicon substrate, lowering the molding difficulty.

[0105] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of this application without departing from the spirit and scope of the technical solutions of this application.

Claims

1. A method for preparing a packaging structure, characterized in that, include: At least one mounting groove is formed on the packaging substrate; Multiple chips are spaced apart in each of the mounting slots, with a first gap between two adjacent chips and a second gap between the chips and the sidewall of the mounting slot. A plurality of second through holes are formed through the bottom of the mounting groove, and the second through holes are located around each of the chips; A filling layer is formed within the first gap and the second gap, and the filling layer extends into the second through hole; A first through-hole is formed by penetrating the filler layer; A conductive post is formed in each of the first through holes, and the conductive post is electrically connected to the chip; as well as A redistribution layer is formed on the surface of the encapsulation substrate opposite to the opening of the mounting groove. The redistribution layer is electrically connected to the conductive pillar, thereby obtaining the encapsulation structure.

2. The method for preparing the packaging structure as described in claim 1, characterized in that, The step of forming a conductive post in each of the first through holes and electrically connecting the conductive post to the chip includes: A dielectric layer is formed on the surface of the filling layer near the opening of the mounting groove, and the dielectric layer extends to the surface of the chip; Pattern the dielectric layer to expose the first via and the pins on the chip; and The conductive post is formed in the first through hole, and a connecting pad is formed on the surface of the filling layer. The connecting pad electrically connects the conductive post and the pin.

3. The method for preparing the packaging structure as described in claim 1, characterized in that, After the step of forming the redistribution layer, the fabrication method further includes: An insulating layer is formed on the surface of the redistribution layer, and a connection portion is formed on the surface of the insulating layer, the connection portion being electrically connected to the redistribution layer.

4. The method for preparing the packaging structure as described in claim 2, characterized in that, The chip is a biochip. The surface of the chip near the opening of the mounting slot is the front side. The front side is provided with a biofunctional layer and pins located around the periphery of the biofunctional layer. The biofunctional layer is exposed from the encapsulation substrate, and the connecting pad extends to the surface of the pins.

5. The method for preparing the packaging structure as described in claim 1, characterized in that, The encapsulation substrate is an integral substrate.

6. The method for preparing the packaging structure as described in claim 1, characterized in that, The encapsulation substrate includes a substrate and an encapsulation layer stacked along the thickness direction. The substrate has at least one opening. The encapsulation layer includes a first part, a second part, and a third part that are connected to each other. The first part is located on the surface of the substrate. The second part corresponds to the opening. The substrate and the second part form the mounting groove. The third part is located in the mounting groove and within the first gap and the second gap. The third part constitutes the filling layer.

7. A packaging structure prepared by the method described in any one of claims 1 to 6, characterized in that, include: The encapsulation substrate has at least one mounting slot; Multiple chips are provided in each mounting slot at intervals, a first gap is formed between two adjacent chips, and a second gap is formed between the chips and the sidewall of the mounting slot. A filling layer, located between the first gap and the second gap, has a plurality of first through holes formed through the bottom of the filling layer and the mounting groove, the first through holes being located around each of the chips; A conductive post is located inside the first through hole, and the conductive post is electrically connected to the chip; as well as A redistribution layer is located on the surface of the package substrate away from the opening of the mounting slot, and the redistribution layer is electrically connected to the conductive pillar.

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